Texas Instruments SN65LVDM176D, SN65LVDM176DGK, SN65LVDM176DGKR, SN65LVDM176DR Datasheet

D

Low-Voltage Differential Driver and
Receiver for Half-Duplex Operation

D

Designed for Signaling Rates of 400 Mbit/s

D

ESD Protection Exceeds 15 kV on Bus Pins

D

Operates from a Single 3.3 V Supply

D

Low–Voltage Differential Signaling with
Typical Output Voltages of 350 mV and a
50Ω Load

D

Propagation Delay Times
– Driver: 1.7 ns Typ
– Receiver: 3.7 ns Typ

D

Power Dissipation at 200 MHz
– Driver: 50 mW Typical
– Receiver: 60 mW Typical

D

LVTTL Levels are 5 V Tolerant

D

Bus Pins are High Impedance When
Disabled or With V

D

Open-Circuit Fail-Safe Receiver

D

Surface-Mount Packaging

Less Than 1.5 V

CC

– D Package (SOIC)
– DGK Package (MSOP)

description

SN65LVDM176

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

SN65LVDM176D (Marked as DM176 or LVM176)

SN65LVDM176DGK (Marked as M76)

(TOP VIEW)

1

R

2

RE

3

DE

4

D

logic diagram (positive logic)

3

DE

4

D

2

RE

1

R

8

V

CC

7

B

6

A

5

GND

6

A

7

B

The SN65L VDM176 is a differential line driver and receiver configured as a transceiver that uses low-voltage
differential signaling (LVDS) to achieve signaling rates as high as 400 Mbit/s. These circuits are similar to
TIA/EIA-644 standard compliant devices (SN65L VDS) counterparts except that the output current of the drivers
is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50Ω
load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference
of less than 100 mV with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of this device and signaling technique is for half-duplex or multiplex baseband data
transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The
transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and
distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to
the environment, and other application specific characteristics).

The SN65LVDM176 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

AVAILABLE OPTIONS

T

A

–40°C to 85°C SN65LVDM176D SN65LVDM176DGK

†

The D package is available taped and reeled. Add the suffix R to the device type
(e.g., SN65LVDM176DR).

H = high level, L = low level, X = irrelevant,
Z = high impedance

SMALL OUTLINE

(D)

†

Function Tables

DRIVER

INPUT ENABLE

D DE

L H L H

H H H L

Open H L H

X L Z Z

PACKAGE

OUTPUTS

A B

MSOP

(DGK)

†

RECEIVER

DIFFERENTIAL INPUTS

VID = VA – V

VID ≥ 100 mV L H

–100 mV < VID < 100 mV L ?

VID ≤ –100 mV L L

Open L H

H = high level, L = low level, X = irrelevant,
Z = high impedance

B

X H Z

ENABLE OUTPUT

RE R

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

equivalent input and output schematic diagrams

V

CC

300 kΩ

D or RE

Input

7 V

50 Ω

300 kΩ

DE

50 Ω

Input

7 V

SN65LVDM176

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

V

CC

V

CC

10 kΩ

5 Ω

Y or Z
Output

7 V

7 V

V

CC

300 kΩ300 kΩ

B InputA Input

7 V

V

CC

5 Ω

R Output

7 V

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3

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range (D, R, DE, RE) –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (A, B , and GND) (see Note 2) CLass 3, A:15 kV, B:600 V. . . . . . . . . . . . . . . . . . . . . .

All terminals Class 3, A:7 kV, B:500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING TABLE

PACKAGE

D 725 mW 5.8 mW/°C 377 mW

DGK 424 mW 3.4 mW/°C 220 mW

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 85°C

POWER RATING

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Magnitude of differential input voltage, VID 0.1 0.6 V

Common–mode input voltage, VIC (see Figure 1)

Operating free–air temperature, T

CC

IH

IL

A

3 3.3 3.6 V
2 V

0.8 V

Ť

Ť

V

ID

2

–40 85 °C

2.4

*

VCC–0.8

Ť

V

ID

2

Ť

V

†

4

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2.5

ICCSu ly current

mA

2

1.5

1

– Common-Mode Input Voltage – V

0.5

IC

V

SN65LVDM176

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

COMMON-MODE INPUT VOLTAGE

vs

DIFFERENTIAL INPUT VOLTAGE

Max at VCC > 3.15 V

Max at VCC = 3 V

Min

0

0.1 0.3

0.2 0.40

|VID| – Differential Input Voltage – V

0.5 0.6

Figure 1

device electrical characteristics over recommended operating conditions (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

I

Supply current

†

All typical values are at 25°C and with a 3.3-V supply.

Driver and receiver enabled, No receiver load,
Driver RL = 50 Ω

Driver enabled, Receiver disabled, RL = 50 Ω
Driver disabled, Receiver enabled, No load 1.8 5
Disabled 0.5 2

10 15

9 15

mA

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5

SN65LVDM176

R

50Ω

IIHHigh-level input current

V

V

A

IILLow-level input current

V

V

A

IOSShort-circuit output current

mA

See Figure 6

mV

IIInput current (A or B inputs)

‡

A

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

driver electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOD Differential output voltage magnitude

∆VOD
V

OC(SS)

∆V

OC(SS)

V

OC(PP)

C

I

†

The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for this parameter.

Change in differential output voltage magnitude between logic
states

Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output voltage between

logic states
Peak-to-peak common-mode output voltage 50 150 mV

p

p

Input capacitance 3 pF

†

†

p

†

DE
D
DE
D

=

,

L

See Figure 2 and Figure 3

See Figure 4

= 5

IH

= 0.8

IL

VOA or VOB = 0 V –10
VOD = 0 V

247 340 454
–50 50

–50 50 mV

0.5 10
2 20

–0.5 –10

2 10

mV

µ

µ

–10

receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

ITH+

V

ITH–

V

OH

V

OL

I

I(OFF)

I

IH

I

IL

I

OZ

†

All typical values are at 25°C and with a 3.3-V supply.

‡

The non-algebraic convention, where the more positive (least negative) limit is designated maximum, is used in this data sheet for this parameter.

Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage IOH = –8 mA 2.4 V
Low-level output voltage IOL = 8 mA 0.4 V

p

Power-off input current (A or B inputs) VCC = 0 V or 1.8 V 20 µA
High-level input current (enables) VIH = 5 V 10 µA
Low-level input current (enables) VIL = 0.8 V 10 µA
High-impedance output current

p

‡

VI = 0 V –2 –20
VI = 2.4 V –1.2

VO = 0 V or 5 V ±1 µA

–100

100

µ

6

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SN65LVDM176

ns

R

L

50Ω

ns

See Figure 5

ns

See Figure 7

ns

See Figure 8

ns

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

driver switching characteristics over recommended operating conditions (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

t

PHL

t

sk(p)

t

r

t

f

t

PZH

t

PZL

t

PHZ

t

pLZ

†

All typical values are at 25°C and with a 3.3 V supply.

‡

t

sk(lim)

receiver switching characteristics over recommended operating conditions (unless otherwise
noted)

t

PLH

t

PHL

t

sk(p)

t

r

t

f

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at 25°C and with a 3.3-V supply.

‡

t

sk(lim)

Propagation delay time, low-to-high-level output 0.5 1.7 2.7
Propagation delay time, high-to-low-level output
Pulse skew (|t
Differential output signal rise time
Differential output signal fall time 0.6 1
Propagation delay time, high-impedance-to-high-level output 8 12
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output 4 10

is the maximum delay time difference between drivers over temperature, VCC, and process.

Propagation delay time, low-to-high-level output 2.3 3.7 4.5
Propagation delay time, high-to-low-level output
Pulse skew (|t
Output signal rise time
Output signal fall time 0.8 1.5
Propagation delay time, high-level-to-high-impedance output 3 10
Propagation delay time, low-level-to-low-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, low-impedance-to-high-level output 6 10

is the maximum delay time difference between drivers over temperature, VCC, and process.

– t

pHL

pHL

|)

pLH

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

– t

|)

pLH

=

=
CL = 10 pF,
See Figure 3

CL = 10 pF,

,

0.5 1.7 2.7

0.2 ns

0.6 1

2.3 3.7 4.5

0.4

0.8 1.5

7 10
3 10

ns

3 10
4 10

driver

PARAMETER MEASUREMENT INFORMATION

I

Driver Enabled

I

I

D

V

I

Figure 2. Driver Voltage and Current Definitions

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OA

A

V

OD

I

OB

B

V

OA

V

V

OB

OC

VOA)

V

OB

2

7

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

driver (continued)

Driver Enabled

A

Input

B

Input

t

PLH

V

Output

OD(H)

V

OD

CL = 10 pF
(2 Places)

t

PHL

50 Ω
±1%

2 V

1.4 V

0.8 V

100%
80%

0 V

V

OD(L)

20%
0%

t

f

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T.

t

r

Figure 3. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

Driver Enabled

Input

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T. The measurement of
V

D

is made on test equipment with a –3 dB bandwidth of at least 300 MHz.

OC(PP)

A

B

25 Ω, ±1% (2 Places)

CL = 10 pF
(2 Places)

D

V

OC

V

O

V

OC(PP)

3 V

0 V

V

OC(SS)

Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output V oltage

8

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driver (continued)

PARAMETER MEASUREMENT INFORMATION

0.8 V or 2 V

DE

A

B

CL = 10 pF

(2 Places)

SN65LVDM176

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

25 Ω, ±1% (2 Places)

V

OAVOB

1.2 V

DE

V

OA

t

PZH

V

OB

t

PZL

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0.06 mm of the D.U.T.

t

PHZ

t

PLZ

2 V

1.4 V

0.8 V
~1.4 V

1.25 V

1.2 V

1.2 V

1.15 V
~1 V

Figure 5. Enable and Disable Time Circuit and Definitions

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9

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

receiver

VIA)

V

IB

2

V

IA

V

IC

Figure 6. Receiver Voltage Definitions

Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages

A

V

ID

B

V

IB

R

V

O

APPLIED VOLTAGES

V

1.215 1.185 30 1.2

1.185 1.215 –30 1.2

2.37 2.4 –30 2.385

0.03 0 30 0.015

(V)

IA

2.4 2.37 30 2.385

0 0.03 –30 0.015

1.5 0.9 600 1.2

0.9 1.5 –600 1.2

2.4 1.8 600 2.1

1.8 2.4 –600 2.1

0.6 0 600 0.3
0 0.6 –600 0.3

V

IB

RESULTING DIFFERENTIAL

INPUT VOLTAGE

(mV)

V

ID

RESULTING COMMON-

MODE INPUT VOLTAGE

V

(V)

IC

10

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receiver (continued)

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

V

ID

V

IA

V

IB

C

L

10 pF

V

O

SN65LVDM176

V

IA

V

IB

V

ID

t

PHL

V

O

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T.

2.4 V

0.4 V
t

f

t

PLH

t

r

1.4 V

1 V

0.4 V

0 V

–0.4 V

V

OH

1.4 V
V

OL

Figure 7. Timing Test Circuit and Waveforms

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11

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

receiver (continued)

1.2 V

Inputs

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulse width = 5000 ± 10 ns. CL includes instrumentation and fixture capacitance within 0.06 m of the D.U.T.

V

TEST

A

RE

t

PZL

t

PZL

RE

B

500 Ω

A

C

L

10 pF

V

O

t

PLZ

+
–

V

2.5 V

1 V

2 V

1.4 V

0.8 V

TEST

2.5 V

1.4 V
V

OL

0 V

1.4 V

2 V

1.4 V

0.8 V

V

OH

1.4 V

0 V

V

TEST

RE

t

R

A

PZH

R

VOL +0.5 V

t

PZH

VOH –0.5 V

t

PHZ

Figure 8. Enable/Disable Time Test Circuit and Waveforms

12

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HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

TYPICAL CHARACTERISTICS

SN65LVDM176

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

4

3

2

1

– Low-Level Output Voltage – V

OL

V

0

DRIVER

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

VCC = 3.3 V
TA = 25°C

6102

IOL – Low-Level Output Current – mA

80

Figure 9

DRIVER

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

3.5

3

2.5

2

1.5

1

– High-Level Output Voltage – V

OH

.5

V

124

0

0

IOH – High-Level Output Current – mA

–4 –6

VCC = 3.3 V
TA = 25°C

–8–2

Figure 10

4

3

2

1

– High-Level Output Voltage – V
OH

V

0

RECEIVER

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

VCC = 3.3 V
TA = 25°C

0

–20

IOH – High-Level Output Current – mA

–40 –60

Figure 11

–80

5

4

3

2

– Low-Level Output Votlage – V

1

OL

V

0

RECEIVER

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

VCC = 3.3 V
TA = 25°C

0

10

IOL – Low-Level Output Current – mA

20 30

Figure 12

40 50

60

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13

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

TYPICAL CHARACTERISTICS

DRIVER

HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

2.5

2

PLH – High-To-Low Propagation Delay Time – ns

1.5

t

–50

VCC = 3 V

–30

–10

TA – Free-Air Temperature – °C

VCC = 3.3 V

VCC = 3.6 V

10

30 70

50 90

Figure 13

DRIVER

LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

2.5

2

PLH – Low-To-High Propagation Delay Time – ns

1.5

t

–50

VCC = 3 V

–30

–10

TA – Free-Air Temperature – °C

VCC = 3.3 V

VCC = 3.6 V

10

30 70

50 90

Figure 14

RECEIVER

HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

4.5

4

3.5

– High-To-Low Level Propagation Dealy T ime – ns

2.5

PLH

t

3

–50

VCC = 3 V

–30

TA – Free–Air Temperature – °C

VCC = 3.3 V

VCC = 3.6 V

–10

10

50 90

30 70

Figure 15

RECEIVER

LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME

vs

FREE–AIR TEMPERATURE

4.5

VCC = 3 V

4

3.5

3

2.5

PLH – Low-To-High Level Propagation Delay Time – ns

t

–50

–30

VCC = 3.3 V

VCC = 3.6 V

–10

TA – Free-Air Temperature – °C

10

50 90

30 70

Figure 16

14

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SN65LVDM176

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

APPLICATION INFORMATION

The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common–mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/Receivers maintain ECL speeds without the
power and dual supply requirements.

1000

100

10

1

Transmission Distance – m

24 AWG UTP 96 Ω (PVC Dielectric)

0.1
100k 10M 100M

5% Jitter

1M

30% Jitter

Data Rate – Hz

Figure 17. Data Transmission Distance Versus Rate

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15

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

APPLICATION INFORMATION

fail safe

One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair . The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the L VDS receiver
will pull each line of the signal pair to near V
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.

300 kΩ 300 kΩ

through 300-kΩ resistors as shown in Figure 1 1. The fail-safe

CC

V

CC

A

Rt = 100 Ω (Typ)

B

VIT ≈ 2.3 V

Y

Figure 18. Open-Circuit Fail Safe of the LVDS Receiver

It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not af fect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pull-up currents from the receiver and the fail-safe feature.

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

APPLICATIONS INFORMATION

SN65LVDM176

A

D

DE
RE

R

100 Ω

Note A: Keep drivers and receivers as close to the LVDS bus side connector as possible.

B

+

_

D/R

100 Ω

Bidirectional Half-Duplex Applications

D/R

D/R

Multipoint Bus Applications

100 Ω

D/R

D/R

D/R

A

B

+

_

Figure 19. Bidirectional Half-Duplex and Multipoint Bus Applications

D
DE

RE

R

D/R

100 Ω

D/R

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

17

SN65LVDM176
HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.050 (1,27)

14

1

0.069 (1,75) MAX

0.020 (0,51)

0.014 (0,35)
8

7

A

0.010 (0,25)

0.004 (0,10)

DIM

0.157 (4,00)

0.150 (3,81)

PINS **

0.010 (0,25)

0.244 (6,20)

0.228 (5,80)

8

M

Seating Plane

0.004 (0,10)

14

0.008 (0,20) NOM

0°–8°

16

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

18

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96

SN65LVDM176

HIGH-SPEED DIFFERENTIAL LINE TRANSCEIVER

SLLS320C – DECEMBER 1998 – REVISED MARCH 2000

MECHANICAL DATA

DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,65

0,38
0,25

8

1

3,05
2,95

5

3,05
2,95

4

Seating Plane

0,25

4,98
4,78

M

0,15 NOM

Gage Plane

0,25

0°–6°

0,69
0,41

1,07 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187

0,15 MIN

0,10

4073329/A 02/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

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