Texas Instruments SM320C6701GLPS16, SM320C6701GLPW14, SMJ320C6701GLPW14 Datasheet

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

 Highest Performance Floating-Point Digital

Signal Processor (DSP) SMJ320C6701 – 7-, 6-ns Instruction Cycle Time – 140-, 167-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – Up to 1 GFLOPS Performance – Pin-Compatible With ’C6201 Fixed-Point

DSP

 SMJ: QML Processing to MIL-PRF-38535  SM: Standard Processing  Operating Temperature Ranges

– Extended (W) –55°C to 115°C – Extended (S) –40°C to 90°C

 VelociTI Advanced Very Long Instruction

Word (VLIW) ’C67x CPU Core – Eight Highly Independent Functional

Units: – Four ALUs (Floating- and Fixed-Point) – Two ALUs (Fixed-Point) – Two Multipliers (Floating- and

Fixed-Point)

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional

 Instruction Set Features

– Hardware Support for IEEE

Single-Precision Instructions – Hardware Support for IEEE

Double-Precision Instructions – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization

 1M-Bit On-Chip SRAM

– 512K-Bit Internal Program/Cache

(16K 32-Bit Instructions)

– 512K-Bit Dual-Access Internal Data

(64K Bytes)

 32-Bit External Memory Interface (EMIF)

– Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

 Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller With an Auxiliary Channel

 16-Bit Host-Port Interface (HPI)

– Access to Entire Memory Map

 Two Multichannel Buffered Serial Ports

(McBSPs) – Direct Interface to T1/E1, MVIP, SCSA

Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

 Two 32-Bit General-Purpose Timers  Flexible Phase-Locked-Loop (PLL) Clock

Generator

 IEEE-1149.1 (JTAG

†

)

Boundary-Scan-Compatible

 429-Pin Ceramic Ball Grid Array (CBGA)

Package (GLP Suffix)

 0.18-µm/5-Level Metal Process

– CMOS Technology

 3.3-V I/Os, 1.9-V Internal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Copyright  2000, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

1

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

GLP PACKAGE

(BOTTOM VIEW)

AA Y W V U T R P N M L K J H G F E D C B A

1

3

5

2

9

7

10

8

64

12 14

19

171311

15

16

21

18

20

description

The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701 (’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by T exas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

TI is a trademark of Texas Instruments Incorporated.

TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation.

Windows is a registered trademark of the Microsoft Corporation.

2

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SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

device characteristics

T able 1 provides an overview of the ’C6701 DSP . The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.

Table 1. Characteristics of the ’C6701 Processors

CHARACTERISTICS DESCRIPTION

Device Number SMJ320C6701 On-Chip Memory

Peripherals

Cycle Time 7 ns at 140 MHz, and 6 ns at 167 MHz Package Type 27 mm × 27 mm, 429-Pin BGA (GLP)

Nominal Voltage

512-Kbit Program Memory 512-Kbit Data Memory (organized as 2 blocks)

2 Mutichannel Buffered Serial Ports (McBSP) 2 General-Purpose Timers Host-Port Interface (HPI) External Memory Interface (EMIF)

1.9 V Core

3.3 V I/O

functional and CPU block diagram

SDRAM

SBSRAM

SRAM ROM/FLASH I/O Devices

Framing Chips:

H.100, MVIP , SCSA, T1, E1

AC97 Devices, SPI Devices, Codecs

HOST CONNECTION MC68360 Glueless MPC860 Glueless PCI9050 Bridge + Inverter MC68302 + PAL MPC750 + PAL MPC960 (Jx/Rx) + PAL

32

16

External Memory

Interface (EMIF)

Timer 0

Timer 1

Multichannel

Buffered Serial

Multichannel

Buffered Serial

Host Port

Interface

(HPI)

Port 0

Port 1

’C6701 Digital Signal Processor

Program

Bus

Access/Cache

Controller

.L1†.S1†.M1†.D1 .D2 .M2†.S2†.L2

DMA Buses

Data Bus

Direct Memory

Access Controller

(DMA)

(4 Channels)

PLL

(x1, x4)

Instruction Fetch

Instruction Dispatch

Instruction Decode

Data Path A

A Register File

Power-

Down Logic

’C67x CPU

Data

Access

Controller

Internal Program Memory

1 Block Program/Cache

(64K Bytes)

Data Path B

B Register File

†

Internal Data

Memory

(64K Bytes)

2 Blocks of 8 Banks

Control

Registers

Control

Logic

Test

In-Circuit

Emulation

Interrupt

Control

Each

†

These functional units execute floating-point instructions.

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SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

CPU description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional and CPU block diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally , each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle.

The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle.

Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

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CPU description (continued)

Data Path A

LD1 32 MSB

ST1

LD1 32 LSB

DA1

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

src1

†

src2

.L1

.S1

.M1

.D1

dst long dst long src

long src long dst

dst

†

src1 src2

dst

†

src1 src2

dst

src1 src2

8

32

Register

File A

(A0–A15)

2X

Data Path B

DA2

LD2 32 LSB

LD2 32 MSB

ST2

.D2

.M2

.S2

.L2

src2 src1

dst

src2

†

src1

dst

src2 src1

†

dst long dst long src

long src long dst

dst

†

src2

src1

1X

Register

File B

8

32

8

(B0–B15)

Control

Register File

†

These functional units execute floating-point instructions.

Figure 1. SMJ320C67x CPU Data Paths

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5

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

signal groups description

CLKIN CLKOUT2 CLKOUT1

CLKMODE1 CLKMODE0

PLLFREQ3 PLLFREQ2 PLLFREQ1

PLLV

PLLG

PLLF

TMS TDO

TDI

TCK

TRST EMU1 EMU0

RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0

CLOCK/PLL

IEEE Standard

1149.1

(JTAG)

Emulation

Reserved

Control/Status

Boot Mode

Reset and Interrupts

Little ENDIAN

Big ENDIAN

DMA Status

Power-Down

Status

BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0

RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4

IACK INUM3 INUM2 INUM1 INUM0

LENDIAN

DMAC3 DMAC2 DMAC1 DMAC0

PD

HPI

Control

HAS HR/W HCS HDS1 HDS2 HRDY HINT

HD[15:0]

HCNTL0 HCNTL1

HHWIL

HBE1

HBE0

16

Data

Register Select

Half-Word/Byte

Select

(Host-Port Interface)

Figure 2. CPU and Peripheral Signals

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signal groups description (continued)

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

ED[31:0]

CE3 CE2 CE1 CE0

EA[21:2]

BE3 BE2 BE1 BE0

HOLD

HOLDA

TOUT1

TINP1

32

20

Data

Memory Map Space Select

Word Address

Byte Enables

HOLD/

HOLDA

Timer 1

Asynchronous

Memory

Control

SBSRAM

Control

SDRAM Control

EMIF

(External Memory Interface)

Timer 0

ARE AOE AWE ARDY

SSADS SSOE SSWE SSCLK

SDA10 SDRAS SDCAS SDWE SDCLK

TOUT0 TINP0

CLKX1

FSX1

DX1

CLKR1

FSR1

DR1

CLKS1

Timers

McBSP1 McBSP0

Receive Receive

Transmit Transmit

Clock Clock

McBSPs

(Multichannel Buffered Serial Ports)

Figure 3. Peripheral Signals

CLKX0 FSX0 DX0

CLKR0 FSR0 DR0

CLKS0

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7

SMJ320C6701

†

I

External interru ts

ggg coding

g

• Encoding order follows the interru t service fetch acket ordering

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Signal Descriptions

SIGNAL

NAME NO.

CLKIN A14 I Clock Input CLKOUT1 Y6 O Clock output at full device speed CLKOUT2 V9 O Clock output at half of device speed CLKMODE1 B17 CLKMODE0 C17 PLLFREQ3 C13 PLL frequency range (3, 2, and 1) PLLFREQ2 G11 PLLFREQ1 F11

‡

PLLV

‡

PLLG PLLF C12 A

TMS K19 I JTAG test port mode select (features an internal pull-up) TDO R12 O/Z JTAG test port data out TDI R13 I JTAG test port data in (features an internal pull-up) TCK M20 I JTAG test port clock TRST N18 I JTAG test port reset (features an internal pull-down) EMU1 R20 I/O/Z Emulation pin 1, pull-up with a dedicated 20-kΩ resistor EMU0 T18 I/O/Z Emulation pin 0, pull-up with a dedicated 20-kΩ resistor

RESET J20 I Device reset NMI K21 I EXT_INT7 R16

EXT_INT6 P20 EXT_INT5 R15 EXT_INT4 R18 IACK R11 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 T19 INUM2 T20 INUM1 T14 INUM0 T16

LENDIAN G20 I

PD D19 O Power-down mode 2 or 3 (active if high)

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

‡

PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect those pins.

§

A = Analog Signal (PLL Filter)

D12 A G10 A

TYPE

I

O

CLOCK/PLL

Clock mode select

• Selects whether the output clock frequency = input clock freq x4 or x1

• The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.

§

PLL analog VCC connection for the low-pass filter

§

PLL analog GND connection for the low-pass filter

§

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

RESET AND INTERRUPTS

Nonmaskable interrupt

• Edge-driven (rising edge)

External interrupts

• Edge-driven (rising edge)

Active interrupt identification number

• Valid during IACK for all active interrupts (not just external)

• En

If high, selects little-endian byte/half-word addressing order within a word If low, selects big-endian addressing

order follows the interrupt service fetch packet orderin

LITTLE ENDIAN/BIG ENDIAN

POWER DOWN STATUS

DESCRIPTION

p

8

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†

I

Boot mode

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME NO.

HINT H2 O/Z Host interrupt (from DSP to host) HCNTL1 J6 I Host control – selects between control, address or data registers HCNTL0 H6 I Host control – selects between control, address or data registers HHWIL E4 I Host halfword select – first or second halfword (not necessarily high or low order) HBE1 G6 I Host byte select within word or half-word HBE0 F6 I Host byte select within word or half-word HR/W D4 I Host read or write select HD15 D11 HD14 B11 HD13 A11 HD12 G9 HD11 D10 HD10 A10 HD9 C10 HD8 B9 HD7 F9 HD6 C9 HD5 A9 HD4 B8 HD3 D9 HD2 D8 HD1 B7 HD0 C7 HAS L6 I Host address strobe HCS C5 I Host chip select HDS1 C4 I Host data strobe 1 HDS2 K6 I Host data strobe 2 HRDY H3 O Host ready (from DSP to host)

BOOTMODE4 B16 BOOTMODE3 G14 BOOTMODE2 F15 BOOTMODE1 C18 BOOTMODE0 D17

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TYPE

HOST PORT INTERFACE (HPI)

I/O/Z Host port data (used for transfer of data, address and control)

BOOT MODE

I Boot mode

DESCRIPTION

SMJ320C6701

SGUS030 – APRIL 2000

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SMJ320C6701

†

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Signal Descriptions (Continued)

SIGNAL

NAME NO.

CE3 Y5 O/Z CE2 V3 O/Z Memory space enables CE1 T6 O/Z • Enabled by bits 24 and 25 of the word address CE0 U2 O/Z • Only one asserted during any external data access BE3 R8 O/Z Byte enable control BE2 T3 O/Z • Decoded from the two lowest bits of the internal address BE1 T2 O/Z • Byte write enables for most types of memory BE0 R2 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM)

EA21 L4 EA20 L3 EA19 J2 EA18 J1 EA17 K1 EA16 K2 EA15 L2 EA14 L1 EA13 M1 EA12 M2 EA11 M6 EA10 N4 EA9 N1 EA8 N2 EA7 N6 EA6 P4 EA5 P3 EA4 P2 EA3 P1 EA2 P6

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TYPE

EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

EMIF – ADDRESS

O/Z External address (word address)

DESCRIPTION

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†

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME NO.

ED31 U18 ED30 U20 ED29 T15 ED28 V18 ED27 V17 ED26 V16 ED25 T12 ED24 W17 ED23 T13 ED22 Y17 ED21 T11 ED20 Y16 ED19 W15 ED18 V14 ED17 Y15 ED16 R9 ED15 Y14 ED14 V13 ED13 AA13 ED12 T10 ED11 Y13 ED10 W12 ED9 Y12 ED8 Y11 ED7 V10 ED6 AA10 ED5 Y10 ED4 W10 ED3 Y9 ED2 AA9 ED1 Y8 ED0 W9

ARE R7 O/Z Asynchronous memory read enable AOE T7 O/Z Asynchronous memory output enable AWE V5 O/Z Asynchronous memory write enable ARDY R4 I Asynchronous memory ready input

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TYPE

EMIF – DATA

I/O/Z External data

EMIF – ASYNCHRONOUS MEMORY CONTROL

SMJ320C6701

SGUS030 – APRIL 2000

DESCRIPTION

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11

SMJ320C6701

†

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Signal Descriptions (Continued)

SIGNAL

NAME NO.

SSADS V8 O/Z SBSRAM address strobe SSOE W7 O/Z SBSRAM output enable SSWE Y7 O/Z SBSRAM write enable SSCLK AA8 O/Z SBSRAM clock

SDA10 V7 O/Z SDRAM address 10 (separate for deactivate command) SDRAS V6 O/Z SDRAM row address strobe SDCAS W5 O/Z SDRAM column address strobe SDWE T8 O/Z SDRAM write enable SDCLK T9 O/Z SDRAM clock

HOLD R6 I Hold request from the host HOLDA B15 O Hold request acknowledge to the host

TOUT1 G2 O/Z Timer 1 or general-purpose output TINP1 K3 I Timer 1 or general-purpose input TOUT0 M18 O/Z T imer 0 or general-purpose output TINP0 J18 I Timer 0 or general-purpose input

DMAC3 E18 DMAC2 F19 DMAC1 E20 DMAC0 G16

CLKS1 F4 I External clock source (as opposed to internal) CLKR1 H4 I/O/Z Receive clock CLKX1 J4 I/O/Z Transmit clock DR1 E2 I Receive data DX1 G4 O/Z Transmit data FSR1 F3 I/O/Z Receive frame sync FSX1 F2 I/O/Z Transmit frame sync

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TYPE

EMIF – SYNCHRONOUS BURST SRAM CONTROL

EMIF – SYNCHRONOUS DRAM CONTROL

EMIF – BUS ARBITRATION

TIMERS

DMA ACTION COMPLETE

O DMA action complete

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

DESCRIPTION

12

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†

DV

DD

S

3.3 V su ly voltage

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME NO.

CLKS0 K18 I External clock source (as opposed to internal) CLKR0 L21 I/O/Z Receive clock CLKX0 K20 I/O/Z Transmit clock DR0 J21 I Receive data DX0 M21 O/Z Transmit data FSR0 P16 I/O/Z Receive frame sync FSX0 N16 I/O/Z Transmit frame sync

RSV0 N21 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV1 K16 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV2 B13 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV3 B14 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor RSV4 F13 I Reserved for testing, RSV5 C15 O Reserved (leave unconnected, RSV6 F7 I Reserved for testing, pull-up with a dedicated 20-k resistor RSV7 D7 I Reserved for testing, pull-up with a dedicated 20-k resistor RSV8 B5 I Reserved for testing, pull-up with a dedicated 20-k resistor RSV9 F16 O Reserved for testing,

C14

E19

H11 H13

DV

DD

K11 K13 K15

L10 L12 L14

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

C8

E3

H9 J10 J12 J14 J19

J3 J8

K7 K9

TYPE

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

S 3.3-V supply voltage

RESERVED FOR TEST

pull-down

with a dedicated 20-kΩ resistor

do not

pull-down

SUPPLY VOLTAGE PINS

with a dedicated 20-kΩ resistor

DESCRIPTION

connect to power or ground)

SMJ320C6701

SGUS030 – APRIL 2000

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13

SMJ320C6701

†

DV

DD

S

3.3 V su ly voltage

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Signal Descriptions (Continued)

SIGNAL

NAME NO.

M11 M13 M15

N10 N12 N14

DV

DD

CV

DD

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

N19

P11 P13

U19

W14

A12 A13 B10 B12

D15 D16 F10 F14

G13

A16

L8

M7 M9

N3 N8

P9

U3

W8

B6

F8

G7 G8

K4 M3 M4

A3

A5

A7

TYPE

SUPPLY VOLTAGE PINS (CONTINUED)

S 3.3-V supply voltage

S 1.9-V supply voltage

DESCRIPTION

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†

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME NO.

A18 AA4 AA6

AA15 AA17 AA19

B19

C20

D21

CV

DD

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

E10

E12

E14

E16

F17

F21

H17

K17

M17

P17

R21

B2 B4

C1 C3

D2

E1 E6 E8

F5

G1 H5

K5

M5

P5

TYPE

SUPPLY VOLTAGE PINS (CONTINUED)

S 1.9-V supply voltage

SMJ320C6701

SGUS030 – APRIL 2000

DESCRIPTION

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15

SMJ320C6701

†

CV

DD

S

1.9 V su ly voltage

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Signal Descriptions (Continued)

SIGNAL

NAME NO.

T17

U10 U12 U14 U16 U21

V20

W19 W21

Y18 Y20

CV

DD

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

AA11 AA12

F20 G18 H16 H18

N20 P18 P19 R10 R14

V11 V12 V15

W13

TYPE

SUPPLY VOLTAGE PINS (CONTINUED)

T1 T5

U6 U8

V1

W2

Y3

S 1.9-V supply voltage

L18 L19 L20

U4

DESCRIPTION

16

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

†

V

SS

GND

Ground ins

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME NO.

C11

C16

H10

H12

H14

V

SS

A15

A17

A19 AA3 AA5 AA7

AA14 AA16 AA18

B18

B20

C19

C21

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

C6 D5 G3

H7

H8 J11 J13

J7 J9 K8 L7

L9 M8 N7 R3

A4

A6

A8

B3

C2

D1

TYPE

GROUND PINS

GND Ground pins

SMJ320C6701

SGUS030 – APRIL 2000

DESCRIPTION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

17

SMJ320C6701

†

V

SS

GND

Ground ins

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Signal Descriptions (Continued)

SIGNAL

NAME NO.

D20

E11 E13 E15 E17 E21

G17 G21

V

SS

N17 P21

R17 T21

U11 U13 U15 U17

V21

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

E5 E7 E9

F1 G5

H1

J5

J17

L5

L17

N5

R1 R5

U1 U5 U7 U9

V2

TYPE

GROUND PINS (CONTINUED)

GND Ground pins

DESCRIPTION

18

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

†

V

SS

GND

Ground ins

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

Signal Descriptions (Continued)

SIGNAL

NAME NO.

W20

Y19 F18

G19

H15

K10 K12 K14

L13 L15

V

SS

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

M10 M12 M14

N11 N13 N15

P10 P12 P14 P15

R19

W11 W16

TYPE

GROUND PINS (CONTINUED)

W1 W3

Y2

Y4

J15 J16

L11

GND Ground pins

N9

P7

P8

T4

W6

SMJ320C6701

SGUS030 – APRIL 2000

DESCRIPTION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

19

SMJ320C6701

†

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Signal Descriptions (Continued)

SIGNAL

NAME NO.

D13 D14 D18

F12 G12 G15

NC

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

H19 H20 H21

M16 M19

V19

W18

D3 D6

L16

V4

W4

TYPE

REMAINING UNCONNECTED PINS

Unconnected pins

p

DESCRIPTION

20

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SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

development support

T exas Instruments (TI) offers an extensive line of development tools for the ’C6x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of ’C6x-based applications:

Software-Development Tools:

Assembly optimizer Assembler/Linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler

Hardware-Development T ools:

Extended development system (XDS) emulator (supports ’C6x multiprocessor system debug) EVM (Evaluation Module)

The

TMS320 DSP Development Support Reference Guide

development-support products for all TMS320 family member devices, including documentation. See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional document, the

TMS320 Third-Party Support Reference Guide

information about TMS320-related products from other companies in the industry . T o receive TMS320 literature, contact the Literature Response Center at 800/477-8924.

(SPRU011) contains information about

(SPRU052), contains

See Table 2 for a complete listing of development-support tools for the ’C6x. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

Table 2. SMJ320C6x Development-Support Tools

DEVELOPMENT TOOL PLATFORM PART NUMBER

Software

Ada 95 Compiler C Compiler/Assembler/Linker/Assembly Optimizer Win32 TMDX3246855-07

C Compiler/Assembler/Linker/Assembly Optimizer SPARCSolaris TMDX3246555-07 Simulator Win32 TMDS3246851-07 Simulator SPARCSolaris TMDS3246551-07 XDS510 Debugger/Emulation Software Win32, Windows NT TMDX324016X-07

XDS510 Emulator XDS510WS Emulator

EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201 EVM Evaluation Kit (including TMDX3246855–07) PC/Win95/Windows NT TMDX326006201

†

Contact IRVINE Compiler Corporation (949) 250-1366 to order.

‡

NT support estimated availability 1Q00.

§

Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.

¶

Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.

†

§ ¶

Sun Solaris 2.3

Hardware

PC TMDS00510

SCSI TMDS00510WS

Software/Hardware

‡

AD0345AS8500RF - Single User AD0345BS8500RF - Multi-user

XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Win32 and Windows NT are trademarks of Microsoft Corporation. SPARC is a trademark of SPARC International, Inc. Solaris is a trademark of Sun Microsystems, Inc.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

21

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

device and development-support tool nomenclature

T o designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all SMJ320 devices and support tools. Each SMJ320 member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (SMX / TMDX) through fully qualified production devices/tools (SMJ/TMDS).

Device development evolutionary flow: SMX Experimental device that is not necessarily representative of the final device’s electrical

specifications

SM Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification

SMJ Fully qualified production device processed to MIL-PRF-38535

Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS Fully qualified development-support product SMX devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” SMJ devices and TMDS development-support tools have been characterized fully , and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production

devices. T exas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLP), the temperature range, and the device speed range in megahertz (for example, 16 is 167 MHz). Figure 4 provides a legend for reading the complete device name for any SMJ320 family member.

22

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FLOATING-POINT DIGITAL SIGNAL PROCESSOR

device and development-support tool nomenclature (continued)

SMJ 320 C 6701 GLP 14

PREFIX DEVICE SPEED RANGE

SMX= Experimental device SMJ = MIL-PRF-38535, QML SM = Commercial

processing

W

14 = 140 MHz 16 = 167 MHz

SMJ320C6701

SGUS030 – APRIL 2000

DEVICE FAMILY

320 = SMJ320 family

TECHNOLOGY

C = CMOS

†

BGA = Ball Grid Array

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

S = –40°C to 90°C, extended temperature W = –55°C to 115°C, extended temperature

PACKAGE TYPE

GLP = 429-pin ceramic BGA

DEVICE

’6x DSP:

6201B 6203 6701

†

Figure 4. SMJ320 Device Nomenclature (Including SMJ320C6701)

documentation support

Extensive documentation supports all SMJ320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the ’C6x devices:

The

TMS320C6000 CPU and Instruction Set Reference Guide

’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.

(literature number SPRU189) describes the

The

TMS320C6000 Peripherals Reference Guide

(literature number SPRU190) describes the functionality of the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories.

The

TMS320C6000 Programmer’s Guide

(literature number SPRU198) describes ways to optimize C and

assembly code for ’C6x devices and includes application program examples. The

TMS320C6x C Source Debugger User’s Guide

(literature number SPRU188) describes how to invoke the ’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.

The

TMS320C6x Peripheral Support Library Programmer’s Reference

(literature number SPRU273) describes the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically , provides a complete description of each, and gives code examples to show how they are used.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

documentation support (continued)

TMS320C6000 Assembly Language T ools User’s Guide

(literature number SPRU186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of devices.

The

TMS320C6x Evaluation Module Reference Guide

(literature number SPRU269) provides instructions for installing and operating the ’C6x evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material.

TMS320C6000 DSP/BIOS User’s Guide

(literature number SPRU303) describes how to use DSP/BIOS tools

and APIs to analyze embedded real-time DSP applications.

Code Composer User’s Guide

(literature number SPRU296) explains how to use the Code Composer

development environment to build and debug embedded real-time DSP applications.

Code Composer Studio T utorial

(literature number SPRU301) introduces the Code Composer Studio integrated

development environment and software tools. The

TMS320C6000 Technical Brief

(literature number SPRU197) gives an introduction to the ’C62x/C67x

devices, associated development tools, and third-party support. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and

education. The TMS320 newsletter,

Details on Signal Processing

, is published quarterly and distributed to update SMJ320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to information pertaining to the SMJ320 family , including documentation, source code, and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

clock PLL

All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3, Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.

To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the electricals section.

Table 3. CLKOUT1 Frequency Ranges

PLLFREQ3

(A9)

0 0 0 50–140 0 0 1 65–167 0 1 0 130–167

†

Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency . For example, for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.

PLLFREQ2

(D11)

PLLFREQ1

(B10)

CLKOUT1 Frequency Range

†

(MHz)

input and output clocks

24

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clock PLL (continued)

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

Table 4. ’C6701 PLL Component Selection Table

CPU CLOCK

FREQUENCY

(CLKOUT1)

RANGE (MHz)

CLKOUT2

RANGE

(MHz)

R1

(Ω)

C1

(nF)

C2

(pF)

TYPICAL

LOCK TIME

‡

(µs)

CLKMODE

CLKIN

RANGE

(MHz)

x4 12.5–41.7 50–167 25–83.5 60.4 27 560 75

‡

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

PLLFREQ3

3.3V

CLKMODE0 CLKMODE1

C3

EMI Filter

10 F

Available Multiply Factors

CLKMODE1 CLKMODE0

0 0 x1(BYPASS) 1 x f(CLKIN) 0 1 Reserved Reserved 1 0 Reserved Reserved 1 1 x4 4 x f(CLKIN)

C4

0.1 F

PLL Multiply

Factors

PLLV

CLKIN

CPU Clock

Frequency

f(CPUCLOCK)

PLLMULT

CLKIN

LOOP FILTER

PLLF

C1

C2

PLLFREQ2 PLLFREQ1

PLL

PLLCLK

1 0

PLLG

R1

(see Table 3)

Internal to ’C6701

CPU CLOCK

NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,

place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the ’C6000 device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,

and the EMI Filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

clock PLL (continued)

3.3V PLLV

CLKMODE0 CLKMODE1

CLKIN

PLLMULT

PLLCLK

CLKIN

LOOP FILTER

PLL

PLLFREQ3 PLLFREQ2 PLLFREQ1

Internal to ’C6701

1 0

(see Table 3)

CPU CLOCK

PLLF

NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.

B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

PLLG

Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only

power-supply sequencing

The 1.9-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be powered up first, or at the same time as the I/O buffers supply . This is to ensure that the I/O buf fers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board.

26

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

absolute maximum ratings over operating case temperature range (unless otherwise noted)

†

Supply voltage range, CVDD (see Note 1) –0.3 V to 2.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, DV

(see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

Input voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating case temperature range, TC S suffix device –40C to 90C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

W suffix device –55C to 115C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

stg

SS

.

–55C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

CV DV V V V I

OH

I

OL

T

SS IH IL

C

Supply voltage 1.81 1.9 1.99 V

DD

Supply voltage 3.14 3.30 3.46 V

DD

Supply ground 0 0 0 V High-level input voltage 2.0 V Low-level input voltage 0.8 V High-level output current –12 mA Low-level output current 12 mA

Case temperature

p

S suffix device –40 90 W suffix device –55 115



C

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

27

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

I

OZ

I

DD2V

I

DD2V

I

DD3V

C

i

C

o

* This parameter is not tested. †

TMS and TDI are not included due to internal pullups. TRST

‡

Measured with average CPU activity: 50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle 50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle

§

Measured with average peripheral activity: 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM 50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs

¶

Measured with average I/O activity (30-pF load, SDCLK on): 25% of time: Reads from external SDRAM 25% of time: Writes to external SDRAM 50% of time: No activity

High-level output voltage DV Low-level output voltage DV Input current Off-state output current V

Supply current, CPU + CPU memory access

Supply current, peripherals

Supply current, I/O pins Input capacitance *15 pF

Output capacitance *15 pF

is not included due to internal pulldown.

†

‡

§

¶

= MIN, I

DD

= MIN, I

DD

V

= V

to DV

I

SS

= DV

O

CV

= NOM,

DD

CPU clock = 150 MHz CV

= NOM,

DD

CPU clock = 150 MHz DV

= NOM,

DD

CPU clock = 150 MHz

DD

or 0 V ±10 uA

DD

= MAX 2.4 V

OH

= MAX 0.6 V

OL

±10 uA

470 mA

250 mA

85 mA

28

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SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

PARAMETER MEASUREMENT INFORMATION

I

OL

Tester Pin

Electronics

SGUS030 – APRIL 2000

Output Under Test

†

Typical distributed load circuit capacitance.

V

ref

I

OH

50 Ω

CT = 30 pF

†

signal-transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

V

ref

Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements

= 1.5 V

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

29

SMJ320C6701

NO.

UNIT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

INPUT AND OUTPUT CLOCKS

timing requirements for CLKIN

NO.

1 t

c(CLKIN)

2 t

w(CLKINH)

3 t

w(CLKINL)

4 t † *This parameter is not tested.

t(CLKIN)

The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.

CLKIN

Cycle time, CLKIN 28.4 7.1 24 6 ns Pulse duration,

CLKIN high Pulse duration,

CLKIN low Transition time, CLKIN *5 *0.6 *5 *0.6 ns

†

(see Figure 8)

’C6701-14 ’C6701-16

CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1

MIN MAX MIN MAX MIN MAX MIN MAX

*10.9 *3 *9.8 *2.7 ns

1

2

3

4

Figure 8. CLKIN Timings

‡§

switching characteristics for CLKOUT1

NO. PARAMETER

1 t

c(CKO1)

2 t

w(CKO1H)

3 t

w(CKO1L)

4 t ‡

§ *This parameter is not tested.

t(CKO1)

P = 1/CPU clock frequency in nanoseconds (ns). PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

Cycle time, CLKOUT1 *P – 0.7 *P + 0.7 *P – 0.7 *P + 0.7 ns Pulse duration, CLKOUT1 high *(P/2) – 0.5 *(P/2) + 0.5 *PH – 0.5 *PH + 0.5 ns Pulse duration, CLKOUT1 low *(P/2) – 0.5 *(P/2) + 0.5 *PL – 0.5 *PL + 0.5 ns Transition time, CLKOUT1 *0.6 *0.6 ns

(see Figure 9)

’C6701-14 ’C6701-16

CLKMODE = x4 CLKMODE = x1

MIN MAX MIN MAX

UNIT

4

UNIT

CLKOUT1

30

1

2

3

Figure 9. CLKOUT1 Timings

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

4

NO

PARAMETER

UNIT

NO

PARAMETER

UNIT

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

INPUT AND OUTPUT CLOCKS (CONTINUED)

switching characteristics for CLKOUT2

NO. PARAMETER

.

1 t

c(CKO2)

2 t

w(CKO2H)

3 t

w(CKO2L)

4 t † *This parameter is not tested.

CLKOUT2

t(CKO2)

P = 1/CPU clock frequency in ns.

Cycle time, CLKOUT2 *2P – 0.7 *2P + 0.7 ns Pulse duration, CLKOUT2 high *P – 0.7 *P + 0.7 ns Pulse duration, CLKOUT2 low *P – 0.7 *P + 0.7 ns Transition time, CLKOUT2 *0.6 ns

†

(see Figure 10)

2

Figure 10. CLKOUT2 Timings

SDCLK, SSCLK timing parameters

SDCLK timing parameters are the same as CLKOUT2 parameters.

’C6701-14 ’C6701-16

MIN MAX

1

3

4

UNIT

SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration.

switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 11)

’C6701-14

.

NO. PARAMETER

1 t

d(CKO1-SSCLK)

2 t

d(CKO1-SSCLK1/2)

3 t

d(CKO1-CKO2)

4 t

d(CKO1-SDCLK)

SSCLK (1/2rate)

CLKOUT1

SSCLK

CLKOUT2

SDCLK

Delay time, CLKOUT1 edge to SSCLK edge –0.8 3.4 ns Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) –1.0 3.0 ns Delay time, CLKOUT1 edge to CLKOUT2 edge –1.5 2.5 ns

Delay time, CLKOUT1 edge to SDCLK edge –1.5 1.9 ns

1

2

3

4

’C6701-16 MIN MAX

UNIT

Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

31

SMJ320C6701

NO

UNIT

NO

PARAMETER

UNIT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles

NO.

.

6 t

su(EDV-CKO1H)

7 t

h(CKO1H-EDV)

10 t

su(ARDY-CKO1H)

11 t

†

h(CKO1H-ARDY)

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

Setup time, read EDx valid before CLKOUT1 high 4.5 ns Hold time, read EDx valid after CLKOUT1 high 1.5 ns Setup time, ARDY valid before CLKOUT1 high 3.5 ns Hold time, ARDY valid after CLKOUT1 high 1.5 ns

†

(see Figure 12 and Figure 13)

’C6701-14 ’C6701-16

MIN MAX

UNIT

switching characteristics for asynchronous memory cycles‡ (see Figure 12 and Figure 13)

’C6701-14

.

NO. PARAMETER

1 t

d(CKO1H-CEV)

2 t

d(CKO1H-BEV)

3 t

d(CKO1H-BEIV)

4 t

d(CKO1H-EAV)

5 t

d(CKO1H-EAIV)

8 t

d(CKO1H-AOEV)

9 t

d(CKO1H-AREV)

12 t

d(CKO1H-EDV)

13 t

d(CKO1H-EDIV)

14 t

‡

d(CKO1H-AWEV)

The minimum delay is also the minimum output hold after CLKOUT1 high.

Delay time, CLKOUT1 high to CEx valid –1.0 4.5 ns Delay time, CLKOUT1 high to BEx valid 4.5 ns Delay time, CLKOUT1 high to BEx invalid –1.0 ns Delay time, CLKOUT1 high to EAx valid 4.5 ns Delay time, CLKOUT1 high to EAx invalid –1.0 ns Delay time, CLKOUT1 high to AOE valid –1.0 4.5 ns Delay time, CLKOUT1 high to ARE valid –1.0 4.5 ns Delay time, CLKOUT1 high to EDx valid 4.5 ns Delay time, CLKOUT1 high to EDx invalid –1.0 ns Delay time, CLKOUT1 high to AWE valid –1.0 4.5 ns

’C6701-16 MIN MAX

UNIT

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

CLKOUT1

CEx

BE[3:0]

EA[21:2]

ED[31:0]

AOE

ARE

AWE

ARDY

Setup = 2 Strobe = 5

10

1111

10

Figure 12. Asynchronous Memory Read Timing

Not ready = 2

6

HOLD = 1

11

32

54

7

88

99

CLKOUT1

CEx

BE[3:0]

EA[21:2]

ED[31:0]

AOE

ARE

AWE

ARDY

Setup = 2 Strobe = 5

12

Figure 13. Asynchronous Memory Write Timing

10

Not ready = 2

11

10

11

HOLD = 1

11

32

54

13

1414

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

33

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 14)

NO.

7 t

su(EDV-SSCLKH)

8 t

h(SSCLKH-EDV)

Setup time, read EDx valid before SSCLK high 2.0 2.0 ns Hold time, read EDx valid after SSCLK high 2.1 2.1 ns

’C6701-14 ’C6701-16 MIN MAX MIN MAX

UNIT

switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 14 and Figure 15)

NO. PARAMETER

1 t

osu(CEV-SSCLKH)

2 t

oh(SSCLKH-CEV)

3 t

osu(BEV-SSCLKH)

4 t

oh(SSCLKH-BEIV)

5 t

osu(EAV-SSCLKH)

6 t

oh(SSCLKH-EAIV)

9 t

osu(ADSV-SSCLKH)

10 t

oh(SSCLKH-ADSV)

11 t

osu(OEV-SSCLKH)

12 t

oh(SSCLKH-OEV)

13 t

osu(EDV-SSCLKH)

14 t

oh(SSCLKH-EDIV)

15 t

osu(WEV-SSCLKH)

16 t

†

oh(SSCLKH-WEV)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times.

Output setup time, CEx valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns Output hold time, CEx valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns Output setup time, BEx valid before SSCLK high 0.5P – 1.6 0.5P – 1.6 ns Output hold time, BEx invalid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns Output setup time, EAx valid before SSCLK high 0.5P – 1.7 0.5P – 1.7 ns Output hold time, EAx invalid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns Output setup time, SSADS valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns Output hold time, SSADS valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns Output setup time, SSOE valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns Output hold time, SSOE valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns Output setup time, EDx valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns Output hold time, EDx invalid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns Output setup time, SSWE valid before SSCLK high 0.5P – 1.5 0.5P – 1.3 ns

Output hold time, SSWE valid after SSCLK high 0.5P – 2.5 0.5P – 2.3 ns

’C6701-14 ’C6701-16

MIN MAX MIN MAX

UNIT

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SSCLK

CEx

BE[3:0]

EA[21:2]

ED[31:0]

SSADS

SSOE

SGUS030 – APRIL 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

21

43

BE1 BE2 BE3 BE4

65

A1 A2 A3 A4

8

7

Q1 Q2 Q3 Q4

109

1211

SSWE

SSCLK

CEx

BE[3:0]

EA[21:2]

ED[31:0]

SSADS

SSOE

SSWE

Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)

21

43

BE1 BE2 BE3 BE4

65

A1 A2 A3 A4

13

14

D1 D2 D3 D4

109

1615

Figure 15. SBSRAM Write Timing (Full-Rate SSCLK)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

35

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16)

NO.

7 t

su(EDV-SSCLKH)

8 t

h(SSCLKH-EDV)

Setup time, read EDx valid before SSCLK high 3.8 3.6 ns Hold time, read EDx valid after SSCLK high 2 1.5 ns

’C6701-14 ’C6701-16 MIN MAX MIN MAX

switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 16 and Figure 17)

NO. PARAMETER

1 t

osu(CEV-SSCLKH)

2 t

oh(SSCLKH-CEV)

3 t

osu(BEV-SSCLKH)

4 t

oh(SSCLKH-BEIV)

5 t

osu(EAV-SSCLKH)

6 t

oh(SSCLKH-EAIV)

9 t

osu(ADSV-SSCLKH)

10 t

oh(SSCLKH-ADSV)

11 t

osu(OEV-SSCLKH)

12 t

oh(SSCLKH-OEV)

13 t

osu(EDV-SSCLKH)

14 t

oh(SSCLKH-EDIV)

15 t

osu(WEV-SSCLKH)

16 t

†

oh(SSCLKH-WEV)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

Output setup time, CEx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, CEx valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns Output setup time, BEx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, BEx invalid after SSCLK high 0.5P – 2.3 0.5P – 2 ns Output setup time, EAx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, EAx invalid after SSCLK high 0.5P – 2.3 0.5P – 2 ns Output setup time, SSADS valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, SSADS valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns Output setup time, SSOE valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, SSOE valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns Output setup time, EDx valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns Output hold time, EDx invalid after SSCLK high 0.5P – 2.3 0.5P – 2 ns Output setup time, SSWE valid before SSCLK high 1.5P – 5.5 1.5P – 4.5 ns

Output hold time, SSWE valid after SSCLK high 0.5P – 2.3 0.5P – 2 ns

’C6701-14 ’C6701-16

MIN MAX MIN MAX

UNIT

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SSCLK

CEx

BE[3:0]

EA[21:2]

ED[31:0]

SSADS

SSOE

SDWE

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

43

BE1 BE2 BE3 BE4

65

A1 A2 A3 A4

7

8

Q1 Q2 Q3 Q4

109

SGUS030 – APRIL 2000

21

1211

SSCLK

CEx

BE[3:0]

EA[21:2]

ED[31:0]

SSADS

SSOE

SSWE

Figure 16. SBSRAM Read Timing (1/2 Rate SSCLK)

21

43

BE1 BE2 BE3 BE4

65

A1 A2 A3 A4

1413

Q1 Q2 Q3 Q4

109

1615

Figure 17. SBSRAM Write Timing (1/2 Rate SSCLK)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

37

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 18)

NO.

7 t

su(EDV-SDCLKH)

8 t

h(SDCLKH-EDV)

Setup time, read EDx valid before SDCLK high 1.8 1.8 ns Hold time, read EDx valid after SDCLK high 3 3 ns

switching characteristics for synchronous DRAM cycles† (see Figure 18–Figure 23)

NO. PARAMETER

1 t

osu(CEV-SDCLKH)

2 t

oh(SDCLKH-CEV)

3 t

osu(BEV-SDCLKH)

4 t

oh(SDCLKH-BEIV)

5 t

osu(EAV-SDCLKH)

6 t

oh(SDCLKH-EAIV)

9 t

osu(SDCAS-SDCLKH)

10 t

oh(SDCLKH-SDCAS)

11 t

osu(EDV-SDCLKH)

12 t

oh(SDCLKH-EDIV)

13 t

osu(SDWE-SDCLKH)

14 t

oh(SDCLKH-SDWE)

15 t

osu(SDA10V-SDCLKH)

16 t

oh(SDCLKH-SDA10IV)

17 t

osu(SDRAS-SDCLKH)

18 t

†

oh(SDCLKH-SDRAS)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

Output setup time, CEx valid before SDCLK high 1.5P – 5 1.5P – 4 ns Output hold time, CEx valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, BEx valid before SDCLK high 1.5P – 5 1.5P – 4 ns Output hold time, BEx invalid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, EAx valid before SDCLK high 1.5P – 5 1.5P – 4 ns Output hold time, EAx invalid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, SDCAS valid before SDCLK

high Output hold time, SDCAS valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, EDx valid before SDCLK high 1.5P – 5 1.5P – 4 ns Output hold time, EDx invalid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, SDWE valid before SDCLK

high Output hold time, SDWE valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns Output setup time, SDA10 valid before SDCLK

high Output hold time, SDA10 invalid after SDCLK

high Output setup time, SDRAS valid before SDCLK

high Output hold time, SDRAS valid after SDCLK high 0.5P – 1.9 0.5P – 1.5 ns

1.5P – 5 1.5P – 4 ns

0.5P – 1.9 0.5P – 1.5 ns

1.5P – 5 1.5P – 4 ns

’C6701-14 ’C6701-16 MIN MAX MIN MAX

’C6701-14 ’C6701-16

MIN MAX MIN MAX

UNIT

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

SDCLK

CEx

BE[3:0]

EA[15:2]

ED[31:0]

SDA10

SDRAS

SDCAS

SDWE

SDCLK

CEx

BE[3:0]

EA[15:2]

ED[31:0]

SDA10

READ

5

CA1 CA2 CA3

6

READ

3

BE1 BE2 BE3

4

READ

21

7

8

D1 D2 D3

1615

109

Figure 18. Three SDRAM Read Commands

WRITE

1

3

BE1 BE2 BE3

5

CA1 CA2 CA3

11

D1 D2 D3

4

6

12

WRITE

2

1615

SDRAS

SDCAS

SDWE

Figure 19. Three SDRAM Write Commands

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

109

1413

39

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

SDCLK

CEx

BE[3:0]

EA[15:2] ED[31:0]

SDA10

SDRAS

SDCAS

Bank Activate/Row Address

15

17

ACTV

1

5

2

Row Address

18

SDWE

SDCLK

CEx

BE[3:0] EA[15:2] ED[31:0]

SDA10

SDRAS

SDCAS

SDWE

Figure 20. SDRAM ACTV Command

DCAB

1

15

17

13

Figure 21. SDRAM DCAB Command

2

16

18

14

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SDCLK

CEx

BE[3:0]

EA[15:2] ED[31:0]

SYNCHRONOUS DRAM TIMING (CONTINUED)

REFR

1

2

SGUS030 – APRIL 2000

SDA10

SDRAS

SDCAS

SDWE

SDCLK

CEx

BE[3:0]

EA[15:2] ED[31:0]

SDA10

SDRAS

SDCAS

SDWE

17

9

Figure 22. SDRAM REFR Command

MRS

1

5

MRS Value

17

9

13

18

10

2

6

18

10

14

Figure 23. SDRAM MRS Command

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

41

SMJ320C6701

NO

UNIT

NO

PARAMETER

UNIT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

HOLD/HOLDA TIMING

timing requirements for the hold/hold acknowledge cycles

NO.

.

1 t

su(HOLDH-CKO1H)

2 t

†

h(CKO1H-HOLDL)

HOLD

is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.

Thus, HOLD

can be an asynchronous input.

Setup time, HOLD high before CLKOUT1 high 5 ns Hold time, HOLD low after CLKOUT1 high 2 ns

†

(see Figure 24)

’C6701-14 ’C6701-16

MIN MAX

UNIT

switching characteristics for the hold/hold acknowledge cycles‡ (see Figure 24)

’C6701-14

.

NO. PARAMETER

3 t

R(HOLDL-EMHZ)

4 t

R(EMHZ-HOLDAL)

5 t

R(HOLDH-HOLDAH)

6 t

d(CKO1H-HOLDAL)

7 t

d(CKO1H-BHZ)

8 t

d(CKO1H-BLZ)

9 t

‡

§

¶ *This parameter is not tested.

R(HOLDH-BLZ)

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. All pending EMIF transactions are allowed to complete before HOLDA with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. EMIF Bus consists of CE[3:0]

Response time, HOLD low to EMIF high impedance 4P Response time, EMIF high impedance to HOLDA low 2P ns Response time, HOLD high to HOLDA high 4P 7P ns Delay time, CLKOUT1 high to HOLDA valid 1 8 ns Delay time, CLKOUT1 high to EMIF Bus high impedance Delay time, CLKOUT1 high to EMIF Bus low impedance Response time, HOLD high to EMIF Bus low impedance

is asserted. The worst cases for this is an asynchronous read or write

, BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.

¶

’C6701-16 MIN MAX

§

*1 *8 ns *1 *12 ns

3P 6P ns

UNIT

ns

DSP Owns Bus External Requester DSP Owns Bus

3

CLKOUT1

2

1

HOLD

HOLDA

EMIF Bus

†

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.

†

’C6701 Ext Req ’C6701

7

4

6

9

2

1

5

6

8

Figure 24. HOLD/HOLDA Timing

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NO

UNIT

1

t

w(RESET)

NO

PARAMETER

UNIT

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

RESET TIMING

timing requirements for reset (see Figure 25)

’C6701-14

NO.

.

1 t

†

This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.

*This parameter is not tested. ‡

This parameter only applies to CLKMODE x4. The RESET need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET to ensure proper device operation. See the

Width of the RESET pulse (PLL stable) Width of the RESET pulse (PLL needs to sync up)

signal is not connected internally to the clock PLL circuit. The PLL, however, may

clock PLL

section for PLL lock times.

†

‡

switching characteristics during reset§ (see Figure 25)

.

NO. PARAMETER

2 t

R(RESET)

3 t

d(CKO1H-CKO2IV)

4 t

d(CKO1H-CKO2V)

5 t

d(CKO1H-SDCLKIV)

6 t

d(CKO1H-SDCLKV)

7 t

d(CKO1H-SSCKIV)

8 t

d(CKO1H-SSCKV)

9 t

d(CKO1H-LOWIV)

10 t

d(CKO1H-LOWV)

11 t

d(CKO1H-HIGHIV)

12 t

d(CKO1H-HIGHV)

13 t

d(CKO1H-ZHZ)

14 t

d(CKO1H-ZV)

§

Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HRDY Z group consists of: EA[21:2], ED[31:0], CE[3:0]

*This parameter is not tested.

Response time to change of value in RESET signal *1 Delay time, CLKOUT1 high to CLKOUT2 invalid *–1 ns

Delay time, CLKOUT1 high to CLKOUT2 valid *10 ns Delay time, CLKOUT1 high to SDCLK invalid *–1 ns Delay time, CLKOUT1 high to SDCLK valid *10 ns Delay time, CLKOUT1 high to SSCLK invalid *–1 ns Delay time, CLKOUT1 high to SSCLK valid *10 ns Delay time, CLKOUT1 high to low group invalid *–1 ns Delay time, CLKOUT1 high to low group valid *10 ns Delay time, CLKOUT1 high to high group invalid *–1 ns Delay time, CLKOUT1 high to high group valid *10 ns Delay time, CLKOUT1 high to Z group high impedance *–1 ns Delay time, CLKOUT1 high to Z group valid *10 ns

and HINT.

, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.

SDWE

, BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,

’C6701-16 MIN MAX

*10

*250 µs

’C6701-14 ’C6701-16

MIN MAX

UNIT

CLKOUT1

cycles

must be asserted

UNIT

CLKOUT1

cycles

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

43

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

RESET TIMING (CONTINUED)

CLKOUT1

1

RESET

CLKOUT2

SDCLK

SSCLK

LOW GROUP

HIGH GROUP

Z GROUP

†

Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. High group consists of: HRDY Z group consists of: EA[21:2], ED[31:0], CE[3:0]

†

and HINT.

SDWE

, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.

, BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,

22

43

65

87

109

1211

1413

Figure 25. Reset Timing

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NO

UNIT

NO

PARAMETER

UNIT

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

EXTERNAL INTERRUPT/RESET TIMING

timing requirements for interrupt response cycles

NO.

.

2 t

w(ILOW)

3 t

†

‡ *This parameter is not tested.

w(IHIGH) Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

Width of the interrupt pulse low *2P ns Width of the interrupt pulse high *2P ns

†‡

(see Figure 26)

’C6701-14 ’C6701-16

MIN MAX

UNIT

switching characteristics during interrupt response cycles§ (see Figure 26)

’C6701-14

NO. PARAMETER

.

1 t

R(EINTH-IACKH)

4 t

d(CKO2L-IACKV)

5 t

d(CKO2L-INUMV)

6 t

§

d(CKO2L-INUMIV) P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.

Response time, EXT_INTx high to IACK high 9P ns Delay time, CLKOUT2 low to IACK valid –0.5P 13 – 0.5P ns Delay time, CLKOUT2 low to INUMx valid 10 – 0.5P ns

Delay time, CLKOUT2 low to INUMx invalid –0.5P ns

1

’C6701-16

MIN MAX

UNIT

CLKOUT2

EXT_INTx, NMI

Intr Flag

IACK

INUMx

2

3

4

5

Interrupt Number

4

6

Figure 26. Interrupt Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

45

SMJ320C6701

NO

UNIT

NO

PARAMETER

UNIT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

HOST-PORT INTERFACE TIMING

timing requirements for host-port interface cycles

†‡

(see Figure 27, Figure 28, Figure 29, and

Figure 30)

’C6701-14

.

NO.

1 t

su(SEL-HSTBL)

2 t

h(HSTBL-SEL)

3 t

w(HSTBL)

4 t

w(HSTBH)

10 t

su(SEL-HASL)

11 t

h(HASL-SEL)

12 t

su(HDV-HSTBH)

13 t

h(HSTBH-HDV)

14 t

h(HRDYL-HSTBL)

18 t

su(HASL-HSTBL)

19 t

h(HSTBL-HASL)

*This parameter is not tested. †

HSTROBE

‡

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

§

Select signals include: HCNTRL[1:0], HR/W

refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Setup time, select signals§ valid before HSTROBE low 4 ns Hold time, select signals§ valid after HSTROBE low 2 ns Pulse duration, HSTROBE low *2P ns Pulse duration, HSTROBE high between consecutive accesses *2P ns Setup time, select signals§ valid before HAS low 4 ns Hold time, select signals§ valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 3 ns Hold time, host data valid after HSTROBE high 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be

inactivated until HRDY complete properly.

Setup time, HAS low before HSTROBE low *2 ns Hold time, HAS low after HSTROBE low *2 ns

, and HHWIL.

is active (low); otherwise, HPI writes will not

’C6701-16

MIN MAX

*1 ns

UNIT

switching characteristics during host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30)

’C6701-14

NO. PARAMETER

.

5 t

d(HCS-HRDY)

6 t

d(HSTBL-HRDYH)

7 t

oh(HSTBL-HDLZ)

8 t

d(HDV-HRDYL)

9 t

oh(HSTBH-HDV)

15 t

d(HSTBH-HDHZ)

16 t

d(HSTBL-HDV)

17 t

d(HSTBH-HRDYH)

*This parameter is not tested. †

HSTROBE

‡

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

¶

HCS completing a previous HPID write or READ with autoincrement.

#

This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE request to the DMA auxiliary channel, and HRDY

||

This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY

refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy

Delay time, HCS to HRDY Delay time, HSTROBE low to HRDY high

Output hold time, HD low impedance after HSTROBE low for an HPI read *4 ns Delay time, HD valid to HRDY low *P – 3 *P + 3 ns Output hold time, HD valid after HSTROBE high 3 12 ns Delay time, HSTROBE high to HD high impedance *3 *12 ns Delay time, HSTROBE low to HD valid 3 12 ns Delay time, HSTROBE high to HRDY high

remains high until the DMA auxiliary channel loads the requested data into HPID.

¶

#

||

remains low if the access is not an HPID write

signal.

’C6701-16 MIN MAX

1 12 ns 1 12 ns

3 12 ns

, the HPI sends the

UNIT

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HR/W

HHWIL

HSTROBE

HD[15:0] (output)

HRDY (case 1)

HRDY

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

†

HCS

(case 2)

1

2

3

15

97

1st half-word 2nd half-word

85

86

1

4

2

Figure 27. HPI Read Timing (HAS Not Used, Tied High)

15

17

916

5

†

HSTROBE

HAS

10

HCNTL[1:0]

10

HR/W

10

HHWIL

HSTROBE

HD[15:0] (output)

HRDY (case 1)

HRDY

refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

†

HCS

(case 2)

19

1011

11

3

18

97

1st half-word 2nd half-word

10

4

15

19

11

18

Figure 28. HPI Read Timing (HAS Used)

916

15

51785

51786

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

47

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HBE[1:0]

HR/W

HHWIL

HSTROBE

HD[15:0] (input)

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

†

HCS

HRDY

1

2

12

1

5

2

3

14

12

1st half-word 2nd half-word

13

1

4

13

2

12

2

12

Figure 29. HPI Write Timing (HAS Not Used, Tied High)

17

13

5

†

HSTROBE

HAS

19

HBE[1:0]

10

HCNTL[1:0]

10

HR/W

10

HHWIL

HSTROBE

HD[15:0] (input)

refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

†

HCS

5

HRDY

11

18

1st half-word 2nd half-word

12

13

19

10

3

14

12

4

13

12

11

18

12

Figure 30. HPI Write Timing (HAS Used)

17

13

5

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NO

UNIT

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP

NO.

.

2 t

c(CKRX)

3 t

w(CKRX)

5 t

su(FRH-CKRL)

6 t

h(CKRL-FRH)

7 t

su(DRV-CKRL)

8 t

h(CKRL-DRV)

10 t

su(FXH-CKXL)

11 t

h(CKXL-FXH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

‡

CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

*This parameter is not tested.

Cycle time, CLKR/X CLKR/X ext *2P ns Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext *P – 1 ns

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

Hold time, DR valid after CLKR low

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

†‡

(see Figure 31)

’C6701-14 ’C6701-16

MIN MAX

CLKR int *13 CLKR ext CLKR int *7 CLKR ext CLKR int 10 CLKR ext CLKR int 4 CLKR ext CLKX int *13 CLKX ext CLKX int *7 CLKX ext 3

UNIT

4

1

4

ns

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

49

SMJ320C6701

NO

PARAMETER

UNIT

Disable time, DX high im edance following last data bit from

Delay time, FSX high to DX valid

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

switching characteristics for McBSP

NO. PARAMETER

.

1 t

d(CKSH-CKRXH)

2 t

c(CKRX)

3 t

w(CKRX)

4 t

d(CKRH-FRV)

9 t

d(CKXH-FXV)

12 t

dis(CKXH-DXHZ)

13 t

d(CKXH-DXV)

14 t

d(FXH-DXV)

†

CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡

Minimum delay times also represent minimum output hold times.

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

¶

C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

*This parameter is not tested.

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input

Cycle time, CLKR/X CLKR/X int 2P ns Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1¶C + 1 Delay time, CLKR high to internal FSR valid CLKR int –4 4 ns

Delay time, CLKX high to internal FSX valid

Disable time, DX high impedance following last data bit from CLKX high

Delay time, CLKX high to DX valid.

Delay time, FSX high to DX valid. ONLY applies when in data delay 0 (XDATDLY = 00b) mode.

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

†‡§

(see Figure 31)

.

’C6701-14 ’C6701-16

MIN MAX

3 15 ns

CLKX int –4 5 CLKX ext CLKX int *–3 *2 CLKX ext CLKX int –2 4 CLKX ext FSX int *–2 *4 FSX ext *2 *10

*3 *16

*2 *9

3 16

UNIT

¶

ns

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS

1

CLKR

4

FSR (int)

5

FSR (ext)

DR

CLKX

9

FSX (int)

10

FSX (ext)

2

3

4

6

7

Bit(n-1) (n-2) (n-3)

2

3

11

8

SGUS030 – APRIL 2000

FSX (XDATDLY=00b)

DX

14

1312

Bit 0 Bit(n-1) (n-2) (n-3)

13

Figure 31. McBSP Timings

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

51

SMJ320C6701

NO

UNIT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 32)

NO.

.

1 t

su(FRH-CKSH)

2 t

h(CKSH-FRH)

*This parameter is not tested.

CLKR/X (no need to resync)

CLKR/X(needs resync)

Setup time, FSR high before CLKS high *4 ns Hold time, FSR high after CLKS high *4 ns

CLKS

1

FSR external

2

Figure 32. FSR Timing When GSYNC = 1

’C6701-14 ’C6701-16

MIN MAX

UNIT

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

’C6701-14

NO.

4 t

su(DRV-CKXL)

5 t

†

‡

h(CKXL-DRV) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency

in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX low 12 2 – 3P ns Hold time, DR valid after CLKX low 4 5 + 6P ns

MASTER SLAVE

MIN MAX MIN MAX

’C6701-16

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

†‡

(see Figure 33)

†‡

UNIT

(see Figure 33)

’C6701-14

NO. PARAMETER

1 t

h(CKXL-FXL)

2 t

d(FXL-CKXH)

3 t

d(CKXH-DXV)

6 t

dis(CKXL-DXHZ)

7 t

dis(FXH-DXHZ)

8 t

d(FXL-DXV)

*This parameter is not tested. †

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

§

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

¶

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high Delay time, CLKX high to DX valid –4 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from

CLKX low Disable time, DX high impedance following last data bit from

FSX high Delay time, FSX low to DX valid 2P + 3 4P + 12 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶

#

MASTER MIN MAX MIN MAX

T – 4 T + 4 ns L – 4 L + 4 ns

*L – 2 *L + 3 ns

’C6701-16

§

SLAVE

*P + 4 *3P + 17 ns

UNIT

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

53

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

21

FSX

87

4

DX

DR

6

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 34)

NO.

4 t

su(DRV-CKXH)

5 t

†

‡

h(CKXH-DRV)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX high 12 2 – 3P ns Hold time, DR valid after CLKX high 4 5 + 6P ns

3

5

’C6701-14 ’C6701-16

MASTER SLAVE

MIN MAX MIN MAX

UNIT

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0

†‡

(see Figure 34)

’C6701-14

NO. PARAMETER

1 t

h(CKXL-FXL)

2 t

d(FXL-CKXH)

3 t

d(CKXL-DXV)

6 t

dis(CKXL-DXHZ)

7 t

d(FXL-DXV)

*This parameter is not tested. †

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

§

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

¶

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high Delay time, CLKX low to DX valid –4 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit

from CLKX low Delay time, FSX low to DX valid *H – 2 *H + 3 2P + 3 4P + 12 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶

#

MASTER

MIN MAX MIN MAX

L – 4 L + 4 ns T – 4 T + 4 ns

*–2 *4 *3P + 4 *5P + 17 ns

’C6701-16

§

SLAVE

UNIT

CLKX

FSX

DX

DR

21

376

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

4

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

5

Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

55

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1

’C6701-14

NO.

4 t

su(DRV-CKXH)

5 t

†

‡

h(CKXH-DRV)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX high 12 2 – 3P ns Hold time, DR valid after CLKX high 4 5 + 6P ns

MASTER SLAVE

MIN MAX MIN MAX

’C6701-16

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1

†‡

(see Figure 35)

†‡

UNIT

(see Figure 35)

’C6701-14

NO. PARAMETER

1 t

h(CKXH-FXL)

2 t

d(FXL-CKXL)

3 t

d(CKXL-DXV)

6 t

dis(CKXH-DXHZ)

7 t

dis(FXH-DXHZ)

8 t

d(FXL-DXV)

*This parameter is not tested. †

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

§

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

¶

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low Delay time, CLKX low to DX valid –4 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit

from CLKX high Disable time, DX high impedance following last data bit

from FSX high Delay time, FSX low to DX valid 2P + 3 4P + 12 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶

#

MASTER MIN MAX MIN MAX

T – 4 T + 4 ns

H – 4 H + 4 ns

*H – 2 *H + 3 ns

’C6701-16

§

SLAVE

*P + 4 *3P + 17 ns

UNIT

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

21

FSX

7

4

DX

DR

6

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 36)

NO.

4 t

su(DRV-CKXL)

5 t

†

‡

h(CKXL-DRV)

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Setup time, DR valid before CLKX low 12 2 – 3P ns Hold time, DR valid after CLKX low 4 5 + 6P ns

38

5

’C6701-14 ’C6701-16

MASTER SLAVE

MIN MAX MIN MAX

UNIT

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

57

SMJ320C6701 FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1

†‡

(see Figure 36)

’C6701-14

NO. PARAMETER

1 t

h(CKXH-FXL)

2 t

d(FXL-CKXL)

3 t

d(CKXH-DXV)

6 t

dis(CKXH-DXHZ)

7 t

d(FXL-DXV)

*This parameter is not tested. †

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

§

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

¶

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low Delay time, CLKX high to DX valid –4 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from

CLKX high Delay time, FSX low to DX valid *L – 2 *L + 3 2P + 3 4P + 12 ns

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶

#

MASTER

MIN MAX MIN MAX

H – 4 H + 4 ns

T – 4 T + 4 ns

*–2 *4 *3P + 4 *5P + 17 ns

’C6701-16

§

SLAVE

UNIT

CLKX

21

FSX

DX

DR

6

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)

7

4

3

5

Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

NO

PARAMETER

UNIT

NO

UNIT

NO

PARAMETER

UNIT

NO

PARAMETER

UNIT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

DMAC, TIMER, POWER-DOWN TIMING

switching characteristics for DMAC outputs (see Figure 37)

NO. PARAMETER

.

1 t

d(CKO1H-DMACV)

CLKOUT1

DMAC[0:3]

Delay time, CLKOUT1 high to DMAC valid 2 11 ns

Figure 37. DMAC Timing

SMJ320C6701

SGUS030 – APRIL 2000

’C6701-14 ’C6701-16

MIN MAX

11

UNIT

timing requirements for timer inputs (see Figure 38)

NO.

.

1 t

†

w(TINPH)

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

Pulse duration, TINP high 2P ns

†

switching characteristics for timer outputs (see Figure 38)

.

NO. PARAMETER

2 t

d(CKO1H-TOUTV)

CLKOUT1

TOUT

TINP

Delay time, CLKOUT1 high to TOUT valid 1 10 ns

1

2

Figure 38. Timer Timing

switching characteristics for power-down outputs (see Figure 39)

NO. PARAMETER

.

1 t

d(CKO1H-PDV)

Delay time, CLKOUT1 high to PD valid 1 9 ns

’C6701-14 ’C6701-16

MIN MAX

’C6701-14 ’C6701-16

MIN MAX

2

’C6701-14 ’C6701-16

MIN MAX

UNIT

CLKOUT1

PD

Figure 39. Power-Down Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

11

59

SMJ320C6701

NO

UNIT

NO

PARAMETER

UNIT

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

JTAG TEST-PORT TIMING

timing requirements for JTAG test port (see Figure 40)

NO.

.

1 t

c(TCK)

3 t

su(TDIV-TCKH)

4 t

h(TCKH-TDIV)

switching characteristics for JTAG test port (see Figure 40)

NO. PARAMETER

.

2 t

d(TCKL-TDOV)

*This parameter is not tested.

Cycle time, TCK 50 ns Setup time, TDI/TMS/TRST valid before TCK high 10 ns Hold time, TDI/TMS/TRST valid after TCK high 5 ns

Delay time, TCK low to TDO valid *0 *15 ns

’C6701-14 ’C6701-16

MIN MAX

’C6701-14 ’C6701-16

MIN MAX

UNIT

TCK

TDO

TDI/TMS/TRST

1

2

3

Figure 40. JTAG T est-Port Timing

2

4

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

RΘ

JMA

Junction to Moving Air

SMJ320C6701

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SGUS030 – APRIL 2000

MECHANICAL DATA

GLP (S-CBGA-N429) CERAMIC BALL GRID ARRAY

1,22 1,00

27,20 26,80

SQ

AA Y W V U T R P N M L K J H G F E D C B A

1

3,30 MAX

25,40 TYP

1,27

3

5

2

9

7

8

64

10 12

1311

15 17

14

16

18

19

21

20

Seating Plane

0,90 0,60

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MO-156 D. Flip chip application only

∅ 0,10

M

0,70 0,50

0,15

4164732/A 08/98

thermal resistance characteristics (S-CBGA package)

NO °C/W Air Flow

1 RΘ 2 RΘ 3 RΘ 4 11.8 150 fpm 5

RΘ

6

7 RΘ

Junction-to-Case, measured to the bottom of solder ball 3.0 N/A

JC

Junction-to-Case, measured to the top of the package lid 7.3 N/A

JC

Junction-to-Ambient 14.5 0

JA

Junction-to-Moving-Air

JMA

Junction-to-Board, measured by soldering a thermocouple to one of the middle

JB

traces on the board at the edge of the package

11.1

10.2 500 fpm

6.2 N/A

250 fpm

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

61

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Texas Instruments SM320C6701GLPS16, SM320C6701GLPW14, SMJ320C6701GLPW14 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual