TEXAS INSTRUMENTS SM320VC33 Technical data

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

D High-Performance Floating-Point Digital

Signal Processor (DSP):

- SM/SMJ320VC33-150

- 13-ns Instruction Cycle Time

- 150 Million Floating-Point Operations Per Second (MFLOPS)

- 75 Million Instructions Per Second (MIPS)

D 34K × 32-Bit (1.1-Mbit) On-Chip Words of

Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K plus 2 × 1K Blocks to improve Internal Performance

D x5 Phase-Locked Loop (PLL) Clock

Generator

D Very Low Power: < 200 mW @ 150 MFLOPS D 32-Bit High-Performance CPU D 16-/32-Bit Integer and 32-/40-Bit

Floating-Point Operations

D Four Internally Decoded Page Strobes to

Simplify Interface to I/O and Memory Devices

D Boot-Program Loader D EDGEMODE Selectable External Interrupts D 32-Bit Instruction Word, 24-Bit Addresses D Eight Extended-Precision Registers D Fabricated Using the 0.18-µm (l

Gate Length) TImeline Technology by Texas Instruments (TI)

description

-Effective

eff

D On-Chip Memory-Mapped Peripherals:

- One Serial Port

- Two 32-Bit Timers

- Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation

D 164-Pin Low-Profile Quad Flatpack (HFG

Suffix)

D 144-Pin Non-hermetic Ceramic Ball Grid

Array (CBGA) (GNM Suffix)

D Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

D Two Low-Power Modes D Two- and Three-Operand Instructions D Parallel Arithmetic/Logic Unit (ALU) and

Multiplier Execution in a Single Cycle

D Block-Repeat Capability D Zero-Overhead Loops With Single-Cycle

Branches

D Conditional Calls and Returns D Interlocked Instructions for

Multiprocessing Support

D Bus-Control Registers Configure

Strobe-Control Wait-State Generation

D 1.8-V (Core) and 3.3-V (I/O) Supply Voltages

The SM/SMJ320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal CMOS (TImeline) technology. The SM/SMJ320VC33 is part of the SM320C3x generation of DSPs from Texas Instruments.

The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM/SMJ320VC33 optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TImeline and SM320C3x are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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On products compliant to MIL−PRF−38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

description (continued)

The SM/SMJ320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features.

General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SM320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

JTAG scan-based emulation logic

The 320VC33 contains a JTAG port for CPU emulation within a chain of any number of other JTAG devices. The JTAG port on this device does not include a pin-by-pin boundary scan for point-to-point board level test. The Boundary Scan tap input and output is internally connected with a single dummy register allowing loop back tests to be performed through that JTAG domain.

The JTAG emulation port of this device also includes two additional pins, EMU0 and EMU1, for global control of multiple processors conforming to the TI emulation standard. These pins are open collector-type outputs which are wire ORed and tied high with a pullup. Non-TI emulation devices should not be connected to these pins.

The VC33 instruction register is 8 bits long. Table 1 shows the instructions code. The uses of SAMPLE and HIGHZ opcodes, though defined, have no meaning for the SM/SMJ320VC33, which has no boundary scan. For example, HIGHZ will affect only the dummy cell (no meaning) and will not put the device pins in a high-impedance state.

Table 1. Boundary-Scan Instruction Code

INSTRUCTION NAME INSTRUCTION CODE

EXTEST 00000000 BYPASS 11111111 SAMPLE 00000010 Boundry is only one dummy cell HIGHZ 00000110 Boundry is only one dummy cell PRIVATE1 PRIVATE2 PRIVATE3 PRIVATE4 PRIVATE5 PRIVATE6 PRIVATE7 PRIVATE8 PRIVATE9 PRIVATE10 PRIVATE11

† † † † † † † † †

† †

00000011 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001

†

Use of Private opcodes could cause the device to operate in an unexpected manner.

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pinout

NC NC

NC A20 V A19 A18 A17

A16 A15 V A14 A13

A12 A11

A10

DV PAGE3 PAGE2

V PAGE1 PAGE0

NC NC

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

RESET

143

144

†‡

MCBL/MP

EDGEMODE

140

141

142

INT0

139

INT1

138

INT2

137

INT3

136

135

XF0

134

XF1

133

132

131

TCLK0

TCLK1DXCLKX0

FSX

127

128

129

130

126

125

124

123 122

121

120

119

CLKR

118

FSR0

117

116

DR0

115

TRST

114

TMS

113

112

TDI

111

TDO

110

TCK

109

108

EMU0

107

EMU1

106

105

104

103

102

101

100

D10

D11

D12

D13

D14

D15

HFG PACKAGE

(TOP VIEW)

163

162

A21

161

160

A22

159

158

A23

157

RSV0

156

RSV1

155

NCNCNC

164

1 2 3 4 5

6 7 8 9

10 11 12

13 14 15

16 17 18

20 21

22 23

35 36 37

38 39 40

154

CLKMD0

CLKMD1

152

153

PLLV

151

XIN

150

XOUT

148

149

PLLV

EXTCLK

147

146

SHZ

145

R/W

STRB

IACK

RDY

HOLD

HOLDA

D30

D31

D29

D28

D27

D25

D24

D26

D23

D22

D21

D20

D19

D18

D17

D16

respectively.

SS,

NC - No internal connection

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

‡

PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and V

The SM/SMJ320VC33 device is packaged in 164-pin low-profile quad flatpacks (HFG Suffix) and in 144-ball fine pitch ball grid arrays (GNL and GNM Suffix).

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

GNM Terminal Assignments† (Sorted by Signal Name)

SIGNAL

NAME

NUMBER

SIGNAL

NAME

NUMBER

SIGNAL

NAME

NUMBER

SIGNAL

NAME

NUMBER

A0 J2 D0 G12 M1 R/W L4 A1 K2 D1 G10 N1 RDY M5 A2 K1 D2 F13 N4 RESET B7 A3 J4 D3 G11 N7 RSV0 B4 A4 H4 D4 H10 M8 RSV1 D5 A5 H3 D5 H13 N12 SHZ D7 A6 H1 D6 H12 A7 G4 D7 J10

L13 STRB M4

H11 TCK F10 A8 G1 D8 J11 F11 TCLK0 C10 A9 G2 D9 J12 B12 TCLK1 A11

A10 F3 D10 K13 A10 TDI E11

A11 F4 D11 K12 A6 TDO D13 A12 F2 D12 K10 A1 TMS E10 A13 E1 D13 M13 DX0 A12 TRST C13 A14 E2 D14 L11 EDGEMODE A7 B1 A15 E4 D15 L12 EMU0 F12 D1 A16 C1 D16 M12 EMU1 E12 G3 A17 C2 D17 L10 EXTCLK C6 J1 A18 D3 D18 K9 FSR0 C12 L2 A19 C3 D19 N11 FSX D10 M3 A20 B2 D20 M11 H1 L3 M6 A21 D4 D21 M10 H3 N2 L7 A22 A2 D22 K8 HOLD N5 A23 B3 D23 N9 HOLDA K5

N10

N13 CLKMD0 C5 D24 M9 IACK K4 K11 CLKMD1 B5 D25 L8 INT0 C8 G13

CLKR0 B13 D26 N8 INT1 B9 E13 CLKX0 B11 D27 M7 INT2 D8 A13

E3 D28 K7 INT3 A9 C11

J3 D29 L6 MCBL/MP B8 C9

L5 D30 N6 PAGE0 M2 C7

L9 D31 K6 PAGE1 N3 C4 J13 DR0 D11 PAGE2 L1 XF0 B10 D12 D2 PAGE3 K3 XF1 D9

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

‡

PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and V

F1 PLLV H2 PLLV

DD SS

‡ ‡

A5 XIN B6 A4 XOUT D6

respectively.

SS,

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SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

GNM Terminal Assignments† (Sorted by Pin Number)

NUMBER

A1 DV A2 A22 C12 FSR0 G11 D3 L5 CV A3 CV A4 PLLV A5 PLLV A6 DV

SIGNAL

NAME

SS DD

NUMBER

C11 V

SIGNAL

NAME

NUMBER

SIGNAL

NAME

NUMBER

G10 D1 L4 R/W

C13 TRST G12 D0 L6 D29

D1 V D2 DV

D3 A18 H2 DV

G13 V

L7 V

H1 A6 L8 D25

L9 CV

SIGNAL

NAME

A7 EDGEMODE D4 A21 H3 A5 L10 D17 A8 CV

D5 RSV1 H4 A4 L11 D14

A9 INT3 D6 XOUT H10 D4 L12 D15

A10 DV

A11 TCLK1 D8 INT2 H12 D6 M1 DV

D7 SHZ H11 DV

L13 DV

DD DD

A12 DX D9 XF1 H13 D5 M2 PAGE0 A13 V

B1 V

SS SS

B2 A20 D12 CV B3 A23 D13 TDO J4 A3 M6 V

D10 FSX J1 V

M3 V

D11 DR0 J2 A0 M4 STRB

J3 CV

M5 RDY

B4 RSV0 E1 A13 J10 D7 M7 D27 B5 CLKMD1 E2 A14 J11 D8 M8 DV B6 XIN E3 CV

B7 RESET E4 A15 J13 CV

J12 D9 M9 D24

M10 D21

B8 MCBL/MP E10 TMS K1 A2 M11 D20

B9 INT1 E11 TDI K2 A1 M12 D16 B10 XF0 E12 EMU1 K3 PAGE3 M13 D13 B11 CLKX0 E13 V B12 DV

F1 DV

K4 IACK N1 DV K5 HOLDA N2 H3

B13 CLKR F2 A12 K6 D31 N3 PAGE1

C1 A16 F3 A10 K7 D28 N4 DV

C2 A17 F4 A11 K8 D22 N5 HOLD

C3 A19 F10 TCK K9 D18 N6 D30

C4 V

C5 CLKMD0 F12 EMU0 K11 V

F11 DV

K10 D12 N7 DV

N8 D26

C6 EXTCLK F13 D2 K12 D11 N9 D23

C7 V

G1 A8 K13 D10 N10 V

C8 INT0 G2 A9 L1 PAGE2 N11 D19

C9 V

C10 TCLK0 G4 A7 L3 H1 N13 V

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

‡

PLLVDD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and V

G3 V

L2 V

respectively.

SS,

N12 DV

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SM320VC33, SMJ320VC33

†

DESCRIPTION

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

Terminal Functions

TERMINAL

NAME QTY

D31- D0 32 I/O/Z A23- A0 24 O/Z 24-bit address port S H R R/W 1 O/Z STRB 1 O/Z Strobe. For all external-accesses S H

PAGE0 PAGE3

RDY 1 I

HOLD 1 I

HOLDA 1 O/Z

RESET 1 I

EDGEMODE 1 I Edge mode. Enables interrupt edge mode detection. INT3- INT0 4 I External interrupts

IACK 1 O/Z MCBL/MP 1 I Microcomputer Bootloader/microprocessor mode-select

SHZ 1 I

XF1, XF0 2 I/O/Z

CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R CLKX0 1 I/O/Z DR0 1 I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R

DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R FSR0 1 I/O/Z

FSX0 1 I/O/Z

†

I = input, O = output, Z = high-impedance state

‡

S = SHZ active, H = HOLD active, R = RESET active

Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.

TYPE

PRIMARY-BUS INTERFACE

32-bit data port S H R Data port bus keepers. (See Figure 9) S

Read/write. R/W is high when a read is performed and low when a write is performed over the parallel interface.

1 O/Z Page strobes. Four decoded page strobes for external access S H R

Ready. RDY indicates that the external device is prepared for a transaction completion.

Hold. When HOLD is a logic low, any ongoing transaction is completed. A23- A0, D31-D0, STRB, and R/W are placed in the high-impedance state and all transactions over the primary-bus interface are held until HOLD becomes a logic high or until the NOHOLD bit of the primary-bus-control register is set.

Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD. HOLDA indicates that A23-A0, D31-D0, STRB, and R/W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set.

CONTROL SIGNALS

Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector.

Internal acknowledge. IACK is generated by the IACK instruction. IACK can be used to indicate when a section of code is being executed.

Shutdown high impedance. When active, SHZ places all pins in the high-impedance state. SHZ can be used for board-level testing or to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory and register contents. Reset the device with SHZ high to restore it to a known operating condition.

External flags. XF1 and XF0 are used as general-purpose I/Os or to support interlocked processor instruction.

SERIAL PORT 0 SIGNALS

Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter.

Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive process using DR0.

Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit process using DX0.

CONDITIONS

WHEN

SIGNAL IS Z TYPE

S H R

S R

‡

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SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

†

DESCRIPTION

Terminal Functions (Continued)

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

TERMINAL

NAME QTY

TYPE

TIMER SIGNALS

TCLK0 1 I/O/Z

TCLK1 1 I/O/Z

Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0.

Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1.

SUPPLY AND OSCILLATOR SIGNALS

H1 1 O/Z External H1 clock S H3 1 O/Z External H3 clock S

DV V

PLLV PLLV

DD SS

8 I

16 I 18 I Ground. All grounds must be connected to a common ground plane.

1 I Internally isolated PLL supply. Connect to CVDD (1.8 V) 1 I Internally isolated PLL ground. Connect to V

EXTCLK 1 I

XOUT 1 O

XIN 1 I CLKMD0,

CLKMD1

2 I Clock mode select pins

+VDD. Dedicated 1.8-V power supply for the core CPU. All must be connected to a common supply plane.

+VDD. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a common supply plane.

External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is used, tie this pin to ground.

Clock out. Output from the internal-crystal oscillator. If a crystal is not used, XOUT should be left unconnected.

Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to ground.

RSV0 - RSV1 2 I Reserved. Use individual pullups to DVDD.

JTAG EMULATION

EMU1- EMU0 2 I/O Emulation pins 0 and 1, use individual pullups to DV

TDI 1 I Test data input TDO 1 O Test data output TCK 1 I Test clock TMS 1 I Test mode select TRST 1 I Test reset

†

I = input, O = output, Z = high-impedance state

‡

S = SHZ active, H = HOLD active, R = RESET active

Recommended decoupling. Four 0.1 µF for CVDD and eight 0.1 µF for DVDD.

CONDITIONS

WHEN

SIGNAL IS Z TYPE

S R

‡

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SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

functional block diagram

PAGE0 PAGE1

PAGE2 PAGE3

RDY

HOLD

HOLDA

STRB

R/W D31- D0 A23- A0

RSV(0,1)

SHZ

EDGEMODE

RESET

INT(3- 0)

IACK

MCBL/MP

XF(1,0)

TDI

TDO

EMU0 EMU1

TCK TMS

TRST

EXTCLK

XOUT

XIN

CLKMD(0,1)

MUX

RAM

Block 0

(1K × 32)

32 32 40 40

REG1

REG2

Multiplier

40 40 40

24 24 32

Cache

(64 × 32)

32 24 24

PDATA Bus PADDR Bus

DDATA Bus

DADDR1 Bus

MUX

DADDR2 Bus

DMADATA Bus DMAADDR Bus

IR PC

Controller

JTAG Emulation

H1 H3

PLL CLK

CPU1

RAM

Block 1

(1K × 32)

24 2432 32 32

CPU1

CPU2 REG1 REG2

ARAU0 ARAU1

32-Bit Barrel

Shifter

ALU

Extended-

Precision Registers

(R7-R0)

DISP0, IR0, IR1

Auxiliary

Registers

(AR0- AR7)

Other

Registers

(12)

DMA Controller

Global-Control

Source-Address

Destination-

Boot

Loader

Address Register

Transfer-

Counter Register

RAM

Block 2

(16K × 32)

Peripheral Data Bus

FSX0

DX0

CLKX0

FSR0

DR0

CLKR0

TCLK0

TCLK1

RAM

Block 3

(16K × 32)

Serial Port 0

Serial-Port-Control

Receive/Transmit

(R/X) Timer Register

Data-Transmit

Data-Receive

Timer 0

Global-Control

Timer-Period

Timer-Counter

Timer 1

Global-Control

Timer-Period

Timer-Counter

Port Control

STRB-Control

MUX

Peripheral Data Bus

Peripheral Address Bus

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memory map

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

03Fh 040h

7FFFFFh

800000h

803FFFh

804000h

807FFFh

808000h

8097FFh 809800h

809BFFh 809C00h

809FFFh 80A000h

FFFFFFh

Reset, Interrupt, Trap V ector, and

Reserved Locations (64)

(External STRB

STRB

(8M Words - 64 Words)

RAM Block 2

(16K Words Internal)

RAM Block 3

(16K Words Internal)

Peripheral Bus

Memory-Mapped Registers

(6K Words Internal)

RAM Block 0

(1K Words Internal)

RAM Block 1

(1K Words Internal)

STRB

(8M Words - 40K Words)

(a) Microprocessor Mode

External

Active

External

Active

Active)

FFFh

1000h

400000h

7FFFFFh

800000h

803FFFh

804000h

807FFFh

808000h

8097FFh

809800h

809BFFh 809C00h

809FC0h

809FC1h

809FFFh

80A000h

FFF000h

FFFFFFh

Reserved for Bootloader

Operations

Boot 1

External

STRB

Active

Boot 2

(16K Words Internal)

Memory-Mapped Registers

(6K Words Internal)

(1K Words Internal)

User-Program Interrupt

and Trap Branch Table

63 Words

Boot 3

(b) Microcomputer/Bootloader Mode

(8M Words -

4K Words)

RAM Block 2

RAM Block 3

Peripheral Bus

RAM Block 0

RAM Block 1

External STRB (8M Words -

40K Words)

Active

NOTE A: STRB is active over all external memory ranges. PAGE0 to PAGE3 are configured as external bus strobes. These are simple

decoded strobes that have no configuration registers and are active only during external bus activity over the following ranges:

Name Active range

PAGE0 0000000h – 03FFFFFh PAGE1 0400000h – 07FFFFFh PAGE2 0800000h – 0BFFFFFh PAGE3 0C00000h – 0FFFFFFh STRB 0000000h – 0FFFFFFh

Figure 1. SM/SMJ320VC33 Memory Maps

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SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

memory map (continued)

00h

01h

02h

03h

04h

05h

06h 07h

08h 09h

0Ah

0Bh

0Ch

1Fh

Reset

INT0

INT1

INT2

INT3

XINT0 RINT0

Reserved

TINT0

TINT1

DINT

Reserved

TRAP 020h

809FC1h

809FC2h

809FC3h

809FC4h

809FC5h

809FC6h

809FC7h

809FC8h 809FC9h

809FCAh

809FCBh

809FCCh 809FDFh

809FE0h

INT0

INT1

INT2

INT3

XINT0

RINT0

Reserved

TINT0

TINT1

DINT

Reserved

TRAP 0

3Ch

3Fh

TRAP 273Bh 809FFBh

Reserved

(a) Microprocessor Mode (b) Microcomputer / Bootloader Mode

809FFCh

809FFFh

TRAP 27

Reserved

Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations

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memory map (continued)

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

808000h

808004h

808006h

808008h

808020h

808024h

808028h

808030h

808034h

808038h

808040h

808042h 808043h 808044h 808045h 808046h

DMA Global Control

DMA Source Address

DMA Destination Address

DMA Transfer Counter

Timer 0 Global Control

Timer 0 Counter

Timer 0 Period Register

Timer 1 Global Control

Timer 1 Counter

Timer 1 Period Register

Serial Global Control

FSX/DX/CLKX Serial Port Control FSR/DR/CLKR Serial Port Control

Serial R/X Timer Control

Serial R/X Timer Counter

Serial R/X Timer Period Register

808048h

80804Ch

808064h

NOTE A: Shading denotes reserved address locations.

Data-Transmit

Data-Receive

Primary-Bus Control

Figure 3. Peripheral Bus Memory-Mapped Registers

clock generator

The clock generator provides clocks to the VC33 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. The PLL circuit generates the device clock by multiplying the reference clock frequency by a x5 scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

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SM320VC33, SMJ320VC33 DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

PLL and clock oscillator control

The clock mode control pins are decoded into four operational modes as shown in Figure 4. These modes control clock divide ratios, oscillator, and PLL power (see Table 2).

When an external clock input or crystal is connected, the opposite unused input is simply grounded. An XOR gate then passes one of the two signal sources to the PLL stage. This allows the direct injection of a clock reference into EXTCLK, or 1-20 MHz crystals and ceramic resonators with the oscillator circuit. The two clock sources include:

D A crystal oscillator circuit, where a crystal or ceramic resonator is connected across the XOUT and XIN pins

and EXTCLK is grounded.

D An external clock input, where an external clock source is directly connected to the EXTCLK pin, and XOUT

is left unconnected and XIN is grounded.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. The PLL is a simple x5 reference multiplier with bypass and power control.

The clock divider, under CPU control, reduces the clock reference by 1 (MAXSPEED), 1/16 (LOWPOWER), or clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state.

A divide-by-two TMS320C31 equivalent mode of operation is also provided. In this case, the clock output reference is further divided by two with clock synchronization being determined by the timing of RESET falling relative to the present H1/H3 state.

Clock DividerPLLClock & Crystal OSC

EXTCLK

XOUT

U X

X1, 1/16, Off

C31 DIV2 Mode

1/2

M U X

XIN

CLKMD0 CLKMD1

RFS1

Oscillator Enable

SEL

XOR

PLLX5

PLL PWR and Bypass

Figure 4. Clock Generation

T able 2. Clock Mode Select Pins

CLKMD0 CLKMD1 FEEDBACK PLLPWR RATIO NOTES

0 0 Off Off 1 Fully static, very low power 0 1 On Off 1/2 Oscillator enabled 1 0 On Off 1 Oscillator enabled 1 1 On On 5 2 mA @ 60 MHz, 1.8 V PLL power. Oscillator enabled

MAXSPEED/ LOWPOWER

IDLE2

CPU CLOCK

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PLL and clock oscillator control (continued)

Typical crystals in the 8-30 MHz range have a series resistance of 25 Ω, which increases below 8 MHz. To maintain proper filtering and phase relationships, Rd and Z the crystal. A series compensation resistor (Rd), shown in Figure 5, is recommended when using lower frequency crystals. The XOUT output, the square wave inverse of XIN, is then filtered by the XOUT output impedance, C1 load capacitor, and Rd (if present). The crystal and C2 input load capacitor then refilters this signal, resulting in a XIN signal that is 75-85% of the oscillator supply voltage.

NOTE: Some ceramic resonators are available in a low-cost, three-terminal package that includes C1 and C2 internally. Typically, ceramic resonators do not provide the frequency accuracy of crystals.

NOTE: Better PLL stability can be achieved using the optional power supply isolation circuit shown in Figure 5. A similar filter can be used to isolate the PLLVSS, as shown in Figure 6. PLL VDD can also be directly connected

to CV

Table 3. Typical Crystal Circuit Loading

FREQUENCY (MHz) Rd (Ω) C1 (pF) C2 (pF) CL† (pF) RL† (Ω)

2 4.7k 18 18 12 200

5 2.2k 18 18 12 60 10 470 15 15 12 30 15 0 15 12 12 25

†

CL and RL are typical internal series load capacitance and resistance of the crystal.

20 0 9 9 10 25

of the oscillator circuit should be 10x-40x that of

out

XOUT XIN

Crystal

C1 C2

Figure 5. Self-Oscillation Mode

EXTCLKRdPLLV

PLLV

0.1 µF

100 Ω

0.01 µF

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PLL isolation

The internal PLL supplies can be directly connected to CVDD and VSS (0 Ω case) or fully isolated as shown in Figure 6. The RC network prevents the PLL supplies from turning high frequency noise in the CVDD and V supplies into jitter.

0 -100 Ω

PLLV

0.1 µF

PLLV

Figure 6. PLL Isolation Circuit Diagram

0.01 µF

0 -100 Ω

clock and PLL considerations on initialization

On power up, the CPU clock divide mode can be in MAXSPEED, LOPOWER or IDLE2, or the PLL could be in an undefined mode. RESET falling in the presence of a valid CPU clock is used to clear this state, after which the device will synchronously terminate any external activity.

The 5x Fclkin PLL of the 320VC33 contains an 8-bit PLL-LOCK counter that will cause the PLL to output a frequency of Fclkin/2 during the initial ramp. This counter, however, does not increment while RESET is low or in the absence of an input clock. A minimum of 256 input clocks are required before the first falling edge of reset for the PLL to output to clear this counter. The setup and behavior that is seen is as follows.

Power is applied to the DSP with RESET low and the input clock high or low. A clock is applied (RESET is still low) and the PLL appears to lock on to the input clock, producing the expected x5 output frequency. RESET is driven high and the PLL output immediately drops to Fclkin/2 for up to 256 input cycles or 128 of the Fclkin/2 output cycles. The PLL/CPU clock then switches to x5 mode.

The switch over is synchronous and does not create a clock glitch, so the only effect is that the CPU will run slow for up to the first 128 cycles after reset goes high. Once the PLL has stabilized, the counter will remain cleared and subsequent resets will not exhibit this condition.

power sequencing considerations

Though an internal ESD and CMOS latchup protection diode exists between CVDD and DVDD, it should not be considered a current-carrying device on power up. An external Schottky diode should be used to prevent CV from exceeding DVDD by more than 0.7 V. The effect of this diode during power up is that if CVDD is powered up first, DVDD will follow by one diode drop even when the DVDD supply is not active.

Typical s y s tems using LDOs of the same family type for both DVDD and CVDD will track each other during power up. In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin can be used to asynchronously disable all outputs. RESET should not be used in this case since some signals require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.

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EDGEMODE

When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer than the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the logic-low and logic-high states is sufficient.

When EDGEMODE = 0, a logic-low interrupt pin will continually set the corresponding interrupt flag. The CPU or DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine (ISR), effectively lengthening the maximum ISR width.

After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload operation.

Delay

DQ DQ

EDGEMODE

INTn

RESET

DDQQ

Figure 7. EDGEMODE and Interrupt Flag CIrcuit

reset operation

When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in progress. This can take as much as 10 CPU cycles, after which, the address, data, and control pins will be in an inactive or high-impedance state.

When both RESET and SHZ are applied, the device will immediately enter the reset state with the pins held in high-impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ can be used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system conflicts.

IF Bit

CPU Reset

CPU Set

PAGE0 - PAGE3 select lines

To facilitate simpler and higher speed connection to external devices, the SM/SMJ320VC33 includes four predecoded select pins that have the same timings as STRB. These pins are decoded from A22, A23, and STRB and are active only during external accesses over the ranges shown in Table 4. All external bus accesses are controlled by a single bus control register.

T able 4. PAGE0 - PAGE3 Ranges

START END

PAGE0 0x000000 0x3FFFFF PAGE1 0x400000 0x7FFFFF PAGE2 0x800000 0xBFFFFF PAGE3 0xC00000 0xFFFFFF

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using external logic with the READY pin

The key to designing external wait-state logic is the internal bus control register and associated internal logic that logically combines the external READY pin with the much faster on-chip bus control logic. This essentially allows slow external logic to interact with the bus while easily meeting the READY input timings. It is also relevant to mention that the combined ready signals are sampled on the rising edge of the internal H1 clock. Please refer to Figure 8 for the following examples.

example 1

A simple 0 or WTCNT wait-state decoder can be created by simply tying an address line back to the READY pin and selecting the AND option. When the tied back address is low, the bus will run with 0 wait states. When the tied back address is high, the bus will be controlled by the internal wait-state counter .

By enabling the bank compare logic, proper operation is further ensured by inserting a null cycle before a read on the next bank is performed (writes are not pre-extended). This extra time can also be used by external logic to affect the feedback path.

example 2

An N-WTCNT minimum wait-state decoder can also be created by tying back an address line to READY and logically ORing it with the internal bank compare and wait count signals. When the address pin is low, bus timing is determined by the internal WTCNT and BNKCMP settings. When the address line is high, the bus can run no faster than the WTCNT counter and will be extended as long as READY is held high.

Bus_Enable_Strobe,

0 = Active

BUS_READY

External Bus Interface

Abus_old

PAGE_0 PAGE_1 PAGE_2 PAGE_3

Device Enable Pins

N_Wait

Counter

A23 A22

0 = Bus Idle To C31 Style

Abus

Decode

D Q

N-Bit Bank

Compare

STRB Pin

Decoder

(C31 Compatibility)

READY Pin

R/W

Figure 8. Internal Ready Logic, Simplified Diagram

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R/W Pin

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example 2 (continued)

Table 5. MUX Select (Bus Control Register Bits 4 and 3)

BIT 4 BIT 3 RESULTS

0 0 Ignore internal wait counter and use only external READY 0 1 Use only internal wait counter and ignore ready pin 1 0 Logically AND internal wait counter with ready pin 1 1 Logically OR internal wait counter with ready pin (reset default)

posted writes

External writes are effectively “posted” to the bus, which then acts like an output latch until the write completes. Therefore, if the application code is executing internally, it can perform a very slow external write with no penalty since the bus acts like it has a one-level-deep write FIFO.

data bus I/O buffer

The circuit shown in Figure 9 is incorporated into each data pin to lightly “hold” the last driven value on the data bus pins when the DSP or an external device is not actively driving the bus. Each bus keeper is built from a three-state driver with nominal 15 kΩ output resistance which is fed back to the input in a positive feedback configuration. The resistance isolated driver then pulls the output in one direction or the other keeping the last driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low.

R/W

Internal Data Bus

30 Ω

15 kΩ

SHZ

Bus keeper

External Data Bus Pin

Figure 9. Bus Keeper Circuit

For an external device to change the state of these pins, it must be able to drive a small dc current until the driver threshold is crossed. At the crossover point, the driver changes state, agreeing with the external driver and assisting the change. The voltage threshold of the bus keeper is approximately at 50% of the DVDD supply voltage. The typical output impedance of 30 Ω for all SM/SMJ320VC33 I/O pins is easily capable of meeting this requirement.

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