Texas Instruments SM320C6713-EP, SM320C6713B-EP Datasheet
SM320C6713-EP
SM320C6713B-EP
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SGUS049K
August 2003–Revised April 2011
SM320C6713-EP
SM320C6713B-EP
SGUS049K–AUGUST 2003– REVISED APRIL 2011
www.ti.com
Contents
1 FEATURES ......................................................................................................................... 9
2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS ..................................... 10
3 DEVICE INFORMATION ...................................................................................................... 11
3.1 Description ................................................................................................................. 14
3.2 Device Characteristics .................................................................................................... 16
3.3 Functional Block and CPU (DSP Core) Diagram ..................................................................... 17
4 OVERVIEW ....................................................................................................................... 18
4.1 CPU (DSP Core) Description ............................................................................................ 18
4.2 Memory Map Summary ................................................................................................... 19
4.3 L2 Memory Structure Expanded ......................................................................................... 21
4.4 Peripheral Register Descriptions ........................................................................................ 22
4.5 Signal Groups Description ................................................................................................ 30
5 DEVICE CONFIGURATIONS ................................................................................................ 35
5.1 Device Configurations at Device Reset ................................................................................. 35
5.2 Peripheral Pin Selection at Device Reset .............................................................................. 36
5.3 Peripheral Selection/Device Configurations Via the DEVCFG Control Register .................................. 36
5.4 Multiplexed Pins ........................................................................................................... 37
5.5 Configuration Examples .................................................................................................. 41
5.6 Debugging Considerations ............................................................................................... 47
6 TERMINAL FUNCTIONS ...................................................................................................... 47
6.1 Development Support ..................................................................................................... 55
6.2 Device and Development-Support Tool Nomenclature ............................................................... 56
6.2.1 Device Development Evolutionary Flow ..................................................................... 56
6.2.2 Support Tool Development Evolutionary Flow .............................................................. 56
6.3 Ordering Nomenclature ................................................................................................... 57
6.4 Documentation Support ................................................................................................... 57
7 REGISTER INFORMATION .................................................................................................. 59
7.1 CPU Control Status Register (CSR) Description ...................................................................... 59
7.2 Cache Configuration (CCFG) Register Description (13B) ........................................................... 60
7.3 Interrupts and Interrupt Selector ......................................................................................... 61
7.4 External Interrupt Sources ............................................................................................... 63
7.5 EDMA Module and EDMA Selector ..................................................................................... 64
8 PLL and PLL Controller ...................................................................................................... 68
8.1 PLL Registers .............................................................................................................. 69
9 MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS ............................................. 75
9.1 McASP Block Diagram .................................................................................................... 75
9.2 Multichannel Time Division Multiplexed (TDM) Synchronous Transfer Mode ..................................... 77
9.3 Burst Transfer Mode ...................................................................................................... 77
9.4 Supported Bit Stream Formats for TDM and Burst Transfer Modes ................................................ 78
9.5 Digital Audio Interface Transmitter (DIT) Transfer Mode (Transmitter Only) ...................................... 78
9.6 McASP Flexible Clock Generators ...................................................................................... 79
9.7 McASP Error Handling and Management .............................................................................. 79
9.8 McASP Interrupts and EDMA Events ................................................................................... 80
9.9 I
10 LOGIC AND POWER SUPPLY .............................................................................................. 82
2
C ........................................................................................................................... 80
2 Contents Copyright © 2003–2011, Texas Instruments Incorporated
SM320C6713-EP
SM320C6713B-EP
www.ti.com
10.1 General-Purpose Input/Output (GPIO) ................................................................................. 82
10.2 Power-Down Mode Logic ................................................................................................. 83
10.2.1 Triggering, Wake-Up, and Effects ............................................................................ 83
10.3 Power-Supply Sequencing ............................................................................................... 84
10.3.1 System-Level Design Considerations ........................................................................ 85
10.3.2 Power-Supply Design Considerations ....................................................................... 85
10.4 Power-Supply Decoupling ................................................................................................ 85
10.5 IEEE Std 1149.1 JTAG Compatibility Statement ...................................................................... 85
10.6 EMIF Device Speed ....................................................................................................... 86
10.7 EMIF Big Endian Mode Correctness (C6713B Only) ................................................................. 87
10.8 Bootmode ................................................................................................................... 88
SGUS049K–AUGUST 2003– REVISED APRIL 2011
11 PARAMETRIC INFORMATION ............................................................................................. 89
11.1 Absolute Maximum Ratings .............................................................................................. 89
11.2 Recommended Operating Conditions .................................................................................. 89
11.3 Electrical Characteristics ................................................................................................. 90
11.4 Parameter Measurement Information ................................................................................... 91
11.4.1 Timing Information .............................................................................................. 91
11.4.2 Signal Transition Levels ....................................................................................... 91
11.4.3 AC Transient Rise/Fall Time Specifications ................................................................. 92
11.4.4 Timing Parameters and Board Routing Analysis ........................................................... 93
11.5 Input and Output Clocks .................................................................................................. 94
11.6 Asynchronous Memory Timing .......................................................................................... 97
11.7 Synchronous-Burst Memory Timing ................................................................................... 100
11.8 Synchronous DRAM Timing ............................................................................................ 101
11.9 HOLD/HOLDA Timing ................................................................................................... 106
11.10 BUSREQ Timing ......................................................................................................... 106
11.11 Reset Timing ............................................................................................................. 107
11.12 External Interrupt Timing ............................................................................................... 109
11.13 Multichannel Audio Serial Port (McASP) Timing .................................................................... 110
11.14 Inter-Integrated Circuits (I
11.15 Host-Port Interface Timing .............................................................................................. 115
11.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 119
11.17 Timer Timing ............................................................................................................. 126
11.18 General-Purpose Input/Output (GPIO) Port Timing ................................................................. 127
11.19 JTAG Test Port Timing .................................................................................................. 128
2
C) Timing .................................................................................. 113
12 MECHANICAL DATA ........................................................................................................ 129
12.1 Mechanical Information .................................................................................................. 129
12.2 Packaging Information ................................................................................................... 129
Copyright © 2003–2011, Texas Instruments Incorporated Contents 3
SM320C6713-EP
SM320C6713B-EP
SGUS049K–AUGUST 2003– REVISED APRIL 2011
www.ti.com
List of Figures
4-1 320C67x™ CPU (DSP Core) Data Paths..................................................................................... 19
4-2 L2 Memory Configuration ....................................................................................................... 21
4-3 EDMA Channel Parameter Entries (Six Words) for Each EDMA Event .................................................. 25
4-4 CPU (DSP Core) and Peripheral Signals ..................................................................................... 31
4-5 Peripheral Signals................................................................................................................ 32
4-6 Peripheral Signals................................................................................................................ 33
4-7 Peripheral Signals................................................................................................................ 34
4-8 Peripheral Signals................................................................................................................ 34
5-1 Configuration Example A (Two I2C + Two McASP + GPIO) ............................................................... 42
5-2 Configuration Example B (One I2C + One McBSP + Two McASP + GPIO) ............................................. 43
5-3 Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO] .................................. 44
5-4 Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers] ....................... 45
5-5 Configuration Example E (1 I2C + HPI + 1 McASP)......................................................................... 46
5-6 Configuration Example F (One McBSP + HPI + One McASP)............................................................. 47
6-1 TMS320C6000™ DSP Device Nomenclature (Including SM320C6713 and C6713B Devices)....................... 57
7-1 CPU Control Status Register (CPU CSR) .................................................................................... 59
7-2 Cache Configuration (CCFG) Register........................................................................................ 61
8-1 PLL and Clock Generator Logic................................................................................................ 68
9-1 McASP0 and McASP1 Configuration.......................................................................................... 76
9-2 I2Cx Module Block Diagram .................................................................................................... 81
10-1 GPIO Enable (GPEN) Register (Hex Address: 01B0 0000) ............................................................... 82
10-2 GPIO Direction (GPDIR) Register (Hex Address: 01B0 0004) ............................................................ 82
10-3 Power-Down Mode Logic........................................................................................................ 83
10-4 PWRD Field of the CSR ........................................................................................................ 84
10-5 Schottky Diode Diagram......................................................................................................... 85
10-6 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1) (C6713B Only) .................................... 87
10-7 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0) (C6713B Only) .................................... 88
11-1 Test Load Circuit for AC Timing Measurements ............................................................................. 91
11-2 Input and Output Voltage Reference Levels for AC Timing Measurements.............................................. 91
11-3 Rise and Fall Transition Time Voltage Reference Levels................................................................... 91
11-4 AC Transient Specification Rise Time......................................................................................... 92
11-5 AC Transient Specification Fall Time .......................................................................................... 92
11-6 Board-Level Input/Output Timings ............................................................................................. 94
11-7 CLKIN.............................................................................................................................. 94
11-8 CLKOUT2 ......................................................................................................................... 94
11-9 CLKOUT3 ......................................................................................................................... 95
11-10 ECLKIN............................................................................................................................ 95
11-11 ECLKOUT......................................................................................................................... 96
11-12 Asynchronous Memory Read................................................................................................... 99
11-13 Asynchronous Memory Write................................................................................................... 99
11-14 SBSRAM Read Timing......................................................................................................... 101
11-15 SBSRAM Write Timing......................................................................................................... 101
11-16 SDRAM Read Command (CAS Latency 3) ................................................................................. 103
11-17 SDRAM Write Command...................................................................................................... 103
11-18 SDRAM ACTV Command ..................................................................................................... 104
11-19 SDRAM DCAB Command..................................................................................................... 104
11-20 SDRAM DEAC Command..................................................................................................... 105
4 List of Figures Copyright © 2003–2011, Texas Instruments Incorporated
SM320C6713-EP
SM320C6713B-EP
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SGUS049K–AUGUST 2003– REVISED APRIL 2011
11-21 SDRAM REFR Command..................................................................................................... 105
11-22 SDRAM MRS Command ...................................................................................................... 105
11-23 HOLD/HOLDA Timing.......................................................................................................... 106
11-24 BUSREQ......................................................................................................................... 107
11-25 Reset Timing .................................................................................................................... 108
11-26 External/NMI Interrupt.......................................................................................................... 109
11-27 McASP Input Timings .......................................................................................................... 112
11-28 McASP Output Timings........................................................................................................ 112
11-29 I
11-30 I
2
C Receive...................................................................................................................... 113
2
C Transmit Timings........................................................................................................... 114
11-31 HPI Read Timing (HAS Not Used, Tied High) .............................................................................. 117
11-32 HPI Read Timing (HAS Used) ................................................................................................ 117
11-33 HPI Write Timing (HAS Not Used, Tied High) .............................................................................. 118
11-34 HPI Write Timing (HAS Used)................................................................................................. 118
11-35 McBSP Timings................................................................................................................. 121
11-36 FSR Timing When GSYNC = 1............................................................................................... 121
11-37 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 122
11-38 McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0............................................................ 123
11-39 McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1............................................................ 124
11-40 McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1............................................................ 125
11-41 Timer ............................................................................................................................. 126
11-42 GPIO Port Timing............................................................................................................... 127
11-43 JTAG Test-Port Timing......................................................................................................... 128
Copyright © 2003–2011, Texas Instruments Incorporated List of Figures 5
SM320C6713-EP
SM320C6713B-EP
SGUS049K–AUGUST 2003– REVISED APRIL 2011
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List of Tables
3-1 Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) ................................................ 12
3-2 Characteristics of the C6713 and C6713B Processor....................................................................... 16
4-1 320C6713/13B Memory Map Summary ...................................................................................... 20
4-2 EMIF Registers ................................................................................................................... 22
4-3 L2 Cache Registers .............................................................................................................. 23
4-4 Interrupt Selector Registers..................................................................................................... 23
4-5 Device Registers ................................................................................................................. 24
4-6 EDMA Parameter RAM ......................................................................................................... 24
4-7 EDMA Registers.................................................................................................................. 25
4-8 Quick DMA (QDMA) and Pseudo Registers ................................................................................. 25
4-9 PLL Controller Registers ........................................................................................................ 25
4-10 McASP0 and McASP1 Registers .............................................................................................. 26
4-11 I2C0 and I2C1 Registers........................................................................................................ 28
4-12 HPI Registers ..................................................................................................................... 28
4-13 Timer 0 and Timer 1 Registers ................................................................................................. 28
4-14 McBSP0 and McBSP1 Registers .............................................................................................. 28
4-15 GPIO Registers................................................................................................................... 29
5-1 Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [13B only], and CLKMODE0) ................... 35
5-2 HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins) .................................. 36
5-3 Device Configuration Register (DEVCFG) [Address Location: 0x019C0200−0x019C02FF] .......................... 36
5-4 Device Configuration Register (DEVCFG) Selection Bit Descriptions .................................................... 37
5-5 Peripheral Pin Selection Matrix ................................................................................................ 38
5-6 C6713/13B Device Multiplexed/Shared Pins ................................................................................. 38
6-1 320C6713 and C6713B Device Part Numbers (P/Ns) and Ordering Information ....................................... 57
7-1 CPU CSR Bit Field Description ................................................................................................ 60
7-2 CCFG Register Bit Field Description .......................................................................................... 61
7-3 DSP Interrupts .................................................................................................................... 61
7-4 Interrupt Selector ................................................................................................................. 63
7-5 External Interrupt Sources and Peripheral Module Control................................................................. 64
7-6 EDMA Channels.................................................................................................................. 65
7-7 EDMA Selector ................................................................................................................... 66
7-8 EDMA Event Selector Registers (ESEL0 Register (0x01A0 FF00) ....................................................... 67
7-9 EDMA Event Selector Registers—ESEL1 Register (0x01A0 FF04) ...................................................... 67
7-10 EDMA Event Selector Registers—ESEL3 Register (0x01A0 FF0C) ..................................................... 67
7-11 EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description............................................ 67
8-1 PLL Lock and Reset Times ..................................................................................................... 69
8-2 CLKOUT Signals, Default Settings, and Control............................................................................. 69
8-3 PLL Clock Frequency Ranges ................................................................................................. 70
8-4 PLL Control/Status Register (PLLCSR) (0x01B7 C100) ................................................................... 70
8-5 PLL Control/Status Register (PLLCSR) Description......................................................................... 71
8-6 PLL Multiplier (PLLM) Control Register (0x01B7 C110) .................................................................... 71
8-7 PLL Multiplier (PLLM) Control Register Description......................................................................... 72
8-8 PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3)
(0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively) ....................................... 72
8-9 PLL Wrapper Divider x Registers
(Prescaler Divider D0 and Post-Scaler Dividers D1, D2, and D3) Description .......................................... 72
8-10 Oscillator Divider 1 (OSCDIV1) Register (0x01B7 C124) .................................................................. 73
6 List of Tables Copyright © 2003–2011, Texas Instruments Incorporated
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SM320C6713B-EP
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SGUS049K–AUGUST 2003– REVISED APRIL 2011
8-11 Oscillator Divider 1 (OSCDIV1) Register Description ....................................................................... 74
10-1 Characteristics of the Power-Down Modes ................................................................................... 84
10-2 C6713/13B Example Boards and Maximum EMIF Speed.................................................................. 87
11-1 Board-Level Timings Example (see ) .......................................................................................... 93
11-2 Timing Requirements for CLKIN ............................................................................................... 94
11-3 Switching Characteristics for CLKOUT2 ...................................................................................... 94
11-4 Switching Characteristics for CLKOUT3 ...................................................................................... 95
11-5 Timing Requirements for ECLKIN ............................................................................................. 95
11-6 Switching Characteristics for ECLKOUT ..................................................................................... 96
11-7 Timing Requirements for Asynchronous Memory Cycles .................................................................. 97
11-8 Switching Characteristics for Asynchronous Memory Cycles ............................................................. 97
11-9 Timing Requirements for Synchronous-Burst SRAM Cycles ............................................................. 100
11-10 Switching Characteristics for Synchronous-Burst SRAM Cycles ........................................................ 100
11-11 Timing Requirements for Synchronous DRAM Cycles .................................................................... 101
11-12 Switching Characteristics for Synchronous DRAM Cycles ............................................................... 101
11-13 Timing Requirements for HOLD/HOLDA Cycles ........................................................................... 106
11-14 Switching Characteristics for HOLD/HOLDA Cycles ...................................................................... 106
11-15 Switching Characteristics for BUSREQ Cycles ............................................................................ 106
11-16 Timing Requirements for RESET ............................................................................................ 107
11-17 Switching Characteristics For RESET ....................................................................................... 107
11-18 Timing Requirements for External Interrupts ............................................................................... 109
11-19 Timing Requirements for McASP ............................................................................................ 110
11-20 Switching Characteristics for McASP ........................................................................................ 110
11-21 Timing Requirements for I
11-22 Switching Characteristics for I
2
C ................................................................................................. 113
2
C ............................................................................................. 114
11-23 Timing Requirements for Host-Port Interface Cycles ..................................................................... 115
11-24 Switching Characteristics for Host-Port Interface Cycles ................................................................. 116
11-25 Timing Requirements for McBSP ............................................................................................ 119
11-26 Switching Characteristics for McBSP ........................................................................................ 120
11-27 Timing Requirements for FSR When GSYNC = 1 ......................................................................... 121
11-28 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 0 .................................................................................................... 121
11-29 Switching Characteristics for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 0 .................................................................................................... 122
11-30 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 0 .................................................................................................... 122
11-31 Switching Characteristics for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 0 .................................................................................................... 123
11-32 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1 .................................................................................................... 124
11-33 Switching Characteristics for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1 .................................................................................................... 124
11-34 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ............................. 125
11-35 Switching Characteristics for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 1 .................................................................................................... 125
11-36 Timing Requirements for Timer Inputs ...................................................................................... 126
11-37 Switching Characteristics for Timer Inputs ................................................................................. 126
11-38 Timing Requirements for GPIO Inputs ...................................................................................... 127
11-39 Switching Characteristics for GPIO Inputs .................................................................................. 127
11-40 Timing Requirements for JTAG Test Port .................................................................................. 128
Copyright © 2003–2011, Texas Instruments Incorporated List of Tables 7
SM320C6713-EP
SM320C6713B-EP
SGUS049K–AUGUST 2003– REVISED APRIL 2011
11-41 Switching Characteristics for JTAG Test Port .............................................................................. 128
12-1 Thermal Resistance Characteristics (S-PBGA Package) for GDP....................................................... 129
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8 List of Tables Copyright © 2003–2011, Texas Instruments Incorporated
SM320C6713-EP
SM320C6713B-EP
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SGUS049K–AUGUST 2003– REVISED APRIL 2011
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
Check for Samples: SM320C6713-EP
1 FEATURES
1
2
• Highest Performance Floating Point Digital • 32 Bit External Memory Interface (EMIF)
Signal Processors (DSPs): C6713/C6713B
– Eight 32 Bit Instructions/Cycle SBSRAM, and SDRAM
– 32/64 Bit Data Word – 512M Byte Total Addressable External
– 200 and 300 MHz Clock Rate
– 5 Instruction Cycle Times
– 2400/1800 and 1600/1200 MIPS/MFLOPS
– Rich Peripheral Set, Optimized for Audio
– Highly Optimized C/C++ Compiler
• Advanced Very Long Instruction Word (VLIW)
320C67x™ DSP Core
– Eight Independent Functional Units:
• Two ALUs (Fixed Point)
• Four ALUs (Floating Point and Fixed
Point)
• Two Multipliers (Floating Point and Fixed
Point)
– Load Store Architecture With 32 32-Bit
General Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
• Instruction Set Features
– Native Instructions for IEEE 754
– Byte Addressable (8/16/32 Bit Data)
– 8 Bit Overflow Protection
– Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
• L1/L2 Memory Architecture
– 4K Byte L1P Program Cache (Direct-Mapped)
– 4K Byte L1D Data Cache (2-Way)
– 256K Byte L2 Memory Total: 64K-Byte L2
Unified Cache/Mapped RAM, and 192K Byte
Additional L2 Mapped RAM
• Device Configuration
– Boot Mode: HPI, 8/16/32 Bit ROM Boot
– Endianness: Little Endian, Big Endian
– Glueless Interface to SRAM, EPROM, Flash,
Memory Space
• Enhanced Direct Memory Access (EDMA)
Controller (16 Independent Channels)
• 16 Bit Host Port Interface (HPI)
• Two Multichannel Audio Serial Ports (McASPs)
– Two Independent Clock Zones Each
(One TX and One RX)
– Eight Serial Data Pins Per Port: Individually
Assignable to any of the Clock Zones
– Wide Variety of I2S™ and Similar Bit Stream
Formats
– Integrated Digital Audio Interface Transmitter
(DIT)
– Extensive Error Checking and Recovery
• Two Inter-Integrated Circuit Bus (I2C™ Bus)
Multi-Master and Slave Interfaces
• Two Multichannel Buffered Serial Ports:
– Serial Peripheral Interface (SPI)
– High Speed TDM Interface
– AC97 Interface
• Two 32 Bit General Purpose Timers
• Dedicated GPIO Module With 16 Pins (External
Interrupt Capable)
• Flexible Phase Locked Loop (PLL) Based Clock
Generator Module
• IEEE-1149.1 (JTAG)
(1)
Boundary-Scan
Compatible
• 272 Ball, Ball Grid Array Package (GDP)
• 0.13 μm/6 Level Copper Metal Process
– CMOS Technology
• 3.3 V I/Os, 1.26 V Internal
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and
Boundary Scan Architecture.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2320C67x, TMS320C6000, TMS320C67x, eXpressDSP, Code Composer Studio, DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x, C67x
are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2011, Texas Instruments Incorporated
SM320C6713-EP
SM320C6713B-EP
SGUS049K–AUGUST 2003– REVISED APRIL 2011
2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
3
• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
• Available in Military (–55°C/125°C) Temperature
Range
(2) Custom temperature ranges available
(2)
break
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
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3320C67x, TMS320C6000, TMS320C67x, eXpressDSP, Code Composer Studio, DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x, C67x
are trademarks of Texas Instruments.
10 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Copyright © 2003–2011, Texas Instruments Incorporated
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V
SSVSSVSSVSS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
EA20
DV
DD
EA18EA16
EA14
V
SS
CLKOUT2/
GP[2]
ECLKIN
ECLKOUT
EA9
EA7DV
DD
EA2ARDY
BE2
ED18
V
SS
V
SS
V
SS
CVDDDV
DD
ED17
V
SS
CE2
EA4
EA6
DV
DD
AOE
SDRAS
SSOE
/
/
AWE
SDWE
SSWE
/
/
ARE
SDCAS
SSADS
/
/
V
SS
DV
DD
EA11
EA13 EA15
V
SS
EA19
CE1
CV
DD
V
SS
BE0
DV
DD
CV
DD
CE0
EA17
DV
DD
EA12
DV
DD
EA10EA8EA5EA3
CE3
BE3
ED16
CV
DD
ED19ED20
ED22
ED28
SCL0
FSX1
CLKR1/
AXR0[6]
DR1/
SDA1
DR0/
AXR0[0]
DX0/
AXR0[1]
FSR1/
AXR0[7]
DV
DD
ED24
ED21
ED29
SDA0
DX1
AXR0[5]
CLKX1/
AMUTE0
CLKS1/
SCL1
GP[5]
(EXT_INT5)
AMUTEIN0
GP[4]
(EXT_INT4)
AMUTEIN1
GP[7]
(EXT_INT7)
GP[6]
(EXT_INT6)
CLKS0
AHCLKR0
ED27
ED25
ED23
ED30
ED31
ED26
DV
DD
EA21
BE1
V
SS
V
SS
V
SS
V
SS
CV
DD
V
SS
CV
DD
V
SS
DV
DD
CV
DD
DVDDVSSV
SS
V
SS
V
SS
CV
DD
CV
DD
CV
DD
CV
DD
DV
DD
DV
DD
V
SS
V
SS
V
SS
CV
DD
CV
DD
CV
DD
V
SS
ED13
ED6
ED9
DV
DD
ED2
ED0
DV
DD
ED15
ED7
V
SS
ED11
ED3
ED1
ED4
ED14
ED8
ED10
ED12
CV
DD
V
SS
ED5
HOLD
HINT/
GP[1]
HRDY/
ACLKR[1]
HCS/
AXR1[1]
HAS/
ACLKX1
HDS/
AXR1[6]
HDS2/
AXR1[5]
HCNTL1/
AXR1[1]
HCNTL0/
AXR1[3]
HD6/
AHCLKR1
HD9/
GP[9]
HD5/
AHCLKX1
HD12/
GP[12]
HD14/
GP[14]
HD15/
GP[15]
HD13/
GP[13]
HD11/
GP[11]
HD10/
GP[10]
HD8/
GP[8]
HD7/
GP[3]
HD4/
GP[0]
HD2/
AFSX1
HD3/
AMUTE1
HD1/
AXR1[7]
HHWIL/
AFSR[1]
HD0/
AXR1[4]
HR/ /
AXR1[0]
W
HOLDA
BUS
REQ
V
SS
V
SS
V
SS
V
SS
V
SS
DV
DD
CV
DD
CV
DD
V
SS
CV
DD
DV
DD
FSR0/
AFSR0
CLKR0/
ACLKR0
CLKX0/
ACLKX0
TOUT0/
AXR0[2]
TOUT1/
AXR0[4]
TINP0/
AXR0[3]
TINP1/
AHCLKX0
FSX0/
AFSX0
V
SS
V
SS
V
SS
DV
DD
DV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
DV
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
EMU2
CLKIN
CLK
MODE0
PLLHV
RSV
RSV
CV
DD
V
SS
TRST
TCK
TDI
TMS
CV
DD
CV
DD
CVDDCV
DD
CV
DD
CV
DD
DV
DD
DV
DD
DV
DD
DV
DD
RSV RSV
RSV
RSV
V
SS
V
SSVSS
TD0
CV
DD
EMU1
EMU0
CLKOUT3
DV
DD
EMU3
CV
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
RSV
EMU4
EMU5
NMI
RESET
DV
DD
1 2
3
4
5 6
7
8 9 10
11 12
13
14
15 16
17
18 19 20
ShadingdenotestheGDPpackagepinfunctionsthatdropoutonthePYPpackage.
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3 DEVICE INFORMATION
GDP 272-BALL BGA PACKAGE
(BOTTOM VIEW)
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Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.)
BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME
A1 V
A2 V
A3 CLKIN C3 CV
A4 CV
A5 RSV C5 PLLHV
A6 TCK C6 V
A7 TDI C7 CV
A8 TDO C8 V
A9 CV
A10 CV
A11 V
A12 RSV (connected directly to CVDD) C12 RSV
A13 RESET C13 NMI
A14 V
A15 HD13/GP[13] C15 HD12/GP[12]
A16 HD11/GP[11] C16 HD9/GP[9]
A17 DV
A18 HD7/GP[3] C18 CV
A19 V
A20 V
B1 V
B2 CV
B3 DV
B4 V
B5 RSV D5 CV
B6 TRST D6 CV
B7 TMS D7 RSV
B8 DV
B9 EMU1 D9 EMU0
B10 EMU3 D10 CLKOUT3
B11 RSV (connected directly to VSS) D11 CV
B12 EMU5 D12 RSV
B13 DV
B14 HD15/GP[15] D14 CV
B15 V
B16 HD10/GP[10] D16 DV
B17 HD8/GP[8] D17 V
B18 HD5/AHCLKX1 D18 HD2/AFSX1
B19 CV
B20 V
E1 CLKS1/SCL1 J17 HOLD
E2 V
E3 GP[7]/(EXP_INT7) J19 BUSREQ
E4 V
E17 V
E18 HAS/ACLKX1 K2 V
E19 HDS1/AXR1[6] K3 CLKS0/AHCLKR0
E20 HD0/AXR1[4] K4 CV
F1 TOUT1/AXR0[4] K9 V
F2 TINP1/AHCLKX0 K10 V
F3 DV
SS
SS
DD
DD
DD
SS
SS
DD
SS
SS
SS
DD
DD
SS
DD
DD
SS
DD
SS
SS
SS
SS
DD
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C1 GP[5](EXT_INT5)/AMUTEIN0
C2 GP[4](EXT_INT4)/AMUTEIN1
DD
C4 CLKMODE0
SS
DD
SS
C9 V
C10 DV
SS
DD
C11 EMU4
C14 HD14/GP[14]
C17 HD6/AHCLKR1
DD
C19 HD4/GP[0]
C20 HD3/AMUTE1
D1 DV
DD
D2 GP[6](EXT_INT6)
D3 EMU2
D4 V
D8 V
D13 V
D15 CV
D19 DV
SS
DD
DD
SS
DD
SS
DD
DD
DD
SS
DD
D20 HD1/AXR1[7]
J18 HOLDA
J20 HINT/GP[1]
K1 CV
K11 V
DD
SS
DD
SS
SS
SS
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Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) (continued)
SGUS049K–AUGUST 2003– REVISED APRIL 2011
BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME
F4 CV
F17 CV
DD
DD
K12 V
K17 CV
SS
DD
F18 HDS2/AXR1[5] K18 ED0
F19 V
SS
F20 HCS/AXR1[2] K20 V
K19 ED1
SS
G1 TOUT0/AXR0[2] L1 FSX1
G2 TINP0/AXR0[3] L2 DX1/AXR0[5]
G3 CLKX0/ACLKX0 L3 CLKX1/AMUTE0
G4 V
G17 V
SS
SS
G18 HCNTL0/AXR1[3] L10 V
G19 HCNTL1/AXR1[1] L11 V
G20 HR/W/AXR1[0] L12 V
H1 FSX0/AFSX0 L17 CV
L4 CV
L9 V
DD
SS
SS
SS
SS
DD
H2 DX0/AXR0[1] L18 ED2
H3 CLKR0/ACLKR0 L19 ED3
H4 V
H17 V
H18 DV
SS
SS
DD
L20 CV
DD
M1 CLKR1/AXR0[6]
M2 DR1/SDA1
H19 HRDY/ACLKR1 M3 FSR1/AXR0[7]
H20 HHWIL/AFSR1 M4 V
J1 DR0/AXR0[0] M9 V
J2 DV
DD
M10 V
J3 FSR0/AFSR0 M11 V
J4 V
J9 V
J10 V
J11 V
J12 V
SS
SS
SS
SS
SS
M12 V
M17 V
M18 DV
M19 ED4
M20 ED5
N1 SCL0 U9 V
N2 SDA0 U10 CV
N3 ED31 U11 CV
N4 V
N17 V
SS
SS
U12 DV
U13 V
N18 ED6 U14 CV
N19 ED7 U15 CV
N20 ED8 U16 DV
P1 ED28 U17 V
SS
SS
SS
SS
SS
SS
DD
SS
DD
DD
DD
SS
DD
DD
DD
SS
P2 ED29 U18 EA21
P3 ED30 U19 BE1
P4 V
P17 V
SS
SS
U20 V
SS
V1 ED20
P18 ED9 V2 ED19
P19 V
SS
V3 CV
DD
P20 ED10 V4 ED16
R1 DV
DD
V5 BE3
R2 ED27 V6 CE3
R3 ED26 V7 EA3
R4 CV
R17 CV
R18 DV
DD
DD
DD
V8 EA5
V9 EA8
V10 EA10
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Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) (continued)
BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME
R19 ED11 V11 ARE/SDCAS/SSADS
R20 ED12 V12 AWE/SDWE/SSWE
T1 ED24 V13 DV
T2 ED25 V14 EA17
T3 DV
T4 V
T17 V
T18 ED13 V18 CV
T19 ED15 V19 DV
T20 ED14 V20 BE0
U1 ED22 W1 V
U2 ED21 W2 CV
U3 ED23 W3 DV
U4 V
U5 DV
U6 CV
U7 DV
U8 V
W9 DV
W10 AOE/SDRAS/SSOE Y6 EA2
W11 V
W12 DV
W13 EA11 Y9 EA9
W14 EA13 Y10 ECLKOUT
W15 EA15 Y11 ECLKIN
W16 V
W17 EA19 Y13 V
W18 CE1 Y14 EA14
W19 CV
W20 V
Y1 V
Y2 V
Y3 ED18 Y19 V
Y4 BE2 Y20 V
DD
SS
SS
SS
DD
DD
DD
SS
DD
SS
DD
SS
DD
SS
SS
SS
DD
V15 DV
V16 EA
V17 CE0
W4 ED17
W5 V
W6 CE2
W7 EA4
W8 EA6
Y5 ARDY
Y7 DV
Y8 EA7
Y12 CLKOUT2/GP[2]
Y15 EA16
Y16 EA18
Y17 DV
Y18 EA20
DD
DD
DD
SS
DD
DD
SS
DD
SS
DD
SS
SS
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3.1 Description
The TMS320C67x™ DSPs (including the SM320C6713 and SM320C6713B devices) compose the
floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713 and C6713B devices are
based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction
applications. Throughout the remainder of this document, the SM320C6713 and SM320C6713B are
referred to as 320C67x or C67x or 13/13B where generic, and where specific, their individual full device
part numbers are used or abbreviated as C6713, C6713B, 13, or 13B, and so forth.
Operating at 225 MHz, the C6713/13B delivers up to 1350 million floating-point operations per second
(MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to
450 million multiply-accumulate operations per second (MMACS).
Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second
(MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to
600 million multiply-accumulate operations per second (MMACS).
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The C6713/13B has a rich peripheral set that includes two multichannel audio serial ports (McASPs), two
multichannel buffered serial ports (McBSPs), two inter-integrated circuit (I2C) buses, one dedicated
general-purpose input/output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and
a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and
asynchronous peripherals.
The two McASP interface modules each support one transmit and one receive clock zone. Each of the
McASPs has eight serial data pins that can be individually allocated to any of the two zones. The serial
port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713/13B has sufficient
bandwidth to support all 16 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone
may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude
of variations on the Philips Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, and
CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of
user data and channel status fields.
The McASP also provides extensive error-checking and recovery features, such as the bad clock
detection circuit for each high-frequency master clock, which verifies that the master clock is within a
programmed frequency range.
The two I2C ports on the 320C6713/13B allow the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP)
may be used to communicate with serial peripheral interface (SPI™) mode peripheral devices.
SGUS049K–AUGUST 2003– REVISED APRIL 2011
The 320C6713/13B device has two boot modes—from the HPI or from external asynchronous ROM. For
more detailed information, see the Bootmode section of this data sheet.
The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark
development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated
Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™
kernel.
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3.2 Device Characteristics
Table 3-2 provides an overview of the C6713/C6713B DSPs. The table shows significant features of each
device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type
with pin count. For more details on the C67x™ DSP device part numbers and part numbering, see
Table 6-1 and Figure 6-1.
Table 3-2. Characteristics of the C6713 and C6713B Processor
HARDWARE FEATURES
EMIF SYSCLK3 or ECLKIN 1 (32 bit)
EDMA
(16 channels)
Peripherals
Not all peripheral pins are available at the
same time. (For more details, see the
Device Configurations section.)
Peripheral performance is dependent on
chip-level configuration.
On-chip memory Size (Bytes) 264K
CPU ID+CPU Rev ID Control Status Register (CSR[31:16]) 0x0203
BSDL file For the C6713/13B BSDL file, contact your field sales representative.
Frequency MHz 200
Time ns 5 ns
Voltage
Clock generator options Multiplier ×4, ×5, ×6, ..., ×25
Package 27 mm × 27 mm 272-ball BGA (GDP)
Process technology μm 0.13
Product status
Product preview (PP)
Advance information (AI)
Production data (PD)
(1) AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock
check (high-frequency) circuit.
(2) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
(2)
HPI (16 bit) SYSCLK2 1
McASPs 2
I2Cs SYSCLK2 2
McBSPs SYSCLK2 2
32-bit timers � of SYSCLK2 2
GPIO module SYSCLK2 1
Organization
Core (V) 1.26 V (C6713/C6713B)
I/O (V) 3.3 V
Prescaler /1, /2, /3, ..., /32
Postscaler /1, /2, /3, ..., /32
INTERNAL CLOCK
SOURCE
CPU clock frequency 1
AUXCLK,
SYSCLK2
(1)
4K-Byte (KB) L1 program (L1P) cache
4KB L1 data (L1D) cache
64KB unified L2 cache/mapped RAM
192KB L2 mapped RAM
C6713/C6713B
(FLOATING-POINT DSPs)
GDP
PD (13)
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Test
C67xä CPU
DataPath B
BRegisterFile
InstructionFetch
InstructionDispatch
InstructionDecode
DataPath A
ARegisterFile
Power-Down
Logic
.L1
(A) (A) (A) (A) (A) (A)
.S1 .M1 .D1. D2 .M2 .S2 .L2
L1PCache
DirectMapped
4KBytesTotal
Control
Registers
Control
Logic
L1DCache
2-Way
SetAssociative
4KBytes
In-Circuit
Emulation
Interrupt
Control
C6713/13B DigitalSignalProcessors
Enhanced
DMA
Controller
(16 channel)
L2Cache/
Memory
4Banks
64KBytes
Total
(upto
4-Way)
ClockGeneratorandPLL
x4throughx25Multiplier
/1through/32Dividers
L2
Memory
192K
Bytes
EMIF
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer1
Timer0
GPIO
HPI
PinMultiplexing
32
16
NOTEA: Inadditiontofixed-pointinstructions,thesefunctionalunitsexecutefloating-pointinstructions.
EMIFinterfacesto: McBSPsinterfaceto: McASPsinterfaceto:
SDRAM- - -
- - -
- -
- -
SPIcontrolport I SmultichannelADC,DAC,codec,DIR
SBSRAM High-speedTDMcodecs DIT:Multipleoutputs
SRAM AC97codecs
ROM/flashand SerialEEPROM
I/Odevices
2
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SM320C6713B-EP
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3.3 Functional Block and CPU (DSP Core) Diagram
SGUS049K–AUGUST 2003– REVISED APRIL 2011
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4 OVERVIEW
4.1 CPU (DSP Core) Description
The 320C6713/13B floating-point digital signal processor is based on the C67x CPU. The CPU fetches
advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the
eight functional units during every clock cycle. The VLIW architecture features controls by which all eight
units do not have to be supplied with instructions if they are not ready to execute. The first bit of every
32-bit instruction determines if the next instruction belongs to the same execute packet as the previous
instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other
VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set
contains functional units .L1, .S1, .M1, and .D1. The other set contains units .D2, .M2, .S2, and .L2. The
two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets
of functional units, along with two register files, compose sides A and B of the CPU (see the Functional
Block and CPU (DSP Core) Diagram and Figure 4-1). The four functional units on each side of the CPU
can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data
from the register files on the opposite side. While register access by functional units on the same side of
the CPU as the register file can service all the units in a single clock cycle, register access using the
register file across the CPU supports one read and one write per cycle.
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The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of
eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The
remaining two functional units (.D1 and .D2) also execute the new LDDW instruction, which loads 64 bits
per CPU side for a total of 128 bits per cycle.
Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on
registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are
responsible for all data transfers between the register files and the memory. The data address driven by
the .D units allows data addresses generated from one register file to be used to load or store data to or
from the other register file. The C67x CPU supports a variety of indirect addressing modes using either
linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can
access any one of the 32 registers. Some registers, however, are singled out to support specific
addressing or to hold the condition for conditional instructions (if the condition is not automatically true).
The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a
general set of arithmetic, logical, and branch functions with results available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program
memory. The 32-bit instructions destined for the individual functional units are chained together by 1 bits
in the least significant bit (LSB) position of the instructions. The instructions that are chained together for
simultaneous execution (up to eight in total) compose an execute packet. A 0 in the LSB of an instruction
breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute
packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet,
while the remainder of the current fetch packet is padded with NOP instructions. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their
respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not
fetched until all the execute packets from the current fetch packet have been dispatched. After decoding,
the instructions simultaneously drive all active functional units for a maximum execution rate of eight
instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently
moved to memory as bytes or half-words as well. All load and store instructions are byte, half-word, or
word addressable.
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8
8
long src
dst
src2
src1
src1
src1
src1
src1
src1
src1
src1
longdst
longdst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
longsrc
longsrc
longdst
longdst
longsrc
8
8
8
2X
1X
.L2
.S2
.M2
.D2
.D1
.M1
.S1
.L1
Control
RegisterFile
DA1
DA2
ST1
LD132LSB
LD232LSB
LD232MSB
32
32
DataPathA
DataPathB
Register
FileA
(A0−A15)
Register
FileB
(B0−B15)
LD132MSB
32
ST2
32
8
8
8
(A)
(A)
(A)
(A)
(A)
(A)
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SGUS049K–AUGUST 2003– REVISED APRIL 2011
A. In addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 4-1. 320C67x™ CPU (DSP Core) Data Paths
4.2 Memory Map Summary
Table 4-1 shows the memory map address ranges of the C6713/13B devices.
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Table 4-1. 320C6713/13B Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
Internal RAM (L2) 192K 0000 0000 0002 FFFF
Internal RAM/Cache 64K 0003 0000 0003 FFFF
Reserved 24M – 256K 0004 0000 017F FFFF
External Memory Interface (EMIF) Registers 256K 0180 0000 0183 FFFF
L2 Registers 128K 0184 0000 0185 FFFF
Reserved 128K 0186 0000 0187 FFFF
HPI Registers 256K 0188 0000 018B FFFF
McBSP 0 Registers 256K 018C 0000 018F FFFF
McBSP 1 Registers 256K 0190 0000 0193 FFFF
Timer 0 Registers 256K 0194 0000 0197 FFFF
Timer 1 Registers 256K 0198 0000 019B FFFF
Interrupt Selector Registers 512 019C 0000 019C 01FF
Device Configuration Registers 4 019C 0200 019C 0203
Reserved 256K − 516 019C 0204 019F FFFF
EDMA RAM and EDMA Registers 256K 01A0 0000 01A3 FFFF
Reserved 768K 01A4 0000 01AF FFFF
GPIO Registers 16K 01B0 0000 01B0 3FFF
Reserved 240K 01B0 4000 01B3 FFFF
I2C0 Registers 16K 01B4 0000 01B4 3FFF
I2C1 Registers 16K 01B4 4000 01B4 7FFF
Reserved 16K 01B4 8000 01B4 BFFF
McASP0 Registers 16K 01B4 C000 01B4 FFFF
McASP1 Registers 16K 01B5 0000 01B5 3FFF
Reserved 160K 01B5 4000 01B7 BFFF
PLL Registers 8K 01B7 C000 01B7 DFFF
Reserved 264K 01B7 E000 01BB FFFF
Emulation Registers 256K 01BC 0000 01BF FFFF
Reserved 4M 01C0 0000 01FF FFFF
QDMA Registers 52 0200 0000 0200 0033
Reserved 16M − 52 0200 0034 02FF FFFF
Reserved 720M 0300 0000 2FFF FFFF
McBSP0 Data Port 64M 3000 0000 33FF FFFF
McBSP1 Data Port 64M 3400 0000 37FF FFFF
Reserved 64M 3800 0000 3BFF FFFF
McASP0 Data Port 1M 3C00 0000 3C0F FFFF
McASP1 Data Port 1M 3C10 0000 3C1F FFFF
Reserved 1G + 62M 3C20 0000 7FFF FFFF
EMIF CE0
EMIF CE1
EMIF CE2
EMIF CE3
(1) The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.
(1)
(1)
(1)
(1)
Reserved 1G C000 0000 FFFF FFFF
256M 8000 0000 8FFF FFFF
256M 9000 0000 9FFF FFFF
256M A000 0000 AFFF FFFF
256M B000 0000 BFFF FFFF
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0x00000000
011010001 111
0x00030000
000
L2Mode L2Memory BlockBase Address
0x0003C000
0x00038000
0x00034000
0x0003FFFF
16K
1-Way
Cache
32K
2-WayCache
48K3-W
ayCache
64K4-W
ayCache
256KSRAM(All)
240KSRAM
224KSRAM
208KSRAM
192KSRAM
192K-ByteRAM
16K-ByteRAM
16K-ByteRAM
16K-ByteRAM
16K-ByteRAM
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4.3 L2 Memory Structure Expanded
Figure 4-2 shows the detail of the L2 memory structure.
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Figure 4-2. L2 Memory Configuration
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4.4 Peripheral Register Descriptions
Table 4-2 through Table 4-15 identify the peripheral registers for the C6713/C6713B devices by their
register names, acronyms, and hex address or hex address range. For more detailed information on the
register contents and bit names and their respective descriptions, see the specific peripheral reference
guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number
SPRU190).
Table 4-2. EMIF Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0180 0000 GBLCTL EMIF global control
0180 0004 CECTL1 EMIF CE1 space control
0180 0008 CECTL0 EMIF CE0 space control
0180 000C — Reserved
0180 0010 CECTL2 EMIF CE2 space control
0180 0014 CECTL3 EMIF CE3 space control
0180 0018 SDCTL EMIF SDRAM control
0180 001C SDTIM EMIF SDRAM refresh control
0180 0020 SDEXT EMIF SDRAM extension
0180 0024−0183 FFFF — Reserved
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Table 4-3. L2 Cache Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 0000 CCFG Cache configuration
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count
0184 4010 L2WIBAR L2 writeback-invalidate base address register
0184 4014 L2WIWC L2 writeback-invalidate word count
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count
0184 4030 L1DWIBAR L1D writeback-invalidate base address register
0184 4034 L1DWIWC L1D writeback-invalidate word count
0184 5000 L2WB L2 writeback all
0184 5004 L2WBINV L2 writeback-invalidate all
0184 8200 MAR0 Memory attribute register 0. Controls CE0 range 8000 0000 80FF FFFF
0184 8204 MAR1 Memory attribute register 1. Controls CE0 range 8100 0000 81FF FFFF
0184 8208 MAR2 Memory attribute register 2. Controls CE0 range 8200 0000 82FF FFFF
0184 820C MAR3 Memory attribute register 3. Controls CE0 range 8300 0000 83FF FFFF
0184 8240 MAR4 Memory attribute register 4. Controls CE1 range 9000 0000 90FF FFFF
0184 8244 MAR5 Memory attribute register 5. Controls CE1 range 9100 0000 91FF FFFF
0184 8248 MAR6 Memory attribute register 6. Controls CE1 range 9200 0000 92FF FFFF
0184 824C MAR7 Memory attribute register 7. Controls CE1 range 9300 0000 93FF FFFF
0184 8280 MAR8 Memory attribute register 8. Controls CE2 range A000 0000 A0FF FFFF
0184 8284 MAR9 Memory attribute register 9. Controls CE2 range A100 0000 A1FF FFFF
0184 8288 MAR10 Memory attribute register 10. Controls CE2 range A200 0000 A2FF FFFF
0184 828C MAR11 Memory attribute register 11. Controls CE2 range A300 0000 A3FF FFFF
0184 82C0 MAR12 Memory attribute register 12. Controls CE3 range B000 0000 B0FF FFFF
0184 82C4 MAR13 Memory attribute register 13. Controls CE3 range B100 0000 B1FF FFFF
0184 82C8 MAR14 Memory attribute register 14. Controls CE3 range B200 0000 B2FF FFFF
0184 82CC MAR15 Memory attribute register 15. Controls CE3 range B300 0000 B3FF FFFF
0184 82D0−0185 FFFF — Reserved
Table 4-4. Interrupt Selector Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
019C 0000 MUXH Interrupt multiplexer high
019C 0004 MUXL Interrupt multiplexer low
019C 0008 EXTPOL External interrupt polarity
019C 000C−019F FFFF — Reserved
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Selects which interrupts drive CPU interrupts
10–15 (INT10−INT15)
Selects which interrupts drive CPU interrupts
4−9 (INT04−INT09)
Sets the polarity of the external interrupts
(EXT_INT4−EXT_INT7)
31 0 EDMA Parameter
Word0 EDMAChannelOptionsParameter(OPT) OPT
Word1 EDMAChannelSourceAddress(SRC) SRC
Word2 Array/FrameCount(FRMCNT) ElementCount(ELECNT) CNT
Word3 EDMAChannelDestinationAddress(DST) DST
Word4 Array/FrameIndex(FRMIDX) ElementIndex(ELEIDX) IDX
Word5 ElementCountReload(ELERLD) LinkAddress(LINK) RLD
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Table 4-5. Device Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
Allows the user to control peripheral
selection. This register also offers the user
019C 0200 DEVCFG Device configuration
019C 0204−019F FFFF — Reserved
N/A CSR CPU control status register
Table 4-6. EDMA Parameter RAM
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0000 01A0 0017 — Parameters for Event 0 (6 words) or Reload/Link parameters for other event
01A0 0018 01A0 002F — Parameters for Event 1 (6 words) or Reload/Link parameters for other event
01A0 0030 01A0 0047 — Parameters for Event 2 (6 words) or Reload/Link parameters for other event
01A0 0048 01A0 005F — Parameters for Event 3 (6 words) or Reload/Link parameters for other event
01A0 0060 01A0 0077 — Parameters for Event 4 (6 words) or Reload/Link parameters for other event
01A0 0078 01A0 008F — Parameters for Event 5 (6 words) or Reload/Link parameters for other event
01A0 0090 01A0 00A7 — Parameters for Event 6 (6 words) or Reload/Link parameters for other event
01A0 00A8 01A0 00BF — Parameters for Event 7 (6 words) or Reload/Link parameters for other event
01A0 00C0 01A0 00D7 — Parameters for Event 8 (6 words) or Reload/Link parameters for other event
01A0 00D8 01A0 00EF — Parameters for Event 9 (6 words) or Reload/Link parameters for other event
01A0 00F0 01A0 00107 — Parameters for Event 10 (6 words) or Reload/Link parameters for other event
01A0 0108 01A0 011F — Parameters for Event 11 (6 words) or Reload/Link parameters for other event
01A0 0120 01A0 0137 — Parameters for Event 12 (6 words) or Reload/Link parameters for other event
01A0 0138 01A0 014F — Parameters for Event 13 (6 words) or Reload/Link parameters for other event
01A0 0150 01A0 0167 — Parameters for Event 14 (6 words) or Reload/Link parameters for other event
01A0 0168 01A0 017F — Parameters for Event 15 (6 words) or Reload/Link parameters for other event
01A0 0180 01A0 0197 — Reload/link parameters for Event 0−15
01A0 0198 01A0 01AF — Reload/link parameters for Event 0−15
... ... ...
01A0 07E0 01A0 07F7 — Reload/link parameters for Event 0−15
01A0 07F8 01A0 07FF — Scratch pad area (two words)
(1) The C6713/13B device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.
control of the EMIF input clock source. For
more detailed information on the device
configuration register, see the Device
Configurations section of this data sheet.
Identifies which CPU and defines the silicon
revision of the CPU. This register also offers
the user control of device operation. For more
detailed information on the CPU Control
Status Register, see the CPU CSR Register
description section of this data sheet.
(1)
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For more details on the EDMA parameter RAM six-word parameter entry structure, see Figure 4-3.
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Figure 4-3. EDMA Channel Parameter Entries (Six Words) for Each EDMA Event
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Table 4-7. EDMA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0800−01A0 FEFC — Reserved
01A0 FF00 ESEL0 EDMA event selector 0
01A0 FF04 ESEL1 EDMA event selector 1
01A0 FF08−01A0 FF0B — Reserved
01A0 FF0C ESEL3 EDMA event selector 3
01A0 FF1F−01A0 FFDC — Reserved
01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPR Channel interrupt pending register
01A0 FFE8 CIER Channel interrupt enable register
01A0 FFEC CCER Channel chain enable register
01A0 FFF0 ER Event register
01A0 FFF4 EER Event enable register
01A0 FFF8 ECR Event clear register
01A0 FFFC ESR Event set register
01A1 0000−01A3 FFFF — Reserved
Table 4-8. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0200 0000 QOPT QDMA options parameter
0200 0004 QSRC QDMA source address
0200 0008 QCNT QDMA frame count
0200 000C QDST QDMA destination address
0200 0010 QIDX QDMA index
0200 0014−0200 001C — Reserved
0200 0020 QSOPT QDMA pseudo options
0200 0024 QSSRC QDMA pseudo source address
0200 0028 QSCNT QDMA pseudo frame count
0200 002C QSDST QDMA pseudo destination address
0200 0030 QSIDX QDMA pseudo index
(1) All the QDMA and Pseudo registers are write accessible only.
SGUS049K–AUGUST 2003– REVISED APRIL 2011
(1)
Table 4-9. PLL Controller Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B7 C000 PLLPID Peripheral identification
01B7 C004−01B7 C0FF — Reserved
01B7 C100 PLLCSR PLL control/status register
01B7 C104−01B7 C10F — Reserved
01B7 C110 PLLM PLL multiplier control
01B7 C114 PLLDIV0 PLL controller divider 0
01B7 C118 PLLDIV1 PLL controller divider 1
01B7 C11C PLLDIV2 PLL controller divider 2
01B7 C120 PLLDIV3 PLL controller divider 3
01B7 C124 OSCDIV1 Oscillator divider 1
01B7 C128−01B7 DFFF — Reserved
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(C6713/13B value: 0x00010801 for PLL Controller)
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Table 4-10. McASP0 and McASP1 Registers
HEX ADDRESS RANGE
McASP0 McASP1
3C00 0000−3C00 FFFF 3C10 0000−3C10 FFFF RBUF/XBUFx data bus. Used when RSEL or XSEL bits = 0 (these bits are located
01B4 C000 01B5 0000 MCASPPIDx
01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management
01B4 C008 01B5 0008 — Reserved
01B4 C00C 01B5 000C — Reserved
01B4 C010 01B5 0010 PFUNCx Pin function
01B4 C014 01B5 0014 PDIRx Pin direction
01B4 C018 01B5 0018 PDOUTx Pin data out
01B4 C01C 01B5 001C PDIN/PDSETx Read returns: PDIN
01B4 C020 01B5 0020 PDCLRx Pin data clear
01B4 C024−01B4 C040 01B5 0024−01B5 0040 — Reserved
01B4 C044 01B5 0044 GBLCTLx Global control
01B4 C048 01B5 0048 AMUTEx Mute control
01B4 C04C 01B5 004C DLBCTLx Digital loopback control
01B4 C050 01B5 0050 DITCTLx DIT mode control
01B4 C054−01B4 C05C 01B5 0054−01B5 005C — Reserved
01B4 C060 01B5 0060 RGBLCTLx
01B4 C064 01B5 0064 RMASKx Receiver format unit bit mask
01B4 C068 01B5 0068 RFMTx Receive bit stream format
01B4 C06C 01B5 006C AFSRCTLx Receive frame sync control
01B4 C070 01B5 0070 ACLKRCTLx Receive clock control
01B4 C074 01B5 0074 AHCLKRCTLx High-frequency receive clock control
01B4 C078 01B5 0078 RTDMx Receive TDM slot 0−31
01B4 C07C 01B5 007C RINTCTLx Receiver interrupt control
01B4 C080 01B5 0080 RSTATx Status − receiver
01B4 C084 01B5 0084 RSLOTx Current receive TDM slot
01B4 C088 01B5 0088 RCLKCHKx Receiver clock check control
01B4 C08C−01B4 C09C 01B5 008C−01B5 009C — Reserved
01B4 C0A0 01B5 00A0 XGBLCTLx
01B4 C0A4 01B5 00A4 XMASKx Transmit format unit bit mask
01B4 C0A8 01B5 00A8 XFMTx Transmit bit stream format
01B4 C0AC 01B5 00AC AFSXCTLx Transmit frame sync control
01B4 C0B0 01B5 00B0 ACLKXCTLx Transmit clock control
01B4 C0B4 01B5 00B4 AHCLKXCTLx High-frequency Transmit clock control
01B4 C0B8 01B5 00B8 XTDMx Transmit TDM slot 0−31
01B4 C0BC 01B5 00BC XINTCTLx Transmit interrupt control
01B4 C0C0 01B5 00C0 XSTATx Status − transmitter
01B4 C0C4 01B5 00C4 XSLOTx Current transmit TDM slot
01B4 C0C8 01B5 00C8 XCLKCHKx Transmit clock check control
01B4 C0D0−01B4 C0FC 01B5 00CC−01B5 00FC — Reserved
01B4 C100 01B5 0100 DITCSRA0x Left (even TDM slot) channel status register file
01B4 C104 01B5 0104 DITCSRA1x Left (even TDM slot) channel status register file
01B4 C108 01B5 0108 DITCSRA2x Left (even TDM slot) channel status register file
01B4 C10C 01B5 0108 DITCSRA3x Left (even TDM slot) channel status register file
01B4 C110 01B5 0110 DITCSRA4x Left (even TDM slot) channel status register file
ACRONYM REGISTER NAME AND DESCRIPTION
McASPx receive buffer or McASPx transmit buffer via the peripheral
in the RFMT or XFMT registers, respectively).
Peripheral identification
[13/13B value: 0x00100101 for McASP0 and for McASP1]
Pin data in/data set
Writes affect: PDSET
Alias of GBLCTL containing only Receiver Reset bits; allows
transmit to be reset independently from receive
Alias of GBLCTL containing only Transmitter Reset bits; allows
transmit to be reset independently from receive
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Table 4-10. McASP0 and McASP1 Registers (continued)
HEX ADDRESS RANGE
McASP0 McASP1
01B4 C114 01B5 0114 DITCSRA5x Left (even TDM slot) channel status register file
01B4 C118 01B5 0118 DITCSRB0x Right (odd TDM slot) channel status register file
01B4 C11C 01B5 011C DITCSRB1x Right (odd TDM slot) channel status register file
01B4 C120 01B5 0120 DITCSRB2x Right (odd TDM slot) channel status register file
01B4 C124 01B5 0124 DITCSRB3x Right (odd TDM slot) channel status register file
01B4 C128 01B5 0128 DITCSRB4x Right (odd TDM slot) channel status register file
01B4 C12C 01B5 012C DITCSRB5x Right (odd TDM slot) channel status register file
01B4 C130 01B5 0130 DITUDRA0x Left (even TDM slot) user data register file
01B4 C134 01B5 0134 DITUDRA1x Left (even TDM slot) user data register file
01B4 C138 01B5 0138 DITUDRA2x Left (even TDM slot) user data register file
01B4 C13C 01B5 013C DITUDRA3x Left (even TDM slot) user data register file
01B4 C140 01B5 0140 DITUDRA4x Left (even TDM slot) user data register file
01B4 C144 01B5 0144 DITUDRA5x Left (even TDM slot) user data register file
01B4 C148 01B5 0148 DITUDRB0x Right (odd TDM slot) user data register file
01B4 C14C 01B5 014C DITUDRB1x Right (odd TDM slot) user data register file
01B4 C150 01B5 0150 DITUDRB2x Right (odd TDM slot) user data register file
01B4 C154 01B5 0154 DITUDRB3x Right (odd TDM slot) user data register file
01B4 C158 01B5 0158 DITUDRB4x Right (odd TDM slot) user data register file
01B4 C15C 01B5 015C DITUDRB5x Right (odd TDM slot) user data register file
01B4 C160−01B4 C17C 01B5 0160−01B5 017C — Reserved
01B4 C180 01B5 0180 SRCTL0x Serializer 0 control
01B4 C184 01B5 0184 SRCTL1x Serializer 1 control
01B4 C188 01B5 0188 SRCTL2x Serializer 2 control
01B4 C18C 01B5 018C SRCTL3x Serializer 3 control
01B4 C190 01B5 0190 SRCTL4x Serializer 4 control
01B4 C194 01B5 0194 SRCTL5x Serializer 5 control
01B4 C198 01B5 0198 SRCTL6x Serializer 6 control
01B4 C19C 01B5 019C SRCTL7x Serializer 7 control
01B4 C1A0−01B4 C1FC 01B5 01A0−01B5 01FC — Reserved
01B4 C200 01B5 0200 XBUF0x Transmit buffer for serializer 0 through configuration bus
01B4 C204 01B5 0204 XBUF1x Transmit buffer for serializer 1 through configuration bus
01B4 C208 01B5 0208 XBUF2x Transmit buffer for serializer 2 through configuration bus
01B4 C20C 01B5 020C XBUF3x Transmit buffer for serializer 3 through configuration bus
01B4 C210 01B5 0210 XBUF4x Transmit buffer for serializer 4 through configuration bus
01B4 C214 01B5 0214 XBUF5x Transmit buffer for serializer 5 through configuration bus
01B4 C218 01B5 0218 XBUF6x Transmit buffer for serializer 6 through configuration bus
01B4 C21C 01B5 021C XBUF7x Transmit buffer for serializer 7 through configuration bus
01B4 C220−01B4 C27C 01B5 C220−01B5 027C — Reserved
01B4 C280 01B5 0280 RBUF0x Receive buffer for serializer 0 through configuration bus
01B4 C284 01B5 0284 RBUF1x Receive buffer for serializer 1 through configuration bus
01B4 C288 01B5 0288 RBUF2x Receive buffer for serializer 2 through configuration bus
01B4 C28C 01B5 028C RBUF3x Receive buffer for serializer 3 through configuration bus
01B4 C290 01B5 0290 RBUF4x Receive buffer for serializer 4 through configuration bus
01B4 C294 01B5 0294 RBUF5x Receive buffer for serializer 5 through configuration bus
01B4 C298 01B5 0298 RBUF5x Receive buffer for serializer 6 through configuration bus
01B4 C29C 01B5 029C RBUF7x Receive buffer for serializer 7 through configuration bus
01B4 C2A0−01B4 FFFF 01B5 02A0−01B5 3FFF — Reserved
(1) The transmit buffers for serializers 0−7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register).
(2) The receive buffers for serializers 0−7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register).
ACRONYM REGISTER NAME AND DESCRIPTION
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
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Table 4-11. I2C0 and I2C1 Registers
HEX ADDRESS RANGE
I2C0 I2C1
01B4 0000 01B4 4000 I2COARx I2Cx own address register
01B4 0004 01B4 4004 I2CIERx I2Cx interrupt enable register
01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register
01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider
01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider
01B4 0014 01B4 4014 I2CCNTx I2Cx data count
01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register
01B4 001C 01B4 401C I2CSARx I2Cx slave address register
01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register
01B4 0024 01B4 4024 I2CMDRx I2Cx mode register
01B4 0028 01B4 4028 I2CISRCx I2Cx interrupt source
01B4 002C 01B4 402C — Reserved
01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler
01B4 0034 01B4 4034
01B4 0038 01B4 4038
01B4 003C−01B4 3FFF 01B4 403C−01B4 7FFF — Reserved
ACRONYM REGISTER NAME AND DESCRIPTION
I2CPID10 I2Cx peripheral identification 1
I2CPID11 (C6713/13B value: 0x0000 0103)
I2CPID20 I2Cx peripheral identification 2
I2CPID21 (C6713/13B value: 0x0000 0005)
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Table 4-12. HPI Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
— HPID HPI data register Host read/write access only
— HPIA HPI address register Host read/write access only
0188 0000 HPIC HPI control register Both Host/CPU read/write access
0188 0004−018B FFFF — Reserved
Table 4-13. Timer 0 and Timer 1 Registers
HEX ADDRESS RANGE
TIMER 0 TIMER 1
0194 0000 0198 0000 CTLx Timer x control register timer, monitors the timer status, and
0194 0004 0198 0004 PRDx Timer x period register clock cycles to count. This number
0194 0008 0198 0008 CNTx Timer x counter register
0194 000C−0197 FFFF 0198 000C−019B FFFF — Reserved
ACRONYM REGISTER NAME COMMENTS
Determines the operating mode of the
controls the function of the TOUT pin.
Contains the number of timer input
controls the TSTAT signal frequency.
Contains the current value of the
incrementing counter.
Table 4-14. McBSP0 and McBSP1 Registers
HEX ADDRESS RANGE
McBSP0 McBSP1
018C 0000 0190 0000 DRRx The CPU and EDMA controller can only read this register; they
3000 0000−33FF FFFF 3400 0000−37FF FFFF DRRx McBSPx data receive register via peripheral data bus
018C 0004 0190 0004 DXRx McBSPx data transmit register via configuration bus
3000 0000−33FF FFFF 3400 0000−37FF FFFF DXRx McBSPx data transmit register via peripheral data bus
018C 0008 0190 0008 SPCRx McBSPx serial port control register
018C 000C 0190 000C RCRx McBSPx receive control register
ACRONYM REGISTER NAME AND DESCRIPTION
McBSPx data receive register via configuration bus.
cannot write to it.
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Table 4-14. McBSP0 and McBSP1 Registers (continued)
HEX ADDRESS RANGE
McBSP0 McBSP1
018C 0010 0190 0010 XCRx McBSPx transmit control register
018C 0014 0190 0014 SRGRx McBSPx sample rate generator register
018C 0018 0190 0018 MCRx McBSPx multichannel control register
018C 001C 0190 001C RCERx McBSPx receive channel enable register
018C 0020 0190 0020 XCERx McBSPx transmit channel enable register
018C 0024 0190 0024 PCRx McBSPx pin control register
018C 0028−018F FFFF 0190 0028−0193 FFFF — Reserved
ACRONYM REGISTER NAME AND DESCRIPTION
Table 4-15. GPIO Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B0 0000 GPEN GPIO enable
01B0 0004 GPDIR GPIO direction
01B0 0008 GPVAL GPIO value
01B0 000C — Reserved
01B0 0010 GPDH GPIO delta high
01B0 0014 GPHM GPIO high mask
01B0 0018 GPDL GPIO delta low
01B0 001C GPLM GPIO low mask
01B0 0020 GPGC GPIO global control
01B0 0024 GPPOL GPIO interrupt polarity
01B0 0028−01B0 3FFF — Reserved
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TRST
GP[7](EXT_INT7)
IEEE Standard
1149.1
(JTAG)
Emulation
Resetand
Interrupts
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
NMI
GP[6](EXT_INT6)
GP[5](EXT_INT5)/AMUTEIN0
GP[4](EXT_INT4)/AMUTEIN1
RESET
Clock/PLL
Oscillator
CLKIN
CLKMODE0
PLLHV
CLKOUT2/GP[2]
EMU2
EMU3
EMU4
EMU5
HHWIL/AFSR1
HCNTL0/AXR1[3]
HCNTL1/AXR1[1]
Data
RegisterSelect
Half-Word
Select
Control
HPI
(Host-PortInterface)
HAS
/ACLKX1
HR/W
/AXR1[0]
HCS
/AXR1[2]
HDS1
/AXR1[6]
HDS2
/AXR1[5]
HRDY
/ACLKR1
HINT
/GP[1]
HD15/GP[15]
HD14/GP[14]
HD13/GP[13]
HD12/GP[12]
HD11/GP[11]
HD10/GP[10]
HD9/GP[9]
HD8/GP[8]
HD7/GP[3]
HD6/AHCLKR1
HD5/AHCLKX1
HD4/GP[0]
HD3/AMUTE1
HD2/AFSX1
HD1/AXR1[7]
HD0/AXR1[4]
CLKOUT3
HD4/GP[0]
(A)
(A)
(A)
(A)
(B)
(B)
(B)
(B)
(B)
(C)
(C)
(C)
(C)
SM320C6713-EP
SM320C6713B-EP
SGUS049K–AUGUST 2003– REVISED APRIL 2011
4.5 Signal Groups Description
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A. These external pins are applicable to the GDP package only.
B. The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the
external interrupt sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000
DSP Interrupt Selector Reference Guide (literature number SPRU646).
C. All of these pins are external interrupt sources. For more details see the External Interrupt Sources section of this
data sheet.
D. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module.
Figure 4-4. CPU (DSP Core) and Peripheral Signals
30 OVERVIEW Copyright © 2003–2011, Texas Instruments Incorporated
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