Texas Instruments SM320C6713-EP, SM320C6713B-EP Datasheet

SM320C6713-EP
SM320C6713B-EP

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

Data Manual

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SGUS049K

August 2003–Revised April 2011

SM320C6713-EP
SM320C6713B-EP

SGUS049K–AUGUST 2003– REVISED APRIL 2011

www.ti.com

Contents

1 FEATURES ......................................................................................................................... 9

2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS ..................................... 10

3 DEVICE INFORMATION ...................................................................................................... 11

3.1 Description ................................................................................................................. 14

3.2 Device Characteristics .................................................................................................... 16

3.3 Functional Block and CPU (DSP Core) Diagram ..................................................................... 17

4 OVERVIEW ....................................................................................................................... 18

4.1 CPU (DSP Core) Description ............................................................................................ 18

4.2 Memory Map Summary ................................................................................................... 19

4.3 L2 Memory Structure Expanded ......................................................................................... 21

4.4 Peripheral Register Descriptions ........................................................................................ 22

4.5 Signal Groups Description ................................................................................................ 30

5 DEVICE CONFIGURATIONS ................................................................................................ 35

5.1 Device Configurations at Device Reset ................................................................................. 35

5.2 Peripheral Pin Selection at Device Reset .............................................................................. 36

5.3 Peripheral Selection/Device Configurations Via the DEVCFG Control Register .................................. 36

5.4 Multiplexed Pins ........................................................................................................... 37

5.5 Configuration Examples .................................................................................................. 41

5.6 Debugging Considerations ............................................................................................... 47

6 TERMINAL FUNCTIONS ...................................................................................................... 47

6.1 Development Support ..................................................................................................... 55

6.2 Device and Development-Support Tool Nomenclature ............................................................... 56

6.2.1 Device Development Evolutionary Flow ..................................................................... 56

6.2.2 Support Tool Development Evolutionary Flow .............................................................. 56

6.3 Ordering Nomenclature ................................................................................................... 57

6.4 Documentation Support ................................................................................................... 57

7 REGISTER INFORMATION .................................................................................................. 59

7.1 CPU Control Status Register (CSR) Description ...................................................................... 59

7.2 Cache Configuration (CCFG) Register Description (13B) ........................................................... 60

7.3 Interrupts and Interrupt Selector ......................................................................................... 61

7.4 External Interrupt Sources ............................................................................................... 63

7.5 EDMA Module and EDMA Selector ..................................................................................... 64

8 PLL and PLL Controller ...................................................................................................... 68

8.1 PLL Registers .............................................................................................................. 69

9 MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS ............................................. 75

9.1 McASP Block Diagram .................................................................................................... 75

9.2 Multichannel Time Division Multiplexed (TDM) Synchronous Transfer Mode ..................................... 77

9.3 Burst Transfer Mode ...................................................................................................... 77

9.4 Supported Bit Stream Formats for TDM and Burst Transfer Modes ................................................ 78

9.5 Digital Audio Interface Transmitter (DIT) Transfer Mode (Transmitter Only) ...................................... 78

9.6 McASP Flexible Clock Generators ...................................................................................... 79

9.7 McASP Error Handling and Management .............................................................................. 79

9.8 McASP Interrupts and EDMA Events ................................................................................... 80

9.9 I

10 LOGIC AND POWER SUPPLY .............................................................................................. 82

2

C ........................................................................................................................... 80

2 Contents Copyright © 2003–2011, Texas Instruments Incorporated

SM320C6713-EP

SM320C6713B-EP

www.ti.com

10.1 General-Purpose Input/Output (GPIO) ................................................................................. 82

10.2 Power-Down Mode Logic ................................................................................................. 83

10.2.1 Triggering, Wake-Up, and Effects ............................................................................ 83

10.3 Power-Supply Sequencing ............................................................................................... 84

10.3.1 System-Level Design Considerations ........................................................................ 85

10.3.2 Power-Supply Design Considerations ....................................................................... 85

10.4 Power-Supply Decoupling ................................................................................................ 85

10.5 IEEE Std 1149.1 JTAG Compatibility Statement ...................................................................... 85

10.6 EMIF Device Speed ....................................................................................................... 86

10.7 EMIF Big Endian Mode Correctness (C6713B Only) ................................................................. 87

10.8 Bootmode ................................................................................................................... 88

SGUS049K–AUGUST 2003– REVISED APRIL 2011

11 PARAMETRIC INFORMATION ............................................................................................. 89

11.1 Absolute Maximum Ratings .............................................................................................. 89

11.2 Recommended Operating Conditions .................................................................................. 89

11.3 Electrical Characteristics ................................................................................................. 90

11.4 Parameter Measurement Information ................................................................................... 91

11.4.1 Timing Information .............................................................................................. 91

11.4.2 Signal Transition Levels ....................................................................................... 91

11.4.3 AC Transient Rise/Fall Time Specifications ................................................................. 92

11.4.4 Timing Parameters and Board Routing Analysis ........................................................... 93

11.5 Input and Output Clocks .................................................................................................. 94

11.6 Asynchronous Memory Timing .......................................................................................... 97

11.7 Synchronous-Burst Memory Timing ................................................................................... 100

11.8 Synchronous DRAM Timing ............................................................................................ 101

11.9 HOLD/HOLDA Timing ................................................................................................... 106

11.10 BUSREQ Timing ......................................................................................................... 106

11.11 Reset Timing ............................................................................................................. 107

11.12 External Interrupt Timing ............................................................................................... 109

11.13 Multichannel Audio Serial Port (McASP) Timing .................................................................... 110

11.14 Inter-Integrated Circuits (I

11.15 Host-Port Interface Timing .............................................................................................. 115

11.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 119

11.17 Timer Timing ............................................................................................................. 126

11.18 General-Purpose Input/Output (GPIO) Port Timing ................................................................. 127

11.19 JTAG Test Port Timing .................................................................................................. 128

2

C) Timing .................................................................................. 113

12 MECHANICAL DATA ........................................................................................................ 129

12.1 Mechanical Information .................................................................................................. 129

12.2 Packaging Information ................................................................................................... 129

Copyright © 2003–2011, Texas Instruments Incorporated Contents 3

SM320C6713-EP
SM320C6713B-EP

SGUS049K–AUGUST 2003– REVISED APRIL 2011

www.ti.com

List of Figures

4-1 320C67x™ CPU (DSP Core) Data Paths..................................................................................... 19

4-2 L2 Memory Configuration ....................................................................................................... 21

4-3 EDMA Channel Parameter Entries (Six Words) for Each EDMA Event .................................................. 25

4-4 CPU (DSP Core) and Peripheral Signals ..................................................................................... 31

4-5 Peripheral Signals................................................................................................................ 32

4-6 Peripheral Signals................................................................................................................ 33

4-7 Peripheral Signals................................................................................................................ 34

4-8 Peripheral Signals................................................................................................................ 34

5-1 Configuration Example A (Two I2C + Two McASP + GPIO) ............................................................... 42

5-2 Configuration Example B (One I2C + One McBSP + Two McASP + GPIO) ............................................. 43

5-3 Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO] .................................. 44

5-4 Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers] ....................... 45

5-5 Configuration Example E (1 I2C + HPI + 1 McASP)......................................................................... 46

5-6 Configuration Example F (One McBSP + HPI + One McASP)............................................................. 47

6-1 TMS320C6000™ DSP Device Nomenclature (Including SM320C6713 and C6713B Devices)....................... 57

7-1 CPU Control Status Register (CPU CSR) .................................................................................... 59

7-2 Cache Configuration (CCFG) Register........................................................................................ 61

8-1 PLL and Clock Generator Logic................................................................................................ 68

9-1 McASP0 and McASP1 Configuration.......................................................................................... 76

9-2 I2Cx Module Block Diagram .................................................................................................... 81

10-1 GPIO Enable (GPEN) Register (Hex Address: 01B0 0000) ............................................................... 82

10-2 GPIO Direction (GPDIR) Register (Hex Address: 01B0 0004) ............................................................ 82

10-3 Power-Down Mode Logic........................................................................................................ 83

10-4 PWRD Field of the CSR ........................................................................................................ 84

10-5 Schottky Diode Diagram......................................................................................................... 85

10-6 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1) (C6713B Only) .................................... 87

10-7 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0) (C6713B Only) .................................... 88

11-1 Test Load Circuit for AC Timing Measurements ............................................................................. 91

11-2 Input and Output Voltage Reference Levels for AC Timing Measurements.............................................. 91

11-3 Rise and Fall Transition Time Voltage Reference Levels................................................................... 91

11-4 AC Transient Specification Rise Time......................................................................................... 92

11-5 AC Transient Specification Fall Time .......................................................................................... 92

11-6 Board-Level Input/Output Timings ............................................................................................. 94

11-7 CLKIN.............................................................................................................................. 94

11-8 CLKOUT2 ......................................................................................................................... 94

11-9 CLKOUT3 ......................................................................................................................... 95

11-10 ECLKIN............................................................................................................................ 95

11-11 ECLKOUT......................................................................................................................... 96

11-12 Asynchronous Memory Read................................................................................................... 99

11-13 Asynchronous Memory Write................................................................................................... 99

11-14 SBSRAM Read Timing......................................................................................................... 101

11-15 SBSRAM Write Timing......................................................................................................... 101

11-16 SDRAM Read Command (CAS Latency 3) ................................................................................. 103

11-17 SDRAM Write Command...................................................................................................... 103

11-18 SDRAM ACTV Command ..................................................................................................... 104

11-19 SDRAM DCAB Command..................................................................................................... 104

11-20 SDRAM DEAC Command..................................................................................................... 105

4 List of Figures Copyright © 2003–2011, Texas Instruments Incorporated

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SM320C6713B-EP

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SGUS049K–AUGUST 2003– REVISED APRIL 2011

11-21 SDRAM REFR Command..................................................................................................... 105

11-22 SDRAM MRS Command ...................................................................................................... 105

11-23 HOLD/HOLDA Timing.......................................................................................................... 106

11-24 BUSREQ......................................................................................................................... 107

11-25 Reset Timing .................................................................................................................... 108

11-26 External/NMI Interrupt.......................................................................................................... 109

11-27 McASP Input Timings .......................................................................................................... 112

11-28 McASP Output Timings........................................................................................................ 112

11-29 I
11-30 I

2

C Receive...................................................................................................................... 113

2

C Transmit Timings........................................................................................................... 114

11-31 HPI Read Timing (HAS Not Used, Tied High) .............................................................................. 117

11-32 HPI Read Timing (HAS Used) ................................................................................................ 117

11-33 HPI Write Timing (HAS Not Used, Tied High) .............................................................................. 118

11-34 HPI Write Timing (HAS Used)................................................................................................. 118

11-35 McBSP Timings................................................................................................................. 121

11-36 FSR Timing When GSYNC = 1............................................................................................... 121

11-37 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0................................................... 122

11-38 McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0............................................................ 123

11-39 McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1............................................................ 124

11-40 McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1............................................................ 125

11-41 Timer ............................................................................................................................. 126

11-42 GPIO Port Timing............................................................................................................... 127

11-43 JTAG Test-Port Timing......................................................................................................... 128

Copyright © 2003–2011, Texas Instruments Incorporated List of Figures 5

SM320C6713-EP
SM320C6713B-EP

SGUS049K–AUGUST 2003– REVISED APRIL 2011

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List of Tables

3-1 Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) ................................................ 12

3-2 Characteristics of the C6713 and C6713B Processor....................................................................... 16

4-1 320C6713/13B Memory Map Summary ...................................................................................... 20

4-2 EMIF Registers ................................................................................................................... 22

4-3 L2 Cache Registers .............................................................................................................. 23

4-4 Interrupt Selector Registers..................................................................................................... 23

4-5 Device Registers ................................................................................................................. 24

4-6 EDMA Parameter RAM ......................................................................................................... 24

4-7 EDMA Registers.................................................................................................................. 25

4-8 Quick DMA (QDMA) and Pseudo Registers ................................................................................. 25

4-9 PLL Controller Registers ........................................................................................................ 25

4-10 McASP0 and McASP1 Registers .............................................................................................. 26

4-11 I2C0 and I2C1 Registers........................................................................................................ 28

4-12 HPI Registers ..................................................................................................................... 28

4-13 Timer 0 and Timer 1 Registers ................................................................................................. 28

4-14 McBSP0 and McBSP1 Registers .............................................................................................. 28

4-15 GPIO Registers................................................................................................................... 29

5-1 Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [13B only], and CLKMODE0) ................... 35

5-2 HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins) .................................. 36

5-3 Device Configuration Register (DEVCFG) [Address Location: 0x019C0200−0x019C02FF] .......................... 36

5-4 Device Configuration Register (DEVCFG) Selection Bit Descriptions .................................................... 37

5-5 Peripheral Pin Selection Matrix ................................................................................................ 38

5-6 C6713/13B Device Multiplexed/Shared Pins ................................................................................. 38

6-1 320C6713 and C6713B Device Part Numbers (P/Ns) and Ordering Information ....................................... 57

7-1 CPU CSR Bit Field Description ................................................................................................ 60

7-2 CCFG Register Bit Field Description .......................................................................................... 61

7-3 DSP Interrupts .................................................................................................................... 61

7-4 Interrupt Selector ................................................................................................................. 63

7-5 External Interrupt Sources and Peripheral Module Control................................................................. 64

7-6 EDMA Channels.................................................................................................................. 65

7-7 EDMA Selector ................................................................................................................... 66

7-8 EDMA Event Selector Registers (ESEL0 Register (0x01A0 FF00) ....................................................... 67

7-9 EDMA Event Selector Registers—ESEL1 Register (0x01A0 FF04) ...................................................... 67

7-10 EDMA Event Selector Registers—ESEL3 Register (0x01A0 FF0C) ..................................................... 67

7-11 EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description............................................ 67

8-1 PLL Lock and Reset Times ..................................................................................................... 69

8-2 CLKOUT Signals, Default Settings, and Control............................................................................. 69

8-3 PLL Clock Frequency Ranges ................................................................................................. 70

8-4 PLL Control/Status Register (PLLCSR) (0x01B7 C100) ................................................................... 70

8-5 PLL Control/Status Register (PLLCSR) Description......................................................................... 71

8-6 PLL Multiplier (PLLM) Control Register (0x01B7 C110) .................................................................... 71

8-7 PLL Multiplier (PLLM) Control Register Description......................................................................... 72

8-8 PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3)

(0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively) ....................................... 72

8-9 PLL Wrapper Divider x Registers

(Prescaler Divider D0 and Post-Scaler Dividers D1, D2, and D3) Description .......................................... 72

8-10 Oscillator Divider 1 (OSCDIV1) Register (0x01B7 C124) .................................................................. 73

6 List of Tables Copyright © 2003–2011, Texas Instruments Incorporated

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SM320C6713B-EP

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SGUS049K–AUGUST 2003– REVISED APRIL 2011

8-11 Oscillator Divider 1 (OSCDIV1) Register Description ....................................................................... 74

10-1 Characteristics of the Power-Down Modes ................................................................................... 84

10-2 C6713/13B Example Boards and Maximum EMIF Speed.................................................................. 87

11-1 Board-Level Timings Example (see ) .......................................................................................... 93

11-2 Timing Requirements for CLKIN ............................................................................................... 94

11-3 Switching Characteristics for CLKOUT2 ...................................................................................... 94

11-4 Switching Characteristics for CLKOUT3 ...................................................................................... 95

11-5 Timing Requirements for ECLKIN ............................................................................................. 95

11-6 Switching Characteristics for ECLKOUT ..................................................................................... 96

11-7 Timing Requirements for Asynchronous Memory Cycles .................................................................. 97

11-8 Switching Characteristics for Asynchronous Memory Cycles ............................................................. 97

11-9 Timing Requirements for Synchronous-Burst SRAM Cycles ............................................................. 100

11-10 Switching Characteristics for Synchronous-Burst SRAM Cycles ........................................................ 100

11-11 Timing Requirements for Synchronous DRAM Cycles .................................................................... 101

11-12 Switching Characteristics for Synchronous DRAM Cycles ............................................................... 101

11-13 Timing Requirements for HOLD/HOLDA Cycles ........................................................................... 106

11-14 Switching Characteristics for HOLD/HOLDA Cycles ...................................................................... 106

11-15 Switching Characteristics for BUSREQ Cycles ............................................................................ 106

11-16 Timing Requirements for RESET ............................................................................................ 107

11-17 Switching Characteristics For RESET ....................................................................................... 107

11-18 Timing Requirements for External Interrupts ............................................................................... 109

11-19 Timing Requirements for McASP ............................................................................................ 110

11-20 Switching Characteristics for McASP ........................................................................................ 110

11-21 Timing Requirements for I
11-22 Switching Characteristics for I

2

C ................................................................................................. 113

2

C ............................................................................................. 114

11-23 Timing Requirements for Host-Port Interface Cycles ..................................................................... 115

11-24 Switching Characteristics for Host-Port Interface Cycles ................................................................. 116

11-25 Timing Requirements for McBSP ............................................................................................ 119

11-26 Switching Characteristics for McBSP ........................................................................................ 120

11-27 Timing Requirements for FSR When GSYNC = 1 ......................................................................... 121

11-28 Timing Requirements for McBSP as SPI Master or Slave:

CLKSTP = 10b, CLKXP = 0 .................................................................................................... 121

11-29 Switching Characteristics for McBSP as SPI Master or Slave:

CLKSTP = 10b, CLKXP = 0 .................................................................................................... 122

11-30 Timing Requirements for McBSP as SPI Master or Slave:

CLKSTP = 11b, CLKXP = 0 .................................................................................................... 122

11-31 Switching Characteristics for McBSP as SPI Master or Slave:

CLKSTP = 11b, CLKXP = 0 .................................................................................................... 123

11-32 Timing Requirements for McBSP as SPI Master or Slave:

CLKSTP = 10b, CLKXP = 1 .................................................................................................... 124

11-33 Switching Characteristics for McBSP as SPI Master or Slave:

CLKSTP = 10b, CLKXP = 1 .................................................................................................... 124

11-34 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ............................. 125

11-35 Switching Characteristics for McBSP as SPI Master or Slave:

CLKSTP = 11b, CLKXP = 1 .................................................................................................... 125

11-36 Timing Requirements for Timer Inputs ...................................................................................... 126

11-37 Switching Characteristics for Timer Inputs ................................................................................. 126

11-38 Timing Requirements for GPIO Inputs ...................................................................................... 127

11-39 Switching Characteristics for GPIO Inputs .................................................................................. 127

11-40 Timing Requirements for JTAG Test Port .................................................................................. 128

Copyright © 2003–2011, Texas Instruments Incorporated List of Tables 7

SM320C6713-EP
SM320C6713B-EP

SGUS049K–AUGUST 2003– REVISED APRIL 2011

11-41 Switching Characteristics for JTAG Test Port .............................................................................. 128

12-1 Thermal Resistance Characteristics (S-PBGA Package) for GDP....................................................... 129

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8 List of Tables Copyright © 2003–2011, Texas Instruments Incorporated

SM320C6713-EP

SM320C6713B-EP

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SGUS049K–AUGUST 2003– REVISED APRIL 2011

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

Check for Samples: SM320C6713-EP

1 FEATURES

1
2

• Highest Performance Floating Point Digital • 32 Bit External Memory Interface (EMIF)

Signal Processors (DSPs): C6713/C6713B

– Eight 32 Bit Instructions/Cycle SBSRAM, and SDRAM
– 32/64 Bit Data Word – 512M Byte Total Addressable External
– 200 and 300 MHz Clock Rate
– 5 Instruction Cycle Times
– 2400/1800 and 1600/1200 MIPS/MFLOPS
– Rich Peripheral Set, Optimized for Audio
– Highly Optimized C/C++ Compiler

• Advanced Very Long Instruction Word (VLIW)

320C67x™ DSP Core
– Eight Independent Functional Units:

• Two ALUs (Fixed Point)

• Four ALUs (Floating Point and Fixed

Point)

• Two Multipliers (Floating Point and Fixed
Point)

– Load Store Architecture With 32 32-Bit

General Purpose Registers

– Instruction Packing Reduces Code Size
– All Instructions Conditional

• Instruction Set Features
– Native Instructions for IEEE 754
– Byte Addressable (8/16/32 Bit Data)
– 8 Bit Overflow Protection
– Saturation; Bit-Field Extract, Set, Clear;

Bit-Counting; Normalization

• L1/L2 Memory Architecture
– 4K Byte L1P Program Cache (Direct-Mapped)
– 4K Byte L1D Data Cache (2-Way)
– 256K Byte L2 Memory Total: 64K-Byte L2

Unified Cache/Mapped RAM, and 192K Byte
Additional L2 Mapped RAM

• Device Configuration
– Boot Mode: HPI, 8/16/32 Bit ROM Boot
– Endianness: Little Endian, Big Endian

– Glueless Interface to SRAM, EPROM, Flash,

Memory Space

• Enhanced Direct Memory Access (EDMA)
Controller (16 Independent Channels)

• 16 Bit Host Port Interface (HPI)

• Two Multichannel Audio Serial Ports (McASPs)
– Two Independent Clock Zones Each

(One TX and One RX)

– Eight Serial Data Pins Per Port: Individually

Assignable to any of the Clock Zones

– Wide Variety of I2S™ and Similar Bit Stream

Formats

– Integrated Digital Audio Interface Transmitter

(DIT)

– Extensive Error Checking and Recovery

• Two Inter-Integrated Circuit Bus (I2C™ Bus)

Multi-Master and Slave Interfaces

• Two Multichannel Buffered Serial Ports:
– Serial Peripheral Interface (SPI)
– High Speed TDM Interface
– AC97 Interface

• Two 32 Bit General Purpose Timers

• Dedicated GPIO Module With 16 Pins (External

Interrupt Capable)

• Flexible Phase Locked Loop (PLL) Based Clock
Generator Module

• IEEE-1149.1 (JTAG)

(1)

Boundary-Scan

Compatible

• 272 Ball, Ball Grid Array Package (GDP)

• 0.13 μm/6 Level Copper Metal Process
– CMOS Technology

• 3.3 V I/Os, 1.26 V Internal

(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and

Boundary Scan Architecture.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2320C67x, TMS320C6000, TMS320C67x, eXpressDSP, Code Composer Studio, DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x, C67x

are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2003–2011, Texas Instruments Incorporated

SM320C6713-EP
SM320C6713B-EP

SGUS049K–AUGUST 2003– REVISED APRIL 2011

2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

3

• Controlled Baseline

• One Assembly/Test Site

• One Fabrication Site

• Available in Military (–55°C/125°C) Temperature

Range

(2) Custom temperature ranges available

(2)

break

• Extended Product Life Cycle

• Extended Product-Change Notification

• Product Traceability

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3320C67x, TMS320C6000, TMS320C67x, eXpressDSP, Code Composer Studio, DSP/BIOS, C6000, XDS, TMS320, PowerPAD, C62x, C67x

are trademarks of Texas Instruments.

10 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Copyright © 2003–2011, Texas Instruments Incorporated

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HD13/

GP[13]

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GP[11]

HD10/

GP[10]

HD8/
GP[8]

HD7/
GP[3]

HD4/

GP[0]

HD2/

AFSX1

HD3/

AMUTE1

HD1/

AXR1[7]

HHWIL/

AFSR[1]

HD0/

AXR1[4]

HR/ /

AXR1[0]

W

HOLDA

BUS
REQ

V

SS

V

SS

V

SS

V

SS

V

SS

DV

DD

CV

DD

CV

DD

V

SS

CV

DD

DV

DD

FSR0/

AFSR0

CLKR0/

ACLKR0

CLKX0/

ACLKX0

TOUT0/
AXR0[2]

TOUT1/

AXR0[4]

TINP0/

AXR0[3]

TINP1/

AHCLKX0

FSX0/

AFSX0

V

SS

V

SS

V

SS

DV

DD

DV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

DV

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

EMU2

CLKIN

CLK

MODE0

PLLHV

RSV

RSV

CV

DD

V

SS

TRST

TCK

TDI

TMS

CV

DD

CV

DD

CVDDCV

DD

CV

DD

CV

DD

DV

DD

DV

DD

DV

DD

DV

DD

RSV RSV

RSV

RSV

V

SS

V

SSVSS

TD0

CV

DD

EMU1

EMU0

CLKOUT3

DV

DD

EMU3

CV

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

RSV

EMU4

EMU5

NMI

RESET

DV

DD

1 2

3

4

5 6

7

8 9 10

11 12

13

14

15 16

17

18 19 20

ShadingdenotestheGDPpackagepinfunctionsthatdropoutonthePYPpackage.

SM320C6713-EP

SM320C6713B-EP

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SGUS049K–AUGUST 2003– REVISED APRIL 2011

3 DEVICE INFORMATION

GDP 272-BALL BGA PACKAGE

(BOTTOM VIEW)

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Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.)

BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME

A1 V
A2 V
A3 CLKIN C3 CV
A4 CV
A5 RSV C5 PLLHV
A6 TCK C6 V
A7 TDI C7 CV
A8 TDO C8 V

A9 CV
A10 CV
A11 V
A12 RSV (connected directly to CVDD) C12 RSV
A13 RESET C13 NMI
A14 V
A15 HD13/GP[13] C15 HD12/GP[12]
A16 HD11/GP[11] C16 HD9/GP[9]
A17 DV
A18 HD7/GP[3] C18 CV
A19 V
A20 V

B1 V

B2 CV

B3 DV

B4 V

B5 RSV D5 CV

B6 TRST D6 CV

B7 TMS D7 RSV

B8 DV

B9 EMU1 D9 EMU0
B10 EMU3 D10 CLKOUT3
B11 RSV (connected directly to VSS) D11 CV
B12 EMU5 D12 RSV
B13 DV
B14 HD15/GP[15] D14 CV
B15 V
B16 HD10/GP[10] D16 DV
B17 HD8/GP[8] D17 V
B18 HD5/AHCLKX1 D18 HD2/AFSX1
B19 CV
B20 V

E1 CLKS1/SCL1 J17 HOLD

E2 V

E3 GP[7]/(EXP_INT7) J19 BUSREQ

E4 V
E17 V
E18 HAS/ACLKX1 K2 V
E19 HDS1/AXR1[6] K3 CLKS0/AHCLKR0
E20 HD0/AXR1[4] K4 CV

F1 TOUT1/AXR0[4] K9 V

F2 TINP1/AHCLKX0 K10 V

F3 DV

SS
SS

DD

DD
DD

SS

SS

DD

SS
SS
SS

DD
DD

SS

DD

DD

SS

DD

SS

SS

SS
SS

DD

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C1 GP[5](EXT_INT5)/AMUTEIN0
C2 GP[4](EXT_INT4)/AMUTEIN1

DD

C4 CLKMODE0

SS

DD

SS

C9 V

C10 DV

SS

DD

C11 EMU4

C14 HD14/GP[14]

C17 HD6/AHCLKR1

DD

C19 HD4/GP[0]
C20 HD3/AMUTE1

D1 DV

DD

D2 GP[6](EXT_INT6)
D3 EMU2
D4 V

D8 V

D13 V

D15 CV

D19 DV

SS

DD
DD

SS

DD

SS

DD
DD
DD

SS

DD

D20 HD1/AXR1[7]

J18 HOLDA

J20 HINT/GP[1]

K1 CV

K11 V

DD

SS

DD
SS
SS
SS

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Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) (continued)

SGUS049K–AUGUST 2003– REVISED APRIL 2011

BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME

F4 CV

F17 CV

DD
DD

K12 V
K17 CV

SS

DD

F18 HDS2/AXR1[5] K18 ED0
F19 V

SS

F20 HCS/AXR1[2] K20 V

K19 ED1

SS

G1 TOUT0/AXR0[2] L1 FSX1
G2 TINP0/AXR0[3] L2 DX1/AXR0[5]
G3 CLKX0/ACLKX0 L3 CLKX1/AMUTE0
G4 V

G17 V

SS
SS

G18 HCNTL0/AXR1[3] L10 V
G19 HCNTL1/AXR1[1] L11 V
G20 HR/W/AXR1[0] L12 V

H1 FSX0/AFSX0 L17 CV

L4 CV
L9 V

DD
SS
SS
SS
SS

DD

H2 DX0/AXR0[1] L18 ED2
H3 CLKR0/ACLKR0 L19 ED3

H4 V
H17 V
H18 DV

SS
SS

DD

L20 CV

DD

M1 CLKR1/AXR0[6]

M2 DR1/SDA1
H19 HRDY/ACLKR1 M3 FSR1/AXR0[7]
H20 HHWIL/AFSR1 M4 V

J1 DR0/AXR0[0] M9 V
J2 DV

DD

M10 V
J3 FSR0/AFSR0 M11 V
J4 V
J9 V

J10 V
J11 V
J12 V

SS
SS
SS
SS
SS

M12 V

M17 V

M18 DV

M19 ED4

M20 ED5
N1 SCL0 U9 V
N2 SDA0 U10 CV
N3 ED31 U11 CV
N4 V

N17 V

SS
SS

U12 DV

U13 V

N18 ED6 U14 CV
N19 ED7 U15 CV
N20 ED8 U16 DV

P1 ED28 U17 V

SS
SS
SS
SS
SS
SS

DD

SS

DD
DD
DD

SS

DD
DD
DD

SS

P2 ED29 U18 EA21
P3 ED30 U19 BE1
P4 V

P17 V

SS
SS

U20 V

SS

V1 ED20
P18 ED9 V2 ED19
P19 V

SS

V3 CV

DD

P20 ED10 V4 ED16

R1 DV

DD

V5 BE3

R2 ED27 V6 CE3
R3 ED26 V7 EA3

R4 CV
R17 CV
R18 DV

DD
DD
DD

V8 EA5
V9 EA8

V10 EA10

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Table 3-1. Terminal Assignments for 272-Ball GDP Package (in Order of Ball No.) (continued)

BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME

R19 ED11 V11 ARE/SDCAS/SSADS
R20 ED12 V12 AWE/SDWE/SSWE

T1 ED24 V13 DV

T2 ED25 V14 EA17

T3 DV

T4 V
T17 V
T18 ED13 V18 CV
T19 ED15 V19 DV
T20 ED14 V20 BE0

U1 ED22 W1 V

U2 ED21 W2 CV

U3 ED23 W3 DV

U4 V

U5 DV

U6 CV

U7 DV

U8 V

W9 DV
W10 AOE/SDRAS/SSOE Y6 EA2
W11 V
W12 DV
W13 EA11 Y9 EA9
W14 EA13 Y10 ECLKOUT
W15 EA15 Y11 ECLKIN
W16 V
W17 EA19 Y13 V
W18 CE1 Y14 EA14
W19 CV
W20 V

Y1 V
Y2 V
Y3 ED18 Y19 V
Y4 BE2 Y20 V

DD
SS
SS

SS

DD

DD

DD
SS

DD

SS

DD

SS

DD
SS
SS
SS

DD

V15 DV
V16 EA
V17 CE0

W4 ED17
W5 V
W6 CE2
W7 EA4
W8 EA6

Y5 ARDY

Y7 DV
Y8 EA7

Y12 CLKOUT2/GP[2]

Y15 EA16
Y16 EA18
Y17 DV
Y18 EA20

DD

DD
DD

SS

DD
DD

SS

DD

SS

DD

SS
SS

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3.1 Description

The TMS320C67x™ DSPs (including the SM320C6713 and SM320C6713B devices) compose the
floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713 and C6713B devices are
based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction
applications. Throughout the remainder of this document, the SM320C6713 and SM320C6713B are
referred to as 320C67x or C67x or 13/13B where generic, and where specific, their individual full device
part numbers are used or abbreviated as C6713, C6713B, 13, or 13B, and so forth.

Operating at 225 MHz, the C6713/13B delivers up to 1350 million floating-point operations per second
(MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to
450 million multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second
(MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to
600 million multiply-accumulate operations per second (MMACS).

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The C6713/13B has a rich peripheral set that includes two multichannel audio serial ports (McASPs), two
multichannel buffered serial ports (McBSPs), two inter-integrated circuit (I2C) buses, one dedicated
general-purpose input/output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and
a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and
asynchronous peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the
McASPs has eight serial data pins that can be individually allocated to any of the two zones. The serial
port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713/13B has sufficient
bandwidth to support all 16 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone
may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude
of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, and
CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of
user data and channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock
detection circuit for each high-frequency master clock, which verifies that the master clock is within a
programmed frequency range.

The two I2C ports on the 320C6713/13B allow the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP)
may be used to communicate with serial peripheral interface (SPI™) mode peripheral devices.

SGUS049K–AUGUST 2003– REVISED APRIL 2011

The 320C6713/13B device has two boot modes—from the HPI or from external asynchronous ROM. For
more detailed information, see the Bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark
development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated
Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™
kernel.

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3.2 Device Characteristics

Table 3-2 provides an overview of the C6713/C6713B DSPs. The table shows significant features of each

device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type
with pin count. For more details on the C67x™ DSP device part numbers and part numbering, see

Table 6-1 and Figure 6-1.

Table 3-2. Characteristics of the C6713 and C6713B Processor

HARDWARE FEATURES

EMIF SYSCLK3 or ECLKIN 1 (32 bit)
EDMA

(16 channels)

Peripherals
Not all peripheral pins are available at the
same time. (For more details, see the

Device Configurations section.)

Peripheral performance is dependent on
chip-level configuration.

On-chip memory Size (Bytes) 264K

CPU ID+CPU Rev ID Control Status Register (CSR[31:16]) 0x0203
BSDL file For the C6713/13B BSDL file, contact your field sales representative.
Frequency MHz 200
Time ns 5 ns

Voltage

Clock generator options Multiplier ×4, ×5, ×6, ..., ×25

Package 27 mm × 27 mm 272-ball BGA (GDP)
Process technology μm 0.13
Product status

Product preview (PP)
Advance information (AI)
Production data (PD)

(1) AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock

check (high-frequency) circuit.

(2) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(2)

HPI (16 bit) SYSCLK2 1
McASPs 2
I2Cs SYSCLK2 2

McBSPs SYSCLK2 2
32-bit timers � of SYSCLK2 2
GPIO module SYSCLK2 1

Organization

Core (V) 1.26 V (C6713/C6713B)
I/O (V) 3.3 V
Prescaler /1, /2, /3, ..., /32

Postscaler /1, /2, /3, ..., /32

INTERNAL CLOCK

SOURCE

CPU clock frequency 1

AUXCLK,
SYSCLK2

(1)

4K-Byte (KB) L1 program (L1P) cache
4KB L1 data (L1D) cache
64KB unified L2 cache/mapped RAM
192KB L2 mapped RAM

C6713/C6713B

(FLOATING-POINT DSPs)

GDP

PD (13)

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Test

C67xä CPU

DataPath B

BRegisterFile

InstructionFetch

InstructionDispatch

InstructionDecode

DataPath A

ARegisterFile

Power-Down

Logic

.L1

(A) (A) (A) (A) (A) (A)

.S1 .M1 .D1. D2 .M2 .S2 .L2

L1PCache
DirectMapped
4KBytesTotal

Control

Registers

Control

Logic

L1DCache

2-Way

SetAssociative

4KBytes

In-Circuit

Emulation

Interrupt

Control

C6713/13B DigitalSignalProcessors

Enhanced

DMA

Controller

(16 channel)

L2Cache/

Memory
4Banks

64KBytes

Total

(upto

4-Way)

ClockGeneratorandPLL

x4throughx25Multiplier

/1through/32Dividers

L2

Memory

192K
Bytes

EMIF

McASP1

McASP0

McBSP1

McBSP0

I2C1

I2C0

Timer1

Timer0

GPIO

HPI

PinMultiplexing

32

16

NOTEA: Inadditiontofixed-pointinstructions,thesefunctionalunitsexecutefloating-pointinstructions.

EMIFinterfacesto: McBSPsinterfaceto: McASPsinterfaceto:

SDRAM- - -

- - -

- -

- -

SPIcontrolport I SmultichannelADC,DAC,codec,DIR
SBSRAM High-speedTDMcodecs DIT:Multipleoutputs
SRAM AC97codecs
ROM/flashand SerialEEPROM
I/Odevices

2

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SM320C6713B-EP

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3.3 Functional Block and CPU (DSP Core) Diagram

SGUS049K–AUGUST 2003– REVISED APRIL 2011

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4 OVERVIEW

4.1 CPU (DSP Core) Description

The 320C6713/13B floating-point digital signal processor is based on the C67x CPU. The CPU fetches
advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the
eight functional units during every clock cycle. The VLIW architecture features controls by which all eight
units do not have to be supplied with instructions if they are not ready to execute. The first bit of every
32-bit instruction determines if the next instruction belongs to the same execute packet as the previous
instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other
VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set
contains functional units .L1, .S1, .M1, and .D1. The other set contains units .D2, .M2, .S2, and .L2. The
two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets
of functional units, along with two register files, compose sides A and B of the CPU (see the Functional

Block and CPU (DSP Core) Diagram and Figure 4-1). The four functional units on each side of the CPU

can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data
from the register files on the opposite side. While register access by functional units on the same side of
the CPU as the register file can service all the units in a single clock cycle, register access using the
register file across the CPU supports one read and one write per cycle.

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The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of
eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The
remaining two functional units (.D1 and .D2) also execute the new LDDW instruction, which loads 64 bits
per CPU side for a total of 128 bits per cycle.

Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on
registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are
responsible for all data transfers between the register files and the memory. The data address driven by
the .D units allows data addresses generated from one register file to be used to load or store data to or
from the other register file. The C67x CPU supports a variety of indirect addressing modes using either
linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can
access any one of the 32 registers. Some registers, however, are singled out to support specific
addressing or to hold the condition for conditional instructions (if the condition is not automatically true).
The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a
general set of arithmetic, logical, and branch functions with results available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program
memory. The 32-bit instructions destined for the individual functional units are chained together by 1 bits
in the least significant bit (LSB) position of the instructions. The instructions that are chained together for
simultaneous execution (up to eight in total) compose an execute packet. A 0 in the LSB of an instruction
breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute
packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet,
while the remainder of the current fetch packet is padded with NOP instructions. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their
respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not
fetched until all the execute packets from the current fetch packet have been dispatched. After decoding,
the instructions simultaneously drive all active functional units for a maximum execution rate of eight
instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently
moved to memory as bytes or half-words as well. All load and store instructions are byte, half-word, or
word addressable.

18 OVERVIEW Copyright © 2003–2011, Texas Instruments Incorporated

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8

8

long src

dst

src2

src1

src1

src1

src1

src1

src1

src1

src1

longdst

longdst

dst

dst

dst

dst

dst

dst

dst

src2

src2

src2

src2

src2

src2

src2

longsrc

longsrc

longdst

longdst

longsrc

8

8

8

2X

1X

.L2

.S2

.M2

.D2

.D1

.M1

.S1

.L1

Control

RegisterFile

DA1

DA2

ST1

LD132LSB

LD232LSB

LD232MSB

32

32

DataPathA

DataPathB

Register

FileA

(A0−A15)

Register

FileB

(B0−B15)

LD132MSB

32

ST2

32

8

8

8

(A)

(A)

(A)

(A)

(A)

(A)

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SGUS049K–AUGUST 2003– REVISED APRIL 2011

A. In addition to fixed-point instructions, these functional units execute floating-point instructions.

Figure 4-1. 320C67x™ CPU (DSP Core) Data Paths

4.2 Memory Map Summary

Table 4-1 shows the memory map address ranges of the C6713/13B devices.

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Table 4-1. 320C6713/13B Memory Map Summary

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Internal RAM (L2) 192K 0000 0000 0002 FFFF

Internal RAM/Cache 64K 0003 0000 0003 FFFF

Reserved 24M – 256K 0004 0000 017F FFFF

External Memory Interface (EMIF) Registers 256K 0180 0000 0183 FFFF

L2 Registers 128K 0184 0000 0185 FFFF

Reserved 128K 0186 0000 0187 FFFF

HPI Registers 256K 0188 0000 018B FFFF
McBSP 0 Registers 256K 018C 0000 018F FFFF
McBSP 1 Registers 256K 0190 0000 0193 FFFF

Timer 0 Registers 256K 0194 0000 0197 FFFF
Timer 1 Registers 256K 0198 0000 019B FFFF

Interrupt Selector Registers 512 019C 0000 019C 01FF

Device Configuration Registers 4 019C 0200 019C 0203

Reserved 256K − 516 019C 0204 019F FFFF

EDMA RAM and EDMA Registers 256K 01A0 0000 01A3 FFFF

Reserved 768K 01A4 0000 01AF FFFF

GPIO Registers 16K 01B0 0000 01B0 3FFF

Reserved 240K 01B0 4000 01B3 FFFF
I2C0 Registers 16K 01B4 0000 01B4 3FFF
I2C1 Registers 16K 01B4 4000 01B4 7FFF

Reserved 16K 01B4 8000 01B4 BFFF

McASP0 Registers 16K 01B4 C000 01B4 FFFF
McASP1 Registers 16K 01B5 0000 01B5 3FFF

Reserved 160K 01B5 4000 01B7 BFFF

PLL Registers 8K 01B7 C000 01B7 DFFF

Reserved 264K 01B7 E000 01BB FFFF

Emulation Registers 256K 01BC 0000 01BF FFFF

Reserved 4M 01C0 0000 01FF FFFF

QDMA Registers 52 0200 0000 0200 0033

Reserved 16M − 52 0200 0034 02FF FFFF

Reserved 720M 0300 0000 2FFF FFFF

McBSP0 Data Port 64M 3000 0000 33FF FFFF
McBSP1 Data Port 64M 3400 0000 37FF FFFF

Reserved 64M 3800 0000 3BFF FFFF

McASP0 Data Port 1M 3C00 0000 3C0F FFFF
McASP1 Data Port 1M 3C10 0000 3C1F FFFF

Reserved 1G + 62M 3C20 0000 7FFF FFFF

EMIF CE0
EMIF CE1
EMIF CE2
EMIF CE3

(1) The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.

(1)
(1)
(1)
(1)

Reserved 1G C000 0000 FFFF FFFF

256M 8000 0000 8FFF FFFF
256M 9000 0000 9FFF FFFF
256M A000 0000 AFFF FFFF
256M B000 0000 BFFF FFFF

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0x00000000

011010001 111

0x00030000

000

L2Mode L2Memory BlockBase Address

0x0003C000

0x00038000

0x00034000

0x0003FFFF

16K

1-Way

Cache

32K

2-WayCache

48K3-W

ayCache

64K4-W

ayCache

256KSRAM(All)

240KSRAM

224KSRAM

208KSRAM

192KSRAM

192K-ByteRAM

16K-ByteRAM

16K-ByteRAM

16K-ByteRAM

16K-ByteRAM

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4.3 L2 Memory Structure Expanded

Figure 4-2 shows the detail of the L2 memory structure.

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Figure 4-2. L2 Memory Configuration

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4.4 Peripheral Register Descriptions

Table 4-2 through Table 4-15 identify the peripheral registers for the C6713/C6713B devices by their

register names, acronyms, and hex address or hex address range. For more detailed information on the
register contents and bit names and their respective descriptions, see the specific peripheral reference
guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number

SPRU190).

Table 4-2. EMIF Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0180 0000 GBLCTL EMIF global control
0180 0004 CECTL1 EMIF CE1 space control
0180 0008 CECTL0 EMIF CE0 space control
0180 000C — Reserved
0180 0010 CECTL2 EMIF CE2 space control
0180 0014 CECTL3 EMIF CE3 space control
0180 0018 SDCTL EMIF SDRAM control
0180 001C SDTIM EMIF SDRAM refresh control
0180 0020 SDEXT EMIF SDRAM extension

0180 0024−0183 FFFF — Reserved

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Table 4-3. L2 Cache Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0184 0000 CCFG Cache configuration
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count
0184 4010 L2WIBAR L2 writeback-invalidate base address register
0184 4014 L2WIWC L2 writeback-invalidate word count
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count
0184 4030 L1DWIBAR L1D writeback-invalidate base address register
0184 4034 L1DWIWC L1D writeback-invalidate word count
0184 5000 L2WB L2 writeback all
0184 5004 L2WBINV L2 writeback-invalidate all
0184 8200 MAR0 Memory attribute register 0. Controls CE0 range 8000 0000 80FF FFFF
0184 8204 MAR1 Memory attribute register 1. Controls CE0 range 8100 0000 81FF FFFF
0184 8208 MAR2 Memory attribute register 2. Controls CE0 range 8200 0000 82FF FFFF
0184 820C MAR3 Memory attribute register 3. Controls CE0 range 8300 0000 83FF FFFF
0184 8240 MAR4 Memory attribute register 4. Controls CE1 range 9000 0000 90FF FFFF
0184 8244 MAR5 Memory attribute register 5. Controls CE1 range 9100 0000 91FF FFFF
0184 8248 MAR6 Memory attribute register 6. Controls CE1 range 9200 0000 92FF FFFF
0184 824C MAR7 Memory attribute register 7. Controls CE1 range 9300 0000 93FF FFFF
0184 8280 MAR8 Memory attribute register 8. Controls CE2 range A000 0000 A0FF FFFF
0184 8284 MAR9 Memory attribute register 9. Controls CE2 range A100 0000 A1FF FFFF
0184 8288 MAR10 Memory attribute register 10. Controls CE2 range A200 0000 A2FF FFFF
0184 828C MAR11 Memory attribute register 11. Controls CE2 range A300 0000 A3FF FFFF
0184 82C0 MAR12 Memory attribute register 12. Controls CE3 range B000 0000 B0FF FFFF
0184 82C4 MAR13 Memory attribute register 13. Controls CE3 range B100 0000 B1FF FFFF
0184 82C8 MAR14 Memory attribute register 14. Controls CE3 range B200 0000 B2FF FFFF

0184 82CC MAR15 Memory attribute register 15. Controls CE3 range B300 0000 B3FF FFFF

0184 82D0−0185 FFFF — Reserved

Table 4-4. Interrupt Selector Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

019C 0000 MUXH Interrupt multiplexer high

019C 0004 MUXL Interrupt multiplexer low

019C 0008 EXTPOL External interrupt polarity

019C 000C−019F FFFF — Reserved

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Selects which interrupts drive CPU interrupts
10–15 (INT10−INT15)

Selects which interrupts drive CPU interrupts
4−9 (INT04−INT09)

Sets the polarity of the external interrupts
(EXT_INT4−EXT_INT7)

31 0 EDMA Parameter

Word0 EDMAChannelOptionsParameter(OPT) OPT

Word1 EDMAChannelSourceAddress(SRC) SRC

Word2 Array/FrameCount(FRMCNT) ElementCount(ELECNT) CNT

Word3 EDMAChannelDestinationAddress(DST) DST

Word4 Array/FrameIndex(FRMIDX) ElementIndex(ELEIDX) IDX

Word5 ElementCountReload(ELERLD) LinkAddress(LINK) RLD

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SM320C6713B-EP

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Table 4-5. Device Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

Allows the user to control peripheral
selection. This register also offers the user

019C 0200 DEVCFG Device configuration

019C 0204−019F FFFF — Reserved

N/A CSR CPU control status register

Table 4-6. EDMA Parameter RAM

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01A0 0000 01A0 0017 — Parameters for Event 0 (6 words) or Reload/Link parameters for other event
01A0 0018 01A0 002F — Parameters for Event 1 (6 words) or Reload/Link parameters for other event
01A0 0030 01A0 0047 — Parameters for Event 2 (6 words) or Reload/Link parameters for other event
01A0 0048 01A0 005F — Parameters for Event 3 (6 words) or Reload/Link parameters for other event
01A0 0060 01A0 0077 — Parameters for Event 4 (6 words) or Reload/Link parameters for other event
01A0 0078 01A0 008F — Parameters for Event 5 (6 words) or Reload/Link parameters for other event

01A0 0090 01A0 00A7 — Parameters for Event 6 (6 words) or Reload/Link parameters for other event
01A0 00A8 01A0 00BF — Parameters for Event 7 (6 words) or Reload/Link parameters for other event
01A0 00C0 01A0 00D7 — Parameters for Event 8 (6 words) or Reload/Link parameters for other event
01A0 00D8 01A0 00EF — Parameters for Event 9 (6 words) or Reload/Link parameters for other event

01A0 00F0 01A0 00107 — Parameters for Event 10 (6 words) or Reload/Link parameters for other event

01A0 0108 01A0 011F — Parameters for Event 11 (6 words) or Reload/Link parameters for other event

01A0 0120 01A0 0137 — Parameters for Event 12 (6 words) or Reload/Link parameters for other event

01A0 0138 01A0 014F — Parameters for Event 13 (6 words) or Reload/Link parameters for other event

01A0 0150 01A0 0167 — Parameters for Event 14 (6 words) or Reload/Link parameters for other event

01A0 0168 01A0 017F — Parameters for Event 15 (6 words) or Reload/Link parameters for other event

01A0 0180 01A0 0197 — Reload/link parameters for Event 0−15
01A0 0198 01A0 01AF — Reload/link parameters for Event 0−15

... ... ...

01A0 07E0 01A0 07F7 — Reload/link parameters for Event 0−15
01A0 07F8 01A0 07FF — Scratch pad area (two words)

(1) The C6713/13B device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.

control of the EMIF input clock source. For
more detailed information on the device
configuration register, see the Device

Configurations section of this data sheet.

Identifies which CPU and defines the silicon
revision of the CPU. This register also offers
the user control of device operation. For more
detailed information on the CPU Control
Status Register, see the CPU CSR Register
description section of this data sheet.

(1)

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For more details on the EDMA parameter RAM six-word parameter entry structure, see Figure 4-3.

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Figure 4-3. EDMA Channel Parameter Entries (Six Words) for Each EDMA Event

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Table 4-7. EDMA Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01A0 0800−01A0 FEFC — Reserved

01A0 FF00 ESEL0 EDMA event selector 0
01A0 FF04 ESEL1 EDMA event selector 1

01A0 FF08−01A0 FF0B — Reserved

01A0 FF0C ESEL3 EDMA event selector 3

01A0 FF1F−01A0 FFDC — Reserved

01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPR Channel interrupt pending register
01A0 FFE8 CIER Channel interrupt enable register
01A0 FFEC CCER Channel chain enable register
01A0 FFF0 ER Event register
01A0 FFF4 EER Event enable register
01A0 FFF8 ECR Event clear register
01A0 FFFC ESR Event set register

01A1 0000−01A3 FFFF — Reserved

Table 4-8. Quick DMA (QDMA) and Pseudo Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0200 0000 QOPT QDMA options parameter
0200 0004 QSRC QDMA source address
0200 0008 QCNT QDMA frame count
0200 000C QDST QDMA destination address
0200 0010 QIDX QDMA index

0200 0014−0200 001C — Reserved

0200 0020 QSOPT QDMA pseudo options
0200 0024 QSSRC QDMA pseudo source address
0200 0028 QSCNT QDMA pseudo frame count
0200 002C QSDST QDMA pseudo destination address
0200 0030 QSIDX QDMA pseudo index

(1) All the QDMA and Pseudo registers are write accessible only.

SGUS049K–AUGUST 2003– REVISED APRIL 2011

(1)

Table 4-9. PLL Controller Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01B7 C000 PLLPID Peripheral identification

01B7 C004−01B7 C0FF — Reserved

01B7 C100 PLLCSR PLL control/status register

01B7 C104−01B7 C10F — Reserved

01B7 C110 PLLM PLL multiplier control
01B7 C114 PLLDIV0 PLL controller divider 0
01B7 C118 PLLDIV1 PLL controller divider 1
01B7 C11C PLLDIV2 PLL controller divider 2
01B7 C120 PLLDIV3 PLL controller divider 3
01B7 C124 OSCDIV1 Oscillator divider 1

01B7 C128−01B7 DFFF — Reserved

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(C6713/13B value: 0x00010801 for PLL Controller)

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Table 4-10. McASP0 and McASP1 Registers

HEX ADDRESS RANGE

McASP0 McASP1

3C00 0000−3C00 FFFF 3C10 0000−3C10 FFFF RBUF/XBUFx data bus. Used when RSEL or XSEL bits = 0 (these bits are located

01B4 C000 01B5 0000 MCASPPIDx
01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management

01B4 C008 01B5 0008 — Reserved
01B4 C00C 01B5 000C — Reserved
01B4 C010 01B5 0010 PFUNCx Pin function
01B4 C014 01B5 0014 PDIRx Pin direction
01B4 C018 01B5 0018 PDOUTx Pin data out

01B4 C01C 01B5 001C PDIN/PDSETx Read returns: PDIN

01B4 C020 01B5 0020 PDCLRx Pin data clear

01B4 C024−01B4 C040 01B5 0024−01B5 0040 — Reserved

01B4 C044 01B5 0044 GBLCTLx Global control
01B4 C048 01B5 0048 AMUTEx Mute control
01B4 C04C 01B5 004C DLBCTLx Digital loopback control
01B4 C050 01B5 0050 DITCTLx DIT mode control

01B4 C054−01B4 C05C 01B5 0054−01B5 005C — Reserved

01B4 C060 01B5 0060 RGBLCTLx
01B4 C064 01B5 0064 RMASKx Receiver format unit bit mask

01B4 C068 01B5 0068 RFMTx Receive bit stream format
01B4 C06C 01B5 006C AFSRCTLx Receive frame sync control
01B4 C070 01B5 0070 ACLKRCTLx Receive clock control
01B4 C074 01B5 0074 AHCLKRCTLx High-frequency receive clock control
01B4 C078 01B5 0078 RTDMx Receive TDM slot 0−31
01B4 C07C 01B5 007C RINTCTLx Receiver interrupt control
01B4 C080 01B5 0080 RSTATx Status − receiver
01B4 C084 01B5 0084 RSLOTx Current receive TDM slot
01B4 C088 01B5 0088 RCLKCHKx Receiver clock check control

01B4 C08C−01B4 C09C 01B5 008C−01B5 009C — Reserved

01B4 C0A0 01B5 00A0 XGBLCTLx
01B4 C0A4 01B5 00A4 XMASKx Transmit format unit bit mask

01B4 C0A8 01B5 00A8 XFMTx Transmit bit stream format

01B4 C0AC 01B5 00AC AFSXCTLx Transmit frame sync control

01B4 C0B0 01B5 00B0 ACLKXCTLx Transmit clock control
01B4 C0B4 01B5 00B4 AHCLKXCTLx High-frequency Transmit clock control
01B4 C0B8 01B5 00B8 XTDMx Transmit TDM slot 0−31

01B4 C0BC 01B5 00BC XINTCTLx Transmit interrupt control

01B4 C0C0 01B5 00C0 XSTATx Status − transmitter
01B4 C0C4 01B5 00C4 XSLOTx Current transmit TDM slot
01B4 C0C8 01B5 00C8 XCLKCHKx Transmit clock check control

01B4 C0D0−01B4 C0FC 01B5 00CC−01B5 00FC — Reserved

01B4 C100 01B5 0100 DITCSRA0x Left (even TDM slot) channel status register file
01B4 C104 01B5 0104 DITCSRA1x Left (even TDM slot) channel status register file
01B4 C108 01B5 0108 DITCSRA2x Left (even TDM slot) channel status register file
01B4 C10C 01B5 0108 DITCSRA3x Left (even TDM slot) channel status register file
01B4 C110 01B5 0110 DITCSRA4x Left (even TDM slot) channel status register file

ACRONYM REGISTER NAME AND DESCRIPTION

McASPx receive buffer or McASPx transmit buffer via the peripheral
in the RFMT or XFMT registers, respectively).

Peripheral identification
[13/13B value: 0x00100101 for McASP0 and for McASP1]

Pin data in/data set
Writes affect: PDSET

Alias of GBLCTL containing only Receiver Reset bits; allows
transmit to be reset independently from receive

Alias of GBLCTL containing only Transmitter Reset bits; allows
transmit to be reset independently from receive

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Table 4-10. McASP0 and McASP1 Registers (continued)

HEX ADDRESS RANGE

McASP0 McASP1

01B4 C114 01B5 0114 DITCSRA5x Left (even TDM slot) channel status register file
01B4 C118 01B5 0118 DITCSRB0x Right (odd TDM slot) channel status register file
01B4 C11C 01B5 011C DITCSRB1x Right (odd TDM slot) channel status register file
01B4 C120 01B5 0120 DITCSRB2x Right (odd TDM slot) channel status register file
01B4 C124 01B5 0124 DITCSRB3x Right (odd TDM slot) channel status register file
01B4 C128 01B5 0128 DITCSRB4x Right (odd TDM slot) channel status register file
01B4 C12C 01B5 012C DITCSRB5x Right (odd TDM slot) channel status register file
01B4 C130 01B5 0130 DITUDRA0x Left (even TDM slot) user data register file
01B4 C134 01B5 0134 DITUDRA1x Left (even TDM slot) user data register file
01B4 C138 01B5 0138 DITUDRA2x Left (even TDM slot) user data register file
01B4 C13C 01B5 013C DITUDRA3x Left (even TDM slot) user data register file
01B4 C140 01B5 0140 DITUDRA4x Left (even TDM slot) user data register file
01B4 C144 01B5 0144 DITUDRA5x Left (even TDM slot) user data register file
01B4 C148 01B5 0148 DITUDRB0x Right (odd TDM slot) user data register file
01B4 C14C 01B5 014C DITUDRB1x Right (odd TDM slot) user data register file
01B4 C150 01B5 0150 DITUDRB2x Right (odd TDM slot) user data register file
01B4 C154 01B5 0154 DITUDRB3x Right (odd TDM slot) user data register file
01B4 C158 01B5 0158 DITUDRB4x Right (odd TDM slot) user data register file
01B4 C15C 01B5 015C DITUDRB5x Right (odd TDM slot) user data register file

01B4 C160−01B4 C17C 01B5 0160−01B5 017C — Reserved

01B4 C180 01B5 0180 SRCTL0x Serializer 0 control
01B4 C184 01B5 0184 SRCTL1x Serializer 1 control
01B4 C188 01B5 0188 SRCTL2x Serializer 2 control
01B4 C18C 01B5 018C SRCTL3x Serializer 3 control
01B4 C190 01B5 0190 SRCTL4x Serializer 4 control
01B4 C194 01B5 0194 SRCTL5x Serializer 5 control
01B4 C198 01B5 0198 SRCTL6x Serializer 6 control
01B4 C19C 01B5 019C SRCTL7x Serializer 7 control

01B4 C1A0−01B4 C1FC 01B5 01A0−01B5 01FC — Reserved

01B4 C200 01B5 0200 XBUF0x Transmit buffer for serializer 0 through configuration bus
01B4 C204 01B5 0204 XBUF1x Transmit buffer for serializer 1 through configuration bus
01B4 C208 01B5 0208 XBUF2x Transmit buffer for serializer 2 through configuration bus
01B4 C20C 01B5 020C XBUF3x Transmit buffer for serializer 3 through configuration bus
01B4 C210 01B5 0210 XBUF4x Transmit buffer for serializer 4 through configuration bus
01B4 C214 01B5 0214 XBUF5x Transmit buffer for serializer 5 through configuration bus
01B4 C218 01B5 0218 XBUF6x Transmit buffer for serializer 6 through configuration bus
01B4 C21C 01B5 021C XBUF7x Transmit buffer for serializer 7 through configuration bus

01B4 C220−01B4 C27C 01B5 C220−01B5 027C — Reserved

01B4 C280 01B5 0280 RBUF0x Receive buffer for serializer 0 through configuration bus
01B4 C284 01B5 0284 RBUF1x Receive buffer for serializer 1 through configuration bus
01B4 C288 01B5 0288 RBUF2x Receive buffer for serializer 2 through configuration bus
01B4 C28C 01B5 028C RBUF3x Receive buffer for serializer 3 through configuration bus
01B4 C290 01B5 0290 RBUF4x Receive buffer for serializer 4 through configuration bus
01B4 C294 01B5 0294 RBUF5x Receive buffer for serializer 5 through configuration bus
01B4 C298 01B5 0298 RBUF5x Receive buffer for serializer 6 through configuration bus
01B4 C29C 01B5 029C RBUF7x Receive buffer for serializer 7 through configuration bus

01B4 C2A0−01B4 FFFF 01B5 02A0−01B5 3FFF — Reserved

(1) The transmit buffers for serializers 0−7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register).
(2) The receive buffers for serializers 0−7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register).

ACRONYM REGISTER NAME AND DESCRIPTION

(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)

(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)

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Table 4-11. I2C0 and I2C1 Registers

HEX ADDRESS RANGE

I2C0 I2C1

01B4 0000 01B4 4000 I2COARx I2Cx own address register
01B4 0004 01B4 4004 I2CIERx I2Cx interrupt enable register
01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register

01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider

01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider
01B4 0014 01B4 4014 I2CCNTx I2Cx data count
01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register

01B4 001C 01B4 401C I2CSARx I2Cx slave address register

01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register
01B4 0024 01B4 4024 I2CMDRx I2Cx mode register
01B4 0028 01B4 4028 I2CISRCx I2Cx interrupt source

01B4 002C 01B4 402C — Reserved

01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler
01B4 0034 01B4 4034

01B4 0038 01B4 4038

01B4 003C−01B4 3FFF 01B4 403C−01B4 7FFF — Reserved

ACRONYM REGISTER NAME AND DESCRIPTION

I2CPID10 I2Cx peripheral identification 1
I2CPID11 (C6713/13B value: 0x0000 0103)

I2CPID20 I2Cx peripheral identification 2
I2CPID21 (C6713/13B value: 0x0000 0005)

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Table 4-12. HPI Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

— HPID HPI data register Host read/write access only
— HPIA HPI address register Host read/write access only

0188 0000 HPIC HPI control register Both Host/CPU read/write access

0188 0004−018B FFFF — Reserved

Table 4-13. Timer 0 and Timer 1 Registers

HEX ADDRESS RANGE

TIMER 0 TIMER 1

0194 0000 0198 0000 CTLx Timer x control register timer, monitors the timer status, and

0194 0004 0198 0004 PRDx Timer x period register clock cycles to count. This number

0194 0008 0198 0008 CNTx Timer x counter register

0194 000C−0197 FFFF 0198 000C−019B FFFF — Reserved

ACRONYM REGISTER NAME COMMENTS

Determines the operating mode of the
controls the function of the TOUT pin.

Contains the number of timer input
controls the TSTAT signal frequency.

Contains the current value of the
incrementing counter.

Table 4-14. McBSP0 and McBSP1 Registers

HEX ADDRESS RANGE

McBSP0 McBSP1

018C 0000 0190 0000 DRRx The CPU and EDMA controller can only read this register; they

3000 0000−33FF FFFF 3400 0000−37FF FFFF DRRx McBSPx data receive register via peripheral data bus

018C 0004 0190 0004 DXRx McBSPx data transmit register via configuration bus

3000 0000−33FF FFFF 3400 0000−37FF FFFF DXRx McBSPx data transmit register via peripheral data bus

018C 0008 0190 0008 SPCRx McBSPx serial port control register

018C 000C 0190 000C RCRx McBSPx receive control register

ACRONYM REGISTER NAME AND DESCRIPTION

McBSPx data receive register via configuration bus.
cannot write to it.

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Table 4-14. McBSP0 and McBSP1 Registers (continued)

HEX ADDRESS RANGE

McBSP0 McBSP1

018C 0010 0190 0010 XCRx McBSPx transmit control register
018C 0014 0190 0014 SRGRx McBSPx sample rate generator register
018C 0018 0190 0018 MCRx McBSPx multichannel control register

018C 001C 0190 001C RCERx McBSPx receive channel enable register

018C 0020 0190 0020 XCERx McBSPx transmit channel enable register
018C 0024 0190 0024 PCRx McBSPx pin control register

018C 0028−018F FFFF 0190 0028−0193 FFFF — Reserved

ACRONYM REGISTER NAME AND DESCRIPTION

Table 4-15. GPIO Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01B0 0000 GPEN GPIO enable
01B0 0004 GPDIR GPIO direction
01B0 0008 GPVAL GPIO value

01B0 000C — Reserved

01B0 0010 GPDH GPIO delta high
01B0 0014 GPHM GPIO high mask
01B0 0018 GPDL GPIO delta low

01B0 001C GPLM GPIO low mask

01B0 0020 GPGC GPIO global control
01B0 0024 GPPOL GPIO interrupt polarity

01B0 0028−01B0 3FFF — Reserved

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TRST

GP[7](EXT_INT7)

IEEE Standard

1149.1
(JTAG)

Emulation

Resetand
Interrupts

Control/Status

TDI

TDO

TMS

TCK

EMU0
EMU1

NMI

GP[6](EXT_INT6)
GP[5](EXT_INT5)/AMUTEIN0
GP[4](EXT_INT4)/AMUTEIN1

RESET

Clock/PLL

Oscillator

CLKIN

CLKMODE0

PLLHV

CLKOUT2/GP[2]

EMU2
EMU3
EMU4
EMU5

HHWIL/AFSR1

HCNTL0/AXR1[3]

HCNTL1/AXR1[1]

Data

RegisterSelect

Half-Word

Select

Control

HPI

(Host-PortInterface)

HAS

/ACLKX1

HR/W

/AXR1[0]

HCS

/AXR1[2]

HDS1

/AXR1[6]

HDS2

/AXR1[5]

HRDY

/ACLKR1

HINT

/GP[1]

HD15/GP[15]
HD14/GP[14]
HD13/GP[13]
HD12/GP[12]

HD11/GP[11]

HD10/GP[10]

HD9/GP[9]
HD8/GP[8]
HD7/GP[3]

HD6/AHCLKR1
HD5/AHCLKX1

HD4/GP[0]

HD3/AMUTE1

HD2/AFSX1
HD1/AXR1[7]
HD0/AXR1[4]

CLKOUT3

HD4/GP[0]

(A)

(A)

(A)

(A)

(B)

(B)

(B)

(B)

(B)

(C)

(C)

(C)

(C)

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4.5 Signal Groups Description

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A. These external pins are applicable to the GDP package only.
B. The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the

external interrupt sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000
DSP Interrupt Selector Reference Guide (literature number SPRU646).

C. All of these pins are external interrupt sources. For more details see the External Interrupt Sources section of this

data sheet.

D. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module.

Figure 4-4. CPU (DSP Core) and Peripheral Signals

30 OVERVIEW Copyright © 2003–2011, Texas Instruments Incorporated

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General-Purpose Input/Output(GPIO)Port

GP[7](EXT_INT7)
GP[6](EXT_INT6)
GP[5](EXT_INT5)/AMUTEIN0
GP[4](EXT_INT4)/AMUTEIN1

HD7/GP[3]
CLKOUT2/GP[2]
HINT

/GP[1]

HD4/GP[0]

GPIO

HD15/GP[15]
HD14/GP[14]
HD13/GP[13]
HD12/GP[12]
HD11/GP[11]

HD10/GP[10]

HD9/GP[9]

HD8/GP[8]

TOUT1/AXR0[4]

TOUT0/AXR0[2]

Timer 1

Timer

0

Timers

TINP1/AHCLKX0

TINP0/AXR0[3]

CLKS1/SCL1

SCL0

I2C1 I2C0

I Cs

2

DR1/SDA1

SDA0

(A)

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A. The GP[15:0} pins, through interrupt sharing, are external interrupt capable via GPINT0. GP[15:0] are also external

EDMA event source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources
sections of this data sheet.

B. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module.

Figure 4-5. Peripheral Signals

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CE3

ECLKOUT

ED[31:16]

CE2
CE1
CE0

EA[21:2]

BE3
BE2

BE1

BE0

CLKX1/AMUTE0

FSX1

DX1/AXR0[5]

CLKR1/AXR0[6]

FSR1/AXR0[7]

DR1/SDA1

CLKS1/SCL1

AOE

/SDRAS/SSOE
AWE/SDWE/SSWE
ARDY

CLKX0/ACLKX0
FSX0/AFSX0
DX0/AXR0[1]

CLKR0/ACLKR0
FSR0/AFSR0
DR0/AXR0[0]

CLKS0/AHCLKR0

Data

Memory Map

SpaceSelect

Address

ByteEnables

16

20

Memory
Control

EMIF

(ExternalMemoryInterface)

Receive Receive

McBSP1 McBSP0

Transmit Transmit

Clock Clock

McBSPs

(MultichannelBufferedSerialPorts)

ECLKIN

HOLD
HOLDA

BUSREQ

Bus

Arbitration

ARE/SDCAS/SSADS

ED[15:0]

16

(A)

(A)

(A)

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A. These external pins are applicable to the GDP package only.
B. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module.

Figure 4-6. Peripheral Signals

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McASP0

(Multichannel AudioSerialPort0)

CLKX0/ACLKX0

CLKS0/AHCLKR0

Transmit

Clock

Generator

GP[5](EXT_INT5)/AMUTEIN0

AutoMute

Logic

CLKX1/AMUTE0

FSX0/AFSX0

Transmit

FrameSync

FSR0/AFSR0

Receive

FrameSync

CLKR0/ACLKR0

TINP1/AHCLKX0

ReceiveClock

Generator

TOUT1/AXR0[4]

TOUT0/AXR0[2]

DX0/AXR0[1]
DR0/AXR0[0]

DX1/AXR0[5]

TINP0/AXR0[3]

CLKR1/AXR0[6]

FSR1/AXR0[7]

8-SerialPorts

Flexible

Partitioning

Tx,Rx,OFF

Transmit

ClockCheck

Circuit

ReceiveClock

CheckCircuit

ErrorDetect

(seeNoteA)

(Transmit/ReceiveDataPins)

(ReceiveBitClock) (TransmitBitClock)

(ReceiveMasterClock) (TransmitMasterClock)

(ReceiveFrameSyncor

Left/RightClock)

(TransmitFrameSyncor
Left/RightClock)

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A. The McASP Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute

input.
B. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module.
C. Boldface and italicized text within parentheses denotes the function of the pins in an audio system.

Figure 4-7. Peripheral Signals

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HD0/AXR1[4]

HCS

/AXR1[2]

HCNTL1/AXR1[1]

HR/W

/AXR1[0]

McASP1

(Multichannel AudioSerialPort1)

HDS2

/AXR1[5]

HAS/ACLKX1

HD5/AHCLKX1

Transmit

Clock

Generator

HCNTL0/AXR1[3]

GP[4](EXT_INT4)/AMUTEIN1

AutoMute

Logic

HD3/AMUTE1

HD2/AFSX1

Transmit

FrameSync

HHWIL/AFSR1

Receive

FrameSync

HDS1/AXR1[6]

HD1/AXR1[7]

HRDY/ACLKR1
HD6/AHCLKR1

ReceiveClock

Generator

8-SerialPorts

Flexible

Partitioning

Tx,Rx,OFF

Transmit

ClockCheck

Circuit

ReceiveClock

CheckCircuit

ErrorDetect
(seeNoteA)

(Transmit/ReceiveDataPins)

(ReceiveBitClock) (TransmitBitClock)

(ReceiveMasterClock) (TransmitMasterClock)

(ReceiveFrameSyncor

Left/RightClock)

(TransmitFrameSyncor
Left/RightClock)

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A. The McASP Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute

input.
B. On multiplexed pins, boldface text denotes the active function of the pin for that particular peripheral module.
C. Boldface and italicized text within parentheses denotes the function of the pins in an audio system.

Figure 4-8. Peripheral Signals

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5 DEVICE CONFIGURATIONS

On the C6713/13B devices, bootmode and certain device configurations/peripheral selections are
determined at device reset, while other device configurations/peripheral selections are
software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200]
after device reset.

5.1 Device Configurations at Device Reset

Table 5-1 describes the C6713 and C6713B device configuration pins, which are set up via internal or

external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, HD12 [13B only]), and
CLKMODE0 pin. These configuration pins must be in the desired state until reset is released. For proper
device operation, do not oppose the HD [13, 11:9, 7, 1, 0] pins with external pullups/pulldowns at reset.
For more details on these device configuration pins, see the Terminal Functions table and the Debugging

Considerations section of this data sheet.

Table 5-1. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12 [13B only], and CLKMODE0)

CONFIGURATION

PIN

(2)

HD12

HD8 B17 0 – System operates in Big Endian mode

HD[4:3]

(BOOTMODE)

CLKMODE0 C4

(1) All other HD pins [HD [15, 13:9, 7:5, 2:0] (for 13) or HD [15, 13, 11:9, 7:5, 2:0] (for 13B)] have pullups/pulldowns (IPUs or IPDs). For

proper device operation of the HD [15, 13:9, 7, 1, 0] (for 13) or HD [13, 11:9, 7, 1, 0] (for 13B), do not oppose these pins with external
pullups/pulldowns at reset; however, the HD[6, 5, 2] (for 13) or HD[15, 6, 5, 2] (for 13B) pins can be opposed and driven during reset.

(2) IPD = Internal pulldown, IPU = Internal pullup. To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown

resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.

(2)

GDP FUNCTIONAL DESCRIPTION

EMIF Big Endian mode correctness (EMIFBE) [C6713B only]
For a C6713BGDP:

0 – The EMIF data will always be presented on the ED[7:0] side of the bus, regardless of the

endianess mode (Little/Big Endian).

1 – In Little Endian mode (HD8 = 1), the 8-bit or 16-bit EMIF data will be present on the

ED[7:0] side of the bus.

C15

For a C6713BPYP, when Big Endian mode is selected (LENDIAN = 0), for proper device operation the
EMIFBE pin must be externally pulled low.
This enhancement is not supported on the C6713 device.
For proper C6713 device operation, do not oppose the internal pullup (IPU) resistor on this pin.
This new functionality does not affect systems using the current default value of HD12 = 1. For more
detailed information on the big endian mode correctness, see the EMIF Big Endian Mode Correctness
[C6713B only] portion of this data sheet.

Device Endian mode (LEND)

Bootmode Configuration pins (BOOTMODE)

C19, C20

For more detailed information on these bootmode configurations, see the Bootmode section of this
data sheet.

Clock generator input clock source select

This pin must be pulled to the correct level even after reset.

In Big Endian mode (HD8 = 0), the 8-bit or 16-bit EMIF data will be present on the
ED[31:24] side of the bus [default].

1 – System operates in Little Endian mode (default)

00 – HPI boot/Emulation boot
01 – CE1 width 8-bit, asynchronous external ROM boot with default timings (default mode)
10 – CE1 width 16-bit, asynchronous external ROM boot with default timings
11 – CE1 width 32-bit, asynchronous external ROM boot with default timings

0 – Reserved. Do not use.
1 – CLKIN square wave [default]

(1)

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5.2 Peripheral Pin Selection at Device Reset

Some C6713/13B peripherals share the same pins (internally MUXed) and are mutually exclusive (that is,
HPI, general-purpose input/output pins GP[15:8, 3, 1, 0], and McASP1).

• HPI, McASP1, and GPIO peripherals
The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or

McASP1 peripheral pins and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 5-2).

Table 5-2. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins)

PERIPHERAL PERIPHERAL

PIN SELECTION PINS SELECTED

HPI_EN McASP1 and

(HD14 Pin) [173, C14] GP[15:8, 3, 1, 0]

0 ✓ are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as

1 ✓

(1) The HPI_EN (HD[14]) pin cannot be controlled via software.

HPI

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(1)

DESCRIPTION

HPI_EN = 0
HPI pins are disabled; McASP1 peripheral pins and GP[15:8, 3, 1, 0] pins

McASP1 and GPIO pins, respectively. To use the GPIO pins, the
appropriate bits in the GPEN and GPDIR registers need to be configured.

HPI_EN = 1
HPI pins are enabled; McASP1 peripheral pins and GP[15:8, 3, 1, 0] pins
are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins
function as HPI pins.

5.3 Peripheral Selection/Device Configurations Via the DEVCFG Control Register

The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0,
McBSP1, McASP0, I2C1, and timer peripherals. The DEVCFG register also offers the user control of the
EMIF input clock source and the timer output pins. For more detailed information on the DEVCFG register
control bits, see Table 5-3 and Table 5-4.

Table 5-3. Device Configuration Register (DEVCFG) [Address Location: 0x019C0200−0x019C02FF]

31 16

Reserved

15 5 4 3 2 1 0

Reserved

LEGEND: R = Read, W = Write, --n = value at reset

(1) Do not write non-zero values to these bit locations.

(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

R/W-0

EKSRC TOUT1SEL TOUT0SEL MCBSP0DIS MCBSP1DIS

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Table 5-4. Device Configuration Register (DEVCFG) Selection Bit Descriptions

BIT NO. NAME DESCRIPTION

31:5 Reserved Reserved. Do not write non-zero values to these bit locations.

EMIF input clock source bit.

4 EKSRC

3 TOUT1SEL

2 TOUT0SEL

1 MCBSP0DIS ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default).

0 MCBSP1DIS

Determines which clock signal is used as the EMIF input clock.

0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default).
1 = ECLKIN external pin is the EMIF input clock source.

Timer 1 output (TOUT1) pin function select bit.
Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral
selection bits in the DEVCFG register.

0 = The pin functions as a Timer 1 output (TOUT1) pin (default).
1 = The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]). The Timer 1 module

is still active.

Timer 0 output (TOUT0) pin function select bit.
Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral
selection bits in the DEVCFG register.

0 = The pin functions as a Timer 0 output (TOUT0) pin (default).
1 = The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]). The Timer 0 module

is still active.

Multichannel Buffered Serial Port 0 (McBSP0) disable bit.
Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled.

0 = McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,

If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT mode only.

1 = McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,

ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled.

Multichannel Buffered Serial Port 1 (McBSP1) disable bit.
Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled.

0 = McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0

peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default)

1 = McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0

peripheral pins (AXR0[7:5] and AMUTE0) are enabled.

5.4 Multiplexed Pins

Multiplexed (MUXed) pins are pins that are shared by more than one peripheral and are internally
multiplexed. Most of these pins are configured by software via the device configuration register
(DEVCFG), and the others (specifically, the HPI pins) are configured by external pullup/pulldown resistors
only at reset. The MUXed pins that are configured by software can be programmed to switch
functionalities at any time. The MUXed pins that are configured by external pullup/pulldown resistors are
mutually exclusive; only one peripheral has primary control of the function of these pins after reset.

Table 5-5 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register.
Table 5-6 identifies the multiplexed pins on the C6713/13B devices, shows the default (primary) function

and the default settings after reset, and describes the pins, registers, etc., necessary to configure the
specific multiplexed functions.

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Table 5-5. Peripheral Pin Selection Matrix

SELECTION BITS PERIPHERAL PIN AVAILABILITY

BIT BIT GPIO

NAME VAL PINS

HPI_EN
(boot config 0 None
pin)

HPI_EN
(boot config 1 None All
pin)

0 None All

ACLKX0

MCBSP0DI
S (DEVCFG
bit)

MCBSP1DI
S (DEVCFG
bit)

TOUT0SEL

(DEVCFG

bit)

TOUT1SEL

(DEVCFG

bit)

HD12 (boot

config pin)

[13BGDP]

(3)

ACLKR0
AFSX0
AFSR0

1 None

AHCLKR
0
AXR0[0]
AXR0[1]

NO

AMUTE0

0 AXR0[5] None All

AXR0[6]
AXR0[7]

AMUTE0
AXR0[5]

1 All None

AXR0[6]
AXR0[7]

NO

0 TOUT0

AXR0[2]

1 AXR0[2]

NO TOUT1

0

AXR0[4]

1 AXR0[4]

0

1

MCASP0

(2)

MCASP1 MCBSP0 MCBSP1 TIMER0 TIMER1 HPI EMIF

AHCLKX1
AHCLKR1 GP[0:1],
ACLKX1 GP[3],
ACLKR1 GP[8:15]
AFSX1 abc
AFSR1 Plus:
AMUTE1 GP[2]
AXR1[0] ctrl’d by
to GP2EN bit
AXR1[7]

I2C0 I2C1

NO

TOUT0

(1)

NO

TOUT1

NO

GP[0:1],
GP[3],
GP[8:15]

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ED[7:0];
HD8 = 1/0

ED[7:0} side
[HD8 = 1 (Little)]
ED[31:24] side
[HD8 = 0 (Big)]

(1) Gray blocks indicate that the peripheral is not affected by the selection bit.
(2) The McASP0 pins, AXR0[3] and AHCLKX0, are shared with the timer input pins, TINP0 and TINP1, respectively. See Table 5-6 for

more detailed information.

(3) For more detailed information on endianness correction, see the EMIF Big Endian Mode Correctness [C6713B only] section of this data

sheet.

Table 5-6. C6713/13B Device Multiplexed/Shared Pins

MULTIPLEXED PIN

NAME GDP FUNCTION DEFAULT SETTING DESCRIPTION

CLKOUT2/GP[2] Y12 CLKOUT2

38 DEVICE CONFIGURATIONS Copyright © 2003–2011, Texas Instruments Incorporated

DEFAULT

GP2EN = 0 (GPEN register bit) When the CLKOUT2 pin is enabled, the CLK2EN bit in the
GP[2] function disabled, CLKOUT2 EMIF global control register (GBLCTL) controls the
enabled CLKOUT2 pin.

CLK2EN = 0: CLKOUT2 held high
CLK2EN = 1: CLKOUT2 enabled to clock [default].

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Table 5-6. C6713/13B Device Multiplexed/Shared Pins (continued)

MULTIPLEXED PIN

NAME GDP FUNCTION DEFAULT SETTING DESCRIPTION

GP[5](EXT_INT5)/AMUTEIN
0 C1 GP[5](EXT_INT5)
GP[4](EXT_INT4)/AMUTEIN C2 GP[4](EXT_INT4)
1

CLKS0/AHCLKR0 K3 By default, McBSP0 peripheral pins are enabled upon
DR0/AXR0[0] J1
DX0/AXR0[1] H2
FSR0/AFSR0 J3 McBSP0 pin function
FSX0/AFSX0 H1
CLKR0/ACLKR0 H3
CLKX0/ACLKX0 G3
CLKS1/SCL1 E1
DR1/SDA1 M2
DX1/AXR0[5] L2
FSR1/AXR0[7] M3
CLKR1/AXR0[6] M1
CLKX1/AMUTE0 L3
HINT/GP[1] J20
HD15/GP[15] B14
HD14/GP[14] C14
HD13/GP[13] A15
HD12/GP[12] C15
HD11/GP[11] A16
HD10/GP[10] B16
HD9/GP[9] C16
HD8/GP[8] B17 GPIO pins, an external pulldown resistor must be provided
HD7/GP[3] A18
HD4/GP[0] C19
HD1/AXR1[7] D20
HD0/AXR1[4] E20
HCNTL1/AXR1[1] G19
HCNTL0/AXR1[3] G18 GPxEN = 1: GP[x] pin enabled.
HR/W/AXR1[0] G20 GPxDIR = 0: GP[x] pin is an input.
HDS1/AXR1[6] E19 GPxDIR = 1: GP[x] pin is an output.
HDS2/AXR1[5] F18
HCS/AXR1[2] F20 McASP1 pin direction is controlled by the PDIR[x] bits in
HD6/AHCLKR1 C17
HD5/AHCLKX1 B18
HD3/AMUTE1 C20
HD2/AFSX1 D18
HHWIL/AFSR1 H20
HRDY/ACLKR1 H19
HAS/ACLKX1 E18

DEFAULT

No Function To use these software-configurable GPIO pins, the
GPxDIR = 0 (input) GPxEN bits in the GP Enable Register and the GPxDIR
GP5EN = 0 (disabled) bits in the GP Direction Register must be properly
GP4EN = 0 (disabled) configured.
[(GPEN register bits)
GP[x] function disabled]

MCBSP0DIS = 0
(DEVCFG register bit)
McASP0 pins disabled,
McBSP0 pins enabled

MCBSP1DIS = 0 reset (I2C1 and McASP0 pins are disabled).

McBSP1 pin function

HPI (HPI enabled)
pin function McASP1 pins and 11 GPIO pins

(DEVCFG register bit) abc
I2C1 and McASP0 pins To enable the I2C1 and McASP0 peripheral pins, the
disabled, McBSP1 pins enabled MCBSP1DIS bit in the DEVCFG register must be set to 1

HPI_EN (HD14 pin) = 1

are disabled.

GPxEN = 1: GP[x] pin enabled.
GPxDIR = 0: GP[x] pin is an input.
GPxDIR = 1: GP[x] pin is an output.

To use AMUTEIN0/1 pin function, the GP[5]/GP[4] pins
must be configured as an input, the INEN bit set to 1, and
the polarity through the INPOL bit selected in the
associated McASP AMUTE register.

reset (McASP0 pins are disabled).

abc

To enable the McASP0 peripheral pins, the MCBSP0DIS
bit in the DEVCFG register must be set to 1 (disabling the
McBSP0 peripheral pins).

By default, McBSP1 peripheral pins are enabled upon

(disabling the McBSP1 peripheral pins).

By default, the HPI peripheral pins are enabled at reset.
McASP1 peripheral pins and eleven GPIO pins are
disabled.

To enable the McASP1 peripheral pins and the eleven
on the HD14 pin setting HPI_EN = 0 at reset.

GP enable register and the GPxDIR bits in the GP
direction register must be properly configured. To use
these software-configurable GPIO pins, the GPxEN bits in
the

the McASP1PDIR register.

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Table 5-6. C6713/13B Device Multiplexed/Shared Pins (continued)

MULTIPLEXED PIN

NAME GDP FUNCTION DEFAULT SETTING DESCRIPTION

TINP0/AXR0[3] G2

TOUT0/AXR0[2] G1 bit) [TOUT0 pin enabled and

TINP1/AHCLKX0 F2 abc

TOUT1/AXR0[4] F1 bit) [TOUT1 pin enabled and

DEFAULT

Timer 0 McASP0PDIR = 0 (input) input until the McASP0 peripheral forces an output).
input function [specifically AXR0[3] bit] abc

Timer 0
output function

Timer 1 McASP0PDIR = 0 (input)
input function [specifically AHCLKX bit]

Timer 1
output function

TOUT0SEL = 0 (DEVCFG register
McASP0 AXR0[2] pin disabled]

TOUT1SEL = 0 (DEVCFG register
McASP0 AXR0[4] pin disabled]

By default, the Timer 0 input pin is enabled (and a shared

McASP0PDIR = 0 input, = 1 output
By default, the Timer 0 output pin is enabled.

abc

To enable the McASP0 AXR0[2] pin, the TOUT0SEL bit in
the DEVCFG register must be set to 1 (disabling the
Timer 0 peripheral output pin function).

abc

The AXR2 bit in the McASP0PDIR register controls the
direction (input/output) of the AXR0[2] pin.

McASP0PDIR = 0 input, = 1 output
By default, the Timer 1 input and McASP0 clock function

are enabled as inputs.
For the McASP0 clock to function as an output:

McASP0PDIR = 1 (specifically the AHCLKX bit).
By default, the Timer 1 output pin is enabled.

abc

To enable the McASP0 AXR0[4] pin, the TOUT1SEL bit in
the DEVCFG register must be set to 1 (disabling the
Timer 1 peripheral output pin function).

abc

The AXR4 bit in the McASP0PDIR register controls the
direction (input/output) of the AXR0[4] pin.

McASP0PDIR = 0 input, = 1 output

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ED[31:16],

ED[15:0]

CE[3:0],BE[3:0],

HOLDA

,HOLD,

BUSREQ,ECLKIN,

ECLKOUT,

ARE

/SDCAS/SSADS,

AWE

/SDWE/SSWE,

AOE

/SDRAS/SSOE,

ARDY

HPI

I2C1

McBSP1

McBSP0

TIMER1

TIMER0

Clock,

System,

EMU,and

Reset

I2C0

GPIO

and

EXT_INT

McASP1

CLKIN,CLKOUT3,CLKMODE0,
PLLHV,TMS,TDO,TDI,TCK,
TRST

,EMU[5:3,1,0],RESET,

NMI

GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)

GP[15:8,3:1]

McASP0

SCL0,SDA0

32

20

8

DEVCFGRegisterValue: 0x0000000F

MCBSP0DIS= 1
MCBSP1DIS= 1
TOUT0SEL=1
TOUT1SEL=1
EKSRC=0

HPI_EN(HD14)=0
GP2ENBIT=1(enablingGPEN.[2])

EA[21:2]

Shadingdenotesaperipheralmodulenotavailableforthisconfiguration.

SCL1,SDA1

8

AXR0[7:0]

{TINP0/AXR0[3]}

AXR1[7:0]

AFSX1,AFSR1,ACLKX1,
ACLKR1,AHCLKR1,
AHCLKX1,AMUTE1

AMUTE0,
TINP1/AHCLKX0,
AHCLKR0,
ACLKR0,
ACLKX0,AFSR0,
AFSX0

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5.5 Configuration Examples

SGUS049K–AUGUST 2003– REVISED APRIL 2011

Figure 5-1 through Figure 5-6 illustrate examples of peripheral selections that are configurable on this

device.

Figure 5-1. Configuration Example A (Two I2C + Two McASP + GPIO)

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ED[31:16],

ED[15:0]

CE[3:0],BE[3:0],

HOLDA

,HOLD,

BUSREQ,ECLKIN,

ECLKOUT,

ARE

/SDCAS/SSADS,

AWE

/SDWE/SSWE,

AOE

/SDRAS/SSOE,

ARDY

HPI

I2C1

McBSP1

McBSP0

TIMER1

TIMER0

Clock,

System,

EMU,and

Reset

I2C0

GPIO

and

EXT_INT

McASP1

CLKIN,CLKOUT3,CLKMODE0,
PLLHV,TMS,TDO,TDI,TCK,
TRST

,EMU[5:3,1,0],RESET,

NMI

GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)

GP[15:8,3:1]

McASP0

SCL0,SDA0

AFSX1,AFSR1,ACLKX1,
ACLKR1,AHCLKR1,
AHCLKX1,AMUTE1

32

20

8

DEVCFGRegisterValue: 0x0000000E

MCBSP0DIS= 1
MCBSP1DIS= 0
TOUT0SEL=1
TOUT1SEL=1
EKSRC=0

HPI_EN(HD14)=0
GP2ENBIT=1(enablingGPEN.[2])

EA[21:2]

Shadingdenotesaperipheralmodulenotavailableforthisconfiguration.

DR1,CLKS1,

CLKR1,CLKX1,

FSR1,DX1,

FSX1

5

AXR1[7:0]

AXR0[4:0]

{TINP0/AXR0[3]}

TINP1/AHCLKX0,
AHCLKR0,
ACLKR0,
ACLKX0,AFSR0,
AFSX0

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Figure 5-2. Configuration Example B (One I2C + One McBSP + Two McASP + GPIO)

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EMIF

ED[31:16],

ED[15:0]

CE[3:0],BE[3:0],

HOLDA

,HOLD,

BUSREQ,ECLKIN,

ECLKOUT,

ARE

/SDCAS/SSADS,

AWE

/SDWE/SSWE,

AOE

/SDRAS/SSOE,

ARDY

HPI

I2C1

McBSP1

SCL1,SDA1

McBSP0

TIMER1

TIMER0

Clock,

System,

EMU,and

Reset

I2C0

GPIO

and

EXT_INT

McASP1

CLKIN,CLKOUT3,CLKMODE0,
PLLHV,TMS,TDO,TDI,TCK,
TRST

,EMU[5:3,1,0],RESET,

NMI

GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)

GP[15:8,3:1]

McASP0

(DITMode)

SCL0,SDA0

AFSX1,AFSR1,ACLKX1,
ACLKR1,AHCLKR1,
AHCLKX1,AMUTE1

32

20

8

DEVCFGRegisterValue: 0x0000000D

MCBSP0DIS= 0
MCBSP1DIS= 1
TOUT0SEL=1
TOUT1SEL=1
EKSRC=0

HPI_EN(HD14)=0
GP2ENBIT=1(enablingGPEN.[2])

EA[21:2]

Shadingdenotesaperipheralmodulenotavailableforthisconfiguration.

DR0,CLKS0,

CLKR0,CLKX0,

FSR0,DX0,

FSX0

6

AXR1[7:0]

AXR0[7:2]

{TINP0/AXR0[3]}

AMUTE0,
TINP1/AHCLKX0

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Figure 5-3. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO]

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EMIF

ED[31:16],

ED[15:0]

CE[3:0],BE[3:0],

HOLDA

,HOLD,

BUSREQ,ECLKIN,

ECLKOUT,

ARE

/SDCAS/SSADS,

AWE

/SDWE/SSWE,

AOE

/SDRAS/SSOE,

ARDY

HPI

I2C1

McBSP1

DR1,CLKS1,

CLKR1,CLKX1,

FSR1,DX1,

FSX1

McBSP0

TIMER1

TIMER0

Clock,

System,

EMU,and

Reset

I2C0

GPIO

and

EXT_INT

McASP1

CLKIN,CLKOUT3,CLKMODE0,
PLLHV,TMS,TDO,TDI,TCK,
TRST

,EMU[5:3,1,0],RESET,

NMI

GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)

GP[15:8,3:1]

McASP0

(DITMode)

SCL0,SDA0

AFSX1,AFSR1,ACLKX1,
ACLKR1,AHCLKR1,
AHCLKX1,AMUTE1

32

20

8

DEVCFGRegisterValue: 0x0000000C

MCBSP0DIS= 0
MCBSP1DIS= 0
TOUT0SEL=1
TOUT1SEL=1
EKSRC=0

HPI_EN(HD14)=0
GP2ENBIT=1(enablingGPEN.[2])

EA[21:2]

Shadingdenotesaperipheralmodulenotavailableforthisconfiguration.

DR0,CLKS0,

CLKR0,CLKX0,

FSR0,DX0,

FSX0

3

AXR1[7:0]

AXR0[4:2]

{TINP0/AXR0[3]}

TINP1/AHCLKX0

TOUT0/AXR0[2]

TOUT1/AXR0[4]

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Figure 5-4. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers]

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ED[31:16],

ED[15:0]

CE[3:0],BE[3:0],

HOLDA

,HOLD,

BUSREQ,ECLKIN,

ECLKOUT,

ARE

/SDCAS/SSADS,

AWE

/SDWE/SSWE,

AOE

/SDRAS/SSOE,

ARDY

HPI

I2C1

McBSP1

SCL1,SDA1

McBSP0

TIMER1

TIMER0

Clock,

System,

EMU,and

Reset

GPIO

and

EXT_INT

McASP1

CLKIN,CLKOUT3,CLKMODE0,
PLLHV,TMS,TDO,TDI,TCK,
TRST

,EMU[5:3,1,0],RESET,

NMI

GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)

McASP0

AXR0[7:0],

{TINP0/AXR0[3]}

32

20

8

DEVCFGRegisterValue: 0x0000000F

MCBSP0DIS= 1
MCBSP1DIS= 1
TOUT0SEL=1
TOUT1SEL=1
EKSRC=0

HPI_EN(HD14)=1
GP2ENBIT=0(enablingGPEN.[2])

EA[21:2]

Shadingdenotesaperipheralmodulenotavailableforthisconfiguration.

CLKOUT2

HD[15:0]

16

HINT,HHWIL,

HRDY

,HR/W,

HCNTRL1,

HCNTRL0,HCS

,

HDS2

,HDS1,

HAS

I2C0

AMUTE0,
TINP1/AHCLKX0,
AHCLKR0,
ACLKR0,
ACLKX0,AFSR0,
AFSX0

SCL0,SDA0

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Figure 5-5. Configuration Example E (1 I2C + HPI + 1 McASP)

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EMIF

ED [31:16],

ED[15:0]

CE[3:0] , BE[3:0] ,

HOLDA

, HOLD,

BUSREQ, ECLKIN ,

ECLKOUT,

ARE

/SDCAS/SSADS,

AWE

/SDWE/SSWE,

AOE

/SDRAS/SSOE,

ARDY

HPI

I2C1

McBSP1

McBSP0

TIMER1

TIMER0

Clock,

System ,

EMU, and

Reset

GPIO

and

EXT_INT

McASP1

CLKIN, CLKOUT3, CLKMODE0 ,
PLLHV, TMS, TDO, TDI, TCK,
TRST

, EMU[5:3,1,0], RESET,

NMI

GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)

McASP0

32

20

5

DEVCFG Register V alue: 0x0000 000E

MCBSP0DIS = 1
MCBSP1DIS = 0
TOUT0SEL = 1
TOUT1SEL = 1
EKSRC = 0

HPI_EN(HD14) = 1
GP2EN BIT = 0 (enabling GPEN.[2])

EA[21:2]

Shading denotes a peripheral module not available for this configuration.

DR1, CLKS1,

CLKR1, CLKX1 ,

FSR1, DX1,

FSX1

CLKOUT2

HD[15:0]

16

HINT, HHWIL,

HRDY

, HR/W,

HCNTRL1,

HCNTRL0, HCS

,

HDS2

, HDS1,

HAS

AXR0[4:0]

{TINP0/AXR0[3]}

I2C0

TINP1/AHCLKX0,
AHCLKR0 ,
ACLKR0 ,
ACLKX0, AFSR0 ,
AFSX0

SCL0, SDA0

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Figure 5-6. Configuration Example F (One McBSP + HPI + One McASP)

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5.6 Debugging Considerations

It is recommended that external connections be provided to peripheral selection/device configuration pins,
including HD[14, 8, 12 (for 13B only), 4, 3], and CLKMODE0. Although internal pullup resistors exist on
these pins, providing external connectivity adds convenience to the user in debugging and flexibility in
switching operating modes.

Internal pullup/pulldown resistors also exist on the non−configuration pins on the HPI data bus (HD[15,
13:9, 7:5, 2:0] (for 13) and HD[15, 13, 11:9, 7:5, 2:0] (for 13B)). For proper device operation of the HD[15,
13:9, 7, 1, 0] (for13) or HD[13, 11:9, 7, 1, 0] (for 13B), do not oppose the internal pullup/pulldown resistors
on these non-configuration pins with external pullup/pulldown resistors at reset. If an external controller
provides signals to these HD[15, 13:9, 7, 1, 0] (for 13) or HD[13, 11:9, 7, 1, 0] (for 13B) non-configuration
pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the
list of routed out, 3-stated, or not-driven pins recommended for external pullup/pulldown resistors, and
internal pullup/pulldown resistors for all devices pins, etc., see Terminal Functions. However, the HD[6, 5,
2] (for 13) or HD[15, 6, 5, 2] (for 13B) non-configuration pins can be opposed and driven during reset.

For the internal pullup/pulldown resistors for all device pins, see the Terminal Functions table.

6 TERMINAL FUNCTIONS

The Terminal Functions table identifies the external signal names, the associated pin (ball) numbers along
with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device

Configurations section of this data sheet.

SGUS049K–AUGUST 2003– REVISED APRIL 2011

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TERMINAL FUNCTIONS

PIN

SIGNAL NAME TYPE

CLKIN A3 I IPD Clock input
CLKOUT2/GP[2] Y12 O/Z IPD
CLKOUT3 D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller

CLKMODE0 C4 I IPU

PLLHV C5 A

TMS B7 I IPU JTAG test-port mode select
TDO A8 O/Z IPU JTAG test-port data out
TDI A7 I IPU JTAG test-port data in
TCK A6 I IPU JTAG test-port clock

TRST B6 I IPD
EMU5 B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.

EMU4 C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3 B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2 D3 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.

EMU1 B9
EMU0 D9

RESET A13 I — Device reset. When using boundary scan mode, drive the EMU[1:0] and RESET pins low.

NMI C13 I IPD

GP[7](EXT_INT7) E3 General-purpose input/output pins (I/O/Z), which also function as external interrupts

GP[6](EXT_INT6) D2

GP[5](EXT_INT5)/
AMUTEIN0

GP[4](EXT_INT4)/
AMUTEIN1

HINT/GP[1] J20 O/Z IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z)
HCNTL1/AXR1[1] G19 I IPU Host control: Selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z)
HCNTL0/AXR1[3] G18 I IPU Host control: Selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z)

HHWIL/AFSR1 H20 I IPU
HR/W/AXR1[0] G20 I IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z)

NO.

GDP

C1

C2

(1)

IPD/IPU

(3)

I/O/Z IPU

I/O/Z IPU

(2)

CLOCK/PLL CONFIGURATION

Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed
as GP[2] pin (I/O/Z).

Clock generator input clock source select

0: Reserved, do not use

1: CLKIN square wave [default]
For proper device operation, this pin must be either left unconnected or externally pulled up with a 1-kΩ resistor.
Analog power (3.3 V) for PLL (PLL filter)

JTAG EMULATION

JTAG test-port reset. For IEEE Std 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data
sheet.

Emulation [1:0]

• Select the device functional mode of operation

Operation: EMU[1:0]:

00 Boundary Scan/Functional Mode (see note)

01 Reserved

10 Reserved

11 Emulation/Functional Mode [default] (see the IEEE 1149.1 JTAG Compatibility Statement of this data

sheet)
The DSP can be placed in Functional mode when the EMU[1:0] pins are configured for either boundary scan or emulation.
Note: When the EMU[1:0] pins are configured for boundary scan mode, the internal pulldown (IPD) on the TRST signal must not be

opposed to operate in functional mode.
For the boundary scan mode, drive EMU[1:0] and RESET pins low.

RESETS AND INTERRUPTS

Nonmaskable interrupt

• Edge-driven (rising edge)

• Edge-driven

• Polarity independently selected via the external interrupt polarity register bits (EXTPOL.[3:0]), in addition to the GPIO registers.

GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by
the INEN bit in the associated McASP AMUTE register.

HOST-PORT INTERFACE (HPI)

Host half-word select: First or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync
or left/right clock (LRCLK) (I/O/Z).

DESCRIPTION

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(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
(2) IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD or 18-kΩ

resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]

(3) A = Analog signal
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TERMINAL FUNCTIONS (continued)

PIN

SIGNAL NAME TYPE

HD15/GP[15] B14
HD14/GP[14] C14
HD13/GP[13] A15
HD12/GP[12] C15
HD11/GP[11] A16 I/O/Z IPU
HD10/GP[10] B16
HD9/GP[9] C16
HD8/GP[8] B17
HD7/GP[3] A18

HD6/AHCLKR1 C17 I/O/Z IPU Host-port data pin 6 (I/O/Z) [default] or McASP1 receive high-frequency master clock (I/O/Z)
HD5/AHCLKX1 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [default] or McASP1 transmit high-frequency master clock (I/O/Z)
HD4/GP[0] C19 I/O/Z IPD Host-port data pin 4 (I/O/Z) [default] or this pin can be programmed as a GP[0] pin (I/O/Z)
HD3/AMUTE1 C20 I/O/Z IPU Host-port data pin 3 (I/O/Z) [default] or McASP1 mute output (O/Z)
HD2/AFSX1 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z)
HD1/AXR1[7] D20 I/O/Z IPU Host-port data pin 1 (I/O/Z) [default] or McASP1 data pin 7 (I/O/Z)
HD0/AXR1[4] E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [default] or McASP1 data pin 4 (I/O/Z)
HAS/ACLKX1 E18 I IPU Host address strobe (I) [default] or McASP1 transmit bit clock (I/O/Z)
HCS/AXR1[2] F20 I IPU Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z)
HDS1/AXR1[6] E19 I IPU Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z)
HDS2/AXR1[5] F18 I IPU Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z)
HRDY/ACLKR1 H19 O/Z IPD Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z)

CE3 V6
CE2 W6
CE1 W18
CE0 V17
BE3 V5
BE2 Y4
BE1 U19
BE0 V20

HOLDA J18 O/Z IPU Hold-request-acknowledge to the host
HOLD J17 I IPU Hold request from the host
BUSREQ J19 O/Z IPU Bus request output

ECLKIN Y11 I IPD External EMIF input clock source

ECLKOUT Y10 O/Z IPD EKSRC = 1 ECLKOUT is based on the external EMIF input clock source pin (ECLKIN)

ARE/SDCAS/
SSADS

AOE/SDRAS/ SSOE W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable
AWE/SDWE/ SSWE V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
ARDY Y5 I IPU Asynchronous memory ready input

NO.

GDP

V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe

(1)

O/Z IPU • Enabled by bits 28 through 31 of the word address

O/Z IPU

(2)

IPD/IPU

Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z)

• Used for transfer of data, address, and control

• Also controls initialization of DSP modes at reset via pullup/pulldown resistors

– Device Endian mode (HD8)

0: Big Endian
1: Little Endian

– Boot mode (HD[4:3])
00: HPI boot/emulation boot
01: CE1 width 8-bit, asynchronous external ROM boot with default timings (default mode)
10: CE1 width 16-bit, asynchronous external ROM boot with default timings
11: CE1 width 32-bit, asynchronous external ROM boot with default timings

– HPI_EN (HD14)

0: HPI disabled, McASP1 enabled
1: HPI enabled, McASP1 disabled (default)

Other HD pins (HD [15, 13:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For proper device operation, do not oppose these pins
with external pullups/pulldowns at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven at reset. For more details, see
the Device Configurations section of this data sheet.

EMIF—COMMON SIGNALS TO ALL TYPES OF MEMORY

Memory space enables

• Only one asserted during any external data access

Byte-enable control

• Decoded from the two lowest bits of the internal address

• Byte-write enables for most types of memory

• Can be directly connected to SDRAM read and write mask signal (SDQM)

EMIF—BUS ARBITRATION

EMIF—ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]).

EKSRC = 0 ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default).

EKEN = 0 ECLKOUT held low
EKEN = 1 ECLKOUT enabled to clock (default)

DESCRIPTION

(4)

(4)

(4)

(4) To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

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TERMINAL FUNCTIONS (continued)

PIN

SIGNAL NAME TYPE

EA21 U18
EA20 Y18
EA19 W17
EA18 Y16
EA17 V16
EA16 Y15
EA15 W15
EA14 Y14
EA13 W14 The EMIF adjusts the address based on memory width:
EA12 V14 Width Pins Address
EA11 W13 32 21:2 21 through 2
EA10 V10 16 21:2 20 through 1
EA9 Y9 8 21:2 19 through 0
EA8 V9
EA7 Y8 For more details on address width adjustments, see the External Memory Interface (EMIF) chapter of the TMS320C6000 Peripherals
EA6 W8
EA5 V8
EA4 W7
EA3 V7
EA2 Y6

NO.

GDP

(1)

IPD/IPU

O/Z IPU

(2)

EMIF—ADDRESS

External address (word, half-word, and byte address)

Reference Guide (literature number SPRU190)

DESCRIPTION

(4)

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TERMINAL FUNCTIONS (continued)

PIN

SIGNAL NAME TYPE

ED31 N3
ED30 P3
ED29 P2
ED28 P1
ED27 R2
ED26 R3
ED25 T2
ED24 T1
ED23 U3
ED22 U1
ED21 U2
ED20 V1
ED19 V2
ED18 Y3
ED17 W4
ED16 V4
ED15 T19
ED14 T20
ED13 T18
ED12 R20
ED11 R19
ED10 P20
ED9 P18
ED8 N20
ED7 N19
ED6 N18
ED5 M20
ED4 M19
ED3 L19
ED2 L18
ED1 K19
ED0 K18

GP[4](EXT_INT4)/
AMUTEIN1

HD3/AMUTE1 C20 I/O/Z IPU Host-port data pin 3 (I/O/Z) [default] or McASP1 mute output (O/Z)
HRDY/ACLKR1 H19 I/O/Z IPU Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z)
HD6/AHCLKR1 C17 I/O/Z IPU Host-port data pin 6 (I/O/Z) [default] or McASP1 receive high-frequency master clock (I/O/Z)
HAS/ACLKX1 E18 I/O/Z IPU Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z)
HD5/AHCLKX1 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [default] or McASP1 transmit high-frequency master clock (I/O/Z)

HHWIL/AFSR1 H20 I/O/Z IPU
HD2/AFSX1 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z)

HD1/AXR1[7] D20 I/O/Z IPU Host-port data pin 1 (I/O/Z) [default] or McASP1 TX/RX data pin 7 (I/O/Z)
HDS1/AXR1[6] E19 I/O/Z IPU Host data strobe 1 (I) [default] or McASP1 TX/RX data pin 6 (I/O/Z)
HDS2/AXR1[5] F18 I/O/Z IPU Host data strobe 2 (I) [default] or McASP1 TX/RX data pin 5 (I/O/Z)
HD0/AXR1[4] E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [default] or McASP1 TX/RX data pin 4 (I/O/Z)
HCNTL0/AXR1[3] G18 I/O/Z IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 TX/RX data pin 3 (I/O/Z)
HCS/AXR1[2] F20 I/O/Z IPU Host chip select (I) [default] or McASP1 TX/RX data pin 2 (I/O/Z)
HCNTL1/AXR1[1] G19 I/O/Z IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 TX/RX data pin 1 (I/O/Z)
HR/W/AXR1[0] G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 TX/RX data pin 0 (I/O/Z)

NO.

GDP

C2 I/O/Z IPU General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or McASP1 mute input (I/O/Z)

(1)

I/O/Z IPU External data pins (ED[31:16] pins applicable to GDP package only)

(2)

IPD/IPU

EMIF—DATA

MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1)

Host half-word select − first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or
left/right clock (LRCLK) (I/O/Z)

(5)

DESCRIPTION

(5) To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

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TERMINAL FUNCTIONS (continued)

PIN

SIGNAL NAME TYPE

GP[5](EXT_INT5)/
AMUTEIN0

CLKX1/AMUTE0 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z)
CLKR0/ACLKR0 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z)
TINP1/AHCLKX0 F2 I/O/Z IPD Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z)
CLKX0/ACLKX0 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z)
CLKS0/AHCLKR0 K3 I/O/Z IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z)
FSR0/AFSR0 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z)
FSX0/AFSX0 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z)
FSR1/AXR0[7] M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z)
CLKR1/AXR0[6] M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z)
DX1/AXR0[5] L2 I/O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z)
TOUT1/AXR0[4] F1 I/O/Z IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z)
TINP0/AXR0[3] G2 I/O/Z IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z)
TOUT0/AXR0[2] G1 I/O/Z IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z)
DX0/AXR0[1] H2 I/O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z)
DR0/AXR0[0] J1 I/O/Z IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z)

TOUT1/AXR0[4] F1 O IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z)
TINP1/AHCLKX0 F2 I IPD

TOUT0/AXR0[2] G1 O IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z)
TINP0/AXR0[3] G2 I IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z)

CLKS1/SCL1 E1 I —

CLKR1/AXR0[6] M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z)
CLKX1/AMUTE0 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z)

DR1/SDA1 M2 I —

DX1/AXR0[5] L2 O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z)
FSR1/AXR0[7] M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z)
FSX1 L1 I/O/Z IPD McBSP1 transmit frame sync

CLKS0/AHCLKR0 K3 I IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z)
CLKR0/ACLKR0 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z)
CLKX0/ACLKX0 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z)
DR0/AXR0[0] J1 I IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z)
DX0/AXR0[1] H2 O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z)
FSR0/AFSR0 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z)
FSX0/AFSX0 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z)

CLKS1/SCL1 E1 I/O/Z — this pin is used as an I2C pin, the value of the pullup resistor depends on the number of devices connected to the I2C bus. For more

DR1/SDA1 M2 I/O/Z —

SCL0 N1 I/O/Z —

NO.

GDP

C1 I/O/Z IPU General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or McASP0 mute input (I/O/Z)

(1)

(2)

IPD/IPU

MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0)

TIMER1

Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z). This pin defaults as Timer 1 input (I) and McASP
transmit high−frequency master clock input (I).

TIMER0

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). This pin does not have an internal pullup or
pulldown. When this pin is used as a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-kΩ
resistor to a valid logic level. Because it is common for some ICs to 3-state their outputs at times, a 10-kΩ pullup resistor may be
desirable even when an external device is driving the pin.

McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). This pin does not have an internal pullup or pulldown. When this pin is used as
a McBSP pin, this pin should either be driven externally at all times or be pulled up with a 10-kΩ resistor to a valid logic level. Because
it is common for some ICs to 3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even when an external device is
driving the pin.

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

INTER-INTEGRATED CIRCUIT 1 (I2C1)

McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). This pin must be externally pulled up. When

details, see the Philips I2C Specification Revision 2.1 (January 2000).
McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). This pin must be externally pulled up. When this pin is used as an I2C pin, the

value of the pullup resistor depends on the number of devices connected to the I2C bus. For more details, see the Philips I2C
Specification Revision 2.1 (January 2000).

INTER-INTEGRATED CIRCUIT 0 (I2C0)

I2C0 clock. This pin must be externally pulled up. When this pin is used as an I2C pin, the value of the pull-up resistor depends on the
number of devices connected to the I2C bus. For more details, see the Philips I2C Specification Revision 2.1 (January 2000).

DESCRIPTION

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TERMINAL FUNCTIONS (continued)

PIN

SIGNAL NAME TYPE

SDA0 N2 I/O/Z —

HD15/GP[15] B14 I/O/Z IPU Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) and some function as boot configuration pins at reset.
HD14/GP[14] C14 I/O/Z IPU
HD13/GP[13] A15 I/O/Z IPU
HD12/GP[12] C15 I/O/Z IPU
HD11/GP[11] A16 I/O/Z IPU
HD10/GP[10] B16 I/O/Z IPU
HD9/GP[9] C16 I/O/Z IPU

HD8/GP[8] B17 I/O/Z IPU

GP[7](EXT_INT7) E3 I/O/Z IPU
GP[6](EXT_INT6) D2 I/O/Z IPU
GP[5](EXT_INT5)/AM

UTEIN0
GP[4](EXT_INT4)/

AMUTEIN1
HD7/GP[3] A18 I/O/Z IPU Host-port data pin 7 (I/O/Z) [default] or general-purpose input/output pin 3 (I/O/Z)
CLKOUT2/GP[2] Y12 I/O/Z IPD Clock output at half of device speed (O/Z) [default] or this pin can be programmed as GP[2] pin
HINT/GP[1] J20 O IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z)
HD4/GP[0] C19 I/O/Z IPD Host-port data pin 4 (I/O/Z) [default] or this pin can be programmed as a GP[0] pin (I/O/Z)

RSV A5 O/Z IPU Reserved. (Leave unconnected; do not connect to power or ground.)
RSV B5 A
RSV C12 O — Reserved. (Leave unconnected; do not connect to power or ground.)
RSV D7 O/Z IPD Reserved. (Leave unconnected; do not connect to power or ground.)

RSV D12 I —

RSV A12 — —

RSV B11 — —

DV

DD

NO.

GDP

C1 I/O/Z IPU

C2 I/O/Z IPU

A17

B3
B8

B13

C10

D1
D16
D19

F3
H18

J2

M18

R1
R18 S —

T3

U5

U7
U12
U16
V13
V15
V19

W3
W9

W12

Y7
Y17

(1)

(6)

(2)

IPD/IPU

I2C0 data. This pin must be externally pulled up. When this pin is used as an I2C pin, the value of the pull-up resistor depends on the
number of devices connected to the I2C bus. For more details, see the Philips I2C Specification Revision 2.1 (January 2000).

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

• Used for transfer of data, address, and control

• Also controls initialization of DSP modes at reset via pullup/pulldown resistors

abc

As general-purpose input/output (GP[x]) functions, these pins are software configurable through registers. The GPxEN bits in the GP
Enable register and the GPxDIR bits in the GP Direction register must be properly configured:

abc

GPxEN = 1; GP[x] pin is enabled.
GPxDIR = 0; GP[x] pin is an input.
GPxDIR = 1; GP[x] pin is an output.

abc

For the functionality description of the Host-port data pins or the boot configuration pins, see the Host-Port Interface (HPI) portion of
this table.

General-purpose input/output pins (I/O/Z) that also function as external interrupts

• Edge-driven

• Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])

abc

GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and AMUTEIN0 McASP0 mute input, respectively, if enabled by
the INEN bit in the associated McASP AMUTE register.

RESERVED FOR TEST

— Reserved. (Leave unconnected; do not connect to power or ground.)

Reserved. This pin does not have an IPU. For proper C6713 device operation, the D12 pin must be externally pulled down with a
10-kΩ resistor.

Reserved. For new designs, it is recommended that this pin be connected directly to CVDD(core power). For old designs, this can be
left unconnected.

Reserved. For new designs, it is recommended that this pin be connected directly to VSS(ground). For old designs, this pin can be left
unconneced.

SUPPLY VOLTAGE PINS

3.3-V supply voltage
(see the Power-Supply Decoupling section of this data sheet)

DESCRIPTION

(6) A = Analog signal

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PIN

SIGNAL NAME TYPE

CV

DD

NO.

GDP

A4

A9
A10

B2
B19

C3

C7
C18

D5

D6
D11
D14
D15

F4
F17

K1 1.26-V supply voltage

K4 (see the Power-Supply Decoupling section of this data sheet)
K17

L4
L17
L20

R4
R17

U6
U10
U11
U14
U15

V3
V18

W2

W19

(1)

IPD/IPU

S —

(2)

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TERMINAL FUNCTIONS (continued)

DESCRIPTION

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TERMINAL FUNCTIONS (continued)

PIN

SIGNAL NAME TYPE

V

SS

NO.

GDP

A1

A2
A11
A14
A19
A20

B1

B4
B15
B20

C6

C8

C9

D4

D8
D13
D17

E2

E4
E17
F19

G4

G17

H4
H17

J4

J9
J10
J11
J12

K2

K9
K10
K11
K12 GND —
K20

L9
L10
L11
L12

M4

M9
M10
M11
M12
M17

N4

N17

P4
P17
P19

T4
T17

U4

U8

U9
U13
U17
U20

W1

W5
W11
W16
W20

Y1

Y2
Y13
Y19
Y20

(1) Shaded pin numbers denote the center thermal balls.

(1)

(2)

IPD/IPU

Ground pins
grounds and thermal relief (thermal dissipation).

(1)

. The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as both electrical

SGUS049K–AUGUST 2003– REVISED APRIL 2011

DESCRIPTION

GROUND PINS

6.1 Development Support

TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.

The following products support development of C6000™ DSP-based applications:

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Software Development Tools

• Code Composer Studio™ Integrated Development Environment (IDE), including Editor

• C/C++/Assembly Code Generation, and Debug plus additional development tools

• Scalable, Real-Time Foundation Software ( DSP/BIOS™), which provides the basic run-time target

software needed to support any DSP application.

Hardware Development Tools

• Extended Development System ( XDS™) Emulator (supports C6000 DSP multiprocessor system
debug)

• EVM (evaluation module)

For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.

6.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320 DSP commercial family member has one of
three prefixes: SMX, TMP, or SM/SMJ. TI recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools
(SM/SMJ/TMDS).

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6.2.1 Device Development Evolutionary Flow

SMX Preproduction device that is not necessarily representative of the final device

electrical specifications

TMP Final silicon die that conforms to the device electrical specifications but has not

completed quality and reliability verification

SM/SMJ Fully qualified production device

6.2.2 Support Tool Development Evolutionary Flow

TMDX Development-support product that has not yet completed Texas Instruments

internal qualification testing

TMDS Fully qualified development-support product

SMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (SMX) may not be representative of a
final product and TI reserves the right to change or discontinue these products without notice.

SM/SMJ devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (SMX or TMP) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, GDP), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range in megahertz (for example, 20 is 200 MHz).

Figure 6-1 provides a legend for reading the complete device name for any TMS320C6000 DSP family

member.

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PREFIX ENHANCED PLASTIC INDICA TOR

SM 320 C 6713 GDP 20

SMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMJ= MIL-PRF-38535, QML
SM High Rel (non-38535)

DEVICE FAMILY

320 = TMS320 ä DSP family

TECHNOLOGY

PACKAGE TYPE (See Note 1)

C CMOS

DEVICE

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

( )

C6000 DSP:

C6713
C6713B

GDP = 272-pin plastic BGA
GFN= 256-pin plastic BGA
GGP = 352-pin plastic BGA
GJC= 352-pin plastic BGA
GJL= 352-pin plastic BGA
GLS= 384-pin plastic BGA
GLW= 340-pin plastic BGA
GNY = 384-pin plastic BGA
GNZ = 352-pin plastic BGA
GLZ= 532-pin plastic BGA
GHK = 288-pin plastic MicroStar BGA

TM

PYP = 208-pin PowerP

AD

TM

plastic QFP

20 = 200 MHz

EP

DEVICE SPEED RANGE

Blank = 0°C to 90°C (commercial temperature)
A = 40°C to 105°C (extended temperature)
M = –55°C to 125°C (extended temperature)
S = -55°C to 105°C (extended temperature)

-

=

=

NOTE (1): BGA = Ball Grid Array

QFP = Quad Flatpack

For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this
the TI website (www.ti.com).

document or

SM320C6713-EP

SM320C6713B-EP

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Table 6-1. 320C6713 and C6713B Device Part Numbers (P/Ns) and Ordering Information

DEVICE ORDERABLE P/N

C6713B

SM32C6713BGDPA20EP 200 MHz/1200 MFlops 1.26 V 3.3 V –40°C to 105°C

SM32C6713BGDPM30EP 300 MHz/1800 MFlops 1.4V 3.3V –55°C to 125°C

SM32C6713BGDPS20EP 200 MHz/1200 MFlops 1.26 V 3.3 V –55°C to 105°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package

(2)

DEVICE SPEED TEMPERATURE

CORE AND I/O VOLTAGE OPERATING CASE

CVDD(CORE) DVDD(I/O)

SGUS049K–AUGUST 2003– REVISED APRIL 2011

(1)

RANGE

6.3 Ordering Nomenclature

Figure 6-1. TMS320C6000™ DSP Device Nomenclature (Including SM320C6713 and C6713B Devices)

6.4 Documentation Support

Extensive documentation supports all the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include data
sheets, such as this document with design specifications complete user’s reference guides for all devices
and tools, technical briefs, development-support tools, on-line help, and hardware and software
applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP
devices, except where noted, all documents are accessible through the TI web site at www.ti.com.

• TMS320C6000™ CPU and Instruction Set Reference Guide (literature number SPRU189) describes
the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.

Copyright © 2003–2011, Texas Instruments Incorporated TERMINAL FUNCTIONS 57

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•

TMS320C6000™ DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000
PRG Overview] (literature number SPRU190) provides an overview and briefly describes the

functionality of the peripherals available on the C6000 DSP platform of devices. This document also
includes a table listing the peripherals available on the C6000 devices along with literature numbers
and hyperlinks to the associated peripheral documents. These C6713/13B peripherals are similar to
the peripherals on the TMS320C6711 and TMS320C64x devices; therefore, see the TMS320C6711
(C6711 or C67x) peripheral information and, in some cases (where indicated), see the TMS320C6711
(C6711 or C671x) peripheral information and, in some cases (where indicated), see the C64x
information in the C6000™ PRG Overview (literature number SPRU190).

• TMS320DA6000™ DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number

SPRU041) describes the functionality of the McASP peripherals available on the C6713/13B device.

• TMS320C6000™ DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide

(literature number SPRU233) describes the functionality of the PLL peripheral available on the
C6713/13B device.

• TMS320C6000™ DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number

SPRU175) describes the functionality of the I2C peripherals available on the C6713/13B device.

• The PowerPAD ™Thermally-Enhanced Package Technical Brief (literature number SLMA002) focuses
on the specifics of integrating a PowerPAD package into the printed circuit board (PCB) design to
make optimum use of the thermal efficiencies designed into the PowerPAD package.

• TMS320C6000™ Technical Brief (literature number SPRU197) gives an introduction to the C62x™/
C67x™ devices, associated development tools, and third-party support.

• Migrating from TMS320C6211(B)/C6711(B) to TMS320C6713 application report (literature number

SPRA851) indicates the differences and describes the issues of interest related to the migration from

the TI TMS320C6211(B)/C6711(B) GFN package to the TMS320C6713 GDP package.

• TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191)
describes the known exceptions to the functional specifications for particular silicon revisions of the
TMS320C6713 and TMS320C6713B devices.

• TMS320C6713/12C/11C Power Consumption Summary application report (literature number

SPRA889) discusses the power consumption for user applications with the TMS320C6713/13B,

TMS320C6712C/12D, and TMS320C6711C/11D DSP devices.

• Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how
to properly use IBIS models to attain accurate timing analysis for a given system.

www.ti.com

The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the
Texas Instruments web site at www.ti.com. Also, see the TI web site for the application report, How To
Begin Development Today With the TMS320C6713 Floating-Point DSP (literature number SPRA809),
which describes in more detail the similarities/differences between the C6713 and C6711 C6000 DSP
devices.

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31 24 23 16

CPUID

REVISIONID

R-0x02 R-0x03[13/13B]

15 10 98 76 54 21 0

PWRD

SAT EN PCC DCC PGIE GIE

R/W-0R /C-0 R-1R /W-0 R/W-0R /W-0 R/W-0

Legend: R=ReadablebytheMVCinstruction,R/W=Readable/WriteablebytheMVCinstruction;W=Read/write;-n=valueafterreset,-x=undefinedvalueafter

reset,C=ClearablebytheMVCinstruction

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7 REGISTER INFORMATION

This section provides the register information for the device.

7.1 CPU Control Status Register (CSR) Description

The CPU CSR contains the CPU ID and CPU Revision ID (bits 16−31), as well as the status of the device
power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the endian bit
(EN, bit 8), and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 7-1 and

Table 7-1 identify the bit fields in the CPU CSR.

For more detailed information on the bit fields in the CPU CSR, see the TMS320C6000 DSP Peripherals

Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set
Reference Guide (literature number SPRU189).

SGUS049K–AUGUST 2003– REVISED APRIL 2011

Figure 7-1. CPU Control Status Register (CPU CSR)

Copyright © 2003–2011, Texas Instruments Incorporated REGISTER INFORMATION 59

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Table 7-1. CPU CSR Bit Field Description

Bit NO. NAME DESCRIPTION

31:24 CPU ID
23:16 REVISION ID
15:10 PWRD Control power-down modes. The values are always read as zero.

9 SAT Saturate bit.

8 EN Endian bit. This bit is read-only. Depicts the device endian mode.

7:5 PCC Program cache control mode.

4:2 DCC Data cache control mode.

1 PGIE Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is taken.

0 GIE Global interrupt enable bit.

CPU ID + REV ID. Read only. Identifies which CPU is used and defines the silicon revision of the CPU.
CPU ID + REVISION ID (31:16) are combined for a value of: 0x0203 for C6713/13B

000000 = No power down (default)
001001 = PD1, wake up by an enabled interrupt
010001 = PD1, wake up by an enabled or not enabled interrupt
011010 = PD2, wake up by a device reset
011100 = PD3, wake up by a device reset

Others = Reserved

Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can be set only
by a functional unit. The set by the a functional unit has priority over a clear (by the MVC instruction) if they
occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after a saturate occurs. This bit
will not be modified by a conditional instruction whose condition is false.

0 = Big Endian mode
1 = Little Endian mode [default]

L1D, Level 1 program cache

000/010 = Cache enabled/cache accessed and updated on reads

All other PCC values are reserved.

L1D, Level 1 data cache

000/010 = Cache enabled/2-way cache

All other DCC values are reserved.

Allows for proper nesting of interrupts.

0 = Previous GIE value is 0 (default).
1 = Previous GIE value is 1.

Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).

0 = Disables all interrupts (except the reset interrupt and NMI) [default].
1 = Enables all interrupts (except the reset interrupt and NMI).

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7.2 Cache Configuration (CCFG) Register Description (13B)

The C6713B device includes an enhancement to the CCFG register. A P bit (CCFG.31) allows the
programmer to select the priority of accesses to L2 memory originating from the transfer crossbar (TC)
over accesses originating from the L1D memory system. An important class of TC accesses is EDMA
transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing
L2 memory because of the high hit rates on the L1D memory system, there are pathological cases where
certain CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a
missed deadline when transferring data to a peripheral such as the McASP or McBSP. This can be
avoided by setting the P bit to 1 because the EDMA will assume a higher priority than the L1D memory
system when accessing L2 memory.

For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2
memory accesses blocked, see the TMS320C6713, TMS320C6713B Digital Signal Processors Silicon
Errata (literature number SPRZ191).

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31 30 10 98

7

32 0

P Reserved IP ID Reserved L2MODE

R/W-0 R-x W-0 W-0 R-00000 R/W-000

(1)

A:UnliketheC6713device,theC6713BdeviceincludesaPbit.

Legend: R=Readable;R/W=Readable/Writeable;-n=valueafterreset,-x=undefinedvalueafterreset

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A. Unlike the C6713 device, the C6713B device includes a P bit.

Figure 7-2. Cache Configuration (CCFG) Register

Table 7-2. CCFG Register Bit Field Description

BIT NO. NAME DESCRIPTION

L1D requestor priority to L2 bit

31 P P = 0: L1D requests to L2 higher priority than TC requests

P = 1: TC requests to L2 higher priority than L1D requests

30:10 Reserved Reserved. Read only, writes have no effect.

Invalidate L1P bit

9 IP 0 = Normal L1P operation

1 = All L1P lines are invalidated
Invalidate L1D bit

8 ID 0 = Normal L1D operation

1 = All L1D lines are invalidated

7:3 Reserved Reserved. Read only, writes have no effect.

L2 operation mode bits (L2MODE)

000b = L2 cache disabled (All SRAM mode) [256K SRAM]
001b = 1-way cache (16K L2 cache) / [240K SRAM]

2:0 L2MODE 010b = 2-way cache (32K L2 cache) / [224K SRAM]

011b = 3-way cache (48K L2 cache) / [208K SRAM]
111b = 4-way cache (64K L2 cache) / [192K SRAM]

All others are reserved.

SGUS049K–AUGUST 2003– REVISED APRIL 2011

7.3 Interrupts and Interrupt Selector

The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 7-3. The highest priority
interrupt is INT_00 (dedicated to RESET), while the lowest priority is INT_15. The first four interrupts are
non-maskable and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source
listed in Table 7-3. However, their interrupt source may be reprogrammed to any one of the sources listed
in Table 7-4 (Interrupt Selector). Table 7-4 lists the selector value corresponding to each of the alternate
interrupt sources. The selector choice for interrupts 4−15 is made by programming the corresponding
fields (listed in Table 7-3) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004)
registers.

Table 7-3. DSP Interrupts

INTERRUPT NUMBER

Copyright © 2003–2011, Texas Instruments Incorporated REGISTER INFORMATION 61

DSP

INT_00 — — RESET
INT_01 — — NMI
INT_02 — — Reserved
INT_03 — — Reserved

INTERRUPT DEFAULT DEFAULT

SELECTOR CONTROL SELECTOR VALUE INTERRUPT

REGISTER (BINARY) EVENT

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DSP

INTERRUPT NUMBER

INT_04 MUXL[4:0] 00100 GPINT4
INT_05 MUXL[9:5] 00101 GPINT5
INT_06 MUXL[14:10] 00110 GPINT6
INT_07 MUXL[20:16] 00111 GPINT7
INT_08 MUXL[25:21] 01000 EDMAINT
INT_09 MUXL[30:26] 01001 EMUDTDMA
INT_10 MUXH[4:0] 00011 SDINT
INT_11 MUXH[9:5] 01010 EMURTDXRX
INT_12 MUXH[14:10] 01011 EMURTDXTX
INT_13 MUXH[20:16] 00000 DSPINT
INT_14 MUXH[25:21] 00001 TINT0
INT_15 MUXH[30:26] 00010 TINT1

(1) Interrupt events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP).

They originate from the device pins GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as edge-sensitive EXT_INTx with
polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins
must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable
Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction Register (GPDIR.[7:4]).
These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0]
bits. For more information on interrupt control via the GPIO module, see the TMS320C6000™ DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).

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Table 7-3. DSP Interrupts (continued)

INTERRUPT DEFAULT DEFAULT

SELECTOR CONTROL SELECTOR VALUE INTERRUPT

REGISTER (BINARY) EVENT

(1)
(1)
(1)
(1)

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Table 7-4. Interrupt Selector

INTERRUPT SELECTOR VALUE

(BINARY)

00000 DSPINT HPI
00001 TINT0 Timer 0
00010 TINT1 Timer 1
00011 SDINT EMIF
00100 GPINT4
00101 GPINT5
00110 GPINT6
00111 GPINT7
01000 EDMAINT EDMA
01001 EMUDTDMA Emulation
01010 EMURTDXRX Emulation
01011 EMURTDXTX Emulation
01100 XINT0 McBSP0
01101 RINT0 McBSP0
01110 XINT1 McBSP1
01111 RINT1 McBSP1
10000 GPINT0 GPIO
10001 Reserved —
10010 Reserved —
10011 Reserved —
10100 Reserved —
10101 Reserved —
10110 I2CINT0 I2C0
10111 I2CINT1 I2C1
11000 Reserved —
11001 Reserved —
11010 Reserved —
11011 Reserved —
11100 AXINT0 McASP0
11101 ARINT0 McASP0
11110 AXINT1 McASP1
11111 ARINT1 McASP1

(1) Interrupt events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP).

They originate from the device pins GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as edge-sensitive EXT_INTx with
polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins
must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable
Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction Register (GPDIR.[7:4]).
These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0]
bits. For more information on interrupt control via the GPIO module, see the TMS320C6000™ DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).

INTERRUPT EVENT MODULE

(1)
(1)
(1)
(1)

GPIO
GPIO
GPIO
GPIO

7.4 External Interrupt Sources

The C6713/13B device supports many external interrupt sources as indicated in Table 7-5. Control of the
interrupt source is done by the associated module and is made available by enabling the corresponding
binary interrupt selector value (see Table 7-4 shaded rows). Because of pin multiplexing and module
usage, not all external interrupt sources are available at the same time.

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Table 7-5. External Interrupt Sources and Peripheral Module Control

PIN NAME INTERRUPT EVENT MODULE

GP[15] GPINT0 GPIO
GP[14] GPINT0 GPIO

GP[13 GPINT0 GPIO
GP[12] GPINT0 GPIO
GP[11] GPINT0 GPIO
GP[10] GPINT0 GPIO

GP[9] GPINT0 GPIO
GP[8] GPINT0 GPIO
GP[7] GPINT0 or GPINT7 GPIO
GP[6] GPINT0 or GPINT6 GPIO
GP[5] GPINT0 or GPINT5 GPIO
GP[4] GPINT0 or GPINT4 GPIO
GP[3] GPINT0 GPIO
GP[2] GPINT0 GPIO
GP[1] GPINT0 GPIO
GP[0] GPINT0 GPIO

7.5 EDMA Module and EDMA Selector

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The C67x EDMA supports up to 16 EDMA channels. Four of the 16 channels (channels 8−11) are
reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices.

The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at
addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA
selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has
an assigned EDMA selector code (see Table 7-7). By loading each EVTSELx register field with an EDMA
selector code, users can map any desired EDMA event to any specified EDMA channel. Table 7-6 lists the
default EDMA selector value for each EDMA channel.

See Table 7-8 and Table 7-11 for the EDMA Event Selector registers and their associated bit descriptions.

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Table 7-6. EDMA Channels

EDMA CHANNEL DEFAULT EDMA EVENT

0 ESEL0[5:0] 000000 DSPINT
1 ESEL0[13:8] 000001 TINT0
2 ESEL0[21:16] 000010 TINT1
3 ESEL0[29:24] 000011 SDINT
4 ESEL1[5:0] 000100 GPINT4
5 ESEL1[13:8] 000101 GPINT5
6 ESEL1[21:16] 000110 GPINT6
7 ESEL1[29:24] 000111 GPINT7
8 — — TCC8 (Chaining)

9 — — TCC9 (Chaining)
10 — — TCC10 (Chaining)
11 — — TCC11 (Chaining)
12 ESEL3[5:0] 001100 XEVT0
13 ESEL3[13:8] 001101 REVT0
14 ESEL3[21:16] 001110 XEVT1
15 ESEL3[29:24] 001111 REVT1

EDMA SELECTOR DEFAULT SELECTOR

CONTROL REGISTER VALUE (BINARY)

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EDMA SELECTOR CODE

(BINARY)

000000 DSPINT HPI
000001 TINT0 TIMER0
000010 TINT1 TIMER1
000011 SDINT EMIF
000100 GPINT4 GPIO
000101 GPINT5 GPIO
000110 GPINT6 GPIO
000111 GPINT7 GPIO
001000 GPINT0 GPIO
001001 GPINT1 GPIO
001010 GPINT2 GPIO
001011 GPINT3 GPIO
001100 XEVT0 McBSP0
001101 REVT0 McBSP0
001110 XEVT1 McBSP1
001111 REVT1 McBSP1

010000−011111 Reserved

100000 AXEVTE0 McASP0
100001 AXEVTO0 McASP0
100010 AXEVT0 McASP0
100011 AREVTE0 McASP0
100100 AREVTO0 McASP0
100101 AREVT0 McASP0
100110 AXEVTE1 McASP1
100111 AXEVTO1 McASP1
101000 AXEVT1 McASP1
101001 AREVTE1 McASP1
101010 AREVTO1 McASP1
101011 AREVT1 McASP1
101100 I2CREVT0 I2C0
101101 I2CXEVT0 I2C0
101110 I2CREVT1 I2C1
101111 I2CXEVT1 I2C1
110000 GPINT8 GPIO
110001 GPINT9 GPIO
110010 GPINT10 GPIO
110011 GPINT11 GPIO
110100 GPINT12 GPIO
110101 GPINT13 GPIO
110110 GPINT14 GPIO
110111 GPINT15 GPIO

111000−111111 Reserved

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Table 7-7. EDMA Selector

EDMA EVENT MODULE

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Table 7-8. EDMA Event Selector Registers (ESEL0 Register (0x01A0 FF00)

31 30 29 28 27 24 23 22 21 20 19 16

Reserved EVTSEL3 Reserved EVTSEL2

R–0 R/W−00 0011b R−0 R/W−00 0010b

15 14 13 12 11 8 7 6 5 4 3 0

Reserved EVTSEL1 Reserved EVTSEL0

R–0 R/W−00 0001b R−0 R/W−00 0000b

Legend: R = Read only, R/W = Read/write, -n = value at reset

Table 7-9. EDMA Event Selector Registers—ESEL1 Register (0x01A0 FF04)

31 30 29 28 27 24 23 22 21 20 19 16

Reserved EVTSEL7 Reserved EVTSEL6

R–0 R/W−00 0111b R−0 R/W−00 0110b

15 14 13 12 11 8 7 6 5 4 3 0

Reserved EVTSEL5 Reserved EVTSEL4

R–0 R/W−00 0101b R−0 R/W−00 0100b

Legend: R = Read only, R/W = Read/write, -n = value at reset

Table 7-10. EDMA Event Selector Registers—ESEL3 Register (0x01A0 FF0C)

31 30 29 28 27 24 23 22 21 20 19 16

Reserved EVTSEL15 Reserved EVTSEL14

R–0 R/W−00 1111b R−0 R/W−00 1110b

15 14 13 12 11 8 7 6 5 4 3 0

Reserved EVTSEL13 Reserved EVTSEL12

R–0 R/W−00 1101b R−0 R/W−00 1100b

Legend: R = Read only, R/W = Read/write, -n = value at reset

Table 7-11. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description

BIT NO. NAME DESCRIPTION

31:30
23:22
15:14

7:6

29:24 The EVTSEL0 through EVTSEL15 bits correspond to channels 0 to 15, respectively. These EVTSELx
21:16 fields are user selectable. By configuring the EVTSELx fields to the EDMA selector value of the desired

13:8 EDMA sync event number (see Table 7-7), users can map any EDMA event to the EDMA channel.

5:0 abc

Reserved Reserved. Read only, writes have no effect.

EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels.

abc

EVTSELx

For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), channel 15
is triggered by Timer 0 TINT0 events.

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CLKIN

CLKOUT3

ForUse

inSystem

/1,/2,
...,/32

...,/32

/1,/2,

PLL

x4tox25

PLLEN(PLL_CSR.[0])

...,/32

/1,/2,

/1,/2,

...,/32

/1,/2,

...,/32

(DSPCore)

SYSCLK1

(Peripherals)

SYSCLK2

ECLKIN

EKSRCBit
(DEVCFG.[4])

EMIF

SYSCLK3

CLKMODE0

(EMIFClockInput)

C6713/13BDSPs

PLLOUT

PLLREF

DIVIDER D0

OSCDIV1

DIVIDERD1

DIVIDERD2

DIVIDERD3

ECLKOUT

AUXCLK
(InternalClockSource
toMcASP0andMcASP1)

1

0

10

1

0

PLLHV

C2C1

EMIfilter

+3.3 V

10 mF0 .1 mF

D0EN(PLLDIV0.[15])

ENA

ENA

OD1EN(OSCDIV1.[15])

ENAENA

ENA

D1EN(PLLDIV1.[15])

ENAD2EN(PLLDIV2.[15])

ENA

D3EN(PLLDIV3.[15])

Reserved

(A)

(A)

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8 PLL and PLL Controller

The 320C6713/13B includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0)
and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for
different parts of the system (that is, DSP core, peripheral data bus, external memory interface, McASP,
and other peripherals). Figure 8-1 shows the PLL, the PLL controller, and the clock generator logic.

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A. Dividers D1 and D2 must never be disabled. Never write a '0' to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2

registers.

B. Place all PLL external components (C1, C2, and the EMI filter) as close to the C67x DSP device as possible. For the

best performance, TI recommends that all the PLL external components be on a single side of the board without
jumpers, switches, or components other than the ones shown.

C. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2,

and the EMI filter).
D. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
E. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.

Figure 8-1. PLL and Clock Generator Logic

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8.1 PLL Registers

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), for
the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL reset
time value, see Table 8-1. The PLL lock time is the amount of time from when PLLRST = 0 with PLLEN =
0 (PLL out of reset, but still bypassed) to when the PLLEN bit can be safely changed to 1 (switching from
bypass to the PLL path); see Table 8-1 and Figure 8-1.

Under some operating conditions, the maximum PLL lock time may vary from the specified typical value.
For the PLL lock time values, see Table 8-1.

Table 8-1. PLL Lock and Reset Times

MIN TYP MAX UNIT

PLL lock time 75 187.5 μs
PLL reset time 125 ns

Table 8-2 shows the C6713/13B device CLKOUT signals, how and by what register control bits they are

derived, and what is the default settings. For more details on the PLL, see the PLL and Clock Generator
Logic diagram (Figure 8-1).

Table 8-2. CLKOUT Signals, Default Settings, and Control

CLOCK OUTPUT DEFAULT SETTING CONTROL BIT(s)

SIGNAL NAME (ENABLED or DISABLED) (Register)

CLKOUT2 ON (ENABLED) SYSCLK2 selected [default]
CLKOUT3 ON (ENABLED) OD1EN = 1 (OSCDIV1.[15]) Derived from CLKIN

ECLKOUT

ON (ENABLED); EKSRC = 0 (DEVCFG.[4]) To select ECLKIN source:

derived from SYSCLK3 EKEN = 1 (EMIF GBLCTL.[5]) EKSRC = 1 (DEVCFG.[4]) and

D2EN = 1 (PLLDIV2.[15])

CK2EN = 1 (EMIF GBLCTL.[3])

SGUS049K–AUGUST 2003– REVISED APRIL 2011

DESCRIPTION

SYSCLK3 selected [default].

EKEN = 1 (EMIF GBLCTL.[5])

The input clock (CLKIN) is directly available to the McASP modules as AUXCLK for use as an internal
high-frequency clock source. The input clock (CLKIN) may also be divided down by a programmable
divider OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system.

Figure 8-1 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and

then multiplied up by a factor of x4, x5, x6, and so on, up to x25.
Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency

reference clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the
EMIF clock may be divided down from this high-frequency clock (each with a unique divider). For
example, with a 30-MHz input if the PLL output is configured for 450 MHz, the DSP core may be operated
at 225 MHz (/2), while the EMIF may be configured to operate at a rate of 75 MHz (/6). Note that there is
a specific minimum and maximum reference clock (PLLREF) and output clock (PLLOUT) for the block
labeled PLL in Figure 8-1, as well as for the DSP core, peripheral bus, and EMIF. The clock generator
must not be configured to exceed any of these constraints (certain combinations of external clock input,
internal dividers, and PLL multiply ratios might not be supported). See Table 8-3 for the PLL clocks input
and output frequency ranges.

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Table 8-3. PLL Clock Frequency Ranges

CLOCK SIGNAL MIN MAX UNIT

PLLREF (PLLEN = 1) 12 100 MHz
PLLOUT 140 600 MHz
SYSCLK1 — Device speed (DSP core) MHz
SYSCLK3 (EKSRC = 0) — 100 MHz
AUXCLK — 50

(1) SYSCLK2 rate must be exactly half of SYSCLK1.
(2) See also the Electrical Specification (timing requirements and switching characteristics parameters) in

the Input and Output Clocks section of this data sheet.

(3) When the McASP module is not used, the AUXCLK maximum frequency can be any frequency up to

the CLKIN maximum frequency.

The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated
on-chip as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 8-1). The EMIF
clock selection is programmable via the EKSRC bit in the DEVCFG register.

The settings for the PLL multiplier and each of the dividers in the clock generation block may be
reconfigured via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or
CLKIN, or if the PLL multiplier is changed, then software must enter bypass first and stay in bypass until
the PLL has had enough time to lock (see electrical specifications). For the programming procedure, see
the TMS320C6000™ DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide
(literature number SPRU233).

(1) (2)

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(3)

MHz

SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be
programmed to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2),
then D2 must be programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin
(see Figure 8-1).

During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2
output clocks, see Figure 8-1), the order of programming the PLLDIV1 and PLLDIV2 registers must be
observed to ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the
divider ratios of D1 and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the
PLLDIV2 register must be programmed before the PLLDIV1 register. The transition ratios become /1, /2;
/1, /10; and then /5, /10. If the divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2, then the
PLLDIV1 register must be programmed before the PLLDIV2 register. The transition ratios, for this case,
become /3, /6; /1, /6; and then /1, /2. The final SYSCLK2 rate must be exactly half of the SYSCLK1 rate.

Note that Divider D1 and Divider D2 must always be enabled (that is, D1EN and D2EN bits are set to 1 in
the PLLDIV1 and PLLDIV2 registers).

The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should not be
used to directly access the PLL Controller registers.

For detailed information on the clock generator (PLL Controller registers) and the associated software bit
descriptions, see Table 8-4 through Table 8-11.

Table 8-4. PLL Control/Status Register (PLLCSR) (0x01B7 C100)

31 28 27 24 23 20 19 16

Reserved

R-0

15 12 11 8 7 6 5 4 3 2 1 0

Reserved Stable Reserved PLLRS Reserv PLLPWRD PLLEN

R-0 R–x R-0 RW−1 R/W−0 R/W−0b RW−0

Legend: R = Read only, R/W = Read/write, -n = value at reset

T ed N

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Table 8-5. PLL Control/Status Register (PLLCSR) Description

BIT NO. NAME DESCRIPTION

31:7 Reserved Reserved. Read only, writes have no effect.

Clock input stable. This bit indicates if the clock input has stabilized.

6 STABLE 0: Clock input not yet stable. Clock counter is not finished counting (default).

1: Clock input stable

5:4 Reserved Reserved. Read only, writes have no effect.

Asserts RESET to PLL

3 PLLRST 0: PLL reset released

1: PLL reset asserted (default)

2 Reserved Reserved. The user must write a 0 to this bit.

Select PLL power down

1 PLLPWRDN 0: PLL operational (default)

1: PLL placed in power-down state

PLL mode enable

0 PLLEN SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock.

0: Bypass mode (default). PLL disabled Divider D0 and PLL are bypassed.

1: PLL enabled Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are

divided down from PLL output.

Table 8-6. PLL Multiplier (PLLM) Control Register (0x01B7 C110)

31 28 27 24 23 20 19 16

Reserved

R-0

15 12 11 8 7 5 4 0

Reserved PLLM

R-0 R/W−0 0111

Legend: R = Read only, R/W = Read/write, -n = value at reset

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Table 8-7. PLL Multiplier (PLLM) Control Register Description

BIT NO. NAME DESCRIPTION

31:5 Reserved Reserved. Read only, writes have no effect.

PLL multiply mode [default is x7 (0 0111)]

00000 = Reserved 10000 = x16
00001 = Reserved 10001 = x17
00010 = Reserved 10010 = x18
00011 = Reserved 10011 = x19
00100 = x4 10100 = x20
00101 = x5 10101 = x21
00110 = x6 10110 = x22

4:0 PLLM

PLLM select values 00000 through 00011 and 11010 through 11111 are not supported.

00111 = x7 10111 = x23
01000 = x8 11000 = x24
01001 = x9 11001 = x25
01010 = x10 11010 = Reserved
01011 = x11 11011 = Reserved
01100 = x12 11100 = Reserved
01101 = x13 11101 = Reserved
01110 = x14 11110 = Reserved
01111 = x15 11111 = Reserved

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Table 8-8. PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3)

(0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively)

31 28 27 24 23 20 19 16

Reserved

R-0

15 14 12 11 8 7 5 4 0

DxEN Reserved PLLDIVx
R/W−1 R−0 R/W−x xxxx
Legend: R = Read only, R/W = Read/write, -n = value at reset

(1) Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001),

respectively.

(1)

CAUTION

D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.

Table 8-9. PLL Wrapper Divider x Registers

(Prescaler Divider D0 and Post-Scaler Dividers D1, D2, and D3) Description

BIT NO. NAME DESCRIPTION

31:16 Reserved Reserved. Read only, writes have no effect.

Divider Dx enable (where x denotes 0 through 3).

15 DxEN

These divider-enable bits are device specific and must be set to 1 to enable.

0: Divider x disabled. No clock output
1: Divider x enabled (default)

(1)

(1) Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For

example, if D1 is set to /2, then D2 must be set to /4.

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Table 8-9. PLL Wrapper Divider x Registers

(Prescaler Divider D0 and Post-Scaler Dividers D1, D2, and D3) Description

BIT NO. NAME DESCRIPTION

14:5 Reserved Reserved. Read only, writes have no effect.

PLL divider ratio (default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1, /2,
and /2, respectively).

00000 = /1 10000 = /17
00001 = /2 10001 = /18
00010 = /3 10010 = /19
00011 = /4 10011 = /20
00100 = /5 10100 = /21
00101 = /6 10101 = /22

4:0 PLLDIVx

00110 = /7 10110 = /23
00111 = /8 10111 = /24
01000 = /9 11000 = /25
01001 = /10 11001 = /26
01010 = /11 11010 = /27
01011 = /12 11011 = /28
01100 = /13 11100 = /29
01101 = /14 11101 = /30
01110 = /15 11110 = /31
01111 = /16 11111 = /32

SGUS049K–AUGUST 2003– REVISED APRIL 2011

(1)

(continued)

Table 8-10. Oscillator Divider 1 (OSCDIV1) Register (0x01B7 C124)

31 28 27 24 23 20 19 16

Reserved

R-0

15 14 12 11 8 7 5 4 0

OD1EN Reserved OSCDIV1

R/W−1 R−0 R/W−0 0111

Legend: R = Read only, R/W = Read/write, -n = value at reset

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Table 8-11. Oscillator Divider 1 (OSCDIV1) Register Description

BIT NO. NAME DESCRIPTION

31:16 Reserved Reserved. Read-only; writes have no effect.

Oscillator Divider 1 enable.

15 OD1EN 0: Oscillator Divider 1 disabled

1: Oscillator Divider 1 enabled (default)

14:5 Reserved Reserved. Read only, writes have no effect.

Oscillator Divider 1 ratio [default is /8 (0 0111)]

00000 = /1 10000 = /17
00001 = /2 10001 = /18
00010 = /3 10010 = /19
00011 = /4 10011 = /20
00100 = /5 10100 = /21
00101 = /6 10101 = /22
00110 = /7 10110 = /23

4:0 OSCDIV1 00111 = /8 10111 = /24

01000 = /9 11000 = /25
01001 = /10 11001 = /26
01010 = /11 11010 = /27
01011 = /12 11011 = /28
01100 = /13 11100 = /29
01101 = /14 11101 = /30
01110 = /15 11110 = /31
01111 = /16 11111 = /32

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9 MULTICHANNEL AUDIO SERIAL PORT (McASP) PERIPHERALS

The 320C6713/13B device includes two multichannel audio serial port (McASP) interface peripherals
(McASP1 and McASP0). The McASP is a serial port optimized for the needs of multichannel audio
applications. With two McASP peripherals, the 320C6713/13B device is capable of supporting two
completely independent audio zones simultaneously.

Each McASP consists of a transmit and receive section. These sections can operate completely
independently with different data formats, separate master clocks, bit clocks, and frame syncs or
alternatively, the transmit and receive sections may be synchronized. Each McASP module also includes
a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or
general-purpose I/O (GPIO).

The transmit section of the McASP can transmit data in either a time division multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
S/PDIF, AES-3, IEC-60958, and CP-430 transmission. The receive section of the McASP supports the
TDM synchronous serial format.

Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive
format at a time. All transmit shift registers use the same format and all receive shift registers use the
same format. However, the transmit and receive formats need not be the same.

Both the transmit and receive sections of the McASP also support burst mode, which is useful for
non-audio data (for example, passing control information between two DSPs).

The McASP peripherals have additional capability for flexible clock generation, and error
detection/handling, as well as error management.

9.1 McASP Block Diagram

Figure 9-1 shows the major blocks along with external signals of the 320C6713/13B McASP1 and

McASP0 peripherals, and shows the eight serial data [AXR] pins for each McASP. Each McASP also
includes full general-purpose I/O (GPIO) control, so any pins not needed for serial transfers can be used
for general-purpose I/O.

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Receive

Clock

Generator

AHCLKR0
ACLKR0

ClockCheck

Transmit

Generator

Clock

Transmit

ACLKX0

AHCLKX0

DIT

RAM

Transmit

Generator

FrameSync

AFSX0

Detect

Error

Receive

FrameSync

GeneratorFormatter

Transmit

Data

AMUTE0
AMUTEIN0

AFSR0

Serializer0

Serializer1

Serializer3

Serializer2

Serializer6

Serializer7

Serializer5

Serializer4

(High-

Frequency)

Receive

ClockCheck

(High-

Frequency)

Receive

Formatter

Data

Formatter

Data

Receive

Serializer4

Serializer3

Serializer7

Serializer6

Serializer5

Serializer0

Serializer1

FrameSync

Generator

Receive

FrameSync

Generator

Transmit

Transmit

Generator

Receive

Generator

Serializer2

Error

Transmit

Formatter

Data

ClockCheck

Frequency)

(High-

Receive

Detect

Frequency)

ClockCheck

(High-

Transmit

RAM

DIT

AMUTE1

AFSR1

ACLKR1

AMUTEIN1

AHCLKR1

Clock

AFSX1

ACLKX1

AHCLKX1

Clock

AXR1[0]

AXR1[1]

AXR1[3]

AXR1[2]

AXR1[6]

AXR1[7]

AXR1[5]

AXR1[4]

McASP0 McASP1

DMA

Transmit

DMA

Transmit

DMA Receive

DMA

Receive

INDIVIDUAL

LY PROGRAMMABLETX/RX/GPI

O

INDIVIDUAL

LY PROGRAMMABLETX/RX/GPI

O

Control

GPIO

Control

GPIO

AXR0[0]

AXR0[1]

AXR0[3]

AXR0[2]

AXR0[6]

AXR0[7]

AXR0[5]

AXR0[4]

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Figure 9-1. McASP0 and McASP1 Configuration

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9.2 Multichannel Time Division Multiplexed (TDM) Synchronous Transfer Mode

The McASP supports a multichannel TDM synchronous transfer mode for both transmit and receive.
Within this transfer mode, a wide variety of serial data formats are supported, including formats compatible
with devices using the Inter-Integrated Sound (IIS) protocol.

TDM synchronous transfer mode is typically used when communicating between integrated circuits, such
as between a DSP and one or more ADC, DAC, codec, or S/PDIF receiver devices. In multichannel
applications, it is typical to find several devices operating synchronized with each other. For example, to
provide six analog outputs, three stereo DAC devices would be driven with the same bit clock and frame
sync, but each stereo DAC would use a different McASP serial data pin carrying stereo data (two TDM
time slots, left and right).

The TDM synchronous serial transfer mode utilizes several control signals and one or more serial data
signals:

• A bit clock signal (ACLKX for transmit, ACKLR for receive)

• A frame sync signal (AFSX for transmit, AFSR for receive)

• An (optional) high-frequency master clock (AHCLKX for transmit, AHCLKR for receive) from which the

bit clock is derived

• One or more serial data pins (AXR for transmit and for receive)
Except for the optional high-frequency master clock, all of the signals in the TDM synchronous serial

transfer mode protocol are synchronous to the bit clocks (ACLKX and ACLKR).
In the TDM synchronous transfer mode, the McASP continually transmits and receives data periodically

(since audio ADCs and DACs operate at a fixed-data rate). The data is organized into frames, and the
beginning of a frame is marked by a frame sync pulse on the AFSX, AFSR pin.

In a typical audio system, one frame is transferred per sample period. To support multiple channels, the
choices are to either include more time slots per frame (and therefore operate with a higher bit clock) or to
keep the bit clock period constant and use additional data pins to transfer the same number of channels.
For example, a particular six-channel DAC might require three McASP serial data pins; transferring two
channels of data on each serial data pin during each sample period (frame). Another similar DAC may be
designed to use only a single McASP serial data pin, but clocked three times faster and transferring six
channels of data per sample period. The McASP is flexible enough to support either type of DAC, but a
transmitter cannot be configured to do both at the same time.

For multiprocessor applications, the McASP supports any number of time slots per frame (between 2 and

32), and includes the ability to disable transfers during specific time slots.
In addition, to support S/PDIF, AES-3, IEC-60958, and CP-430 receiver chips whose natural block

(McASP frame) size is 384 samples; the McASP receiver supports a 384 time slot mode. The advantage
to using the 384 time slot mode is that interrupts may be generated synchronous to the S/PDIF, AES-3,
IEC-60958, and CP-430 receivers; for example, the last slot interrupt.

9.3 Burst Transfer Mode

The McASP also supports a burst transfer mode, which is useful for non-audio data (for example, passing
control information between two DSPs). Burst transfer mode uses a synchronous serial format similar to
TDM, except the frame sync is generated for each data word transferred. In addition, frame sync
generation is not periodic or time driven as in TDM mode, but rather data driven.

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9.4 Supported Bit Stream Formats for TDM and Burst Transfer Modes

The serial data pins support a wide variety of formats. In the TDM and burst synchronous modes, the data
may be transmitted/received with the following options:

• Time slots per frame: 1 (burst/data driven), or 2,3...32 (TDM/time driven)

• Time slot size: 8, 12, 16, 20, 24, 28, 32 bits per time slot

• Data size: 8, 12, 16, 20, 24, 28, 32 bits (must be less than or equal to time slot)

• Data alignment within time slot: left or right justified

• Bit order: MSB or LSB first

• Unused bits in time slot: Padded with 0, 1 or extended with value of another bit

• Time slot delay from frame sync: 0-, 1-, or 2-bit delay

The data format can be programmed independently for transmit and receive, and for McASP0 versus
McASP1. In addition, the McASP can automatically realign the data as processed natively by the DSP
(any format on a nibble boundary) adjusting the data in hardware to any of the supported serial bit stream
formats (TDM, burst, and DIT modes). This adjustment reduces the amount of bit manipulation that the
DSP must perform and simplifies software architecture.

9.5 Digital Audio Interface Transmitter (DIT) Transfer Mode (Transmitter Only)

The McASP transmit section may also be configured in DIT mode where it outputs data formatted for
transmission over an S/PDIF, AES-3, IEC-60958, or CP-430 standard link. These standards encode the
serial data such that the equivalent of clock and frame sync are embedded within the data stream. DIT
transfer mode is used as an interconnect between audio components and can transfer multichannel digital
audio data over a single optical or coaxial cable.

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From an internal DSP standpoint, the McASP operation in DIT transfer mode is similar to the two-time-slot
TDM mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble,
channel status, user data, validity, and parity automatically stuffed into the bit stream by the McASP
module. The McASP includes separate validity bits for even/odd subframes and two 384-bit register file
modules to hold channel status and user data bits.

DIT mode requires (at a minimum):

• One serial data pin (if the AUXCLK is used as the reference (see Figure 8-1)
OR

• One serial data pin plus either the AHCLKX or ACLKX pin (if an external clock is needed)

If additional serial data pins are used, each McASP may be used to transmit multiple encoded bit streams
(one per pin). However, the bit streams will all be synchronized to the same clock and the user data,
channel status, and validity information carried by each bit stream will be the same for all bit streams
transmitted by the same McASP module.

The McASP can also automatically realign the data as processed by the DSP (any format on a nibble
boundary) in DIT mode; reducing the amount of bit manipulation that the DSP must perform and
simplifying software architecture.

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9.6 McASP Flexible Clock Generators

The McASP transmit and receive clock generators are identical. Each clock generator can accept a
high-frequency master clock input (on the AHCLKX and AHCLKR pins).

The transmit and receive bit clocks (on the ACLKX and ACLKR pins) can also be sourced externally or
can be sourced internally by dividing down the high-frequency master clock input (programmable factor /1,
/2, /3, ... /4096). The polarity of each bit clock is individually programmable.

The frame sync pins are AFSX (transmit) and AFSR (receive). A typical usage for these pins is to carry
the left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals
are individually programmable for either internal or external generation, either bit or slot length, and either
rising or falling edge polarity.

Some examples of the things that a system designer can use the McASP clocking flexibility for are:

• Input a high-frequency master clock (for example, 512 fSof the receiver) and receive with an internally
generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2.
(An example application would be to receive data from a DVD at 48 kHz but output up-sampled or
decoded audio at 96 kHz or 192 kHz.)

• Transmit/receive data based on sample rate (for example, 44.1 kHz) using McASP0 while transmitting
and receiving at a different sample rate (for example, 48 kHz) on McASP1.

• Use the DSP on-board AUXCLK to supply the system clock when the input source is an A/D converter.

9.7 McASP Error Handling and Management

SGUS049K–AUGUST 2003– REVISED APRIL 2011

To support the design of a robust audio system, the McASP module includes error-checking capability for
the serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that
continually measures the high-frequency master clock every 32 SYSCLK2 clock cycles. The timer value
can be read to get a measurement of the high-frequency master clock frequency and has a min-max
range setting that can raise an error flag if the high-frequency master clock goes out of a specified range.
The user would read the high-frequency transmit master clock measurement (AHCLKX0 or AHCLKX1) by
reading the XCNT field of the XCLKCHK register and the user would read the high-frequency receive
master clock measurement (AHCLKR0 or AHCLKR1) by reading the RCNT field of the RCLKCHK
register.

Upon the detection of any one or more of the above errors (software selectable) or the assertion of the
AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately
mute the audio output. In addition, an interrupt may be generated if enabled based on any one or more of
the error sources.

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9.8 McASP Interrupts and EDMA Events

The McASP transmitter and receiver sections each generate an event on every time slot. This event can
be serviced by an interrupt or by the EDMA controller.

When using interrupts to service the McASP, each shift register buffer has a unique address in the McASP
registers space (see Table 4-1).

When using the EDMA to service the McASP, the McASP DATA Port space, shown in Table 4-1, is
accessed. In this case, the address least-significant bits are ignored. Writes to any address in this range
access the transmitting buffers in order from lowest (serializer 0) to highest (serializer 15), skipping over
disabled and receiving serializers. Likewise, reads from any address in this space access the receiving
buffers in the same order but skip over disabled and transmitting buffers.

9.9 I2C

Having two I2C modules on the 320C6713/13B simplifies system architecture, since one module may be
used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to
communicate with other controllers in a system or to implement a user interface.

I2C ports are compatible with Philips I2C Specification Revision 2.1 (January 2000).

The 320C6713/13B also includes two I2C serial ports for control purposes. Each I2C port supports:

• Fast mode up to 400 Kbps (no fail-safe I/O buffers)

• Noise filter to remove noise 50 ns or less

• 7- and 10-bit device addressing modes

• Master (transmit/receive) and slave (transmit/receive) functionality

• Events: DMA, interrupt, or polling

• Slew-rate limited open-drain output buffers

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NOTE

Figure 9-2 shows a block diagram of the I2Cx module.

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Clock

Prescale

I2CPSCx

SYSCLK2
FromPLL
ClockGenerator

I2CCLKHx

Generator

BitClock

I2CCLKLx

Noise

Filter

I2CClock

SCL

I2CXSRx

I2CDXRx

Transmit

Transmit
Shift

Transmit
Buffer

I2CDRRx

Shift

I2CRSRx

Receive
Buffer

Receive

Receive

Filter

SDA

I2CData

Noise

I2COARx

I2CSARx

Slave
Address

Control

Address

Own

I2CMDRx

I2CCNTx

Mode

Data
Count

Source

Interrupt

Interrupt
Status

I2CISRCx

I2CSTRx

Enable

Interrupt

I2CIERx

Interrupt/DMA

I2CxModule

NOTE:Shadingdenotescontrol/statusregisters.

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Figure 9-2. I2Cx Module Block Diagram

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10 LOGIC AND POWER SUPPLY

This section discusses the logic and power-supply configuration of the SM320C6713-EP and
SM320C6713B-EP.

10.1 General-Purpose Input/Output (GPIO)

To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP enable (GPEN) register
and the GPxDIR bits in the GP direction (GPDIR) register must be properly configured.

GPxEN = 1 GP[x] pin is enabled.
GPxDIR = 0 GP[x] pin is an input.
GPxDIR = 1 GP[x] pin is an output.

where x represents one of the 15 through 0 GPIO pins.

Figure 10-1 shows the GPIO enable bits in the GPEN register for the C6713/13B device. To use any of

the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to 1
(enabled). Default values are device-specific, so refer to Figure 10-1 for the C6713/13B default
configuration.

31 24 23 16

Reserved

R-0

15 14 13 12 11 10 9 8

GP15EN GP14EN GP13EN GP12EN GP11EN GP10EN GP9EN GP8EN

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

GP7EN GP6EN GP5EN GP4EN GP3EN GP2EN GP1EN GP0EN

R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset

Figure 10-1. GPIO Enable (GPEN) Register (Hex Address: 01B0 0000)

Figure 10-2 shows the GPIO direction bits in the GPIO Direction (GPDIR) register. This register

determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled
(set to 1) in the GPEN register. By default, all the GPIO pins are configured as input pins.

31 24 23 16

Reserved

R-0

15 14 13 12 11 10 9 8

GP15DIR GP14DIR GP13DIR GP12DIR GP11DIR GP10DIR GP9DIR GP8DIR

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

GP7DIR GP6DIR GP5DIR GP4DIR GP3DIR GP2DIR GP1DIR GP0DIR

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset

Figure 10-2. GPIO Direction (GPDIR) Register (Hex Address: 01B0 0004)

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PWRD

Internal ClockTree

CPU

IFR

IER

CSR

PD1

PD2

Power-

Down

Logic

Clock

PLL

CLKIN RESET

PD3

Internal

Peripherals

Clock

andDividers

Distribution

320C6713/13B

CLKOUT2

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SM320C6713B-EP

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For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).

10.2 Power-Down Mode Logic

Figure 10-3 shows the power-down mode logic on the C6713/13B.

SGUS049K–AUGUST 2003– REVISED APRIL 2011

A. External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic.

Figure 10-3. Power-Down Mode Logic

10.2.1 Triggering, Wake-Up, and Effects

The device includes a programmable PLL which allows software control of PLL bypass via the PLLEN bit
in the PLLCSR register. With this enhanced functionality come some additional considerations when
entering power-down modes.

The power-down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the C6713 device.
However, if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock
input (CLKIN). Therefore, bypassing the PLL makes the power-down modes PD2 and PD3 ineffective.

The PLL needs to be enabled by writing a “1” to PLLEN bit (PLLCSR.0) before being able to enter either
PD3 (CSR.11) or PD2 (CSR.10) in order for these modes to have an effect.

For the TMS320C6713B device it is recommended to use the PLLPWDN bit (PLLCSR.1) to enter a deep
power−down state equivalent to PD3 since the PLLPWDN bit takes full advantage of the PLL power−down
feature.

The power-down modes (PD1, PD2 and PD3) and their wake-up methods are programmed by setting the
PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in

Figure 10-4 and described in Table 10-1. When writing to the CSR, all bits of the PWRD field should be

set at the same time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field.
The CSR is discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189).

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31 16

15 14 13 12 11 10 9 8

Reserved Non-Enabled PD3 PD2 PD1

Enable or

Interrupt Wake

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 0

Legend: R/W-x = Read/write reset value

Enabled

Interrupt Wake

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Figure 10-4. PWRD Field of the CSR

A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR
before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in
the CSR to account for this delay.

If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction
where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will
be executed first, then the program execution returns to the instruction where PD1 took effect. In the case
with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER)
must also be set for the interrupt service routine to execute; otherwise, execution returns to the instruction
where PD1 took effect upon PD1 mode termination by an enabled interrupt.

PD2 and PD3 modes can only be aborted by device reset. Table 10-1 summarizes all the power-down
modes.

Table 10-1. Characteristics of the Power-Down Modes

PRWD FIELD POWER-DOWN
(BITS 15−10) MODE

000000 No power down — —
001001 PD1

010001 PD1

011010 PD2

011100 PD3

All others Reserved — —

(1) When entering PD2 and PD3, all functional I/Os remain in the previous state. However, for peripherals that are asynchronous in nature

or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.

(1)

(1)

WAKE-UP METHOD EFFECT ON CHIP OPERATION

Wake by an enabled CPU halted (except for the interrupt logic)
interrupt Power-down mode blocks the internal clock inputs at the

Wake by an enabled or
non-enabled interrupt

Wake by a device reset halted. All register and internal RAM contents are preserved.

Wake by a device reset

boundary of the CPU, preventing most of the CPU logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.

Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being

All functional I/O freeze in the last state when the PLL clock is
turned off.

Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O freeze
in the last state when the PLL clock is turned off. Following
reset, the PLL needs time to relock, just as it does following
power up. Wake-up from PD3 takes longer than wake-up from
PD2 because the PLL needs to be relocked, just as it does
following power up. It is recommended to use the PLLPWDN
bit (PLLCSR.1) as an alternative to PD3.

10.3 Power-Supply Sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.

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DV

DD

CV

DD

V

SS

C6000

DSP

Schottky

Diode

I/OSupply

CoreSupply

GND

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10.3.1 System-Level Design Considerations

System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up before, and powered down after, the I/O
buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers
are powered up, thus preventing bus contention with other chips on the board.

10.3.2 Power-Supply Design Considerations

A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and
I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 10-5).

SGUS049K–AUGUST 2003– REVISED APRIL 2011

Figure 10-5. Schottky Diode Diagram

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the printed circuit board (PCB) should include separate
power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

10.4 Power-Supply Decoupling

To properly decouple the supply planes from system noise, place as many capacitors (caps) as possible
close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps—30 for the core
supply and 30 for the I/O supply. These caps need to be close (no more than 1.25-cm maximum distance)
to the DSP to be effective. Physically smaller caps are better, such as 0402, but the size needs to be
evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the
decoupling capacitors; therefore, physically smaller capacitors should be used while maintaining the
largest available capacitance value. As with the selection of any component, verification of capacitor
availability over the product’s production lifetime needs to be considered.

10.5 IEEE Std 1149.1 JTAG Compatibility Statement

The 320C6713/13B DSP requires that both TRST and RESET resets be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP emulation logic. Both
resets are required for proper operation.

NOTE

TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as
expected after TRST is asserted.

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While both TRST and RESET need to be asserted upon power-up, only RESET needs to be released for
the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port
interface and DSP emulation logic in the reset state.

TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or
exercise the DSP boundary scan functionality.

The TMS320C6713B DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will
always be asserted upon power up and the DSP’s internal emulation logic will always be properly
initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST
high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an
external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the
DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan
operations.

Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of
EMU1 and EMU0. The EMU[1:0] pins configure the device for either boundary scan mode or emulation
mode. For more detailed information, see the terminal functions section of this data sheet.

Note: The DESIGN−WARNING section of the TMS320C6713B BSDL file contains
information and constraints regarding proper device operation while in boundary scan mode.

For more detailed information on the C6713B JTAG emulation, see the TMS320C6000 DSP Designing for
JTAG Emulation Reference Guide (literature number SPRU641).

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NOTE

10.6 EMIF Device Speed

The maximum EMIF speed on the C6713/13B device is 100 MHz. TI recommends utilizing I/O buffer
information specification (IBIS) to analyze all ac timings to determine if the maximum EMIF speed is
achievable for a given board layout. To properly use IBIS models to attain accurate timing analysis for a
given system, see the application report Using IBIS Models for Timing Analysis (literature number

SPRA839).

For ease of design evaluation, Table 10-2 contains IBIS simulation results showing the maximum
EMIF-SDRAM interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing
analysis should be performed to verify that all ac timings are met for the specified board layout. Other
configurations are also possible, but again, timing analysis must be done to verify proper ac timings.

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines
(see the Terminal Functions table for the EMIF output signals).

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Table 10-2. C6713/13B Example Boards and Maximum EMIF Speed

BOARD CONFIGURATION

TYPE BOARD TRACE

1-Load
Short
Traces

2-Loads
Short 143-MHz 16-bit SDRAM (−7E) 100 MHz
Traces

3-Loads One bank of
Short two 16-bit SDRAMs 143-MHz 16-bit SDRAM (−7E) 100 MHz
Traces One bank of buffer

3-Loads 4 to 7 in from EMIF;
Long Traces Trace impedance ~63 Ω

(1) Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing

requirements can be met for the particular system.

EMIF INTERFACE EMIF-SDRAM

COMPONENTS INTERFACE SPEED

1- to 3-in traces with

One bank of proper termination

one 32-bit SDRAM resistors;

Trace impedance ~50 Ω

1.2 to 3 in from EMIF to

One bank of each load, with proper

two 16-bit SDRAMs termination resistors;

Trace impedance ~78 Ω

1.2 to 3 inches from EMIF
to each load, with proper
termination resistors;
Trace impedance ~78 Ω

One bank of

one 32-bit-bit SDRAM,

One bank of

one 32-bit-bit SDRAM,

One bank of buffer

SDRAM SPEED GRADE

143-MHz 32-bit SDRAM (−7) 100 MHz
166-MHz 32-bit SDRAM (−6) For short traces, SDRAM data

183-MHz 32-bit SDRAM (−55)

200-MHz 32-bit SDRAM (−5)
125-MHz 16-bit SDRAM (−8E) 100 MHz
133-MHz 16-bit SDRAM (−75) 100 MHz

167-MHz 16-bit SDRAM (−6A) 100 MHz

167-MHz 16-bit SDRAM (−6) 100 MHz

125-MHz 16-bit SDRAM (−8E) meet SDRAM input hold

133-MHz 16-bit SDRAM (−75) 100 MHz

167-MHz 16-bit SDRAM (−6A) 100 MHz

167-MHz 16-bit SDRAM (−6) meet SDRAM input hold

143-MHz 32-bit SDRAM (−7) 83 MHz

166-MHz 32-bit SDRAM (−6) 83 MHz
183-MHz 32-bit SDRAM (−55) 83 MHz

200-MHz 32-bit SDRAM (−5) cannot meet EMIF input hold

MAXIMUM ACHIEVABLE

output hold time on these SDRAM
speed grades cannot meet EMIF
input hold time requirement.

For short traces, EMIF cannot
requirement.

For short traces, EMIF cannot
requirement.

SDRAM data output hold time
requirement.

(1)

(1)

(1)

(1)

10.7 EMIF Big Endian Mode Correctness (C6713B Only)

The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian).
For the C6713/13B device Little Endian is the default setting.

The C6713B HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility
to change the EMIF data placement on the EMIF bus.

When using the default setting of HD12 = 1 for the C6713B, the EMIF will present 8-bit or 16-bit data on
the ED[7:0] side of the bus if using Little Endian mode (HD8 = 1), and to the ED[31:24] side of the bus if
using Big Endian mode. Figure 10-6 shows the mapping of 16-bit and 8-bit C6713B devices.

abc

EMIF DATA LINES (PINS) WHERE DATA PRESENT

ED[31:24] (BE3) ED[23:16] (BE2) ED[15:8] (BE1) ED[7:0] (BE0)

32-Bit Device in Any Endianness Mode

16-Bit Device in Big Endianness Mode 16-Bit Device in Little Endianness Mode

8-Bit Device in 8-Bit Device in

Big Endianness Mode Little Endianness Mode

Figure 10-6. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1) (C6713B Only)

When HD12 = 0 for the C6713B, enabling EMIF endianness correction, the EMIF will present 8-bit or
16-bit data on the ED[7:0] side of the bus, regardless of the endianess mode (see Figure 10-7)

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abc

EMIF DATA LINES (PINS) WHERE DATA PRESENT

ED[31:24] (BE3) ED[23:16] (BE2) ED[15:8] (BE1) ED[7:0] (BE0)

Figure 10-7. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0) (C6713B Only)

This new C6713B endianness correction functionality does not affect systems using the default value of
HD12 = 1.

This new C6713B feature does not affect systems operating in Little Endian mode.

10.8 Bootmode

The C6713/13B device resets using the active-low signal RESET and the internal reset signal. While
RESET is low, the internal reset is also asserted and the device is held in reset and is initialized to the
prescribed reset state. Refer to Reset Timing for reset timing characteristics and states of device pins
during reset. The release of the internal reset signal (see the Reset phase 3 discussion in the RESET

Timing section of this data sheet) starts the processor running with the prescribed device configuration

and boot mode.

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32-Bit Device in Any Endianness Mode

16-Bit Device in Any Endianness Mode

8-Bit Device in

Any Endianness Mode

The C6713/13B has three types of boot modes:

• Host boot
If host boot is selected, upon release of internal reset, the CPU is internally stalled while the remainder

of the device is released. During this period, an external host can initialize the CPU memory space as
necessary through the host interface, including internal configuration registers, such as those that
control the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must
set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot
configuration logic to bring the CPU out of the stalled state. The CPU then begins execution from
address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still
internally stalled. Also, DSPINT brings the CPU out of the stalled state only if the host boot process is
selected. All memory may be written to and read by the host. This allows for the host to verify what it
sends to the DSP if required. After the CPU is out of the stalled state , the CPU needs to clear the
DSPINT; otherwise, no more DSPINTs can be received.

• Emulation boot
Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load

code or to set DSPINT to release the CPU from the stalled state. Instead, the emulator will set DSPINT
if it has not been previously set so that the CPU can begin executing code from address 0. Before
beginning execution, the emulator sets a breakpoint at address 0. This prevents the execution of
invalid code by halting the CPU before executing the first instruction. Emulation boot is a good tool in
the debug phase of development.

• EMIF boot (using default ROM timings)
Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to

address 0 by the EDMA using the default ROM timings, while the CPU is internally stalled. The data
should be stored in the endian format that the system is using. The boot process also lets you choose
the width of the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit
half-words to form the 32-bit instruction words to be copied. The transfer is automatically done by the
EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the stalled state and start running from address 0.

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11 PARAMETRIC INFORMATION

11.1 Absolute Maximum Ratings

over operating case temperature range (unless otherwise noted)

Supply voltage range, CV
Supply voltage range, DV
Input voltage range −0.3 to DVDD+ 0.5 V
Output voltage range −0.3 to DVDD+ 0.5 V

Operating case temperature range T

Storage temperature range, T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) Long-term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of

overall device life. See http://ti.com/ep_quality for additional information on enhanced product packaging.

DD
DD

(2)
(2)

C

stg

11.2 Recommended Operating Conditions

CV

DV
V

(C – D)

V

(D – C)

V

IH

V

IL

I

OH

I

OL

V

OS

Supply voltage,

DD

core referenced to V
Supply voltage, I/O referenced to V

DD

SS

Maximum supply voltage difference, CVDD− DV
Maximum supply voltage difference, DVDD− CV

High-level
input voltage

Low-level
input voltage

(2)

C6713
High-level
output mA
current

C6713B

C6713

(2)

(2)

Low-level
output mA
current

C6713B

(2)

Maximum voltage during overshoot (See Figure 11-4) 4

(1)

VALUE UNIT

–0.3 to 1.8 V

–0.3 to 4 V

A version –40 to 105
S version –55 to 105
M version

(3)

–55 to 125
–60 to 150 °C

(1)

MIN NOM MAX UNIT

C6713B 1.20 1.26 1.32
C6713B 300 MHz only 1.33 1.40 1.47

SS

DD
DD

All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and
RESET

3.13 3.3 3.47 V

1.32 V

2.75 V

2

CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 2
All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and 0.8

RESET
CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET 0.3 ×

DV

DD

All signals except ECLKOUT, CLKOUT2, CLKOUT3,
CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0

–8

ECLKOUT, CLKOUT2, and CLKOUT3 –16
All signals except ECLKOUT, CLKOUT2, CLKS1/SCL1,

DR1/SDA1, SCL0, and SDA0

–8

ECLKOUT and CLKOUT2 –16
All signals except ECLKOUT, CLKOUT2, CLKOUT3,

CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0
ECLKOUT, CLKOUT2, and CLKOUT3 16
CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 3
All signals except ECLKOUT, CLKOUT2, CLKS1/SCL1,

DR1/SDA1, SCL0, and SDA0
ECLKOUT and CLKOUT2 16
CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 3

°C

V

V

V

8

8

(3)

V

(1) The core supply should be powered up before, and powered down after, the I/O supply. Systems should be designed to ensure that

neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage.
(2) Refers to dc (or steady state) currents only; actual switching currents are higher. For more details, see the device-specific IBIS models.
(3) The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.

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Recommended Operating Conditions

(1)

(continued)

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MIN NOM MAX UNIT

V

US

Maximum voltage during undershoot (See Figure 11-5) –0.7

(3)

A version –40 105

T

C

Operating case temperature S version –55 105 °C

M version –55 125

11.3 Electrical Characteristics

(1)

over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output All signals except SCL1, SDA1,

V

OH

voltage SCL0, and SDA0

Low-level output

V

OL

voltage

All signals except SCL1, SDA1,
SCL0, and SDA0

SCL1, SDA1, SCL0, and SDA0 IOL= MAX 0.4
All signals except SCL1, SDA1,

I

Input current VI= VSSto DV

I

SCL0, and SDA0
SCL1, SDA1, SCL0, and SDA0 ±10
All signals except SCL1, SDA1,

I

Off-state output current VO= DVDDor 0 V μA

OZ

SCL0, and SDA0
SCL1, SDA1, SCL0, and SDA0 ±10

I

Core supply current

DD2V

I

I/O supply current

DD3V

(2)

(2)

CIInput capacitance 7 pF
CoOutput capacitance 7 pF

(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a

device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The

high/low-DSP-activity models are defined as follows:

• High DSP activity model:

• CPU: 8 instructions/cycle with 2 LDDW instructions [L1 data memory: 128 bits/cycle via LDDW instructions; L1 program memory:

256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit switching)]

• McBSP: 2 channels at E1 rate

• Timers: 2 timers at maximum rate

• Low DSP activity model:

• CPU: 2 instructions/cycle with 1 LDH instruction [L1 data memory: 16 bits/cycle; L1 program memory: 256 bits per 4 cycles;

L2/EMIF EDMA: None]

• McBSP: 2 channels at E1 rate

• Timers: 2 timers at maximum rate

The actual current draw is highly application dependent. For more details on core and I/O activity, refer to the TMS320C6713/12C/11C

Power Consumption Summary application report (literature number SPRA889).

IOH= MAX 2.4 V

IOL= MAX 0.4

±170

DD

±170

13GDPA, CVDD= 1.4 V,
CPU clock = 300 MHz

13GDPA, CVDD= 1.26 V,
CPU clock = 200 MHz

C6713/13B, DVDD= 3.3 V,
EMIF speed = 100 MHz

945

mA

560

75 mA

V

μA

V

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Transmission Line

4.0pF 1.85pF

Z0=50
(seeNoteA)

TesterPinElectronics

DataSheetTimingReferencePoint

Output
Under
Test

42 3.5nH

DevicePin
(seeNote1)

NOTEA:Thedatasheetprovidestimingatthedevicepin.Foroutputtiminganalysis,thetesterpinelectronicsanditstransmissionlineeffects

mustbetakenintoaccount.Atransmissionlinewithadelayof2nsorlongercanbeusedto producethedesiredtransmissionline
effect.Thetransmissionlineisintendedasaloadonly.Itisnotnecessarytoaddorsubtractthetransmissionlinedelay(2nsorlonger)
fromthedata-sheettimings.

Inputrequirementsinthisdatasheetaretestedwithaninputslewrateof<4Vpernanosecond(4V/ns)atthedevicepin.

V

ref

=1.5V

V

ref

=VILMAX(orVOLMAX)

V

ref

=VIHMIN(or VOHMIN)

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11.4 Parameter Measurement Information

11.4.1 Timing Information

SGUS049K–AUGUST 2003– REVISED APRIL 2011

Figure 11-1. Test Load Circuit for AC Timing Measurements

11.4.2 Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both 0 and 1 logic levels.

Figure 11-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VILMAX and VIHMIN for input clocks, VOLMAX
and VOHMIN for output clocks.

Figure 11-3. Rise and Fall Transition Time Voltage Reference Levels

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VOS(max)

VIH(min)

Minimum
Risetime

Waveform
Valid Region

t = 0.3 tc(max)

†

Ground

= the peripheral cycle time.

†

t

c

t = 0.3 tc(max)

†

VIL(max)

Ground

VUS(max)

= the peripheral cycle time.

†

t

c

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11.4.3 AC Transient Rise/Fall Time Specifications

Figure 11-4 and Figure 11-5 show the AC transient specifications for rise and fall time. For device-specific

information on these values, refer to the Recommended Operating Conditions section of this data sheet.

Figure 11-4. AC Transient Specification Rise Time

92 PARAMETRIC INFORMATION Copyright © 2003–2011, Texas Instruments Incorporated

Figure 11-5. AC Transient Specification Fall Time

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1

2

3

4

5

6

7

8

10

11

ECLKOUT

(OutputfromDSP)

ECLKOUT

(InputtoExternalDevice)

ControlSignals

(OutputfromDSP)

ControlSignals

(InputtoExternalDevice)

DataSignals

(OutputfromExternalDevice)

DataSignals
(InputtoDSP)

9

(A)

(B)

(B)

NOTESA:Controlsignalsincludedataforwrites.

B:Datasignalsaregeneratedduringreadsfromanexternaldevice.

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11.4.4 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 11-1 and Figure 11-6).

Figure 11-6 represents a general transfer between the DSP and an external device. The figure also represents

board route delays and how they are perceived by the DSP and the external device.

Table 11-1. Board-Level Timings Example (see

Figure 11-6)

NO. DESCRIPTION

1 Clock route delay
2 Minimum DSP hold time
3 Minimum DSP setup time
4 External device hold time requirement
5 External device setup time requirement
6 Control signal route delay
7 External device hold time
8 External device access time

9 DSP hold time requirement
10 DSP setup time requirement
11 Data route delay

Copyright © 2003–2011, Texas Instruments Incorporated PARAMETRIC INFORMATION 93

Figure 11-6. Board-Level Input/Output Timings

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CLKIN

1

2

3

4

4

CLKOUT2

1

2

3

4

4

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11.5 Input and Output Clocks

Table 11-2. Timing Requirements for CLKIN

See Figure 11-7

NO. UNIT

t

c(CLKIN)

1 Cycle time, CLKIN ns

2 t

w(CLKINH)

3 t

w(CLKINL)

4 t

t(CLKIN)

(1) The reference points for the rise and fall transitions are measured at VILMAX and VIHMIN.
(2) C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.
(3) See the PLL and PLL Controller section of this data sheet.

Pulse duration, CLKIN high 0.4C 0.4C ns
Pulse duration, CLKIN low 0.4C 0.4C ns
Transition time, CLKIN 5 5 ns

GDP-200 5 83.3 6.7
GDP-300 4 83.3 6.7

(1) (2) (3)

PLL MODE BYPASS MODE

(PLLEN = 1) (PLLEN = 0)

MIN MAX MIN MAX

Figure 11-7. CLKIN

Table 11-3. Switching Characteristics for CLKOUT2

over recommended operating conditions (see Figure 11-8)

NO. PARAMETER MIN MAX UNIT

1 t
2 t
3 t
4 t

(1) The reference points for the rise and fall transitions are measured at VOLMAX and VOHMIN.
(2) C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU

period divide-by-2.

c(CKO2)
w(CKO2H)
w(CKO2L)
t(CKO2)

Cycle time, CLKOUT2 C2 – 0.8 C2 + 0.8 ns
Pulse duration, CLKOUT2 high (C2/2) – 0.8 (C2/2) + 0.8 ns
Pulse duration, CLKOUT2 low (C2/2) – 0.8 (C2/2) + 0.8 ns
Transition time, CLKOUT2 2 ns

(1) (2)

Figure 11-8. CLKOUT2

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CLKIN

CLKOUT3

3

1

2

4

4

5

5

ECLKIN

1

2

3

4

4

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Table 11-4. Switching Characteristics for CLKOUT3

SGUS049K–AUGUST 2003– REVISED APRIL 2011

(1) (2)

over recommended operating conditions (see Figure 11-9)

NO. PARAMETER UNIT

1 t
2 t
3 t
4 t
5 t

c(CKO3)
w(CKO3H)
w(CKO3L)
t(CKO3)
d(CLKINH-CKO3V)

Cycle time, CLKOUT3 C3 – 0.6 C3 + 0.6 C3 – 0.9 C3 + 0.9 ns
Pulse duration, CLKOUT3 high (C3/2) – 0.6 (C3/2) + 0.6 (C3/2) – 0.9 (C3/2) + 0.9 ns
Pulse duration, CLKOUT3 low (C3/2) – 0.6 (C3/2) + 0.6 (C3/2) – 0.9 (C3/2) + 0.9 ns
Transition time, CLKOUT3 2 3 ns
Delay time, CLKIN high to CLKOUT3 valid 1.5 6.5 1.5 7.5 ns

(1) The reference points for the rise and fall transitions are measured at VOLMAX and VOHMIN.
(2) C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the RATIO field in the PLLDIV3

register.

6713 6713B

MIN MAX MIN MAX

Figure 11-9. CLKOUT3

Table 11-5. Timing Requirements for ECLKIN

(1)

See Figure 11-10

NO. MIN MAX UNIT

1 t
2 t
3 t
4 t

c(EKI)
w(EKIH)
w(EKIL)
t(EKI)

Cycle time, ECLKIN 10 ns
Pulse duration, ECLKIN high 4.5 ns
Pulse duration, ECLKIN low 4.5 ns
Transition time, ECLKIN 3 ns

(1) The reference points for the rise and fall transitions are measured at VILMAX and VIHMIN.

Figure 11-10. ECLKIN

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5

6

1

2

3

ECLKINECLKIN

ECLKOUT

4

4

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Table 11-6. Switching Characteristics for ECLKOUT

(1) (2) (3)

over recommended operating conditions (see Figure 11-11)

NO. PARAMETER MIN MAX UNIT

1 t
2 t
3 t
4 t
5 t
6 t

(1) The reference points for the rise and fall transitions are measured at VOLMAX and VOHMIN.
(2) E = ECLKIN period in ns
(3) EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.

c (EKO)
w (EKOH)
w (EKOL)
t (EKO)
d (EKIH-EKOH)
d (EKIL-EKOL)

Cycle time, ECLKOUT E – 0.9 E + 0.9 ns
Pulse duration, ECLKOUT high EH – 0.9 EH + 0.9 ns
Pulse duration, ECLKOUT low EL – 0.9 EL + 0.9 ns
Transition time, ECLKOUT 2 ns
Delay time, ECLKIN high to ECLKOUT high 1 6.5 ns
Delay time, ECLKIN low to ECLKOUT low 1 6.5 ns

Figure 11-11. ECLKOUT

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11.6 Asynchronous Memory Timing

Table 11-7. Timing Requirements for Asynchronous Memory Cycles

See Figure 11-12 and Figure 11-13

NO. MIN MAX UNIT

3 t
4 t
6 t
7 t

su(EDV-AREH)
h(AREH-EDV)
su(ARDY-EKOH)
h(EKOH-ARDY)

(1) To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is

recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY
signal should be wide enough (for example, pulse width = 2E) to ensure setup and hold time is met.

(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIF CE space control registers.

(3) E = ECLKOUT period in ns

Setup time, EDx valid before ARE high 6.5 ns
Hold time, EDx valid after ARE high 1 ns
Setup time, ARDY valid before ECLKOUT high 3 ns
ARDY valid after ECLKOUT high 2.3 ns

Table 11-8. Switching Characteristics for Asynchronous Memory Cycles

over recommended operating condition (see Figure 11-12 and Figure 11-13)

NO. PARAMETER MIN MAX UNIT

1 t
2 t
5 t
8 t

9 t
10 t
11 t

osu(SELV-AREL)
oh(AREH-SELIV)
d(EKOH-AREV)
osu(SELV-AWEL)
oh(AWEH-SELIV)
d(EKOH-AWEV)
osu(EDV-AWEL)

(1) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIF CE space control registers.
(2) E = ECLKOUT period in ns
(3) Select signals include CEx, BE[3:0], EA[21:2], and AOE.

Output setup time, select signals valid to ARE low RS*E – 1.7 ns
Output hold time, ARE high to select signals invalid RH*E – 1.7 ns
Delay time, ECLKOUT high to ARE valid 1.5 7 ns
Output setup time, select signals valid to AWE low WS*E – 1.7 ns
Output hold time, AWE high to select signals and EDx invalid WH*E – 1.7 ns
Delay time, ECLKOUT high to AWE valid 1.5 7 ns
Output setup time, ED valid to AWE low (WS – 1)*E – 1.7 ns

(1) (2) (3)

(1) (2) (3)

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Setup= 2S trobe=3 NotReady Hold= 2

BE

Address

ReadData

21

21

21

21

5

4

3

ARDY

77

66

5

ECLKOUT

CEx

EA[21:2]

ED[31:0]

AOE

/SDRAS/SSOE

ARE/SDCAS/SSADS

BE[3:0]

AWE/SDWE/SSWE

(A)

(A)

(A)

NOTEA: / / , / / ,and / / operateas (identifiedunderselectsignals), ,and ,

respectively,duringasynchronousmemoryaccesses.

AOESDRASSSOEARESDCASSSADS AWESDWESSWE AOE ARE AWE

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Figure 11-12. Asynchronous Memory Read

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Setup= 2

Strobe=3 NotReady

Hold= 2

BE

Address

WriteData

1010

9

11

9

8

9

8

9

8

77

66

ECLKOUT

CEx

EA[21:2]

ED[31:0]

BE[3:0]

ARDY

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

(A)

(A)

(A)

NOTEA: / / , / / ,and / / operateas (identifiedunderselectsignals), ,and ,

respectively,duringasynchronousmemoryaccesses.

AOESDRASSSOEARESDCASSSADS AWESDWESSWE AOE ARE AWE

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Figure 11-13. Asynchronous Memory Write

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ECLKOUT

CEx

BE[3:0]

EA[21:2]

ED[31:0]

ARE

/SDCAS/SSADS

AOE/SDRAS/SSOE

AWE/SDWE/SSWE

BE1 BE2 BE3 BE4

EA

Q1 Q2 Q3 Q4

9

1

4

5

8

8

9

6

7

3

1

2

(1)

(1)

(1)

NOTE(1): / / , and / / operateas duringSBSRAMaccesses.ARESDCASSSADS AWESDWESSWE SSADSAO SSOE SSWE, ,and ,respectively,ESDRASSSOE/ / ,

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11.7 Synchronous-Burst Memory Timing

Table 11-9. Timing Requirements for Synchronous-Burst SRAM Cycles

See Figure 11-14

NO. MIN MAX UNIT

6 t
7 t

su(EDV-EKOH)
h(EKOH-EDV)

(1) The C6713/13B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing

4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain

continuous data flow.

Setup time, read EDx valid before ECLKOUT high 1.5 ns
Hold time, read EDx valid after ECLKOUT high 2.5 ns

Table 11-10. Switching Characteristics for Synchronous-Burst SRAM Cycles

over recommended operating conditions (see Figure 11-14 and Figure 11-15)

NO. PARAMETER MIN MAX UNIT

1 t

d (EKOH-CEV)

2 t

d (EKOH-BEV)

3 t

d (EKOH-BEIV)

4 t

d (EKOH-EAV)

5 t

d (EKOH-EAIV)

8 t

d (EKOH-ADSV)

9 t

d (EKOH-OEV)

10 t
11 t
12 t

d (EKOH-EDV)
d (EKOH-EDIV)
d (EKOH-WEV)

(1) The C6713/13B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing

4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain

continuous data flow.
(2) ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during

SBSRAM accesses.

Delay time, ECLKOUT high to CEx valid 1.2 7 ns
Delay time, ECLKOUT high to BEx valid 7 ns
Delay time, ECLKOUT high to BEx invalid 1.2 ns
Delay time, ECLKOUT high to EAx valid 7 ns
Delay time, ECLKOUT high to EAx invalid 1.2 ns
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.2 7 ns
Delay time, ECLKOUT high to AOE/SDRAS/SSOE valid 1.2 7 ns
Delay time, ECLKOUT high to EDx valid 7 ns
Delay time, ECLKOUT high to EDx invalid 1.2 ns
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.2 7 ns

(1)

(1) (2)

100 PARAMETRIC INFORMATION Copyright © 2003–2011, Texas Instruments Incorporated

Figure 11-14. SBSRAM Read Timing

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