Texas Instruments SM320C6701GLPS16, SM320C6701GLPW14, SMJ320C6701GLPW14 Datasheet
SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
Highest Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
– 7-, 6-ns Instruction Cycle Time
– 140-, 167-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– Up to 1 GFLOPS Performance
– Pin-Compatible With ’C6201 Fixed-Point
DSP
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Operating Temperature Ranges
– Extended (W) –55°C to 115°C
– Extended (S) –40°C to 90°C
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
– Eight Highly Independent Functional
Units:
– Four ALUs (Floating- and Fixed-Point)
– Two ALUs (Fixed-Point)
– Two Multipliers (Floating- and
Fixed-Point)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions
– Hardware Support for IEEE
Double-Precision Instructions
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data
(64K Bytes)
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
†
)
Boundary-Scan-Compatible
429-Pin Ceramic Ball Grid Array (CBGA)
Package (GLP Suffix)
0.18-µm/5-Level Metal Process
– CMOS Technology
3.3-V I/Os, 1.9-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
GLP PACKAGE
(BOTTOM VIEW)
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
2
9
7
10
8
64
12 14
19
171311
15
16
21
18
20
description
The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701
(’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW)
architecture developed by T exas Instruments (TI), making this DSP an excellent choice for multichannel and
multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at
a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming
challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two
fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates
(MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.
Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program
space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel
buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external
memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
TI is a trademark of Texas Instruments Incorporated.
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.
Windows is a registered trademark of the Microsoft Corporation.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
device characteristics
T able 1 provides an overview of the ’C6701 DSP . The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the ’C6701 Processors
CHARACTERISTICS DESCRIPTION
Device Number SMJ320C6701
On-Chip Memory
Peripherals
Cycle Time 7 ns at 140 MHz, and 6 ns at 167 MHz
Package Type 27 mm × 27 mm, 429-Pin BGA (GLP)
Nominal Voltage
512-Kbit Program Memory
512-Kbit Data Memory (organized as 2 blocks)
2 Mutichannel Buffered Serial Ports (McBSP)
2 General-Purpose Timers
Host-Port Interface (HPI)
External Memory Interface (EMIF)
1.9 V Core
3.3 V I/O
functional and CPU block diagram
SDRAM
SBSRAM
SRAM
ROM/FLASH
I/O Devices
Framing Chips:
H.100, MVIP ,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
HOST CONNECTION
MC68360 Glueless
MPC860 Glueless
PCI9050 Bridge + Inverter
MC68302 + PAL
MPC750 + PAL
MPC960 (Jx/Rx) + PAL
32
16
External Memory
Interface (EMIF)
Timer 0
Timer 1
Multichannel
Buffered Serial
Multichannel
Buffered Serial
Host Port
Interface
(HPI)
Port 0
Port 1
’C6701 Digital Signal Processor
Program
Program
Bus
Access/Cache
Controller
.L1†.S1†.M1†.D1 .D2 .M2†.S2†.L2
DMA Buses
Data Bus
Direct Memory
Access Controller
(DMA)
(4 Channels)
PLL
(x1, x4)
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-
Down
Logic
’C67x CPU
Data
Access
Controller
Internal Program Memory
1 Block Program/Cache
(64K Bytes)
Data Path B
B Register File
†
Internal Data
Memory
(64K Bytes)
2 Blocks of 8 Banks
Control
Registers
Control
Logic
Test
In-Circuit
Emulation
Interrupt
Control
Each
†
These functional units execute floating-point instructions.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units,
along with two register files, compose sides A and B of the CPU (see the functional and CPU block diagram
and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to
that side. Additionally , each side features a single data bus connected to all registers on the other side, by which
the two sets of functional units can access data from the register files on opposite sides. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight
functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two
functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU description (continued)
Data Path A
LD1 32 MSB
ST1
LD1 32 LSB
DA1
SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
src1
†
src2
.L1
.S1
.M1
.D1
dst
long dst
long src
long src
long dst
dst
†
src1
src2
dst
†
src1
src2
dst
src1
src2
8
8
8
8
32
32
Register
File A
(A0–A15)
2X
Data Path B
DA2
LD2 32 LSB
LD2 32 MSB
ST2
.D2
.M2
.S2
.L2
src2
src1
dst
src2
†
src1
dst
src2
src1
†
dst
long dst
long src
long src
long dst
dst
†
src2
src1
1X
Register
File B
8
8
32
32
8
8
(B0–B15)
Control
Register File
†
These functional units execute floating-point instructions.
Figure 1. SMJ320C67x CPU Data Paths
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
5
SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
signal groups description
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
CLOCK/PLL
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Control/Status
Boot Mode
Reset and
Interrupts
Little ENDIAN
Big ENDIAN
DMA Status
Power-Down
Status
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
LENDIAN
DMAC3
DMAC2
DMAC1
DMAC0
PD
HPI
Control
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
HD[15:0]
HCNTL0
HCNTL1
HHWIL
HBE1
HBE0
16
Data
Register Select
Half-Word/Byte
Select
(Host-Port Interface)
Figure 2. CPU and Peripheral Signals
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
signal groups description (continued)
SMJ320C6701
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
ED[31:0]
CE3
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
HOLD
HOLDA
TOUT1
TINP1
32
20
Data
Memory Map
Space Select
Word Address
Byte Enables
HOLD/
HOLDA
Timer 1
Asynchronous
Memory
Control
SBSRAM
Control
SDRAM
Control
EMIF
(External Memory Interface)
Timer 0
ARE
AOE
AWE
ARDY
SSADS
SSOE
SSWE
SSCLK
SDA10
SDRAS
SDCAS
SDWE
SDCLK
TOUT0
TINP0
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
Timers
McBSP1 McBSP0
Receive Receive
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
7
SMJ320C6701
†
I
External interru ts
ggg
coding
g
• Encoding order follows the interru t service fetch acket ordering
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
Signal Descriptions
SIGNAL
NAME NO.
CLKIN A14 I Clock Input
CLKOUT1 Y6 O Clock output at full device speed
CLKOUT2 V9 O Clock output at half of device speed
CLKMODE1 B17
CLKMODE0 C17
PLLFREQ3 C13 PLL frequency range (3, 2, and 1)
PLLFREQ2 G11
PLLFREQ1 F11
‡
PLLV
‡
PLLG
PLLF C12 A
TMS K19 I JTAG test port mode select (features an internal pull-up)
TDO R12 O/Z JTAG test port data out
TDI R13 I JTAG test port data in (features an internal pull-up)
TCK M20 I JTAG test port clock
TRST N18 I JTAG test port reset (features an internal pull-down)
EMU1 R20 I/O/Z Emulation pin 1, pull-up with a dedicated 20-kΩ resistor
EMU0 T18 I/O/Z Emulation pin 0, pull-up with a dedicated 20-kΩ resistor
RESET J20 I Device reset
NMI K21 I
EXT_INT7 R16
EXT_INT6 P20
EXT_INT5 R15
EXT_INT4 R18
IACK R11 O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3 T19
INUM2 T20
INUM1 T14
INUM0 T16
LENDIAN G20 I
PD D19 O Power-down mode 2 or 3 (active if high)
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡
PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect
those pins.
§
A = Analog Signal (PLL Filter)
D12 A
G10 A
TYPE
I
I
I
O
CLOCK/PLL
Clock mode select
• Selects whether the output clock frequency = input clock freq x4 or x1
• The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
§
PLL analog VCC connection for the low-pass filter
§
PLL analog GND connection for the low-pass filter
§
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
RESET AND INTERRUPTS
Nonmaskable interrupt
• Edge-driven (rising edge)
External interrupts
• Edge-driven (rising edge)
Active interrupt identification number
• Valid during IACK for all active interrupts (not just external)
• En
If high, selects little-endian byte/half-word addressing order within a word
If low, selects big-endian addressing
order follows the interrupt service fetch packet orderin
LITTLE ENDIAN/BIG ENDIAN
POWER DOWN STATUS
DESCRIPTION
p
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
†
I
Boot mode
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Signal Descriptions (Continued)
SIGNAL
NAME NO.
HINT H2 O/Z Host interrupt (from DSP to host)
HCNTL1 J6 I Host control – selects between control, address or data registers
HCNTL0 H6 I Host control – selects between control, address or data registers
HHWIL E4 I Host halfword select – first or second halfword (not necessarily high or low order)
HBE1 G6 I Host byte select within word or half-word
HBE0 F6 I Host byte select within word or half-word
HR/W D4 I Host read or write select
HD15 D11
HD14 B11
HD13 A11
HD12 G9
HD11 D10
HD10 A10
HD9 C10
HD8 B9
HD7 F9
HD6 C9
HD5 A9
HD4 B8
HD3 D9
HD2 D8
HD1 B7
HD0 C7
HAS L6 I Host address strobe
HCS C5 I Host chip select
HDS1 C4 I Host data strobe 1
HDS2 K6 I Host data strobe 2
HRDY H3 O Host ready (from DSP to host)
BOOTMODE4 B16
BOOTMODE3 G14
BOOTMODE2 F15
BOOTMODE1 C18
BOOTMODE0 D17
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TYPE
HOST PORT INTERFACE (HPI)
I/O/Z Host port data (used for transfer of data, address and control)
BOOT MODE
I Boot mode
DESCRIPTION
SMJ320C6701
SGUS030 – APRIL 2000
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
9
SMJ320C6701
†
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
Signal Descriptions (Continued)
SIGNAL
NAME NO.
CE3 Y5 O/Z
CE2 V3 O/Z Memory space enables
CE1 T6 O/Z • Enabled by bits 24 and 25 of the word address
CE0 U2 O/Z • Only one asserted during any external data access
BE3 R8 O/Z Byte enable control
BE2 T3 O/Z • Decoded from the two lowest bits of the internal address
BE1 T2 O/Z • Byte write enables for most types of memory
BE0 R2 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM)
EA21 L4
EA20 L3
EA19 J2
EA18 J1
EA17 K1
EA16 K2
EA15 L2
EA14 L1
EA13 M1
EA12 M2
EA11 M6
EA10 N4
EA9 N1
EA8 N2
EA7 N6
EA6 P4
EA5 P3
EA4 P2
EA3 P1
EA2 P6
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TYPE
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
EMIF – ADDRESS
O/Z External address (word address)
DESCRIPTION
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
†
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Signal Descriptions (Continued)
SIGNAL
NAME NO.
ED31 U18
ED30 U20
ED29 T15
ED28 V18
ED27 V17
ED26 V16
ED25 T12
ED24 W17
ED23 T13
ED22 Y17
ED21 T11
ED20 Y16
ED19 W15
ED18 V14
ED17 Y15
ED16 R9
ED15 Y14
ED14 V13
ED13 AA13
ED12 T10
ED11 Y13
ED10 W12
ED9 Y12
ED8 Y11
ED7 V10
ED6 AA10
ED5 Y10
ED4 W10
ED3 Y9
ED2 AA9
ED1 Y8
ED0 W9
ARE R7 O/Z Asynchronous memory read enable
AOE T7 O/Z Asynchronous memory output enable
AWE V5 O/Z Asynchronous memory write enable
ARDY R4 I Asynchronous memory ready input
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TYPE
EMIF – DATA
I/O/Z External data
EMIF – ASYNCHRONOUS MEMORY CONTROL
SMJ320C6701
SGUS030 – APRIL 2000
DESCRIPTION
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
11
SMJ320C6701
†
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
Signal Descriptions (Continued)
SIGNAL
NAME NO.
SSADS V8 O/Z SBSRAM address strobe
SSOE W7 O/Z SBSRAM output enable
SSWE Y7 O/Z SBSRAM write enable
SSCLK AA8 O/Z SBSRAM clock
SDA10 V7 O/Z SDRAM address 10 (separate for deactivate command)
SDRAS V6 O/Z SDRAM row address strobe
SDCAS W5 O/Z SDRAM column address strobe
SDWE T8 O/Z SDRAM write enable
SDCLK T9 O/Z SDRAM clock
HOLD R6 I Hold request from the host
HOLDA B15 O Hold request acknowledge to the host
TOUT1 G2 O/Z Timer 1 or general-purpose output
TINP1 K3 I Timer 1 or general-purpose input
TOUT0 M18 O/Z T imer 0 or general-purpose output
TINP0 J18 I Timer 0 or general-purpose input
DMAC3 E18
DMAC2 F19
DMAC1 E20
DMAC0 G16
CLKS1 F4 I External clock source (as opposed to internal)
CLKR1 H4 I/O/Z Receive clock
CLKX1 J4 I/O/Z Transmit clock
DR1 E2 I Receive data
DX1 G4 O/Z Transmit data
FSR1 F3 I/O/Z Receive frame sync
FSX1 F2 I/O/Z Transmit frame sync
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
TYPE
EMIF – SYNCHRONOUS BURST SRAM CONTROL
EMIF – SYNCHRONOUS DRAM CONTROL
EMIF – BUS ARBITRATION
TIMERS
DMA ACTION COMPLETE
O DMA action complete
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
DESCRIPTION
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
†
DV
DD
S
3.3 V su ly voltage
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Signal Descriptions (Continued)
SIGNAL
NAME NO.
CLKS0 K18 I External clock source (as opposed to internal)
CLKR0 L21 I/O/Z Receive clock
CLKX0 K20 I/O/Z Transmit clock
DR0 J21 I Receive data
DX0 M21 O/Z Transmit data
FSR0 P16 I/O/Z Receive frame sync
FSX0 N16 I/O/Z Transmit frame sync
RSV0 N21 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV1 K16 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV2 B13 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV3 B14 I Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV4 F13 I Reserved for testing,
RSV5 C15 O Reserved (leave unconnected,
RSV6 F7 I Reserved for testing, pull-up with a dedicated 20-k resistor
RSV7 D7 I Reserved for testing, pull-up with a dedicated 20-k resistor
RSV8 B5 I Reserved for testing, pull-up with a dedicated 20-k resistor
RSV9 F16 O Reserved for testing,
C14
E19
H11
H13
DV
DD
K11
K13
K15
L10
L12
L14
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
C8
E3
H9
J10
J12
J14
J19
J3
J8
K7
K9
TYPE
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
S 3.3-V supply voltage
RESERVED FOR TEST
pull-down
with a dedicated 20-kΩ resistor
do not
pull-down
SUPPLY VOLTAGE PINS
with a dedicated 20-kΩ resistor
DESCRIPTION
connect to power or ground)
SMJ320C6701
SGUS030 – APRIL 2000
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
13
SMJ320C6701
†
DV
DD
S
3.3 V su ly voltage
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
Signal Descriptions (Continued)
SIGNAL
NAME NO.
M11
M13
M15
N10
N12
N14
DV
DD
CV
DD
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
N19
P11
P13
U19
W14
A12
A13
B10
B12
D15
D16
F10
F14
G13
A16
L8
M7
M9
N3
N8
P9
U3
W8
B6
F8
G7
G8
K4
M3
M4
A3
A5
A7
TYPE
SUPPLY VOLTAGE PINS (CONTINUED)
S 3.3-V supply voltage
S 1.9-V supply voltage
DESCRIPTION
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
†
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Signal Descriptions (Continued)
SIGNAL
NAME NO.
A18
AA4
AA6
AA15
AA17
AA19
B19
C20
D21
CV
DD
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
E10
E12
E14
E16
F17
F21
H17
K17
M17
P17
R21
B2
B4
C1
C3
D2
E1
E6
E8
F5
G1
H5
K5
M5
P5
TYPE
SUPPLY VOLTAGE PINS (CONTINUED)
S 1.9-V supply voltage
SMJ320C6701
SGUS030 – APRIL 2000
DESCRIPTION
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
15
SMJ320C6701
†
CV
DD
S
1.9 V su ly voltage
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
Signal Descriptions (Continued)
SIGNAL
NAME NO.
T17
U10
U12
U14
U16
U21
V20
W19
W21
Y18
Y20
CV
DD
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
AA11
AA12
F20
G18
H16
H18
N20
P18
P19
R10
R14
V11
V12
V15
W13
TYPE
SUPPLY VOLTAGE PINS (CONTINUED)
T1
T5
U6
U8
V1
W2
Y3
S 1.9-V supply voltage
L18
L19
L20
U4
DESCRIPTION
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
†
V
SS
GND
Ground ins
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Signal Descriptions (Continued)
SIGNAL
NAME NO.
C11
C16
H10
H12
H14
V
SS
A15
A17
A19
AA3
AA5
AA7
AA14
AA16
AA18
B18
B20
C19
C21
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
C6
D5
G3
H7
H8
J11
J13
J7
J9
K8
L7
L9
M8
N7
R3
A4
A6
A8
B3
C2
D1
TYPE
GROUND PINS
GND Ground pins
SMJ320C6701
SGUS030 – APRIL 2000
DESCRIPTION
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
17
SMJ320C6701
†
V
SS
GND
Ground ins
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SGUS030 – APRIL 2000
Signal Descriptions (Continued)
SIGNAL
NAME NO.
D20
E11
E13
E15
E17
E21
G17
G21
V
SS
N17
P21
R17
T21
U11
U13
U15
U17
V21
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
E5
E7
E9
F1
G5
H1
J5
J17
L5
L17
N5
R1
R5
U1
U5
U7
U9
V2
TYPE
GROUND PINS (CONTINUED)
GND Ground pins
DESCRIPTION
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
†
V
SS
GND
Ground ins
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Signal Descriptions (Continued)
SIGNAL
NAME NO.
W20
Y19
F18
G19
H15
K10
K12
K14
L13
L15
V
SS
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
M10
M12
M14
N11
N13
N15
P10
P12
P14
P15
R19
W11
W16
TYPE
GROUND PINS (CONTINUED)
W1
W3
Y2
Y4
J15
J16
L11
GND Ground pins
N9
P7
P8
T4
W6
SMJ320C6701
SGUS030 – APRIL 2000
DESCRIPTION
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
19
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