Texas Instruments SM320C50GFAM66, SM320C50HFGM50, SM320C50HFGM66, SM320C50GFAM50, SMQ320C50PQM66 Datasheet

SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Military Operating Temperature Range:

– 55°C to 125°C

Processed to MIL-PRF-38535

Fast Instruction Cycle Time (30 ns and 40 ns)

Source-Code Compatible With All ’C1x and ’C2x Devices

RAM-Based Operation – 9K × 16-Bit Single-Cycle On-Chip

Program/Data RAM

– 1056 × 16-Bit Dual-Access On-Chip

Data RAM

2K × 16-Bit On-Chip Boot ROM

224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global)

32-Bit Arithmetic Logic Unit (ALU) – 32-bit Accumulator (ACC) – 32-Bit Accumulator Buffer (ACCB)

16-Bit Parallel Logic Unit (PLU)

16 × 16-Bit Multiplier, 32-Bit Product

11 Context-Switch Registers

Two Buffers for Circular Addressing

Full-Duplex Synchronous Serial Port

Time-Division Multiplexed Serial Port (TDM)

Timer With Control and Counter Registers

16 Software Programmable Wait-State Generators

Divide-by-One Clock Option

IEEE 1149.1† Boundary Scan Logic

Operations Are Fully Static

Enhanced Performance Implanted CMOS (EPIC) 0.72-µm Technology Fabricated by T exas Instruments

Packaging – 141-Pin Ceramic Grid Array (GFA Suffix) – 132-Lead Ceramic Quad Flat Package

(HFG Suffix)

– 132-Lead Plastic Quad Flat Package

(PQ Suffix)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

HFG PACKAGE

(TOP VIEW)

100

991

132

6733

1 3 5 7 9 11 13 15 17 19

4681012141618

GFA PACKAGE

(TOP VIEW)

PQ PACKAGE

(TOP VIEW)

117

116

132

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture

EPIC and TI are trademarks of Texas Instruments Incorporated.

SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description

The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor manufactured in 0.72-µm double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI designed as a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high performance, making it ideal for applications such as battery-operated communications systems, satellite systems, and advanced control algorithms.

A number of enhancements to the basic SMJ320C2x architecture give the ’C50 a minimum 2× performance over the previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the ’C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the ’C50 a method for manipulating bits in data memory without using the accumulator and ALU. The ’C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.

The ’C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the ’C50, which puts it into a total-sleep mode that uses only 7 µA. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.

The ’C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time, and 66 MHz, providing a 30-ns cycle time. The available options are listed in the following table.

AVAILABLE OPTIONS

PART NUMBER

SPEED

SUPPLY

VOLTAGE

TOLERANCE

PACKAGE

SMJ320C50GFAM66 30-ns cycle time ±5% Pin grid array SMJ320C50HFGM66 30-ns cycle time ±5% Quad flat package SMJ320C50GFAM50 40 ns cycle time ±5% Pin grid array SMJ320C50HFGM50 40 ns cycle time ±5% Quad flat package SMQ320C50PQM66

†

30 ns cycle time ±5% Plastic Quad flat package

†

When ordering use DESC P/N 5962-9455804NZD

SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

BMAR

MUX

PC(16)

Stack

(8 × 16)

PASR BRAF

IPTR INT# INTM IMR IFR

MP/MC

CNF RAM

Program MemoryPAERCompare

BRCR

MUX

TRM

TREG0TREG1TREG2

COUNT

Prescaler

OVM SXM

Multiplier

PREG(32)

P-Scaler

ALU(32)

ACC(32)ACCB(32)

Post-Scaler

OV TC C

DBMR

BIM

MUX

PLU(16)

MUX

CBERMUX INDX ARCR

ARP

ARB

NDX CBSR

DP(9) dma(7)

AUXREGS

(8 × 16)

CBCR

ARAU(16)

Data Memory GREG

BRCNF OVLY

Program Bus (Address) Program Bus (Data)

Data Bus (Address)

Data Bus (Data)

SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

pin assignments

PQ PKG HFG PKG GFA PKG NAME PQ PKG HFG PKG GFA PKG NAME

18 1 NC

†

57 40 W3 A2

19 2 NC

†

58 41 U7 A3 20 3 D8 VSS3 59 42 V6 A4 21 4 D10 VSS4 60 43 W5 A5 22 5 NC

†

61 44 U9 A6 23 6 E3 D7 62 45 V8 A7 24 7 D2 D6 63 46 W7 A8 25 8 C1 D5 64 47 W9 A9 26 9 G3 D4 65 48 E9 VDD7 27 10 F2 D3 66 49 E11 VDD8 28 11 E1 D2 67 50 V10 TDI 29 12 J3 D1 68 51 K4 VSS9 30 13 H2 D0(LSB) 69 52 M4 VSS10 31 14 G1 TMS 70 53 NC

†

32 15 C3 VDD3 71 54 W11 CLKMD1 33 16 D4 VDD4 72 55 W13 A10 34 17 J1 TCK 73 56 V12 A11 35 18 D12 VSS5 74 57 U11 A12 36 19 F4 VSS6 75 58 W15 A13 37 20 NC

†

76 59 V14 A14 38 21 L1 INT1 77 60 U13 A15(MSB) 39 22 N1 INT2 78 61 NC

†

40 23 M2 INT3 79 62 NC

†

41 24 L3 INT4 80 63 E13 VDD9 42 25 R1 NMI 81 64 G5 VDD10 43 26 P2 DR 82 65 V16 RD 44 27 N3 TDR 83 66 U15 WE 45 28 T2 FSR 84 67 NC

†

46 29 R3 CLKR 85 68 NC

†

47 30 E5 VDD5 86 69 P4 VSS11 48 31 E7 VDD6 87 70 T4 VSS12 49 32 NC

†

88 71 NC

†

50 33 NC

†

89 72 R17 DS 51 34 NC

†

90 73 T18 IS 52 35 NC

†

91 74 U19 PS 53 36 H4 VSS7 92 75 N17 R/W 54 37 K2 VSS8 93 76 P18 STRB 55 38 U5 A0 94 77 R19 BR 56 39 V4 A1 95 78 L17 CLKIN2

†

NC = No internal connection GFA Package additional connections: VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19 VSS: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16

SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

pin assignments (continued)

PQ PKG HFG PKG GFA PKG NAME PQ PKG HFG PKG GFA PKG NAME

96 79 M18 X2/CLKIN 123 106 B16 TCLKX 97 80 N19 X1 124 107 A17 CLKX 98 81 J5 VDD11 125 108 C13 TFSR/TADD

99 82 L5 VDD12 126 109 B14 TCLKR 100 83 L19 TDO 127 110 A15 RS 101 84 T6 VSS13 128 111 C11 READY 102 85 T8 VSS14 129 112 B12 HOLD 103 86 K18 CLKMD2 130 113 A13 BIO 104 87 J19 FSX 131 114 R7 VDD15 105 88 G19 TFSX/TFRM 132 115 R9 VDD16 106 89 H18 DX 1 116 A11 IAQ 107 90 J17 TDX 2 117 A9 TRST 108 91 E19 HOLDA 3 118 B10 VSS1 109 92 F18 XF 4 119 D6 VSS2 110 93 G17 CLKOUT1 5 120 A7 MP/MC 111 94 NC

†

6 121 B8 D15(MSB) 112 95 E17 IACK 7 122 C9 D14 113 96 N5 VDD13 8 123 A5 D13 114 97 R5 VDD14 9 124 B6 D12 115 98 NC

†

10 125 C7 D11

116 99 NC

†

11 126 A3 D10

117 100 NC

†

12 127 B4 D9 118 101 B18 EMU0 13 128 C5 D8 119 102 A19 EMU1/OFF 14 129 A1 VDD1 120 103 T10 VSS15 15 130 B2 VDD2 121 104 T12 VSS16 16 131 NC

†

122 105 C15 TOUT 17 132 NC

†

SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions

NAME TYPE

†

DESCRIPTION

ADDRESS AND DATA BUSES

A15 (MSB) A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB)

I/O/Z

Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0–A15 are in the high-impedance state in hold mode and when OFF

is active (low). These signals are used as inputs for external DMA

access of the on-chip single-access RAM. They become inputs while HOLDA

is active (low) if BR is driven low

externally.

D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

I/O/Z

Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program memory, or I/O devices. D0–D15 are in the high-impedance state when not outputting data, when RS

or HOLD is asserted, or when

OFF

is active (low). These signals also are used in external DMA access of the on-chip single-access RAM.

MEMORY CONTROL SIGNALS

DS PS IS

O/Z

Data, program, and I/O space select signals. Always high unless asserted for communicating to a particular external space. DS

, PS, and IS are in the high-impedance state in hold mode or when OFF is active (low).

READY I

Data ready input. Indicates that an external device is prepared for the bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus grant to an external device after a BR

(bus request) signal.

R/W I/O/Z

Read/write. R/W indicates transfer direction during communication to an external device and is normally in read mode (high) unless asserted for performing a write operation. R/W

is in the high-impedance state in hold mode or

when OFF

is active (low). Used in external DMA access of the 9K RAM cell, this signal indicates the direction of the

data bus for DMA reads (high) and writes (low) when HOLDA

and IAQ are active (low).

STRB I/O/Z

Strobe. Always high unless asserted to indicate an external bus cycle, STRB is in the high-impedance state in the hold mode or when OFF

is active (low). Used in external DMA access of the on-chip single-access RAM and while

HOLDA

and IAQ are active (low), STRB is used to select the memory access.

RD O/Z

Read select. RD indicates an active external read cycle and can connect directly to the output enable (OE) of external devices. This signal is active on all external program, data, and I/O reads. RD

is in the high-impedance state in hold

mode or when OFF

is active (low).

†

I = input, O = output, Z = high-impedance

NOTE: All input pins that are unused should be connected to VDD or an external pullup resistor. The BR

pin has an internal pullup for performing

DMA to the on-chip RAM. For emulation, TRST

has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1

require external pullups to support emulation.

SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (continued)

NAME TYPE

†

DESCRIPTION

MEMORY CONTROL SIGNALS (CONTINUED)

WE O/Z

Write enable. The falling edge indicates that the device is driving the external data bus (D15 –D0). Data can be latched by an external device on the rising edge of WE

. This signal is active on all external program, data, and I/O

writes. WE

is in the high-impedance state in hold mode or when OFF is active (low).

MULTIPROCESSING SIGNALS

HOLD I

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the ’C50, these lines go to the high-impedance state.

HOLDA O/Z

Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and memory control lines are in the high-impedance state so that they are available to the external circuitry for access to local memory. This signal also goes to the high-impedance state when OFF

is active (low).

BR I/O/Z

Bus request. BR is asserted during access of external global data memory space. READY is asserted when the global data memory is available for the bus transaction. BR

can be used to extend the data memory address space

by up to 32K words. BR

goes to the high-impedance state when OFF is active low. BR is used in external DMA access

of the on-chip single-access RAM. While HOLDA

is active (low), BR is externally driven (low) to request access to

the on-chip single-access RAM.

IAQ O/Z

Instruction acquisition. Asserted (active) when there is an instruction address on the address bus; goes into the high-impedance state when OFF

is active (low). IAQ is also used in external DMA access of the on-chip

single-access RAM. While HOLDA

is active (low), IAQ acknowledges the BR request for access of the on-chip

single-access RAM and stops indicating instruction acquisition.

BIO I

Branch control. BIO samples as the BIO condition and, if it is low, causes the device to execute the conditional instruction. BIO

must be active during the fetch of the conditional instruction.

XF O/Z

External flag (latched software-programmable signal). Set high or low by a specific instruction or by loading status register 1 (ST1). Used for signaling other processors in multiprocessor configurations or as a general-purpose output. XF goes to the high-impedance state when OFF

is active (low) and is set high at reset.

IACK O/Z

Interrupt acknowledge. Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15–A0. IACK

goes to the high-impedance state when OFF is active (low).

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

INT4 INT3 INT2 INT1

External interrupts. INT1–INT4 are prioritized and maskable by the interrupt mask register (IMR) and interrupt mode bit (INTM, bit 9 of status register 0). These signals can be polled and reset by using the interrupt flag register.

NMI I

Nonmaskable interrupt. NMI is the external interrupt that cannot be masked via INTM or IMR. When NMI is activated, the processor traps to the appropriate vector location.

RS I

Reset. RS causes the device to terminate execution and forces the program counter to zero. When RS is brought to a high level, execution begins at location zero of program memory.

MP/MC I

Microprocessor/microcomputer select. If active (low) at reset (microcomputer mode), the signal causes the internal program ROM to be mapped into program memory space. In the microprocessor mode, all program memory is mapped externally . This signal is sampled only during reset, and the mode that is set at reset can be overridden via the software control bit MP/MC

in the PMST register.

OSCILLATOR/TIMER SIGNALS

CLKOUT1 O/Z

Master clock (or CLKIN2 frequency). CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by the rising edges of this signal. This signal goes to the high-impedance state when OFF

is active

(low).

†

I = input, O = output, Z = high-impedance

SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (continued)

NAME TYPE

†

DESCRIPTION

OSCILLATOR/TIMER SIGNALS (CONTINUED)

CLKMD1 CLKMD2

CLKMD1 CLKMD2 Clock mode

0 0 External clock with divide-by-two option. Input clock is provided to X2/CLKIN1. Internal

oscillator and PLL are disabled. 0 1 Reserved for test purposes 1 0 External divide-by-one option. Input clock is provided to CLKIN2. Internal oscillator is

disabled and internal PLL is enabled. 1 1 Internal or external divide-by-two option. Input clock is provided to X2/CLKIN1. Internal

oscillator is enabled and internal PLL is disabled.

X2/CLKIN I

Input to the internal oscillator from the crystal. If the internal oscillator is not being used, a clock can be input to the device on X2/CLKIN. The internal machine cycle is half this clock rate.

X1 O

Output from the internal oscillator for the crystal. If the internal oscillator is not used, X1 must be left unconnected. This signal does not go to the high-impedance state when OFF

is active (low).

CLKIN2 I Divide-by-one input clock for driving the internal machine rate. TOUT O

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1 cycle wide.

SUPPLY PINS

DD1

DD2

DD3

DD4

I Power supply for data bus

DD5

DD6

I Power supply for address bus

DD7

DD8

I Power supply for inputs and internal logic

DD9

DD10

I Power supply for address bus

DD11

DD12

I Power supply for memory control signals

DD13

DD14

I Power supply for inputs and internal logic

DD15

DD16

I Power supply for memory control signals

SS1

SS2

I Ground for memory control signals

SS3

SS4

SS5

SS6

I Ground for data bus

SS7

SS8

SS9

SS10

I Ground for address bus

SS11

SS12

I Ground for memory control signals

SS13

SS14

SS15

SS16

I Ground for inputs and internal logic

†

I = input, O = output, Z = high-impedance

SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions (continued)

NAME TYPE

†

DESCRIPTION

SERIAL PORT SIGNALS

CLKR TCLKR

Receive clock. External clock signal for clocking data from DR (data receive) or TDR (TDM data receive) into the RSR (serial port receive shift register). Must be present during serial port transfers. If the serial port is not being used, these signals can be sampled as an input via the IN0 bit of the serial port control (SPC) or TDR serial port control (TSPC) registers.

CLKX TCLKX

I/O/Z

Transmit clock. Clock signal for clocking data from the DR or TDR to the DX (data transmit) or TDX (TDM data transmit pins). CLKX can be an input if the MCM bit in the serial port control register is set to 0. It can also be driven by the device at 1/4 the CLKOUT1 frequency when the MCM bit is set to 1. If the serial port is not being used, this pin can be sampled as an input via the IN1 bit of the SPC or TSPC register. This signal goes into the high-impedance state when OFF

is active (low).

DR TDR

I Serial data receive. Serial data is received in the RSR (serial port receive shift register) via DR or TDR.

DX TDX

O/Z

Serial port transmit. Serial data transmitted from XSR (serial port transmit shift register) via DX or TDX. This signal is in the high-impedance state when not transmitting and when OFF

is active (low).

FSR TFSR/TADDII/O/Z

Frame synchronization pulse for receive. The falling edge of FSR or TFSR initiates the data receive process, which begins the clocking of the RSR. TFSR becomes an input/output (TADD) pin when the serial port is operating in the TDM mode (TDM bit = 1). In TDM mode, this pin is used to input/output the address of the port. This signal goes into the high-impedance state when OFF

is active (low).

FSX TFSX/TFRM

I/O/Z

Frame synchronization pulse for transmit. The falling edge of FSX/TFSX initiates the data transmit process, which begins the clocking of the XSR. Following reset, the default operating condition of FSX/TFSX is an input. This pin may be selected by software to be an output when the TXM bit in the serial control register is set to 1. This signal goes to the high-impedance state when OFF

is active (low). When operating in TDM mode (TDM bit = 1), TFSX

becomes TFRM, the TDM frame-synchronization pulse.

TEST SIGNALS

TCK I

Boundary scan test clock. This is normally a free-running clock with a 50% duty cycle. The changes of TAP (test access port) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.

TDI I Boundary scan test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.

TDO O/Z

Boundary scan test data output. The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in progress. This signal also goes to the high-impedance state when OFF

is active (low).

TMS I

Boundary scan test mode select. This serial control input is clocked into the test access port (TAP) controller on the rising edge of TCK.

TRST I

Boundary scan test reset. Asserting this signal gives the JTAG scan system control of the operations of the device. If this signal is not connected or is driven low, the device operates in its functional mode and the boundary scan signals are ignored.

EMU0 I/O/Z

Emulator 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition (see EMU1/OFF). When TRST

is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output

put via boundary scan.

EMU1/OFF I/O/Z

Emulator 1/OFF . When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output via boundary scan. When TRST

is driven low, EMU1/OFF is configured as OFF. When

the OFF

signal is active (low), all output drivers are in the high-impedance state. OFF is used exclusively for testing

and emulation purposes (not for multiprocessing applications). For the OFF

condition, the following conditions apply:

• TRST

= Low

• EMU0 = High

• EMU1/OFF

= Low

RESERVED

‡

N/C Reserved. This pin must be left unconnected.

†

I = input, O = output, Z = high-impedance

‡

Quad flat pack only

SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESSOR

SGUS020 – JUNE 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum operating case temperature, T

125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Minimum operating free-air temperature, T

– 55°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

– 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

VDDSupply voltage 4.75 5 5.25 V VSSSupply voltage 0 V

CLKIN, CLKIN2 3.0 VDD +

0.3

VIHHigh-level input voltage

CLKX, CLKR, TCLKX, TCLKR

2.5 VDD +

0.3

All others 2.2 VDD +

0.3

V VILLow-level input voltage – 0.3 0.6 V I

High-level output current – 300

‡

µA

Low-level output current 2 mA

Operating case temperature 125 °C

Operating free-air temperature – 55 °C

‡

This IOH can be exceeded when using a 1-KΩ pulldown resistor on the TDM serial port TADD output, however this output still meets V

specifications under these conditions.

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS

MIN TYP¶MAX UNIT

High-level output voltage#IOH = MAX 2.4 3 V

Low-level output voltage¶IOL = MAX 0.3 0.6 V High-impedance output

BR (with internal pullup) – 500

current (VDD = MAX)

All others

– 30

TRST (with internal pulldown) – 30

800

Input current

TMS, TCK, TDI (with internal pullups)

– 500

µA

(VI = VSS to VDD)

X2/CLKIN

– 50

All other inputs – 30

30 µA

DDC

Supply current, core CPU Operating, TA = 25°C, VDD = 5.25 V , fx = 50 MHz 60 225 mA

DDP

Supply current, pins Operating, TA = 25°C, VDD = 5.25 V , fx = 50 MHz 40 225 mA

IDLE instruction, TA = 125°C, VDD = 5.25 V , fx = 50 MHz 30 mA

IDDSupply current, standb

IDLE2 instruction, Clocks shut off, TA =125°C, VDD =5.25 V

7 µA

Input capacitance 15 40 pF

Output capacitance 15 40 pF

For conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.

All typical or nominal values are at VDD = 5 V, TA = 25°C.

All input and output voltage levels are TTL-compatible. Figure 1 shows the test load circuit; Figure 2 and Figure 3 show the voltage reference levels.

These values are not specified pending detailed characterization.

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