The PCIE16X-800EVK is a PCIe add-in riser card for PCIe 16x applications. It provides a complete
platform to evaluate 4 - DS80PCI800SQ, 8 channels PCIe repeater for PCIe system protocol and lane
negotiation validation. The card has a 16X PCIe edge fingers at J1 which plugs into a motherboard
that has a PCIe 16X connector. The card also has a PCIe 16X connector at J2 for endpoint connection
(PCIe graphic card or SATA/SAS raid controller card).
Features:
■ 8 channel PCIe repeater up to 8 Gbps (GEN 3)
■ Low power consumption, with option to power down unused channels
■ Adjustable receive equalization
■ Adjustable transmit VOD and De-emphasis
■ IDLE detection — squelch function auto mutes the output
■ Programmable via pin selection or SMBus interface
■ Single supply operation: VIN = 3.3V±10% or VDD = 2.5V ±5%
■ -40°C to +85°C Operation
■ >6 kV HBM ESD Rating
■ High speed signal flow–thru pin-out package - SQA54A: 54-pin LLP (10 mm x 5.5 mm, 0.5 mm pitch)
Applications:
■ Extends FR-4 Backplane Trace for PCIe Applications
Table 1. Switches to set the 4-level input control pins
4 – level Input Settings
0 – Tie 249 ohm to GND ON – OFF – OFF
R – Tie 5k ohm to GND OFF – ON – OFF
F – FLOAT (open) OFF – OFF – OFF
1 – Tie 249 ohm to VIH OFF – OFF – ON
The following switches are used to set the input condition for the 4-level inputs:
SW1, SW2, SW3, SW5, SW6, SW10, SW11.
There are 3 switches connected to an input signal pin. Each switch when set to the ON position sets the pin to
one of the 4-level setting. The 6 pin switches are assigned similar to the 3 pin switches. The only difference is 2
signal pins are connected and thus 6-5-4 is for the one signal pin and 3-2-1 is for another signal pin. Please note
only 1 switch at the ON position is allowed.
Table 2. Connection and Control Description
Component Name
J1 PCIE TX/RX High speed differential TX/RX from/to Root Complex
J2 PCIE TX/RX High speed differential TX/RX to/from End Point
J3, J5 3.3V to VIN
J4, J6 2.5V to VDD
J7 VIN or VDD Jumper VIH: set 1-2 = VIN (3.3V) or set 2-3 = VDD (2.5V)
J8 SDA, SCL
J9 EEPROM Optional socket for EEPROM
Function
3.3V DC Power – VIN to DS80PCI800SQ
Jumper ON = 3.3V mode operation
Jumper OFF = 2.5V mode operation
2.5V DC Power – VDD to DS80PCI800SQ
Jumper ON (1-2, 3-4) = 2.5V mode operation
Jumper OFF (1-2, 3-4) = 3.3V mode operation
Optional SMBUS access pins.
See the datasheet for additional information on SMBUS.
Setting for 3 pin switches (3-2-1)
SW1
SW2
SW3
SW4 SDA/SCL “ON” position connects SDA and SCL lines to the device pin.
SW5
SW6
SW7
EQB[1:0] or
AD[3:2]
ENSMB
DEMA[1:0]
DEMB[1:0] or
AD[1:0]
SD_TH and
LPBK - RES
VDD_SEL1_2
VDD_SEL3_4
READ_EN,
SW8
RD_EN2,
RD_EN3 and
RD_EN4
A_D1 to
SW9
SW10
SW11
RD_EN2 …
A_D3 to
RD_EN4
RXDET and
RATE
EQA[1:0]
PIN MODE – EQ control for channel B inputs
SMBUS MODE – AD[3:2] device address bits
PIN MODE – DE control for channel B outputs
SMBUS MODE – AD[1:0] device address bits
SD_TH – Signal detect threshold level (FLOAT = Default level)
LPBK function for PCI402 and RESERVED for PCI800 (FLOAT = Normal operation)
VDD_SEL – Enable or disable the internal 3.3V to 2.5V regulator for U1 and U2.
ON connects to GND to enable the internal LDO regulator for 3.3V mode operation.
For manual control of loading the external EEPROM and daisy chain the READ_EN
to the ALL_DONE pins.
Pin1 = ON connects the SW13 push button to the READ_EN of U1.
Pin2,3,4 = OFF
Pin1 = ON connects the ALL_DONE of U1 to READ_EN of U2.
Pin2 = ON connects the ALL_DONE of U2 to READ_EN of U3.
Pin3 = ON connects the ALL_DONE of U3 to READ_EN of U4.
Pin4 = OFF
RXDET – Input internal 50 ohm to VDD terminations
RXDET = F (AUTO RX Detect), RXDET = 1 (50 ohm input termination).
RATE = 0 (GEN1,2) = 2.5G / 5.0G.
RATE = R (GEN3) = 8.0G.
RATE = F (AUTO Detect). The RATE auto detect circuit requires the idle and active
signal which occurs during the link training negotiation.
“ON” connect the SDA/SCL bus to the PCIe SMCLK and SMDAT bus.
Default is “OFF”.
ENSMB = FLOAT – SMBUS (master mode – load configuration from EEPROM)
SW6: SD_TH becomes the READ_EN pin.
To start the loading at power up, set SW6 pin 3 to “ON” position (pull to GND).
To manually control the start, set SW6 to “OFF” position and set SW8 pin1 to “ON”
and pin2 to “OFF” position and push the SW13 button for the high to low transition to
start the loading. When the loading is complete the LEDs – D1 thru D4 light should
turn OFF.
“ON” connects the PCIe PRSNT signal to the device PRSNT pin.
For 16X, set all the switches to the “ON” position.
Quick Start User Guide:
1. Connect J1 – PCIe 16x edge finger to the motherboard (root complex)
2. Connect J2 - PCIe 16x connector to an add-in card (end point).
3. For 3.3V mode operation, set J3 jumper to ON and do not use J4 (leave jumper OFF).
For 2.5V mode operation, set J3 jumper to OFF and set J4 jumper to ON (1-2 and 3-4).
4. Set jumper – J7 for VIH connection to VIN (3.3V) or VDD (2.5V). Default is 1-2 set to ON for VIH = 3.3V.
5. Set SW7 – VDD_SEL1_2 and VDD_SEL3_4 to “ON” position for 3.3V mode operation.
6. Set the control pins for normal operation
SW10 – RXDET = F (continuous receiver detection): set switches (3-2-1) = (OFF-OFF-OFF).
RXDET = 1 (50 ohm input termination): set switches (3-2-1) = (OFF-OFF-ON). SW10 – RATE = F (enable rate detection): set switches (6-5-4) to (OFF-OFF-OFF).
RATE = R (GEN3 mode): set switches (6-5-4) = (OFF-ON-OFF). RATE = 0 (GEN1,2 mode): set switches (6-5-4) = (ON-OFF-OFF). SW6 – SD_TH = F (default signal detect threshold level): set switches (3-2-1) = (OFF-OFF-OFF).
SW6 – LPBK - RES = F (normal operation): set switches (6-5-4) = (OFF-OFF-OFF).
SW8: Set switches to “OFF” position.
SW9: Set switches to “OFF” position.
SW14 – PRSNT = GND (enables the device): set switches to “ON” position.
5. Set the input equalization level.
For external pin mode control of the equalization level:
Set ENSMB = 0 (1kohm to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF). SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected.
Refer to Table 1 for information on the 3 switch settings for the 4 level input.
Example:
Set EQB[1:0] with SW1 for the B bank of inputs (top 2 left inputs of DS80PCI800).
SW1 (6-5-4),(3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQB[1:0] = R,R = 14.6 dB at 4 GHz (level 6).
Set EQA[1:0] with SW11 for the A bank of inputs (bottom 2 left inputs of DS80PCI800).
SW8 (6-5-4),(3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQA[1:0] = R,R = 14.6 dB at 4 GHz (level 6).
The table below is the 16 possible EQ settings when in pin mode.
Level EQA/B[1:0]
6 5 4 3 2 1
1 0, 0
2 0, R
3 0, F
4 0, 1
5 R, 0 OFF
6 R, R OFF
7 R, F OFF
SW1 - EQB[1:0]
SW11 - EQA[1:0] EQ (dB) at 4 GHz
ON
ON
ON
ON
OFF OFF
OFF OFF OFF
OFF OFF OFF OFF OFF 9.9
OFF OFF OFF OFF
10 F, R OFF OFF OFF OFF
11 F, F OFF OFF OFF OFF OFF OFF 24.4
12 F, 1 OFF OFF OFF OFF OFF
13 1, 0 OFF OFF
14 1, R OFF OFF
15 1, F OFF OFF
16 1, 1 OFF OFF
6. Set the output VOD and De-emphasis level.
For external pin mode control for the VOD and De-emphasis level (Gen1&2 only):
Set ENSMB = 0 (1kohm to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF).
SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected.
Refer to Table 1 for information on the 3 switch settings for the 4 level input.
Example:
Set DEMB[1:0] with SW5 for the B bank of outputs (top 2 right outputs of DS80PCI800).
SW5 (6-5-4),(3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMB[1:0] = 0,1 (VOD=1.0V, DE=0 dB).
Set DEMA[1:0] with SW3 for the A bank of outputs (bottom 2 right outputs of DS80PCI800).
SW3 (6-5-4),(3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMA1:0] = 0,1 (VOD=1.0V, DE=0 dB).
The table below is the 16 possible settings of VOD and DE when in pin mode.
In Gen 1/2, the de-emphasis level can be set with the DEMx[1:0] pins, but is not available in Gen 3.
Level DEMA/B[1:0]
6 5 4 3 2 1 VOD (Vp-p) DE (dB)
1 0, 0
2 0, R
3 0, F
4 0, 1
5 R, 0 OFF
6 R, R OFF
7 R, F OFF
8 R ,1 OFF
9 F ,0 OFF OFF OFF
10 F, R OFF OFF OFF OFF
11 F, F OFF OFF OFF OFF OFF OFF 1.2
12 F, 1 OFF OFF OFF OFF OFF
13 1, 0 OFF OFF
14 1, R OFF OFF
15 1, F OFF OFF
16 1, 1 OFF OFF
ON
ON
ON
ON
ON
OFF OFF
OFF OFF OFF
OFF OFF OFF OFF OFF 0.9
OFF OFF OFF OFF
ON
ON
ON
ON
OFF OFFOFF
ON
ON ON
ON
ON
ON
SW5 - DEMB[1:0]
SW3 - DEMA[1:0]
OFF
OFF OFF
OFF OFF OFF OFF 1.1
OFF OFF OFF
ON ON
ON
ON
ON
OFF
OFF OFF OFF 31.4
OFF OFF
ON
ON
ON
OFF
OFF OFF OFF 1.3
OFF OFF
OFF OFF 18.0
ON
OFF OFF27.4
ON
OFF OFF0.8
ON
OFF OFF1.0
ON
OFF OFF1.1
ON
OFF OFF1.3
ON
For SMBUS mode control of the EQ, VOD and De-emphasis level:
Set ENSMB = 1 (1kohm to VIH) by using the SW2 (3-2-1) = (OFF-OFF-ON). Set SW4 pin1,2 to the ON position so the SMBUS signals are connected.
Set SW3 pin1 thru pin6 switches to the OFF position so they do not connect to the SDA and SCL line.
Set the SW1 and SW5 for the AD[3:0] pins. AD[3:0]=0000 sets device slave address = B0’hex.
Connect SDA, SCL and GND to J17. Please refer to datasheet for register map for EQ, VOD and DEM.
PIN MODE SETTINGS:
SW1 - EQB0, EQB1
SW2 - ENSMB = 1K TO GND
SW3 - DEMA0, DEMA1
SW4 - OFF POSITION
SW5 - DEMB0, DEMB1
SW6 - SD_TH, RES
SW7 - ON (GND) FOR 3.3V
SW8 - RD_EN2-4=ON (SD_TH)
SW9 - OFF POSTION
SW10 - RXDET, RATE
SW11 - EQA0, EQA1
SW12 - OFF POSITION
SW13 - OFF POSITION
SW14 - PRSNT2_4=ON
SMBUS SLAVE MODE SETTINGS:
SW1 - AD3, AD2
SW2 - ENSMB = 1K TO VDD
SW3 - OFF POSTION
SW4 - ON POSTION (SDA, SCL)
SW5 - AD1, AD0
SW6 - SD_TH, RES
SW7 - ON (GND) FOR 3.3V
SW8 - RD_EN2-4=ON (SD_TH)
SW9 - OFF POSTION
SW10 - RXDET, RATE
SW11 - EQA0, EQA1
SW12 - OFF POSITION WHEN USING SPA BOARD
SW13 - OFF POSTION
SW14 - PRSNT2_4=ON
SMBUS MASTER (READ EEPROM) MODE SETTINGS:
SW1 - AD3, AD2
SW2 - ENSMB = FLOAT
SW3 - OFF POSTION
SW4 - ON POSTION (SDA, SCL)
SW5 - AD1, AD0
SW6 - OFF POSITION
SW7 - ON (GND) FOR 3.3V
SW8 - SD_TH=ON, RD_EN2-4=OFF
SW9 - ON POSTION (ALL_DONE TO RD_EN, ALL_DONE4 TO PRSNT)
SW10 - RXDET, RATE
SW11 - EQA0, EQA1
SW12 - OFF POSITION
SW13 - GND TO START THE READ PROCESS
SW14 - OFF POSITION
Title
PCIE16X_800EVK
SizeDocument NumberRev
DS80PCI800 PCIE 16X CARD PAGE 2A
B
of
5
4
3
2
Date:Sheet
11Thursday, January 06, 2011
1
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