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June 2004 Connectivity Solutions
SCPS081
IMPORTANT NOTICE
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Products Applications
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Contents
Section Title Page
1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Controller Functional Description 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 PCI7621 Controller 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 PCI7421 Controller 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 PCI7611 Controller 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 PCI7411 Controller 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.5 Multifunctional Terminals 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.6 PCI Bus Power Management 1−3. . . . . . . . . . . . . . . . . . . . . . . . .
1.1.7 Power Switch Interface 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Trademarks 1−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terms and Definitions 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Ordering Information 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Detailed Terminal Descriptions 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Power Supply Sequencing 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 I/O Characteristics 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Clamping Voltages 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Component Interconnect (PCI) Interface 3−2. . . . . . . . . . . . . .
3.4.1 1394 PCI Bus Master 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Device Resets 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Serial EEPROM I
3.4.4 Functions 0 and 1 (CardBus) Subsystem Identification 3−4. . .
3.4.5 Function 2 (OHCI 1394) Subsystem Identification 3−5. . . . . . .
3.4.6 Function 3 (Flash Media) Subsystem Identification 3−5. . . . . .
3.4.7 Function 4 (SD Host) Subsystem Identification 3−5. . . . . . . . . .
3.4.8 Function 5 (Smart Card) Subsystem Identification 3−5. . . . . . .
3.5 PC Card Applications 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 PC Card Insertion/Removal and Recognition 3−6. . . . . . . . . . .
3.5.2 Low Voltage CardBus Card Detection 3−6. . . . . . . . . . . . . . . . .
3.5.3 UltraMedia Card Detection 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Flash Media Card Detection 3−7. . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Power Switch Interface 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Internal Ring Oscillator 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 Integrated Pullup Resistors for PC Card Interface 3−9. . . . . . .
2
C Bus 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
Section Title Page
3.5.8 SPKROUT and CAUDPWM Usage 3−9. . . . . . . . . . . . . . . . . . .
3.5.9 LED Socket Activity Indicators 3−9. . . . . . . . . . . . . . . . . . . . . . . .
3.5.10 CardBus Socket Registers 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.11 48-MHz Clock Requirements 3−10. . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Serial EEPROM Interface 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Serial-Bus Interface Implementation 3−11. . . . . . . . . . . . . . . . . . .
3.6.2 Accessing Serial-Bus Devices Through Software 3−11. . . . . . .
3.6.3 Serial-Bus Interface Protocol 3−11. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4 Serial-Bus EEPROM Application 3−13. . . . . . . . . . . . . . . . . . . . . .
3.7 Programmable Interrupt Subsystem 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 PC Card Functional and Card Status Change Interrupts 3−17.
3.7.2 Interrupt Masks and Flags 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Using Parallel IRQ Interrupts 3−19. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Using Parallel PCI Interrupts 3−19. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Using Serialized IRQSER Interrupts 3−20. . . . . . . . . . . . . . . . . . .
3.7.6 SMI Support in the PCI7x21/PCI7x11 Controller 3−20. . . . . . . .
3.8 Power Management Overview 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 1394 Power Management (Function 2) 3−21. . . . . . . . . . . . . . . .
3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) 3−22. . . .
3.8.3 CardBus (Functions 0 and 1) Clock Run Protocol 3−22. . . . . . .
3.8.4 CardBus PC Card Power Management 3−22. . . . . . . . . . . . . . . .
3.8.5 16-Bit PC Card Power Management 3−23. . . . . . . . . . . . . . . . . . .
3.8.6 Suspend Mode 3−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.7 Requirements for Suspend Mode 3−23. . . . . . . . . . . . . . . . . . . . .
3.8.8 Ring Indicate 3−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.9 PCI Power Management 3−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.9.1 CardBus Power Management
(Functions 0 and 1) 3−25. . . . . . . . . . . . . . . . . . . . . .
3.8.9.2 OHCI 1394 (Function 2)
Power Management 3−26. . . . . . . . . . . . . . . . . . . . . .
3.8.9.3 Flash Media (Function 3)
Power Management 3−26. . . . . . . . . . . . . . . . . . . . . .
3.8.9.4 SD Host (Function 4)
Power Management 3−26. . . . . . . . . . . . . . . . . . . . . .
3.8.9.5 Smart Card (Function 5)
Power Management 3−26. . . . . . . . . . . . . . . . . . . . . .
3.8.10 CardBus Bridge Power Management 3−26. . . . . . . . . . . . . . . . . .
3.8.11 ACPI Support 3−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.12 Master List of PME Context Bits and Global Reset-Only
Bits 3−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 IEEE 1394 Application Information 3−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1 PHY Port Cable Connection 3−30. . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Crystal Selection 3−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.3 Bus Reset 3−32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Section Title Page
4 PC Card Controller Programming Model 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Configuration Register Map (Functions 0 and 1) 4−1. . . . . . . . . . . . .
4.2 Vendor ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Device ID Register Functions 0 and 1 4−3. . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Command Register 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Status Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Revision ID Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Class Code Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Cache Line Size Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Latency Timer Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket Registers/ExCA Base Address Register 4−8. . . . . . . . .
4.13 Capability Pointer Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 CardBus Memory Base Registers 0, 1 4−11. . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 CardBus Memory Limit Registers 0, 1 4−12. . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 CardBus I/O Base Registers 0, 1 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 CardBus I/O Limit Registers 0, 1 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register 4−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register 4−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register 4−17. . . . . . . . .
4.29 System Control Register 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 MC_CD Debounce Register 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 General Control Register 4−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 General-Purpose Event Status Register 4−23. . . . . . . . . . . . . . . . . . . . . . . .
4.33 General-Purpose Event Enable Register 4−24. . . . . . . . . . . . . . . . . . . . . . .
4.34 General-Purpose Input Register 4−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 General-Purpose Output Register 4−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.36 Multifunction Routing Status Register 4−26. . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 Retry Status Register 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 Card Control Register 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 Device Control Register 4−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 Diagnostic Register 4−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 Capability ID Register 4−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
Section Title Page
4.42 Next Item Pointer Register 4−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.43 Power Management Capabilities Register 4−32. . . . . . . . . . . . . . . . . . . . . .
4.44 Power Management Control/Status Register 4−33. . . . . . . . . . . . . . . . . . . .
4.45 Power Management Control/Status Bridge Support Extensions
Register 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 Power-Management Data Register 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Serial Bus Data Register 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Serial Bus Index Register 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.49 Serial Bus Slave Address Register 4−36. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.50 Serial Bus Control/Status Register 4−37. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 ExCA Compatibility Registers (Functions 0 and 1) 5−1. . . . . . . . . . . . . . . . . .
5.1 ExCA Identification and Revision Register 5−5. . . . . . . . . . . . . . . . . . . . . .
5.2 ExCA Interface Status Register 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 ExCA Power Control Register 5−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ExCA Interrupt and General Control Register 5−8. . . . . . . . . . . . . . . . . . .
5.5 ExCA Card Status-Change Register 5−9. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ExCA Card Status-Change Interrupt Configuration Register 5−10. . . . . . .
5.7 ExCA Address Window Enable Register 5−11. . . . . . . . . . . . . . . . . . . . . . . .
5.8 ExCA I/O Window Control Register 5−12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5−13. . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5−13. . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5−14. . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5−14. . . .
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers 5−15. . .
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers 5−16. . .
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers 5−17. . . .
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers 5−18. . .
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers 5−19. .
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers 5−20.
5.19 ExCA Card Detect and General Control Register 5−21. . . . . . . . . . . . . . . .
5.20 ExCA Global Control Register 5−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5−23. . .
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5−23. . .
5.23 ExCA Memory Windows 0−4 Page Registers 5−24. . . . . . . . . . . . . . . . . . .
6 CardBus Socket Registers (Functions 0 and 1) 6−1. . . . . . . . . . . . . . . . . . . . . .
6.1 Socket Event Register 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Socket Mask Register 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Socket Present State Register 6−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Socket Force Event Register 6−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Socket Control Register 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Socket Power Management Register 6−8. . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
Section Title Page
7 OHCI Controller Programming Model 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Vendor ID Register 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Device ID Register 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Command Register 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Status Register 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Class Code and Revision ID Register 7−5. . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 Latency Timer and Class Cache Line Size Register 7−5. . . . . . . . . . . . . .
7.7 Header Type and BIST Register 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 OHCI Base Address Register 7−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 TI Extension Base Address Register 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 CardBus CIS Base Address Register 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 CardBus CIS Pointer Register 7−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Subsystem Identification Register 7−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Power Management Capabilities Pointer Register 7−9. . . . . . . . . . . . . . .
7.14 Interrupt Line Register 7−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 Interrupt Pin Register 7−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.16 Minimum Grant and Maximum Latency Register 7−11. . . . . . . . . . . . . . . . .
7.17 OHCI Control Register 7−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18 Capability ID and Next Item Pointer Registers 7−12. . . . . . . . . . . . . . . . . . .
7.19 Power Management Capabilities Register 7−13. . . . . . . . . . . . . . . . . . . . . .
7.20 Power Management Control and Status Register 7−14. . . . . . . . . . . . . . . .
7.21 Power Management Extension Registers 7−14. . . . . . . . . . . . . . . . . . . . . . .
7.22 PCI PHY Control Register 7−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.23 PCI Miscellaneous Configuration Register 7−16. . . . . . . . . . . . . . . . . . . . . .
7.24 Link Enhancement Control Register 7−17. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.25 Subsystem Access Register 7−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.26 GPIO Control Register 7−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 OHCI Registers 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 OHCI Version Register 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 GUID ROM Register 8−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Asynchronous Transmit Retries Register 8−6. . . . . . . . . . . . . . . . . . . . . . .
8.4 CSR Data Register 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 CSR Compare Register 8−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6 CSR Control Register 8−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7 Configuration ROM Header Register 8−8. . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8 Bus Identification Register 8−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9 Bus Options Register 8−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.10 GUID High Register 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.11 GUID Low Register 8−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.12 Configuration ROM Mapping Register 8−11. . . . . . . . . . . . . . . . . . . . . . . . . .
8.13 Posted Write Address Low Register 8−11. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.14 Posted Write Address High Register 8−12. . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
Section Title Page
8.15 Vendor ID Register 8−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.16 Host Controller Control Register 8−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.17 Self-ID Buffer Pointer Register 8−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.18 Self-ID Count Register 8−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.19 Isochronous Receive Channel Mask High Register 8−16. . . . . . . . . . . . . .
8.20 Isochronous Receive Channel Mask Low Register 8−17. . . . . . . . . . . . . . .
8.21 Interrupt Event Register 8−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.22 Interrupt Mask Register 8−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.23 Isochronous Transmit Interrupt Event Register 8−22. . . . . . . . . . . . . . . . . .
8.24 Isochronous Transmit Interrupt Mask Register 8−23. . . . . . . . . . . . . . . . . . .
8.25 Isochronous Receive Interrupt Event Register 8−24. . . . . . . . . . . . . . . . . . .
8.26 Isochronous Receive Interrupt Mask Register 8−25. . . . . . . . . . . . . . . . . . .
8.27 Initial Bandwidth Available Register 8−25. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.28 Initial Channels Available High Register 8−26. . . . . . . . . . . . . . . . . . . . . . . .
8.29 Initial Channels Available Low Register 8−26. . . . . . . . . . . . . . . . . . . . . . . . .
8.30 Fairness Control Register 8−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.31 Link Control Register 8−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.32 Node Identification Register 8−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.33 PHY Layer Control Register 8−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.34 Isochronous Cycle Timer Register 8−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.35 Asynchronous Request Filter High Register 8−32. . . . . . . . . . . . . . . . . . . . .
8.36 Asynchronous Request Filter Low Register 8−34. . . . . . . . . . . . . . . . . . . . .
8.37 Physical Request Filter High Register 8−35. . . . . . . . . . . . . . . . . . . . . . . . . .
8.38 Physical Request Filter Low Register 8−37. . . . . . . . . . . . . . . . . . . . . . . . . .
8.39 Physical Upper Bound Register (Optional Register) 8−37. . . . . . . . . . . . . .
8.40 Asynchronous Context Control Register 8−38. . . . . . . . . . . . . . . . . . . . . . . .
8.41 Asynchronous Context Command Pointer Register 8−39. . . . . . . . . . . . . .
8.42 Isochronous Transmit Context Control Register 8−40. . . . . . . . . . . . . . . . . .
8.43 Isochronous Transmit Context Command Pointer Register 8−41. . . . . . . .
8.44 Isochronous Receive Context Control Register 8−41. . . . . . . . . . . . . . . . . .
8.45 Isochronous Receive Context Command Pointer Register 8−43. . . . . . . .
8.46 Isochronous Receive Context Match Register 8−44. . . . . . . . . . . . . . . . . . .
9 TI Extension Registers 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 DV and MPEG2 Timestamp Enhancements 9−1. . . . . . . . . . . . . . . . . . . . .
9.2 Isochronous Receive Digital Video Enhancements 9−2. . . . . . . . . . . . . . .
9.3 Isochronous Receive Digital Video Enhancements Register 9−2. . . . . . .
9.4 Link Enhancement Register 9−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 Timestamp Offset Register 9−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 PHY Register Configuration 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1 Base Registers 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 Port Status Register 10−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Vendor Identification Register 10−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
Section Title Page
10.4 Vendor-Dependent Register 10−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 Power-Class Programming 10−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Flash Media Controller Programming Model 11−1. . . . . . . . . . . . . . . . . . . . . . . .
11.1 Vendor ID Register 11−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 Device ID Register 11−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 Command Register 11−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4 Status Register 11−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5 Class Code and Revision ID Register 11−5. . . . . . . . . . . . . . . . . . . . . . . . . .
11.6 Latency Timer and Class Cache Line Size Register 11−5. . . . . . . . . . . . . .
11.7 Header Type and BIST Register 11−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8 Flash Media Base Address Register 11−6. . . . . . . . . . . . . . . . . . . . . . . . . . .
11.9 Subsystem Vendor Identification Register 11−7. . . . . . . . . . . . . . . . . . . . . . .
11.10 Subsystem Identification Register 11−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.11 Capabilities Pointer Register 11−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.12 Interrupt Line Register 11−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.13 Interrupt Pin Register 11−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.14 Minimum Grant Register 11−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.15 Maximum Latency Register 11−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.16 Capability ID and Next Item Pointer Registers 11−10. . . . . . . . . . . . . . . . .
11.17 Power Management Capabilities Register 11−11. . . . . . . . . . . . . . . . . . . .
11.18 Power Management Control and Status Register 11−12. . . . . . . . . . . . . .
11.19 Power Management Bridge Support Extension Register 11−12. . . . . . . .
11.20 Power Management Data Register 11−13. . . . . . . . . . . . . . . . . . . . . . . . . .
11.21 General Control Register 11−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.22 Subsystem Access Register 11−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.23 Diagnostic Register 11−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 SD Host Controller Programming Model 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 Vendor ID Register 12−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Device ID Register 12−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Command Register 12−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 Status Register 12−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 Class Code and Revision ID Register 12−5. . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 Latency Timer and Class Cache Line Size Register 12−6. . . . . . . . . . . . . .
12.7 Header Type and BIST Register 12−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.8 SD Host Base Address Register 12−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.9 Subsystem Vendor Identification Register 12−7. . . . . . . . . . . . . . . . . . . . . . .
12.10 Subsystem Identification Register 12−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.11 Capabilities Pointer Register 12−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.12 Interrupt Line Register 12−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.13 Interrupt Pin Register 12−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.14 Minimum Grant Register 12−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.15 Maximum Latency Register 12−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
Section Title Page
12.16 Slot Information Register 12−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.17 Capability ID and Next Item Pointer Registers 12−11. . . . . . . . . . . . . . . . .
12.18 Power Management Capabilities Register 12−12. . . . . . . . . . . . . . . . . . . .
12.19 Power Management Control and Status Register 12−13. . . . . . . . . . . . . .
12.20 Power Management Bridge Support Extension Register 12−13. . . . . . . .
12.21 Power Management Data Register 12−14. . . . . . . . . . . . . . . . . . . . . . . . . .
12.22 General Control Register 12−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.23 Subsystem Access Register 12−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.24 Diagnostic Register 12−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.25 Slot 0 3.3-V Maximum Current Register 12−16. . . . . . . . . . . . . . . . . . . . . .
12.26 Slot 1 3.3-V Maximum Current Register 12−16. . . . . . . . . . . . . . . . . . . . . .
12.27 Slot 2 3.3-V Maximum Current Register 12−16. . . . . . . . . . . . . . . . . . . . . .
12.28 Slot 3 3.3-V Maximum Current Register 12−17. . . . . . . . . . . . . . . . . . . . . .
12.29 Slot 4 3.3-V Maximum Current Register 12−17. . . . . . . . . . . . . . . . . . . . . .
12.30 Slot 5 3.3-V Maximum Current Register 12−17. . . . . . . . . . . . . . . . . . . . . .
13 Smart Card Controller Programming Model 13−1. . . . . . . . . . . . . . . . . . . . . . . . .
13.1 Vendor ID Register 13−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 Device ID Register 13−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Command Register 13−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 Status Register 13−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.5 Class Code and Revision ID Register 13−5. . . . . . . . . . . . . . . . . . . . . . . . . .
13.6 Latency Timer and Class Cache Line Size Register 13−5. . . . . . . . . . . . . .
13.7 Header Type and BIST Register 13−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8 Smart Card Base Address Register 0 13−6. . . . . . . . . . . . . . . . . . . . . . . . . .
13.9 Smart Card Base Address Register 1−4 13−7. . . . . . . . . . . . . . . . . . . . . . . .
13.10 Subsystem Vendor Identification Register 13−7. . . . . . . . . . . . . . . . . . . . . . .
13.11 Subsystem Identification Register 13−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.12 Capabilities Pointer Register 13−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.13 Interrupt Line Register 13−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.14 Interrupt Pin Register 13−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.15 Minimum Grant Register 13−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.16 Maximum Latency Register 13−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.17 Capability ID and Next Item Pointer Registers 13−10. . . . . . . . . . . . . . . . .
13.18 Power Management Capabilities Register 13−11. . . . . . . . . . . . . . . . . . . .
13.19 Power Management Control and Status Register 13−12. . . . . . . . . . . . . .
13.20 Power Management Bridge Support Extension Register 13−12. . . . . . . .
13.21 Power Management Data Register 13−13. . . . . . . . . . . . . . . . . . . . . . . . . .
13.22 General Control Register 13−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.23 Subsystem ID Alias Register 13−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.24 Class Code Alias Register 13−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.25 Smart Card Configuration 1 Register 13−15. . . . . . . . . . . . . . . . . . . . . . . . .
13.26 Smart Card Configuration 2 Register 13−17. . . . . . . . . . . . . . . . . . . . . . . . .
x
Section Title Page
14 Electrical Characteristics 14−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1 Absolute Maximum Ratings Over Operating Temperature Ranges 14−1.
14.2 Recommended Operating Conditions 14−1. . . . . . . . . . . . . . . . . . . . . . . . . .
14.3 Electrical Characteristics Over Recommended Operating
Conditions 14−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4 Electrical Characteristics Over Recommended Ranges of Operating
Conditions 14−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.1 Device 14−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.2 Driver 14−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.4.3 Receiver 14−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges
of Supply Voltage and Operating Free-Air Temperature 14−6. . . . . . . . . . .
14.6 Switching Characteristics for PHY Port Interface 14−6. . . . . . . . . . . . . . . . .
14.7 Operating, Timing, and Switching Characteristics of XI 14−6. . . . . . . . . . .
14.8 PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature 14−6. . . . . . . . . . . . . . . . . . . .
15 Mechanical Information 15−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
List of Illustrations
Figure Title Page
2−1 PCI7621 GHK/ZHK-Package Terminal Diagram 2−1. . . . . . . . . . . . . . . . . . . . .
2−2 PCI7421 GHK/ZHK-Package Terminal Diagram 2−2. . . . . . . . . . . . . . . . . . . . .
2−3 PCI7611 GHK/ZHK-Package Terminal Diagram 2−3. . . . . . . . . . . . . . . . . . . . .
2−4 PCI7411 GHK/ZHK-Package Terminal Diagram 2−4. . . . . . . . . . . . . . . . . . . . .
3−1 PCI7x21/PCI7x11 System Block Diagram 3−1. . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 3-State Bidirectional Buffer 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 PCI Reset Requirement 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Serial ROM Application 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 SPKROUT Connection to Speaker Driver 3−9. . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Two Sample LED Circuits 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Serial-Bus Start/Stop Conditions and Bit Transfers 3−12. . . . . . . . . . . . . . . . . .
3−8 Serial-Bus Protocol Acknowledge 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Serial-Bus Protocol—Byte Write 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Serial-Bus Protocol—Byte Read 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 EEPROM Interface Doubleword Data Collection 3−13. . . . . . . . . . . . . . . . . . . .
3−12 IRQ Implementation 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 System Diagram Implementing CardBus Device Class Power
Management 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 Signal Diagram of Suspend Function 3−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 RI_OUT
3−16 Block Diagram of a Status/Enable Cell 3−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 TP Cable Connections 3−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 Typical Compliant DC Isolated Outer Shield Termination 3−30. . . . . . . . . . . . .
3−19 Non-DC Isolated Outer Shield Termination 3−31. . . . . . . . . . . . . . . . . . . . . . . . .
3−20 Load Capacitance for the PCI7x21/PCI7x11 PHY 3−32. . . . . . . . . . . . . . . . . . .
3−21 Recommended Crystal and Capacitor Layout 3−32. . . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Register Access Through I/O 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Register Access Through Memory 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Accessing CardBus Socket Registers Through PCI Memory 6−1. . . . . . . . . .
14−1 Test Load Diagram 14−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Diagram 3−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
List of Tables
Table Title Page
1−1 Terms and Definitions 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 Signal Names by GHK Terminal Number 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 CardBus PC Card Signal Names Sorted Alphabetically 2−9. . . . . . . . . . . . . .
2−3 16-Bit PC Card Signal Names Sorted Alphabetically 2−11. . . . . . . . . . . . . . . . .
2−4 Power Supply Terminals 2−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 PC Card Power Switch Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 PCI System Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 PCI Address and Data Terminals 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 PCI Interface Control Terminals 2−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Multifunction and Miscellaneous Terminals 2−18. . . . . . . . . . . . . . . . . . . . . . . . .
2−10 16-Bit PC Card Address and Data Terminals 2−19. . . . . . . . . . . . . . . . . . . . . . .
2−11 16-Bit PC Card Interface Control Terminals 2−20. . . . . . . . . . . . . . . . . . . . . . . . .
2−12 CardBus PC Card Interface System Terminals 2−22. . . . . . . . . . . . . . . . . . . . . .
2−13 CardBus PC Card Address and Data Terminals 2−23. . . . . . . . . . . . . . . . . . . . .
2−14 CardBus PC Card Interface Control Terminals 2−24. . . . . . . . . . . . . . . . . . . . . .
2−15 IEEE 1394 Physical Layer Terminals 2−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 SD/MMC Terminals 2−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 Memory Stick/PRO Terminals 2−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−18 Smart Media/XD Terminals 2−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−19 Smart Card Terminals 2−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PCI Bus Support 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 PC Card—Card Detect and Voltage Sense Connections 3−7. . . . . . . . . . . . .
3−3 TPS2228 Control Logic—xVPP/VCORE 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 TPS2228 Control Logic—xVCC 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 TPS2226 Control Logic—xVPP 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 TPS2226 Control Logic—xVCC 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 CardBus Socket Registers 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 PCI7x21/PCI7x11 Registers Used to Program Serial-Bus Devices 3−11. . . . .
3−9 EEPROM Loading Map 3−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Interrupt Mask and Flag Registers 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 PC Card Interrupt Events and Description 3−18. . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Interrupt Pin Register Cross Reference 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 SMI Control 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 Requirements for Internal/External 1.5-V Core Power Supply 3−22. . . . . . . . .
3−15 Power-Management Registers 3−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 Function 2 Power-Management Registers 3−26. . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 Function 3 Power-Management Registers 3−26. . . . . . . . . . . . . . . . . . . . . . . . . .
xiii
Table Title Page
3−18 Function 4 Power-Management Registers 3−26. . . . . . . . . . . . . . . . . . . . . . . . . .
3−19 Function 5 Power-Management Registers 3−26. . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Bit Field Access Tag Descriptions 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Functions 0 and 1 PCI Configuration Register Map 4−1. . . . . . . . . . . . . . . . . .
4−3 Command Register Description 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Status Register Description 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Secondary Status Register Description 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Interrupt Pin Register Cross Reference 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Bridge Control Register Description 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 System Control Register Description 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 General Control Register Description 4−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 General-Purpose Event Status Register Description 4−23. . . . . . . . . . . . . . . . .
4−11 General-Purpose Event Enable Register Description 4−24. . . . . . . . . . . . . . . .
4−12 General-Purpose Input Register Description 4−24. . . . . . . . . . . . . . . . . . . . . . . .
4−13 General-Purpose Output Register Description 4−25. . . . . . . . . . . . . . . . . . . . . .
4−14 Multifunction Routing Status Register Description 4−26. . . . . . . . . . . . . . . . . . .
4−15 Retry Status Register Description 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 Card Control Register Description 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 Device Control Register Description 4−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 Diagnostic Register Description 4−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 Power Management Capabilities Register Description 4−32. . . . . . . . . . . . . . .
4−20 Power Management Control/Status Register Description 4−33. . . . . . . . . . . . .
4−21 Power Management Control/Status Bridge Support Extensions Register
Description 4−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 Serial Bus Data Register Description 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−23 Serial Bus Index Register Description 4−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 Serial Bus Slave Address Register Description 4−36. . . . . . . . . . . . . . . . . . . . .
4−25 Serial Bus Control/Status Register Description 4−37. . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Registers and Offsets 5−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Identification and Revision Register Description 5−5. . . . . . . . . . . . . . .
5−3 ExCA Interface Status Register Description 5−6. . . . . . . . . . . . . . . . . . . . . . . .
5−4 ExCA Power Control Register Description—82365SL Support 5−7. . . . . . . .
5−5 ExCA Power Control Register Description—82365SL-DF Support 5−7. . . . .
5−6 ExCA Interrupt and General Control Register Description 5−8. . . . . . . . . . . .
5−7 ExCA Card Status-Change Register Description 5−9. . . . . . . . . . . . . . . . . . . .
5−8 ExCA Card Status-Change Interrupt Configuration Register
Description 5−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 ExCA Address Window Enable Register Description 5−11. . . . . . . . . . . . . . . .
5−10 ExCA I/O Window Control Register Description 5−12. . . . . . . . . . . . . . . . . . . . .
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
Description 5−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers
Description 5−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiv
Table Title Page
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
Description 5−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 ExCA Card Detect and General Control Register Description 5−21. . . . . . . . .
5−15 ExCA Global Control Register Description 5−22. . . . . . . . . . . . . . . . . . . . . . . . .
6−1 CardBus Socket Registers 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Socket Event Register Description 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Socket Mask Register Description 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Socket Present State Register Description 6−4. . . . . . . . . . . . . . . . . . . . . . . . .
6−5 Socket Force Event Register Description 6−6. . . . . . . . . . . . . . . . . . . . . . . . . .
6−6 Socket Control Register Description 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7 Socket Power Management Register Description 6−8. . . . . . . . . . . . . . . . . . .
7−1 Function 2 Configuration Register Map 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2 Command Register Description 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 Status Register Description 7−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4 Class Code and Revision ID Register Description 7−5. . . . . . . . . . . . . . . . . . .
7−5 Latency Timer and Class Cache Line Size Register Description 7−5. . . . . . .
7−6 Header Type and BIST Register Description 7−6. . . . . . . . . . . . . . . . . . . . . . . .
7−7 OHCI Base Address Register Description 7−6. . . . . . . . . . . . . . . . . . . . . . . . . .
7−8 TI Base Address Register Description 7−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−9 CardBus CIS Base Address Register Description 7−8. . . . . . . . . . . . . . . . . . .
7−10 Subsystem Identification Register Description 7−9. . . . . . . . . . . . . . . . . . . . . .
7−11 Interrupt Line Register Description 7−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−12 PCI Interrupt Pin Register—Read-Only INTPIN Per Function 7−10. . . . . . . . .
7−13 Minimum Grant and Maximum Latency Register Description 7−11. . . . . . . . .
7−14 OHCI Control Register Description 7−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−15 Capability ID and Next Item Pointer Registers Description 7−12. . . . . . . . . . . .
7−16 Power Management Capabilities Register Description 7−13. . . . . . . . . . . . . . .
7−17 Power Management Control and Status Register Description 7−14. . . . . . . . .
7−18 Power Management Extension Registers Description 7−14. . . . . . . . . . . . . . . .
7−19 PCI PHY Control Register Description 7−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−20 PCI Miscellaneous Configuration Register Description 7−16. . . . . . . . . . . . . . .
7−21 Link Enhancement Control Register Description 7−17. . . . . . . . . . . . . . . . . . . .
7−22 Subsystem Access Register Description 7−18. . . . . . . . . . . . . . . . . . . . . . . . . . .
8−1 OHCI Register Map 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−2 OHCI Version Register Description 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−3 GUID ROM Register Description 8−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−4 Asynchronous Transmit Retries Register Description 8−6. . . . . . . . . . . . . . . .
8−5 CSR Control Register Description 8−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−6 Configuration ROM Header Register Description 8−8. . . . . . . . . . . . . . . . . . . .
8−7 Bus Options Register Description 8−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−8 Configuration ROM Mapping Register Description 8−11. . . . . . . . . . . . . . . . . . .
8−9 Posted Write Address Low Register Description 8−11. . . . . . . . . . . . . . . . . . . .
8−10 Posted Write Address High Register Description 8−12. . . . . . . . . . . . . . . . . . . .
xv
Table Title Page
8−11 Host Controller Control Register Description 8−13. . . . . . . . . . . . . . . . . . . . . . . .
8−12 Self-ID Count Register Description 8−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−13 Isochronous Receive Channel Mask High Register Description 8−16. . . . . . .
8−14 Isochronous Receive Channel Mask Low Register Description 8−17. . . . . . . .
8−15 Interrupt Event Register Description 8−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−16 Interrupt Mask Register Description 8−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−17 Isochronous Transmit Interrupt Event Register Description 8−22. . . . . . . . . . .
8−18 Isochronous Receive Interrupt Event Register Description 8−24. . . . . . . . . . .
8−19 Initial Bandwidth Available Register Description 8−25. . . . . . . . . . . . . . . . . . . . .
8−20 Initial Channels Available High Register Description 8−26. . . . . . . . . . . . . . . . .
8−21 Initial Channels Available Low Register Description 8−26. . . . . . . . . . . . . . . . .
8−22 Fairness Control Register Description 8−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−23 Link Control Register Description 8−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−24 Node Identification Register Description 8−29. . . . . . . . . . . . . . . . . . . . . . . . . . .
8−25 PHY Control Register Description 8−30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−26 Isochronous Cycle Timer Register Description 8−31. . . . . . . . . . . . . . . . . . . . . .
8−27 Asynchronous Request Filter High Register Description 8−32. . . . . . . . . . . . .
8−28 Asynchronous Request Filter Low Register Description 8−34. . . . . . . . . . . . . .
8−29 Physical Request Filter High Register Description 8−35. . . . . . . . . . . . . . . . . . .
8−30 Physical Request Filter Low Register Description 8−37. . . . . . . . . . . . . . . . . . .
8−31 Asynchronous Context Control Register Description 8−38. . . . . . . . . . . . . . . . .
8−32 Asynchronous Context Command Pointer Register Description 8−39. . . . . . .
8−33 Isochronous Transmit Context Control Register Description 8−40. . . . . . . . . .
8−34 Isochronous Receive Context Control Register Description 8−41. . . . . . . . . . .
8−35 Isochronous Receive Context Match Register Description 8−44. . . . . . . . . . . .
9−1 TI Extension Register Map 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−2 Isochronous Receive Digital Video Enhancements Register
Description 9−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9−3 Link Enhancement Register Description 9−4. . . . . . . . . . . . . . . . . . . . . . . . . . .
9−4 Timestamp Offset Register Description 9−5. . . . . . . . . . . . . . . . . . . . . . . . . . . .
10−1 Base Register Configuration 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10−2 Base Register Field Descriptions 10−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10−3 Page 0 (Port Status) Register Configuration 10−4. . . . . . . . . . . . . . . . . . . . . . . .
10−4 Page 0 (Port Status) Register Field Descriptions 10−4. . . . . . . . . . . . . . . . . . . .
10−5 Page 1 (Vendor ID) Register Configuration 10−5. . . . . . . . . . . . . . . . . . . . . . . . .
10−6 Page 1 (Vendor ID) Register Field Descriptions 10−5. . . . . . . . . . . . . . . . . . . . .
10−7 Page 7 (Vendor-Dependent) Register Configuration 10−6. . . . . . . . . . . . . . . . .
10−8 Page 7 (Vendor-Dependent) Register Field Descriptions 10−6. . . . . . . . . . . . .
10−9 Power Class Descriptions 10−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−1 Function 3 Configuration Register Map 11−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−2 Command Register Description 11−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−3 Status Register Description 11−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−4 Class Code and Revision ID Register Description 11−5. . . . . . . . . . . . . . . . . . .
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Table Title Page
11−5 Latency Timer and Class Cache Line Size Register Description 11−5. . . . . . .
11−6 Header Type and BIST Register Description 11−6. . . . . . . . . . . . . . . . . . . . . . . .
11−7 Flash Media Base Address Register Description 11−6. . . . . . . . . . . . . . . . . . . .
11−8 PCI Interrupt Pin Register 11−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−9 Minimum Grant Register Description 11−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−10 Maximum Latency Register Description 11−9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−11 Capability ID and Next Item Pointer Registers Description 11−10. . . . . . . . . . .
11−12 Power Management Capabilities Register Description 11−11. . . . . . . . . . . . . .
11−13 Power Management Control and Status Register Description 11−12. . . . . . . .
11−14 General Control Register 11−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11−15 Subsystem Access Register Description 11−14. . . . . . . . . . . . . . . . . . . . . . . . . .
11−16 Diagnostic Register Description 11−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−1 Function 4 Configuration Register Map 12−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−2 Command Register Description 12−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−3 Status Register Description 12−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−4 Class Code and Revision ID Register Description 12−5. . . . . . . . . . . . . . . . . . .
12−5 Latency Timer and Class Cache Line Size Register Description 12−6. . . . . . .
12−6 Header Type and BIST Register Description 12−6. . . . . . . . . . . . . . . . . . . . . . . .
12−7 SD host Base Address Register Description 12−7. . . . . . . . . . . . . . . . . . . . . . . .
12−8 PCI Interrupt Pin Register 12−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−9 Minimum Grant Register Description 12−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−10 Maximum Latency Register Description 12−10. . . . . . . . . . . . . . . . . . . . . . . . . . .
12−11 Maximum Latency Register Description 12−10. . . . . . . . . . . . . . . . . . . . . . . . . . .
12−12 Capability ID and Next Item Pointer Registers Description 12−11. . . . . . . . . . .
12−13 Power Management Capabilities Register Description 12−12. . . . . . . . . . . . . .
12−14 Power Management Control and Status Register Description 12−13. . . . . . . .
12−15 General Control Register 12−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12−16 Subsystem Access Register Description 12−15. . . . . . . . . . . . . . . . . . . . . . . . . .
12−17 Diagnostic Register Description 12−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13−1 Function 5 Configuration Register Map 13−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
13−2 Command Register Description 13−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13−3 Status Register Description 13−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13−4 Class Code and Revision ID Register Description 13−5. . . . . . . . . . . . . . . . . . .
13−5 Latency Timer and Class Cache Line Size Register Description 13−5. . . . . . .
13−6 Header Type and BIST Register Description 13−6. . . . . . . . . . . . . . . . . . . . . . . .
13−7 PCI Interrupt Pin Register 13−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13−8 Minimum Grant Register Description 13−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13−9 Maximum Latency Register Description 13−10. . . . . . . . . . . . . . . . . . . . . . . . . . .
13−10 Capability ID and Next Item Pointer Registers Description 13−10. . . . . . . . . . .
13−11 Power Management Capabilities Register Description 13−11. . . . . . . . . . . . . .
13−12 Power Management Control and Status Register Description 13−12. . . . . . . .
13−13 General Control Register 13−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13−14 Subsystem ID Alias Register Description 13−14. . . . . . . . . . . . . . . . . . . . . . . . . .
xvii
Table Title Page
13−15 Smart Card Configuration 1 Register Description 13−16. . . . . . . . . . . . . . . . . . .
13−16 Smart Card Configuration 2 Register Description 13−17. . . . . . . . . . . . . . . . . . .
xviii
1 Introduction
The Texas Instruments PCI7621 controller is an integrated dual-socket UltraMedia PC Card controller, Smart Card
controller, IEEE 1394 open HCI host controller and PHY, and flash media controller. This high-performance integrated
solution provides the latest in PC Card, Smart Card, IEEE 1394, Secure Digital (SD), MultiMediaCard (MMC),
Memory Stick/PRO, SmartMedia, and XD technology.
The Texas Instruments PCI7421 controller is an integrated dual-socket UltraMedia PC Card controller, IEEE 1394
Open HCI host controller and PHY, and flash media controller. This high-performance integrated solution provides
the latest in PC Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and XD technology.
The Texas Instruments PCI7611 controller is an integrated single-socket UltraMedia PC Card controller, Smart Card
controller, IEEE 1394 open HCI host controller and PHY, and flash media controller. This high-performance integrated
solution provides the latest in PC Card, Smart Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and
XD technology.
The Texas Instruments PCI7411 controller is an integrated single-socket UltraMedia PC Card controller, IEEE 1394
open HCI host controller and PHY, and flash media controller. This high-performance integrated solution provides
the latest in PC Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and XD technology.
For the remainder of this document, the PCI7x21 controller refers to the PCI7621 and PCI7421 controllers, and the
PCI7x11 controller refers to the PCI7611 and PCI7411 controllers.
1.1 Controller Functional Description
1.1.1 PCI7621 Controller
The PCI7621 controller is a six-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard (Release
8.1). The PCI7621 controller provides features that make it the best choice for bridging between the PCI bus and PC
Cards, and supports any combination of Smart Card, Flash Media, 16-bit, CardBus, and USB custom card interface
PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7621
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7621 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI7621 controller can be programmed to accept posted writes to improve bus utilization.
Function 2 of the PCI7621 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host
Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible
with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and
accommodate large host bus latencies. The PCI7621 controller provides physical write posting and a highly tuned
physical data path for SBP-2 performance.
Function 3 of the PCI7621 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes DMA
capabilities for improved Flash Media performance.
Function 4 of the PCI7621 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
1−1
Function 5 of the PCI7621 controller is a PCI-based Smart Card controller used for communication with Smart Cards
inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with
many different types of Smart Cards.
1.1.2 PCI7421 Controller
The PCI7421 controller is a five-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard (Release
8.1). The PCI7421 controller provides features that make it the best choice for bridging between the PCI bus and PC
Cards, and supports any combination of Smart Card, Flash Media, 16-bit, CardBus, and USB custom card interface
PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7421
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7421 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI7421 controller can be programmed to accept posted writes to improve bus utilization.
Function 2 of the PCI7421 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host
Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible
with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and
accommodate large host bus latencies. The PCI7421 provides physical write posting and a highly tuned physical data
path for SBP-2 performance.
Function 3 of the PCI7421 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes DMA
capabilities for improved Flash Media performance.
Function 4 of the PCI7421 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
1.1.3 PCI7611 Controller
The PCI7611 controller is a five-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1).
The PCI7611 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards,
and supports Smart Card, Flash Media, 16-bit, CardBus or USB custom card interface PC Cards, powered at 5 V
or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7611
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7611 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI7611 controller can be programmed to accept posted writes to improve bus utilization.
Function 2 of the PCI7611 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host
Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible
with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and
accommodate large host bus latencies. The PCI7611 controller provides physical write posting and a highly tuned
physical data path for SBP-2 performance.
Function 3 of the PCI7611 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
1−2
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes DMA
capabilities for improved Flash Media performance.
Function 4 of the PCI7611 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
Function 5 of the PCI7611 controller is a PCI-based Smart Card controller used for communication with Smart Cards
inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with
many different types of Smart Cards.
1.1.4 PCI7411 Controller
The PCI7411 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.
Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1).
The PCI7411 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards,
and supports Smart Card, Flash Media, 16-bit, CardBus or USB custom card interface PC Cards, powered at 5 V
or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7411
controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7411 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI7411 controller can be programmed to accept posted writes to improve bus utilization.
Function 2 of the PCI7411 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host
Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible
with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and
accommodate large host bus latencies. The PCI7411 controller provides physical write posting and a highly tuned
physical data path for SBP-2 performance.
Function 3 of the PCI7411 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory
Stick-Pro, SmartMedia, XD, SD, and MMC cards. This function controls communication with these Flash Media cards
through a passive PC Card adapter or through a dedicated Flash Media socket. In addition, this function includes DMA
capabilities for improved Flash Media performance.
Function 4 of the PCI7411 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This
function controls communication with these Flash Media cards through a passive PC Card adapter or through a
dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard
Specification and includes both DMA capabilities and support for SD suspend/resume.
1.1.5 Multifunctional Terminals
Various implementation-specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PC/PCI DMA, serial and parallel interrupts,
PC Card activity indicator LEDs, flash media LEDs, and other platform-specific signals. PCI complaint
general-purpose events may be programmed and controlled through the multifunction terminals, and an
ACPI-compliant programming interface is included for the general-purpose inputs and outputs.
1.1.6 PCI Bus Power Management
The PCI7x21/PCI7x11 controller is compliant with the latest PCI Bus Power Management Specification, and provides
several low-power modes, which enable the host power system to further reduce power consumption.
1.1.7 Power Switch Interface
The PCI7x21/PCI7x11 controller also has a three-pin serial interface compatible with the Texas Instruments TPS2228
(default), TPS2226, TPS2224, and TPS2223A power switches. All four power switches provide power to the CardBus
socket(s) on the PCI7x21/PCI7x11 controller. The power to each dedicated socket is controlled through separate
power control pins. Each of these power control pins can be connected to an external 3.3-V power switch.
1−3
1.2 Features
The PCI7x21/PCI7x11 controller supports the following features:
• PC Card Standard 8.1 compliant
• PCI Bus Power Management Interface Specification 1.1 compliant
• Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
• PCI Local Bus Specification Revision 2.3 compliant
• PC 98/99 and PC2001 compliant
• Windows Logo Program 2.0 compliant
• PCI Bus Interface Specification for PCI-to-CardBus Bridges
• Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std
1394a-2000
• Fully compliant with 1394 Open Host Controller Interface Specification 1.1
• 1.5-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.5-V core V
CC
• Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Supports PC Card or CardBus with hot insertion and removal
• Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
• Supports serialized IRQ with PCI interrupts
• Programmable multifunction terminals
• Many interrupt modes supported
• Serial ROM interface for loading subsystem ID and subsystem vendor ID
• ExCA-compatible registers are mapped in memory or I/O space
• Intel 82365SL-DF register compatible
• Supports ring indicate, SUSPEND
, and PCI CLKRUN protocols
• Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
• Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
• Compliant with Intel Mobile Power Guideline 2000
• Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed
concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
• Power-down features to conserve energy in battery-powered applications include: automatic device power
down during suspend, PCI power management for link-layer, and inactive ports powered down,
ultralow-power sleep mode
• Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
• Cable ports monitor line conditions for active connection to remote node
• Cable power presence monitoring
• Separate cable bias (TPBIAS) for each port
• Physical write posting of up to three outstanding transactions
• PCI burst transfers and deep FIFOs to tolerate large host latency
1−4
• External cycle timer control for customized synchronization
• Extended resume signaling for compatibility with legacy DV components
• PHY-Link logic performs system initialization and arbitration functions
• PHY-Link encode and decode functions included for data-strobe bit level encoding
• PHY-Link incoming data resynchronized to local clock
• Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M
bits/s
• Node power class information signaling for system power management
• Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std
1394a-2000 features
• Isochronous receive dual-buffer mode
• Out-of-order pipelining for asynchronous transmit requests
• Register access fail interrupt when the PHY SCLK is not active
• PCI power-management D0, D1, D2, and D3 power states
• Initial bandwidth available and initial channels available registers
• PME
• Advanced submicron, low-power CMOS technology
support per 1394 Open Host Controller Interface Specification
1.3 Related Documents
• Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)
• 1394 Open Host Controller Interface Specification (Release 1.1)
• IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995)
• IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000)
• PC Card Standard (Release 8.1)
• PCI Bus Power Management Interface Specification (Revision 1.1)
• Serial Bus Protocol 2 (SBP-2)
• Serialized IRQ Support for PCI Systems
• PCI Mobile Design Guide
• PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
• PCI14xx Implementation Guide for D3 Wake-Up
• PCI to PCMCIA CardBus Bridge Register Description
• Texas Instruments TPS2224 and TPS2226 product data sheet, SLVS317
• Texas Instruments TPS2223A product data sheet, SLVS428
• Texas Instruments TPS2228 product data sheet, SLVS419
• PCI Local Bus Specification (Revision 2.3)
• PCMCIA Proposal (262)
• The Multimedia Card System Specification, Version 3.31
1−5
• SD Memory Card Specifications, SD Group, March 2000
• Memory Stick Format Specification, Version 2.0 (Memory Stick-Pro)
• ISO Standards for Identification Cards ISO/IEC 7816
• SD Host Controller Standard Specification, rev. 1.0
• Memory Stick Format Specification, Sony Confidential, ver. 2.0
• SmartMedia Standard 2000, May 19, 2000
1.4 Trademarks
Intel is a trademark of Intel Corporation.
TI and MicroStar BGA are trademarks of Texas Instruments.
FireWire is a trademark of Apple Computer, Inc.
i.LINK is a trademark of Sony Corporation of America.
Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.
Other trademarks are the property of their respective owners.
1−6
1.5 Terms and Definitions
Terms and definitions used in this document are given in Table 1−1.
Table 1−1. Terms and Definitions
TERM DEFINITIONS
AT AT (advanced technology, as in PC A T) attachment interface
ATA driver An existing host software component that loads when any flash media adapter and card is inserted into a PC Card
CIS Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host
CSR Control and status register
Flash Media SmartMedia, Memory Stick, MS/PRO, xD, MMC, or SD/MMC Flash operating in an ATA compatible mode
ISO/IEC 7816 The Smart Card standard
Memory Stick A small-form-factor flash interface that is defined, promoted, and licensed by Sony
Memory Stick Pro Memory Stick Version 2.0, same physical dimensions of MS with higher speed data exchange and higher data
MMC MultiMediaCard. Specified by the MMC Association, and scope is encompassed by the SD Flash specification.
OHCI Open host controller interface
PCMCIA Personal Computer Memory Card International Association. Standards body that governs the PC Card standards
RSVD Reserved for future use
SD Flash Secure Digital Flash. Standard governed by the SD Association
Smart Card The name applied to ID cards containing integrated circuits, as defined by ISO/IEC 7816-1
SPI Serial peripheral interface, a general-purpose synchronous serial interface. For more information, see the
SSFDC Solid State Floppy Disk Card. The SSFDC Forum specifies SmartMedia
TI Smart Card driver A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card
UltraMedia De facto industry standard promoted by Texas Instruments that integrates CardBus, Smart Card, Memory Stick,
xD Extreme Digital, small form factor flash based on SmartMedia cards, developed by Fuji Film and Olympus Optical.
socket. This driver is logically attached to a predefined CIS provided by the PCI7x21/PCI7x11 controller when the
adapter and media are both inserted.
computer
capacity than conventional Memory Stick.
Multimedia Card System Specification, version 3.2.
adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI7621 when the
adapter and media are both inserted.
MultiMediaCard/Secure Digital and SmartMedia functionality into one controller.
1.6 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI7621 Dual Socket CardBus and UltraMedia Controller with
Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer
Controller with Dedicated Flash Media Socket
PCI7421 Dual Socket CardBus and UltraMedia Controller with
Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer
Controller with Dedicated Flash Media Socket
PCI7611 Single Socket CardBus and UltraMedia Controller with
Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer
Controller with Dedicated Flash Media Socket
PCI7411 Single Socket CardBus and UltraMedia Controller with
Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer
Controller with Dedicated Flash Media Socket
3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
3.3-V, 5-V tolerant I/Os 288-ball PBGA
(GHK or ZHK)
1−7
1−8
2 Terminal Descriptions
The PCI7x21/PCI7x11 controller is available in the 288-terminal MicroStar BGA package (GHK) or the 288-terminal
lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a pin diagram of the PCI7621
package. Figure 2−2 is a pin diagram of the PCI7421 package. Figure 2−3 is a pin diagram of the PCI7611 package.
Figure 2−4 is a pin diagram of the PCI7411 package.
W
AD30 AD26
V
REQ
U
GRST
T
MFUNC6
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
SUSPEND
MFUNC2 MFUNC4MFUNC3
DATA LATCH
CLK_48
SC_
DATA
SM_PHYS
SM_R/B//
SC_RFU
SD_DAT2
//SM_D6//
SC_GPIO4
VR_
PORT
MS_SDIO
MS_DATA1
(DATA0)//
SD_DAT0//
SM_D0
MC_PWR
MC_PWR
_CTRL_0
A_USB_EN
B_USB_EN
A_CAD31
//A_D10
A_CAD30
//A_D9
A_CSTSCHG
A_CAD27
//A_D0
(STSCHG
A_CAUDIO
AD27
VCCP
AD29
AD31
AD28
RI_OUT
GNT
//PME
PRST
MFUNC0 MFUNC5
SCL
SDA
SC_CD
SC_OC
SC_RST
_WP//
SC_FCB
SD_CMD//
SD_DAT3
SM_ALE//
//SM_D7//
SC_GPIO2
SC_GPIO3
SD_DAT0//
VR_EN
SM_D4//
SC_GPIO6
MS_DATA2
//SD_DAT2
//SD_DAT1
//SM_D2
//SM_D1
MS_BS//
SD_CMD
_CTRL_1
//SM_WE
SD_CD
A_RSVD
A_CAD29
//A_D1
//A_D2
A_CCLKRUN
A_CAD28
//A_WP
//A_D8
(IOIS16
A_CSERR
//A_BVD1
//A_WAIT
/RI)
A_CVS1
//A_BVD2
//A_VS1
(SPKR
)
)
C/BE3
AD24
AD25
A_CINT//
A_READY
(IREQ
A_CAD26
//A_A0
A_CAD25
//A_A1
IDSEL
AD23
AD22
PCLK
MFUNC1
SC_
PWR_
CTRL
SC_CLK
SD_CLK//
SM_RE//
SC_GPIO1
MS_DATA3//
SD_DAT3
//SM_D3
MS_CLK//
SD_CLK//
SM_EL_WP
MS_CD SM_CD
A_CCD2
//A_CD2
A_CC/BE3
//A_REG
)
A_CAD23
//A_A3
VCCA
AD19
AD18
AD17
AD21
AD20
CLOCK
SD_DAT1//
SM_D5//
SC_GPIO5
A_CAD24
//A_A2
A_CAD22
//A_A4
A_CAD21
//A_A5
A_CRST
//A_RESET
C/BE2
FRAME
IRDY
AD16 TRDY
VCC
DEVSEL
VCC GND
SPKROUT
SC_VCC
_5V
SM_CLE//
SC_GPIO0
SD_WP//
SM_CE
GND GND
A_CREQ
//A_INPACK
A_CAD19
A_CFRAME
//A_A25
A_CAD18
A_CIRDY
//A_A7
A_CAD17
A_CTRDY
//A_A24
C/BE1
AD15
AD14
VCCP
AD11
AD10
STOP
PERR
SERR
AD13
PAR
AD12
VCC
VCC
GND
GND GND GND GND
GND
VCC
VCC
VCC
A_CVS2
//A_VS2
//A_A23
//A_A15
//A_A22
A_CC/BE2
A_CDEVSEL
A_CSTOP
GND
VCC
A_CAD20
//A_A6
//A_A12
A_CCLK
//A_A16
//A_A21
A_CGNT
//A_WE
//A_A20
A_CPERR
A_CBLOCK
A_RSVD
A_CC/BE1
A_CAD16
GND GND VCC
GND GND
VCC
A_CPAR
//A_A13
//A_A14
//A_A19
//A_A18
//A_A8
//A_A17
AD9
AD8
C/BE0
AD7
AD6
AD5
AD1
CPS
VCC
A_CAD14
//A_A9
A_CAD15
//A_IOWR
A_CAD13
//A_IORD
A_CAD12
//A_A11
VCCA
AD4
AD3
AD2
PC0
(TEST1)
TEST0
AGND
VCC
VCC
VCC
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD8
//A_D15
A_CAD11
//A_OE
A_CAD10
//A_CE2
A_CAD9
//A_A10
AD0 TPB0N TPA0NR0TPB1N
PC2
TPB0P TPA0PR1TPB1P AVDD TPA1P
(TEST3)
PC1
(TEST2)
AVDD
B_CCD1
//B_CD1
B_CAD3
//B_D5
B_CAD15
//B_IOWR
B_CPAR
//B_A13
B_CIRDY
//B_A15
GND
GND
A_CAD3
//A_D5
A_CAD7
//A_D7
A_RSVD
//A_D14
A_CAD5
//A_D6
AGND
AVDD
VSSPLL
B_CAD8
//B_D15
B_CC/BE1
//B_A8
B_CAD19
//B_A25
B_CSTSCHG
//B_BVD1
(STSCHG
A_CAD0
//A_D3
A_CAD4
//A_D12
A_CAD1
//A_D4
A_CAD2
//A_D11
TPBIAS0
B_CAD13
//B_IORD
B_RSVD
B_CGNT
B_CAD18
B_CAD21
B_CC/BE3
/RI)
B_CAD31
CNA
B_CAD4
//B_D12
B_CAD7
//B_D7
//B_A18
//B_WE
//B_A7
//B_A5
//B_REG
A_CCD1
//A_CD1
//B_D10
B_RSVD
//B_D2
AGND
B_CAD27
//B_D0
B_CAD29
//B_D1
B_CAD30
//B_D9
NC
TPBIAS1
VSSPLL
PHY_
TEST_
MA
B_CAD1
//B_D4
B_RSVD
//B_D14
B_CAD9
//B_A10
B_CAD12
//B_A11
B_CAD16
//B_A17
B_CSTOP
//B_A20
B_CTRDY
//B_A22
B_CAD17
//B_A24
B_CRST
//B_RESET
B_CAD23
//B_A3
B_CAD26
//B_A0
B_CAUDIO
//B_BVD2
(SPKR
B_CCD2
//B_CD2
B_CAD28
//B_D8
VDPLL_
B_CC/BE0
B_CAD14
//B_INPACK
B_CAD24
)
B_CSERR
B_CCLKRUN
TPA1N
15
XI
B_CAD2
//B_D11
B_CAD5
//B_D6
//B_CE1
B_CAD11
//B_OE
//B_A9
B_CPERR
//B_A14
B_CCLK
//B_A16
B_CC/BE2
//B_A12
B_CAD20
//B_A6
B_CREQ
//B_A2
B_CVS1
//B_VS1
//B_WAIT
//B_WP
(IOIS16)
VDPLL_
33
RSVD
XO
B_CAD0
//B_D3
B_CAD6
//B_D13
VR_
PORT
B_CAD10
//B_CE2
VCCB
B_CBLOCK
//B_A19
B_CDEVSEL
//B_A21
B_CFRAME
//B_A23
B_CVS2
//B_VS2
B_CAD22
//B_A4
VCCB
B_CAD25
//B_A1
B_CINT
//B_READY
(IREQ
)
Figure 2−1. PCI7621 GHK/ZHK-Package Terminal Diagram
19151051 14131211 169876432 17 18
2−1
AD27
W
VCCP
C/BE3
IDSEL
AD19
C/BE2
STOP
C/BE1
VCCP
C/BE0
AD0 TPB0N TPA0NR0TPB1N
AD4
NC
TPA1N
AD30 AD26
V
REQ
U
GRST
T
MFUNC6
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
SUSPEND
MFUNC2 MFUNC4MFUNC3
DATA LATCH
CLK_48 SDA
RSVD
SM_PHYS
SM_R/B
SD_DAT2
SD_DAT3
//SM_D6
VR_
VR_EN
PORT
MS_SDIO
MS_DATA1
(DATA0)//
//SD_DAT1
SD_DAT0//
SM_D0
MC_PWR
MC_PWR
_CTRL_0
_CTRL_1
B_USB_EN
A_USB_EN
A_RSVD
A_CAD31
//A_D10
A_CAD30
A_CAD28
//A_D9
A_CSTSCHG
A_CAD27
//A_D0
(STSCHG
A_CAUDIO
AD29
AD31
AD28
RI_OUT
GNT
//PME
PRST
MFUNC0 MFUNC5
SCL
RSVD
RSVD
RSVD
_WP
SD_CMD//
SM_ALE
//SM_D7
SD_DAT0
//SM_D4
MS_DATA2
//SD_DAT2
//SM_D2
//SM_D1
MS_BS//
SD_CMD
//SM_WE
SD_CD
A_CAD29
//A_D1
//A_D2
A_CCLKRUN
//A_WP
//A_D8
(IOIS16)
A_CSERR
//A_BVD1
//A_WAIT
/RI)
A_CVS1
//A_BVD2
//A_VS1
(SPKR
)
AD24
AD25
A_CINT//
A_READY
(IREQ
A_CAD26
//A_A0
A_CAD25
//A_A1
AD23
AD22
PCLK
MFUNC1
RSVD
RSVD
SD_CLK
//SM_RE
MS_DATA3//
SD_DAT3
//SM_D3
MS_CLK//
SD_CLK//
SM_EL_WP
MS_CD SM_CD
A_CCD2
//A_CD2
A_CC/BE3
//A_REG
)
A_CAD23
//A_A3
VCCA
AD18
AD17
AD21
AD20
CLOCK
SD_DAT1
//SM_D5
A_CAD24
//A_A2
A_CAD22
//A_A4
A_CAD21
//A_A5
A_CRST
//A_RESET
FRAME
IRDY
AD16 TRDY
VCC
DEVSEL
VCC
SPKROUT
RSVD
SM_CLE
SD_WP//
SM_CE
GND GND
A_CVS2
A_CREQ
//A_INPACK
//A_VS2
A_CAD19
A_CFRAME
//A_A25
A_CAD18
A_CIRDY
//A_A7
//A_A15
A_CAD17
A_CTRDY
//A_A24
AD15
AD14
AD13
AD11
AD10
AD9
PERR
SERR
PAR
AD12
AD8
VCC
GND
GND
VCC
VCC
VCC
//A_A23
//A_A22
A_CAD20
A_CC/BE2
A_CDEVSEL
A_CGNT
A_CSTOP
VCC
GND GND GND GND
GND
GND GND VCC
GND
GND GND
VCC
VCC
A_CPAR
//A_A6
//A_A13
A_CPERR
//A_A12
//A_A14
A_CCLK
A_CBLOCK
//A_A16
//A_A19
A_RSVD
//A_A18
//A_A21
A_CC/BE1
//A_A8
//A_WE
A_CAD16
//A_A17
//A_A20
AD7
AD6
AD5
AD1
CPS
VCC
A_CAD14
//A_A9
A_CAD15
//A_IOWR
A_CAD13
//A_IORD
A_CAD12
//A_A11
VCCA
AD3
AD2
PC0
(TEST1)
TEST0
AGND
VCC
VCC
VCC
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD8
//A_D15
A_CAD11
//A_OE
A_CAD10
//A_CE2
A_CAD9
//A_A10
PC2
TPB0P TPA0PR1TPB1P AVDD TPA1P
(TEST3)
PC1
AGND
TPBIAS0
CNA
B_CAD4
//B_D12
B_CAD7
//B_D7
B_CAD13
//B_IORD
B_RSVD
//B_A18
B_CGNT
//B_WE
B_CAD18
//B_A7
B_CAD21
//B_A5
B_CC/BE3
//B_REG
A_CCD1
//A_CD1
B_CAD31
//B_D10
B_RSVD
//B_D2
AGND
B_CAD27
//B_D0
B_CAD29
//B_D1
B_CAD30
//B_D9
(TEST2)
AVDD
B_CCD1
//B_CD1
B_CAD3
//B_D5
B_CAD15
//B_IOWR
B_CPAR
//B_A13
B_CIRDY
//B_A15
GND
GND
A_CAD3
//A_D5
A_CAD7
//A_D7
A_RSVD
//A_D14
A_CAD5
//A_D6
AVDD
VSSPLL
B_CAD8
//B_D15
B_CC/BE1
//B_A8
B_CAD19
//B_A25
B_CSTSCHG
//B_BVD1
(STSCHG
A_CAD0
//A_D3
A_CAD4
//A_D12
A_CAD1
//A_D4
A_CAD2
//A_D11
/RI)
TPBIAS1
VSSPLL
PHY_
TEST_
MA
B_CAD1
//B_D4
B_RSVD
//B_D14
B_CAD9
//B_A10
B_CAD12
//B_A11
B_CAD16
//B_A17
B_CSTOP
//B_A20
B_CTRDY
//B_A22
B_CAD17
//B_A24
B_CRST
//B_RESET
B_CAD23
//B_A3
B_CAD26
//B_A0
B_CAUDIO
//B_BVD2
(SPKR
B_CCD2
//B_CD2
B_CAD28
//B_D8
B_CC/BE0
B_CAD14
B_CC/BE2
//B_INPACK
B_CVS1
)
B_CSERR
B_CCLKRUN
VDPLL
_15
XI
B_CAD2
//B_D11
B_CAD5
//B_D6
//B_CE1
B_CAD11
//B_OE
//B_A9
B_CPERR
//B_A14
B_CCLK
//B_A16
//B_A12
B_CAD20
//B_A6
B_CREQ
B_CAD24
//B_A2
//B_VS1
//B_WAIT
//B_WP
(IOIS16
B_CAD10
B_CDEVSEL
B_CFRAME
B_CAD22
B_CAD25
//B_READY
)
VDPLL
_33
RSVD
XO
B_CAD0
//B_D3
B_CAD6
//B_D13
VR_
PORT
//B_CE2
VCCB
B_CBLOCK
//B_A19
//B_A21
//B_A23
B_CVS2
//B_VS2
//B_A4
VCCB
//B_A1
B_CINT
(IREQ)
2−2
19151051 14131211 169876432 17 18
Figure 2−2. PCI7421 GHK/ZHK-Package Terminal Diagram
AD27
W
VCCP
C/BE3
IDSEL
AD19
C/BE2
STOP
C/BE1
VCCP
AD0 TPB0N TPA0NR0TPB1N
AD4
NC
TPA1N
C/BE0
AD30 AD26
V
REQ
U
GRST
T
MFUNC6
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
SUSPEND
MFUNC2 MFUNC4MFUNC3
DATA LATCH
CLK_48 SDA
SC_
DATA
SM_PHYS
SM_R/B//
SC_RFU
SD_DAT2
//SM_D6//
SC_GPIO4
SC_GPIO3
VR_
PORT
MS_SDIO
MS_DATA1
(DATA0)//
SD_DAT0//
SM_D0
MC_PWR
MC_PWR
_CTRL_0
B_USB_EN
A_USB_EN
A_CAD31
//A_D10
A_CAD30
//A_D9
A_CSTSCHG
A_CAD27
//A_D0
(STSCHG
A_CAUDIO
AD29
AD28
AD31
RI_OUT
GNT
//PME
PRST
MFUNC0 MFUNC5
SCL
SC_OC
SC_CD
SC_RST
_WP//
SC_FCB
SD_DAT3
SD_CMD//
//SM_D7//
SM_ALE//
SC_GPIO2
SD_DAT0//
VR_EN
SM_D4//
SC_GPIO6
MS_DATA2
//SD_DAT2
//SD_DAT1
//SM_D2
//SM_D1
MS_BS//
SD_CMD
_CTRL_1
//SM_WE
SD_CD
A_RSVD
A_CAD29
//A_D1
//A_D2
A_CCLKRUN
A_CAD28
//A_WP
//A_D8
(IOIS16)
A_CSERR
//A_BVD1
//A_WAIT
/RI)
A_CVS1
//A_BVD2
//A_VS1
(SPKR
)
AD24
AD25
A_CINT//
A_READY
(IREQ
A_CAD26
//A_A0
A_CAD25
//A_A1
AD23
AD22
PCLK
MFUNC1
SC_
PWR_
CTRL
SC_CLK
SD_CLK//
SM_RE
//
SC_GPIO1
MS_DATA3//
SD_DAT3
//SM_D3
MS_CLK//
SD_CLK//
SM_EL_WP
MS_CD SM_CD
A_CCD2
//A_CD2
A_CC/BE3
//A_REG
)
A_CAD23
//A_A3
VCCA
AD18
AD17
AD21
AD20
CLOCK
SD_DAT1//
SM_D5//
SC_GPIO5
A_CAD24
//A_A2
A_CAD22
//A_A4
A_CAD21
//A_A5
A_CRST
//A_RESET
FRAME
IRDY
AD16 TRDY
VCC
DEVSEL
VCC GND
SPKROUT
SC_VCC
_5V
SM_CLE//
SC_GPIO0
SD_WP//
SM_CE
GND GND
A_CVS2
A_CREQ
//A_INPACK
//A_VS2
A_CAD19
A_CFRAME
//A_A25
//A_A23
A_CAD18
A_CIRDY
//A_A7
//A_A15
A_CAD17
A_CTRDY
//A_A24
//A_A22
AD15
AD14
AD13
AD11
AD10
AD9
PERR
SERR
PAR
AD12
AD8
VCC
VCC
GND
GND GND GND GND
GND
VCC
VCC
VCC
A_CC/BE2
A_CDEVSEL
GND
VCC
A_CAD20
//A_A6
//A_A12
A_CCLK
//A_A16
//A_A21
A_CGNT
//A_WE
A_CSTOP
//A_A20
A_CPERR
A_CBLOCK
A_RSVD
A_CC/BE1
A_CAD16
GND GND VCC
GND GND
VCC
A_CPAR
//A_A13
//A_A14
//A_A19
//A_A18
//A_A8
//A_A17
AD7
AD6
AD5
AD1
CPS
VCC
A_CAD14
//A_A9
A_CAD15
//A_IOWR
A_CAD13
//A_IORD
A_CAD12
//A_A11
VCCA
AD3
AD2
PC0
(TEST1)
TEST0
AGND
VCC
VCC
VCC
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD8
//A_D15
A_CAD11
//A_OE
A_CAD10
//A_CE2
A_CAD9
//A_A10
PC2
TPB0P TPA0PR1TPB1P AVDD TPA1P
(TEST3)
PC1
AGND
TPBIAS0
(TEST2)
AVDD
RSVD
RSVD
RSVD
RSVD
RSVD
GND
GND
AVDD
VSSPLL
RSVD
RSVD
RSVD
AGND
CNA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
A_CAD0
A_CAD3
//A_D3
//A_D5
A_CAD4
//A_D12
A_CAD1
//A_D4
A_CAD2
//A_D11
A_CCD1
RSVD RSVD RSVD
//A_CD1
RSVD RSVD RSVD
RSVD
RSVD
RSVD
A_CAD7
//A_D7
A_RSVD
//A_D14
A_CAD5
//A_D6
VDPLL
TPBIAS1
VDPLL
VSSPLL
PHY_
TEST_
MA
RSVD RSVD
_15
XI
RSVD
RSVDRSVD
RSVDRSVD
RSVD
RSVD
PORT
RSVD RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
_33
XO
VR_
Figure 2−3. PCI7611 GHK/ZHK-Package Terminal Diagram
19151051 14131211 169876432 17 18
2−3
AD27
W
VCCP
C/BE3
IDSEL
AD19
C/BE2
STOP
C/BE1
VCCP
C/BE0
AD0 TPB0N TPA0NR0TPB1N
AD4
NC
TPA1N
AD30 AD26
V
REQ
U
GRST
T
MFUNC6
R
P
N
M
SUSPEND
MFUNC2 MFUNC4MFUNC3
DATA LATCH
CLK_48 SDA
L
SM_PHYS
SM_R/B
K
SD_DAT2
//SM_D6
VR_
PORT
MS_SDIO
(DATA0)//
SD_DAT0//
SM_D0
MC_PWR
_CTRL_0
B_USB_EN
A_CAD31
//A_D10
A_CAD30
//A_D9
A_CAD27
//A_D0
SD_DAT3
VR_EN
MS_DATA1
//SD_DAT1
MC_PWR
_CTRL_1
A_USB_EN
A_RSVD
A_CSTSCHG
(STSCHG
A_CAUDIO
//A_BVD2
J
H
G
F
E
D
C
B
A
AD29
AD31
GNT
AD28
RI_OUT
//PME
AD24
AD25
AD23
AD22
PRST
PCLK
MFUNC0 MFUNC5
SCL
MFUNC1
RSVDRSVD RSVD RSVD
A_CINT//
A_READY
(IREQ
A_CAD26
//A_A0
A_CAD25
//A_A1
RSVD
SD_CLK//
SM_RE
MS_DATA3//
SD_DAT3
//SM_D3
MS_CLK//
SD_CLK//
SM_EL_WP
MS_CD SM_CD
A_CCD2
//A_CD2
A_CC/BE3
//A_REG
)
A_CAD23
//A_A3
VCCA
RSVD RSVD
_WP
SD_CMD//
SM_ALE
//SM_D7
SD_DAT0
//SM_D4
MS_DATA2
//SD_DAT2
//SM_D2
//SM_D1
MS_BS//
SD_CMD
//SM_WE
SD_CD
A_CAD29
//A_D1
//A_D2
A_CCLKRUN
A_CAD28
//A_WP
//A_D8
(IOIS16)
A_CSERR
//A_BVD1
//A_WAIT
/RI)
A_CVS1
//A_VS1
(SPKR
)
AD18
AD17
AD21
AD20
CLOCK
SD_DAT1
//SM_D5
A_CAD24
//A_A2
A_CAD22
//A_A4
A_CAD21
//A_A5
A_CRST
//A_RESET
FRAME
IRDY
AD16 TRDY
VCC
DEVSEL
VCC GND
SPKROUT
SM_CLE
SD_WP//
SM_CE
GND GND
A_CVS2
A_CREQ
//A_INPACK
//A_VS2
A_CAD19
A_CFRAME
//A_A25
A_CAD18
A_CIRDY
//A_A7
//A_A15
A_CAD17
A_CTRDY
//A_A24
AD15
AD14
AD13
AD11
AD10
AD9
PERR
SERR
PAR
AD12
AD8
VCC
VCC
GND
GND GND GND GND
GND
VCC
VCC
VCC
A_CC/BE2
//A_A23
//A_A22
GND
VCC
A_CAD20
//A_A6
//A_A12
A_CCLK
//A_A16
A_CDEVSEL
//A_A21
A_CGNT
//A_WE
A_CSTOP
//A_A20
A_CPAR
A_CPERR
A_CBLOCK
A_RSVD
A_CC/BE1
A_CAD16
GND GND VCC
GND GND
VCC
//A_A13
//A_A14
//A_A19
//A_A18
//A_A8
//A_A17
AD7
AD6
AD5
AD1
CPS
VCC
A_CAD14
//A_A9
A_CAD15
//A_IOWR
A_CAD13
//A_IORD
A_CAD12
//A_A11
VCCA
AD3
AD2
PC0
(TEST1)
TEST0
AGND
VCC
VCC
VCC
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD8
//A_D15
A_CAD11
//A_OE
A_CAD10
//A_CE2
A_CAD9
//A_A10
PC2
TPB0P TPA0PR1TPB1P AVDD TPA1P
(TEST3)
PC1
AGND
TPBIAS0
(TEST2)
AVDD
RSVD
RSVD
RSVD
RSVD
RSVD
GND
GND
AVDD
VSSPLL
RSVD
RSVD
RSVD
AGND
CNA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD RSVD
A_CAD0
A_CAD3
//A_D3
//A_D5
A_CAD4
//A_D12
A_CAD1
//A_D4
A_CAD2
//A_D11
A_CCD1
RSVD RSVD RSVD
//A_CD1
RSVD RSVD RSVD
RSVD
RSVD
RSVD
A_CAD7
//A_D7
A_RSVD
//A_D14
A_CAD5
//A_D6
VDPLL_
TPBIAS1
VDPLL_
VSSPLL
PHY_
TEST_
MA
RSVD RSVD
15
XI
RSVD
RSVDRSVD
RSVDRSVD
RSVD
RSVD
PORT
RSVD RSVD RSVD
RSVD RSVD
RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
33
XO
VR_
19151051 14131211 169876432 17 18
Figure 2−4. PCI7411 GHK/ZHK-Package Terminal Diagram
Table 2−1 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for
both CardBus and 16-bit PC Cards for the PCI7421 and PCI7621 GHK packages. Table 2−2 and Table 2−3 list the
terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the
GHK package; Table 2−2 is for CardBus signal names and Table 2−3 is for 16-bit PC Card signal names.
Terminal E5 on the GHK package is an identification ball used for device orientation.
2−4
Table 2−1. Signal Names by GHK Terminal Number
TERMINAL
TERMINAL
TERMINAL
TERMINAL
SIGNAL NAME
NUMBER
A02 A_CAUDIO A_BVD2(SPKR) C06 A_CAD22 A_A4
A03 A_CVS1 A_VS1 C07 A_CAD19 A_A25
A04 A_CAD25 A_A1 C08 A_CFRAME A_A23
A05 V
A06 A_CRST A_RESET C10 A_RSVD A_A18
A07 A_CAD17 A_A24 C11 A_CAD13 A_IORD
A08 A_CTRDY A_A22 C12 A_CAD11 A_OE
A09 A_CSTOP A_A20 C13 A_CAD7 A_D7
A10 A_CAD16 A_A17 C14 A_CAD4 A_D12
A11 V
A12 A_CAD9 A_A10 C16 B_CAD27 B_D0
A13 A_CAD5 A_D6 C17 B_CAUDIO B_BVD2(SPKR)
A14 A_CAD2 A_D11 C18 B_CVS1 B_VS1
A15 B_RSVD B_D2 C19 B_CAD25 B_A1
A16 B_CAD30 B_D9 D01 A_CAD31 A_D10
A17 B_CAD28 B_D8 D02 A_RSVD A_D2
A18 B_CCLKRUN B_WP(IOIS16) D03 A_CAD29 A_D1
B01 A_CAD27 A_D0 D17 B_CAD26 B_A0
B02 A_CSTSCHG A_BVD1(STSCHG/RI) D18 B_CAD24 B_A2
B03 A_CSERR A_WAIT D19 V
B04 A_CAD26 A_A0 E01 B_USB_EN B_USB_EN
B05 A_CAD23 A_A3 E02 A_USB_EN A_USB_EN
B06 A_CAD21 A_A5 E03 SD_CD SD_CD
B07 A_CAD18 A_A7 E05 A_CCD2 A_CD2
B08 A_CIRDY A_A15 E06 A_CAD24 A_A2
B09 A_CGNT A_WE E07 A_CREQ A_INPACK
B10 A_CC/BE1 A_A8 E08 A_CVS2 A_VS2
B11 A_CAD12 A_A11 E09 A_CCLK A_A16
B12 A_CAD10 A_CE2 E10 A_CBLOCK A_A19
B13 A_RSVD A_D14 E11 A_CAD15 A_IOWR
B14 A_CAD1 A_D4 E12 A_CAD8 A_D15
B15 B_CAD31 B_D10 E13 A_CAD3 A_D5
B16 B_CAD29 B_D1 E14 A_CAD0 A_D3
B17 B_CCD2 B_CD2 E17 B_CAD23 B_A3
B18 B_CSERR B_WAIT E18 B_CREQ B_INPACK
B19 B_CINT B_READY(IREQ) E19 B_CAD22 B_A4
C01 A_CAD30 A_D9 F01 MC_PWR_CTRL_0 MC_PWR_CTRL_0
C02 A_CAD28 A_D8 F02 MC_PWR_CTRL_1 MC_PWR_CTRL_1
C03 A_CCLKRUN A_WP(IOIS16) F03 MS_BS
C04 A_CINT A_READY(IREQ) F05 MC_CD MC_CD
C05 A_CC/BE3 A_REG F06 SM_CD SM_CD
CardBus PC Card 16-Bit PC Card
CCA
CCA
V
V
CCA
CCA
NUMBER
C09 A_CDEVSEL A_A21
C15 A_CCD1 A_CD1
CardBus PC Card 16-Bit PC Card
//SD_CMD
//SM_WE
CCB
SIGNAL NAME
V
CCB
MS_BS
//SD_CMD
//SM_WE
2−5
Table 2−1. Signal Names by GHK Terminal Number (Continued)
TERMINAL
TERMINAL
TERMINAL
TERMINAL
SIGNAL NAME
NUMBER
F09 A_CC/BE2 A_A12 H09 V
F10 A_CPERR A_A14 H10 V
F12 A_CAD6 A_D13 H11 V
F14 B_CSTSCHG B_BVD1(STSCHG/RI) H12 V
F15 B_CC/BE3 B_REG H13 GND GND
F17 B_CRST B_RESET H14 B_CAD19 B_A25
F18 B_CAD20 B_A6 H15 B_CAD18 B_A7
F19 B_CVS2 B_VS2 H17 B_CTRDY B_A22
G01 MS_SDIO(DATA0)
G02 MS_DATA1
G03 MS_DATA2
G05 MS_CLK
G07 GND GND J03 SD_CMD
G08 GND GND J05 SD_CLK
G09 A_CAD20 A_A6 J06 SD_DAT1
G10 A_CPAR A_A13 J07 SM_CLE
G11 A_CAD14 A_A9 J08 V
G12 A_CC/BE0 A_CE1 J09 GND GND
G13 GND GND J10 GND GND
G15 B_CAD21 B_A5 J11 GND GND
G17 B_CAD17 B_A24 J12 V
G18 B_CC/BE2 B_A12 J13 B_CIRDY B_A15
G19 B_CFRAME B_A23 J15 B_CGNT B_WE
H01 VR_PORT VR_PORT J17 B_CSTOP B_A20
H02 VR_EN VR_EN J18 B_CPERR B_A14
H03 SD_DAT0
H05 MS_DATA3
H07 SD_WP
H08 V
CardBus PC Card 16-Bit PC Card
//SD_DAT0
//SM_D0
//SD_DAT1
//SM_D1
//SD_DAT2
//SM_D2
//SD_CLK
//SM_EL_WP
//SM_D4
//SC_GPIO6
//SD_DAT3
//SM_D3
//SM_CE
CC
MS_SDIO(DATA0)
//SD_DAT0
//SM_D0
MS_DATA1
//SD_DAT1
//SM_D1
MS_DATA2
//SD_DAT2
//SM_D2
MS_CLK
//SD_CLK
//SM_EL_WP
SD_DAT0
//SM_D4
//SC_GPIO6
MS_DATA3
//SD_DAT3
//SM_D3
SD_WP
//SM_CE
V
CC
NUMBER
H18 B_CCLK B_A16
H19 B_CDEVSEL B_A21
J01 SD_DAT2
J02 SD_DAT3
J19 B_CBLOCK B_A19
K01 SM_R/B
K02 SM_PHYS_WP
K03 SC_RST SC_RST
CardBus PC Card 16-Bit PC Card
//SM_D6
//SC_GPIO4
//SM_D7
//SC_GPIO3
//SM_ALE
//SC_GPIO2
//SM_RE
//SC_GPIO1
//SM_D5
//SC_GPIO5
//SC_GPIO0
//SC_RFU
//SC_FCB
SIGNAL NAME
CC
CC
CC
CC
SD_DAT2
//SC_GPIO4
SD_DAT3
//SC_GPIO3
SD_CMD
//SM_ALE
//SC_GPIO2
//SC_GPIO1
SD_DAT1
//SC_GPIO5
//SC_GPIO0
CC
CC
//SC_RFU
SM_PHYS_WP
//SC_FCB
V
CC
V
CC
V
CC
V
CC
//SM_D6
//SM_D7
SD_CLK
//SM_RE
//SM_D5
SM_CLE
V
CC
V
CC
SM_R/B
2−6
Table 2−1. Signal Names by GHK Terminal Number (Continued)
TERMINAL
TERMINAL
TERMINAL
TERMINAL
SIGNAL NAME
NUMBER
K05 SC_CLK SC_CLK M18 B_CC/BE0 B_CE1
K07 SC_VCC_5V SC_VCC_5V M19 VR_PORT VR_PORT
K08 V
K09 GND GND N02 LATCH LATCH
K10 GND GND N03 MFUNC0 MFUNC0
K11 GND GND N05 MFUNC5 MFUNC5
K12 V
K13 B_CPAR B_A13 N08 DEVSEL DEVSEL
K14 B_CC/BE1 B_A8 N09 AD12 AD12
K15 B_RSVD B_A18 N10 AD8 AD8
K17 B_CAD16 B_A17 N11 AD1 AD1
K18 B_CAD14 B_A9 N12 AGND AGND
K19 V
L01 SC_DATA SC_DATA N15 B_CAD4 B_D12
L02 SC_CD SC_CD N17 B_RSVD B_D14
L03 SC_OC SC_OC N18 B_CAD5 B_D6
L05 SC_PWR_CTRL SC_PWR_CTRL N19 B_CAD6 B_D13
L06 CLOCK CLOCK P01 MFUNC2 MFUNC2
L07 SPKROUT SPKROUT P02 MFUNC3 MFUNC3
L08 GND GND P03 MFUNC4 MFUNC4
L09 GND GND P05 PCLK PCLK
L10 GND GND P06 AD20 AD20
L11 GND GND P09 PAR PAR
L12 GND GND P12 TEST0 TEST0
L13 B_CAD15 B_IOWR P14 VSSPLL VSSPLL
L15 B_CAD13 B_IORD P15 CNA CNA
L17 B_CAD12 B_A11 P17 B_CAD1 B_D4
L18 B_CAD11 B_OE P18 B_CAD2 B_D11
L19 B_CAD10 B_CE2 P19 B_CAD0 B_D3
M01 CLK_48 CLK_48 R01 MFUNC6 MFUNC6
M02 SDA SDA R02 SUSPEND SUSPEND
M03 SCL SCL R03 PRST PRST
M05 MFUNC1 MFUNC1 R06 AD21 AD21
M07 V
M08 GND GND R08 TRDY TRDY
M09 V
M10 V
M11 CPS CPS R11 AD5 AD5
M12 V
M13 B_CAD3 B_D5 R13 AVDD AVDD
M14 B_CAD8 B_D15 R14 AVDD AVDD
M15 B_CAD7 B_D7 R17 PHY_TEST_MA PHY_TEST_MA
M17 B_CAD9 B_A10 R18 XI XI
CardBus PC Card 16-Bit PC Card
CC
CC
CCB
CC
CC
CC
CC
V
V
V
V
V
V
V
CC
CC
CCB
CC
CC
CC
CC
NUMBER
N01 DATA DATA
N07 V
N13 B_CCD1 B_CD1
R07 AD16 AD16
R09 AD13 AD13
R10 AD9 AD9
R12 PC0(TEST1) PC0(TEST1)
CardBus PC Card 16-Bit PC Card
CC
SIGNAL NAME
V
CC
2−7
Table 2−1. Signal Names by GHK Terminal Number (Continued)
TERMINAL
TERMINAL
TERMINAL
TERMINAL
SIGNAL NAME
NUMBER
R19 XO XO V06 AD18 AD18
T01 GRST GRST V07 FRAME FRAME
T02 GNT GNT V08 PERR PERR
T03 RI_OUT/PME RI_OUT/PME V09 AD15 AD15
T17 VSSPLL VSSPLL V10 AD11 AD11
T18 VDPLL_15 VDPLL_15 V11 AD7 AD7
T19 RSVD RSVD V12 AD3 AD3
U01 REQ REQ V13 PC2(TEST3) PC2(TEST3)
U02 AD31 AD31 V14 TPB0P TPB0P
U03 AD28 AD28 V15 TPA0P TPA0P
U04 AD25 AD25 V16 TPB1P TPB1P
U05 AD22 AD22 V17 AVDD AVDD
U06 AD17 AD17 V18 TPA1P TPA1P
U07 IRDY IRDY V19 VDPLL_33 VDPLL_33
U08 SERR SERR W02 AD27 AD27
U09 AD14 AD14 W03 V
U10 AD10 AD10 W04 C/BE3 C/BE3
U11 AD6 AD6 W05 IDSEL IDSEL
U12 AD2 AD2 W06 AD19 AD19
U13 PC1(TEST2) PC1(TEST2) W07 C/BE2 C/BE2
U14 AGND AGND W08 STOP STOP
U15 TPBIAS0 TPBIAS0 W09 C/BE1 C/BE1
U16 AGND AGND W10 V
U17 TPBIAS1 TPBIAS1 W11 C/BE0 C/BE0
U18 R0 R0 W12 AD4 AD4
U19 R1 R1 W13 AD0 AD0
V01 AD30 AD30 W14 TPB0N TPB0N
V02 AD29 AD29 W15 TPA0N TPA0N
V03 AD26 AD26 W16 TPB1N TPB1N
V04 AD24 AD24 W17 NC NC
V05 AD23 AD23 W18 TPA1N TPA1N
CardBus PC Card 16-Bit PC Card
NUMBER
CardBus PC Card 16-Bit PC Card
CCP
CCP
SIGNAL NAME
V
V
CCP
CCP
2−8
Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically
SIGNAL NAME
AD0 W13 A_CAD5 A13 A_CPERR F10 B_CAD30 A16
AD1 N11 A_CAD6 F12 A_CREQ E07 B_CAD31 B15
AD2 U12 A_CAD7 C13 A_CRST A06 B_CAUDIO C17
AD3 V12 A_CAD8 E12 A_CSERR B03 B_CBLOCK J19
AD4 W12 A_CAD9 A12 A_CSTOP A09 B_CC/BE0 M18
AD5 R11 A_CAD10 B12 A_CSTSCHG B02 B_CC/BE1 K14
AD6 U11 A_CAD11 C12 A_CTRDY A08 B_CC/BE2 G18
AD7 V11 A_CAD12 B11 A_CVS1 A03 B_CC/BE3 F15
AD8 N10 A_CAD13 C11 A_CVS2 E08 B_CCD1 N13
AD9 R10 A_CAD14 G11 A_RSVD B13 B_CCD2 B17
AD10 U10 A_CAD15 E11 A_RSVD C10 B_CCLK H18
AD11 V10 A_CAD16 A10 A_RSVD D02 B_CCLKRUN A18
AD12 N09 A_CAD17 A07 A_USB_EN E02 B_CDEVSEL H19
AD13 R09 A_CAD18 B07 B_CAD0 P19 B_CFRAME G19
AD14 U09 A_CAD19 C07 B_CAD1 P17 B_CGNT J15
AD15 V09 A_CAD20 G09 B_CAD2 P18 B_CINT B19
AD16 R07 A_CAD21 B06 B_CAD3 M13 B_CIRDY J13
AD17 U06 A_CAD22 C06 B_CAD4 N15 B_CPAR K13
AD18 V06 A_CAD23 B05 B_CAD5 N18 B_CPERR J18
AD19 W06 A_CAD24 E06 B_CAD6 N19 B_CREQ E18
AD20 P06 A_CAD25 A04 B_CAD7 M15 B_CRST F17
AD21 R06 A_CAD26 B04 B_CAD8 M14 B_CSERR B18
AD22 U05 A_CAD27 B01 B_CAD9 M17 B_CSTOP J17
AD23 V05 A_CAD28 C02 B_CAD10 L19 B_CSTSCHG F14
AD24 V04 A_CAD29 D03 B_CAD11 L18 B_CTRDY H17
AD25 U04 A_CAD30 C01 B_CAD12 L17 B_CVS1 C18
AD26 V03 A_CAD31 D01 B_CAD13 L15 B_CVS2 F19
AD27 W02 A_CAUDIO A02 B_CAD14 K18 B_RSVD A15
AD28 U03 A_CBLOCK E10 B_CAD15 L13 B_RSVD K15
AD29 V02 A_CC/BE0 G12 B_CAD16 K17 B_RSVD N17
AD30 V01 A_CC/BE1 B10 B_CAD17 G17 B_USB_EN E01
AD31 U02 A_CC/BE2 F09 B_CAD18 H15 C/BE0 W11
AGND N12 A_CC/BE3 C05 B_CAD19 H14 C/BE1 W09
AGND U14 A_CCD1 C15 B_CAD20 F18 C/BE2 W07
AGND U16 A_CCD2 E05 B_CAD21 G15 C/BE3 W04
AVDD R13 A_CCLK E09 B_CAD22 E19 CLK_48 M01
AVDD R14 A_CCLKRUN C03 B_CAD23 E17 CLOCK L06
AVDD V17 A_CDEVSEL C09 B_CAD24 D18 CNA P15
A_CAD0 E14 A_CFRAME C08 B_CAD25 C19 CPS M11
A_CAD1 B14 A_CGNT B09 B_CAD26 D17 DATA N01
A_CAD2 A14 A_CINT C04 B_CAD27 C16 DEVSEL N08
A_CAD3 E13 A_CIRDY B08 B_CAD28 A17 FRAME V07
A_CAD4 C14 A_CPAR G10 B_CAD29 B16 GND G07
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
2−9
Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
GND G08 NC W17 SD_CMD J03 TPBIAS0 U15
GND G13 PAR P09 SD_DAT0 G01 TPBIAS1 U17
GND H13 PCLK P05 SD_DAT0 H03 TPB0N W14
GND J09 PC0(TEST1) R12 SD_DAT1 G02 TPB0P V14
GND J10 PC1(TEST2) U13 SD_DAT1 J06 TPB1N W16
GND J11 PC2(TEST3) V13 SD_DAT2 G03 TPB1P V16
GND K09 PERR V08 SD_DAT2 J01 TRDY R08
GND K10 PHY_TEST_MA R17 SD_DAT3 H05 V
GND K11 PRST R03 SD_DAT3 J02 V
GND L08 REQ U01 SD_WP H07 V
GND L09 RI_OUT/PME T03 SERR U08 V
GND L10 RSVD T19 SM_ALE J03 V
GND L11 R0 U18 SM_CD F06 V
GND L12 R1 U19 SM_CE H07 V
GND M08 SCL M03 SM_CLE J07 V
GNT T02 SC_CD L02 SM_D0 G01 V
GRST T01 SC_CLK K05 SM_D1 G02 V
IDSEL W05 SC_DATA L01 SM_D2 G03 V
IRDY U07 SC_FCB K02 SM_D3 H05 V
LATCH N02 SC_GPIO0 J07 SM_D4 H03 V
MC_PWR_CTRL_0 F01 SC_GPIO1 J05 SM_D5 J06 V
MC_PWR_CTRL_1 F02 SC_GPIO2 J03 SM_D6 J01 V
MFUNC0 N03 SC_GPIO3 J02 SM_D7 J02 V
MFUNC1 M05 SC_GPIO4 J01 SM_EL_WP G05 V
MFUNC2 P01 SC_GPIO5 J06 SM_PHYS_WP K02 V
MFUNC3 P02 SC_GPIO6 H03 SM_R/B K01 V
MFUNC4 P03 SC_OC L03 SM_RE J05 V
MFUNC5 N05 SC_PWR_CTRL L05 SM_WE F03 VDPLL_15 T18
MFUNC6 R01 SC_RFU K01 SPKROUT L07 VDPLL_33 V19
MS_BS F03 SC_RST K03 STOP W08 VR_EN H02
MS_CD F05 SC_VCC_5V K07 SUSPEND R02 VR_PORT H01
MS_CLK G05 SDA M02 TEST0 P12 VR_PORT M19
MS_DATA1 G02 SD_CD E03 TPA0N W15 VSSPLL P14
MS_DATA2 G03 SD_CLK G05 TPA0P V15 VSSPLL T17
MS_DATA3 H05 SD_CLK J05 TPA1N W18 XI R18
MS_SDIO(DATA0) G01 SD_CMD F03 TPA1P V18 XO R19
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL
NAME
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCA
CCB
CCB
CCP
CCP
TERMINAL
NUMBER
H08
H09
H10
H11
H12
J08
J12
K08
K12
M07
M09
M10
M12
N07
A05
A11
D19
K19
W03
W10
2−10
Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically
SIGNAL
NAME
AD0 W13 A_A5 B06 A_INPACK E07 B_CE1 M18
AD1 N11 A_A6 G09 A_IORD C11 B_CE2 L19
AD2 U12 A_A7 B07 A_IOWR E11 B_D0 C16
AD3 V12 A_A8 B10 A_OE C12 B_D1 B16
AD4 W12 A_A9 G11 A_READY(IREQ) C04 B_D2 A15
AD5 R11 A_A10 A12 A_REG C05 B_D3 P19
AD6 U11 A_A11 B11 A_RESET A06 B_D4 P17
AD7 V11 A_A12 F09 A_USB_EN E02 B_D5 M13
AD8 N10 A_A13 G10 A_VS1 A03 B_D6 N18
AD9 R10 A_A14 F10 A_VS2 E08 B_D7 M15
AD10 U10 A_A15 B08 A_WAIT B03 B_D8 A17
AD11 V10 A_A16 E09 A_WE B09 B_D9 A16
AD12 N09 A_A17 A10 A_WP(IOIS16) C03 B_D10 B15
AD13 R09 A_A18 C10 B_A0 D17 B_D11 P18
AD14 U09 A_A19 E10 B_A1 C19 B_D12 N15
AD15 V09 A_A20 A09 B_A2 D18 B_D13 N19
AD16 R07 A_A21 C09 B_A3 E17 B_D14 N17
AD17 U06 A_A22 A08 B_A4 E19 B_D15 M14
AD18 V06 A_A23 C08 B_A5 G15 B_INPACK E18
AD19 W06 A_A24 A07 B_A6 F18 B_IORD L15
AD20 P06 A_A25 C07 B_A7 H15 B_IOWR L13
AD21 R06 A_BVD1(STSCHG/RI) B02 B_A8 K14 B_OE L18
AD22 U05 A_BVD2(SPKR) A02 B_A9 K18 B_READY(IREQ) B19
AD23 V05 A_CD1 C15 B_A10 M17 B_REG F15
AD24 V04 A_CD2 E05 B_A11 L17 B_RESET F17
AD25 U04 A_CE1 G12 B_A12 G18 B_USB_EN E01
AD26 V03 A_CE2 B12 B_A13 K13 B_VS1 C18
AD27 W02 A_D0 B01 B_A14 J18 B_VS2 F19
AD28 U03 A_D1 D03 B_A15 J13 B_WAIT B18
AD29 V02 A_D2 D02 B_A16 H18 B_WE J15
AD30 V01 A_D3 E14 B_A17 K17 B_WP(IOIS16) A18
AD31 U02 A_D4 B14 B_A18 K15 C/BE0 W11
AGND N12 A_D5 E13 B_A19 J19 C/BE1 W09
AGND U14 A_D6 A13 B_A20 J17 C/BE2 W07
AGND U16 A_D7 C13 B_A21 H19 C/BE3 W04
AVDD R13 A_D8 C02 B_A22 H17 CLK_48 M01
AVDD R14 A_D9 C01 B_A23 G19 CLOCK L06
AVDD V17 A_D10 D01 B_A24 G17 CNA P15
A_A0 B04 A_D11 A14 B_A25 H14 CPS M11
A_A1 A04 A_D12 C14 B_BVD1(STSCHG/RI) F14 DATA N01
A_A2 E06 A_D13 F12 B_BVD2(SPKR) C17 DEVSEL N08
A_A3 B05 A_D14 B13 B_CD1 N13 FRAME V07
A_A4 C06 A_D15 E12 B_CD2 B17 GND G07
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
2−11
Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
GND G08 NC W17 SD_CMD J03 TPBIAS0 U15
GND G13 PAR P09 SD_DAT0 G01 TPBIAS1 U17
GND H13 PCLK P05 SD_DAT0 H03 TPB0N W14
GND J09 PC0(TEST1) R12 SD_DAT1 G02 TPB0P V14
GND J10 PC1(TEST2) U13 SD_DAT1 J06 TPB1N W16
GND J11 PC2(TEST3) V13 SD_DAT2 G03 TPB1P V16
GND K09 PERR V08 SD_DAT2 J01 TRDY R08
GND K10 PHY_TEST_MA R17 SD_DAT3 H05 V
GND K11 PRST R03 SD_DAT3 J02 V
GND L08 REQ U01 SD_WP H07 V
GND L09 RI_OUT/PME T03 SERR U08 V
GND L10 RSVD T19 SM_ALE J03 V
GND L11 R0 U18 SM_CD F06 V
GND L12 R1 U19 SM_CE H07 V
GND M08 SCL M03 SM_CLE J07 V
GNT T02 SC_CD L02 SM_D0 G01 V
GRST T01 SC_CLK K05 SM_D1 G02 V
IDSEL W05 SC_DATA L01 SM_D2 G03 V
IRDY U07 SC_FCB K02 SM_D3 H05 V
LATCH N02 SC_GPIO0 J07 SM_D4 H03 V
MC_PWR_CTRL_0 F01 SC_GPIO1 J05 SM_D5 J06 V
MC_PWR_CTRL_1 F02 SC_GPIO2 J03 SM_D6 J01 V
MFUNC0 N03 SC_GPIO3 J02 SM_D7 J02 V
MFUNC1 M05 SC_GPIO4 J01 SM_EL_WP G05 V
MFUNC2 P01 SC_GPIO5 J06 SM_PHYS_WP K02 V
MFUNC3 P02 SC_GPIO6 H03 SM_R/B K01 V
MFUNC4 P03 SC_OC L03 SM_RE J05 V
MFUNC5 N05 SC_PWR_CTRL L05 SM_WE F03 VDPLL_15 T18
MFUNC6 R01 SC_RFU K01 SPKROUT L07 VDPLL_33 V19
MS_BS F03 SC_RST K03 STOP W08 VR_EN H02
MS_CD F05 SC_VCC_5V K07 SUSPEND R02 VR_PORT H01
MS_CLK G05 SDA M02 TEST0 P12 VR_PORT M19
MS_DATA1 G02 SD_CD E03 TPA0N W15 VSSPLL P14
MS_DATA2 G03 SD_CLK G05 TPA0P V15 VSSPLL T17
MS_DATA3 H05 SD_CLK J05 TPA1N W18 XI R18
MS_SDIO(DATA0) G01 SD_CMD F03 TPA1P V18 XO R19
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL NAME
TERMINAL
NUMBER
SIGNAL
NAME
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CCA
CCA
CCB
CCB
CCP
CCP
TERMINAL
NUMBER
H08
H09
H10
H11
H12
J08
J12
K08
K12
M07
M09
M10
M12
N07
A05
A11
D19
K19
W03
W10
2−12
2.1 Detailed Terminal Descriptions
Please see Table 2−4 through Table 2−19 for more detailed terminal descriptions. The following list defines the
column headings and the abbreviations used in the detailed terminal description tables.
• I/O Type:
− I = Digital input
− O = Digital output
− I/O = Digital input/output
− AI = Analog input
− PWR = Power
− GND = Ground
• Input/Output Description:
− AF = Analog feedthrough
− TTLI1 = 5-V tolerant TTL input buffer
− TTLI2 = 5-V tolerant TTL input buffer with hysteresis
− TTLO1 = 5-V tolerant low-noise 4-mA TTL output buffer
− PCII1 = 5-V tolerant PCI input buffer
− PCII2 = 5-V tolerant PCI input buffer
− PCII3 = 5-V tolerant PCI input buffer
− PCII4 = 5-V tolerant PCI input buffer
− PCII5 = 5-V tolerant PCI input buffer
− PCIO2 = 5-V tolerant PCI output buffer
− PCIO4 = 5-V tolerant PCI output buffer
− PCIO5 = 5-V tolerant PCI output buffer
− LVCI1 = LVCMOS input buffer
− LVCO1 = Low-noise 4-mA LVCMOS open drain output buffer
− LVCO2 = Low-noise 4-mA LVCMOS open drain output buffer
− LVCO3 = Low-noise 8-mA LVCMOS open drain output buffer
• PU/PD signifies whether the terminal has an internal pullup or pulldown resistor. These pullups are disabled
and enabled by design when appropriate to preserve power.
− PD1 = 20-µA failsafe pulldown
− PD2 = 100-µA failsafe pulldown
− PU1 = 200-µA pullup
− PU2 = 100-µA pullup
− PU3 = 100-µA pullup
− PU4 = 100-µA pullup
− SW = Switchable 50-µA pullup/200-µA pulldown implemented depending on situation
• Power Rail signifies which rail the terminal is clamped to for protection.
• External Components signifies any external components needed for normal operation.
• Pin Strapping (If Unused) signifies how the terminal must be implemented if its function is not needed.
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
2−13
Table 2−4. Power Supply Terminals
I/O
EXTERNAL
PIN STRAPPING
I/O
EXTERNAL
PIN STRAPPING
Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power
supply terminals.
TERMINAL
NAME NUMBER
AGND
AVDD
GND
V
CC
V
CCA
V
CCB
V
CCP
VDPLL_15 T18
VDPLL_33 V19
VR_EN H02 Internal voltage regulator enable. Active low FT FT
VR_PORT H01, M19 1.5-V output from the internal voltage regulator PWR
VSSPLL P14, T17
N12, U14,
U16
R13, R14,
V17
G07, G08,
G13, H13,
J09, J10,
J11, K09,
K10, K11,
L08, L09,
L10, L11,
L12, M08
H08, H09,
H10, H11,
H12, J08,
J12, K08,
K12, M07,
M09, M10,
M12, N07
A05, A11
D19, K19
W03, W10 Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V PWR NA
Analog circuit ground terminals GND NA
Analog circuit power terminals. A parallel combination of high
frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are
separated from VDPLL_33 internal to the controller to provide
noise isolation. They must be tied to a low-impedance point on the
circuit board.
Digital ground terminal GND NA
Power supply terminal for I/O and internal voltage regulator PWR NA
Clamp voltage for PC Card A interface. Matches card A signaling
environment, 5 V or 3.3 V
Clamp voltage for PC Card B interface. Matches card B signaling
environment, 5 V or 3.3 V
1.5-V PLL circuit power terminal. An external capacitor (0.1 µF
recommended) must be placed between terminals T18 and T17
(VSSPLL) when the internal voltage regulator is enabled
(VR_EN
= 0 V). When the internal voltage regulator is disabled,
1.5-V must be supplied to this terminal and a parallel combination
of high frequency decoupling capacitors near the terminal is
suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF
filtering capacitors are also recommended.
3.3-V PLL circuit power terminal. A parallel combination of high
frequency decoupling capacitors near the terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. This supply terminal is
separated from AVDD internal to the controller to provide noise
isolation. It must be tied to a low-impedance point on the circuit
board. When the internal voltage regulator is disabled
(VR_EN
= 3.3 V), no voltage is required to be supplied to this
terminal.
PLL circuit ground terminal. This terminal must be tied to the
low-impedance circuit board ground plane.
DESCRIPTION
INPUT
TYPE
GND
PWR Float
PWR Float
PWR
GND NA
COMPONENTS
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
AGND
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
VSPLL
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
VSPLL
Pulled directly to
GND
0.1-µF capacitor
tied to GND
(IF UNUSED)
NA
NA
NA
NA
NA
2−14
Table 2−5. PC Card Power Switch Terminals
I/O
EXTERNAL
I/O
EXTERNAL
I/O
POWER
EXTERNAL
I/O
POWER
EXTERNAL
Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch
terminals.
TERMINAL
NAME NO.
CLOCK L06
DATA N01
LATCH N02
Power switch clock. Information on the DATA line is sampled at the rising edge of
CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27
(P2CCLK) in the system control register (offset 80h, see Section 4.29).
Power switch data. DATA is used to communicate socket power control information
serially to the power switch.
Power switch latch. LATCH is asserted by the controller to indicate to the power
switch that the data on the DATA line is valid.
DESCRIPTION
INPUT OUTPUT
TYPE
I/O TTLI1 TTLO1
O LVCO1
O LVCO1
COMPONENTS
PCMCIA power
switch
PCMCIA power
switch
PCMCIA power
switch
Table 2−6. PCI System Terminals
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals.
TERMINAL
NAME NO.
GRST T01
PCLK P05
PRST
R03
Global reset. When the global reset is asserted, the GRST signal causes the
controller to place all output buffers in a high-impedance state and reset all internal
registers. When GRST
systems that require wake-up from D3, GRST
boot. PRST
when transitioning from D3 to D0. For systems that do not require wake-up from D3,
GRST
protected from the GRST
placed in a high-impedance state, but the contents of the registers are preserved.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI
signals are sampled at the rising edge of PCLK.
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to
place all output buffers in a high-impedance state and reset some internal registers.
When PRST
deasserted, the controller is in a default state.
When SUSPEND
clearing the internal registers. All outputs are placed in a high-impedance state, but
the contents of the registers are preserved.
must be asserted following initial boot so that PME context is retained
must be tied to PRST. When the SUSPEND mode is enabled, the controller is
is asserted, the controller is completely nonfunctional. After PRST is
is asserted, the controller is completely in its default state. For
, and the internal registers are preserved. All outputs are
and PRST are asserted, the controller is protected from PRST
DESCRIPTION
is normally asserted only during initial
INPUT
TYPE
I LVCI2
I PCII3 V
I PCII3 V
RAIL
CCP
CCP
COMPONENTS
Power-on reset or
tied to PRST
2−15
Table 2−7. PCI Address and Data Terminals
I/O
POWER
I/O
POWER
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals.
TERMINAL
NAME NO.
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3
C/BE2
C/BE1
C/BE0
PAR P09
U02
V01
V02
U03
W02
V03
U04
V04
V05
U05
R06
P06
W06
V06
U06
R07
V09
U09
R09
N09
V10
U10
R10
N10
V11
U11
R11
W12
V12
U12
N11
W13
W04
W07
W09
W11
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a
32-bit address or other destination information. During the data phase, AD31−AD0 contain data.
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a primary-bus PCI cycle, C/BE3
command. During the data phase, this 4-bit bus is used as byte enables. The byte enables
determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0
byte 0 (AD7−AD0), C/BE1
(AD23−AD16), and C/BE3
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across
the AD31−AD0 and C/BE3
outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller
compares its calculated parity to the parity indicator of the initiator. A compare error results in
the assertion of a parity error (PERR
applies to byte 1 (AD15−AD8), C/BE2 applies to byte 2
applies to byte 3 (AD31−AD24).
−C/BE0 buses. As an initiator during PCI cycles, the controller
DESCRIPTION
).
−C/BE0 define the bus
applies to
INPUT OUTPUT
TYPE
I/O PCII3 PCIO3 V
I/O PCII3 PCIO3 V
I/O PCII3 PCIO3 V
RAIL
CCP
CCP
CCP
2−16
Table 2−8. PCI Interface Control Terminals
I/O
POWER
EXTERNAL
I/O
POWER
EXTERNAL
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals.
TERMINAL
NAME NO.
DEVSEL
FRAME
GNT
IDSEL W05
IRDY
PERR
REQ
SERR
STOP
TRDY
N08
V07
T02
U07
V08
U01
U08
W08
R08
PCI device select. The controller asserts DEVSEL to claim a PCI cycle
as the target device. As a PCI initiator on the bus, the controller monitors
DEVSEL
until a target responds. If no target responds before timeout
occurs, then the controller terminates the cycle with an initiator abort.
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME
is asserted to indicate that a bus transaction is beginning, and data
transfers continue while this signal is asserted. When FRAME
deasserted, the PCI bus transaction is in the final data phase.
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the
controller access to the PCI bus after the current data transaction has
completed. GNT
the PCI bus parking algorithm.
Initialization device select. IDSEL selects the controller during
configuration space accesses. IDSEL can be connected to one of the
upper 24 PCI address lines on the PCI bus.
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to
complete the current data phase of the transaction. A data phase is
completed on a rising edge of PCLK where both IRDY
asserted. Until IRDY
are inserted.
PCI parity error indicator. PERR is driven by a PCI controller to indicate
that calculated parity does not match PAR when PERR
through bit 6 of the command register (PCI offset 04h, see Section 4.4).
PCI bus request. REQ is asserted by the controller to request access to
the PCI bus as an initiator.
PCI system error. SERR is an output that is pulsed from the controller
when enabled through bit 8 of the command register (PCI offset 04h,
see Section 4.4) indicating a system error has occurred. The controller
need not be the target of the PCI cycle to assert this signal. When SERR
is enabled in the command register, this signal also pulses, indicating
that an address parity error has occurred on a CardBus interface.
PCI cycle stop signal. STOP is driven by a PCI target to request the
initiator to stop the current PCI bus transaction. STOP
disconnects and is commonly asserted by target devices that do not
support burst data transfers.
PCI target ready. TRDY indicates the ability of the primary bus target to
complete the current data phase of the transaction. A data phase is
completed on a rising edge of PCLK when both IRDY
asserted. Until both IRDY
inserted.
may or may not follow a PCI bus request, depending on
DESCRIPTION
is
and TRDY are
and TRDY are both sampled asserted, wait states
is enabled
is used for target
and TRDY are
and TRDY are asserted, wait states are
INPUT OUTPUT
TYPE
I/O PCII3 PCIO3 V
I/O PCII3 PCIO3 V
I PCII3 V
I PCII3 V
I/O PCII3 PCIO3 V
I/O PCII3 PCIO3 V
O PCIO3 V
O PCIO3 V
I/O PCII3 PCIO3 V
I/O PCII3 PCIO3 V
RAIL
CCP
CCP
CCP
CCP
CCP
CCP
CCP
CCP
CCP
CCP
COMPONENTS
Pullup resistor per
PCI specification
Pullup resistor per
PCI specification
Pullup resistor per
PCI specification
Pullup resistor per
PCI specification
Pullup resistor per
PCI specification
Pullup resistor per
PCI specification
Pullup resistor per
PCI specification
2−17
Table 2−9. Multifunction and Miscellaneous Terminals
I/O
PU/
EXTERNAL
PIN STRAPPING
I/O
PU/PDEXTERNAL
PIN STRAPPING
configuration details.
The power rail designation is not applicable for the multifunction and miscellaneous terminals.
TERMINAL
NAME NO.
USB enable. These output terminals control an
A_USB_EN
B_USB_EN
CLK_48 M01 A 48-MHz clock must be connected to this terminal. I LVCI1
MFUNC0 N03 I/O PCII3 PCIO3
MFUNC1 M05 I/O PCII3 PCIO3
MFUNC2 P01
MFUNC3 P02
MFUNC4 P03
MFUNC5 N05 I/O PCII3 PCIO3
MFUNC6 R01 I/O PCII3 PCIO3
NC W17
PHY_TEST_
MA
RI_OUT/
PME
RSVD T19
SCL M03
SDA M02
SPKROUT
SUSPEND R02
TEST0 P12
E02
external CBT switch for each socket when an USB
E01
card is inserted into the socket.
Multifunction terminals 0−6. See Section 4.36,
Multifunction Routing Status Register, for
Reserved. This terminal has no connection
anywhere within the package.
PHY test pin. Not for customer use. It must be pulled
R17
high with a 4.7-kΩ resistor.
Ring indicate out and power management event
output. This terminal provides an output for
T03
ring-indicate or PME
Reserved. This terminal has no connection
anywhere within the package.
Serial clock. At PRST, the SCL signal is sampled to
determine if a two-wire serial ROM is present. If the
serial ROM is detected, then this terminal provides
the serial clock signaling and is implemented as
open-drain. For normal operation (a ROM is
implemented in the design), this terminal must be
pulled high to the ROM VDD with a 2.7-kΩ resistor.
Otherwise, it must be pulled low to ground with a
220-Ω resistor.
Serial data. This terminal is implemented as
open-drain, and for normal operation (a ROM is
implemented in the design), this terminal must be
pulled high to the ROM VDD with a 2.7-kΩ resistor.
Otherwise, it must be pulled low to ground with a
220-Ω resistor.
Speaker output. SPKROUT is the output to the host
system that can carry SPKR
controller from the PC Card interface. SPKROUT is
L07
driven as the exclusive-OR combination of card
SPKR
//CAUDIO inputs.
Suspend. SUSPEND protects the internal registers
from clearing when the GRST
asserted. See Section 3.8.6, Suspend Mode, for
details.
Terminal TEST0 is used for factory test of the
controller and must be connected to ground for
normal operation.
DESCRIPTION
signals.
or CAUDIO through the
or PRST signal is
INPUT OUTPUT
TYPE
O LVCO1 CBT switch Float
I/O PCII3 PCIO3
I/O PCII3 PCIO3
I/O PCII3 PCIO3
I LVCI1 PD1 NA
O LVCO2
— Float
I/O TTLI1 TTLO1
I/O TTLI1 TTLO1
O TTLO1
I PCII6
I/O LVCI1 PD1 Tie to GND
COMPONENTS
48 MHz clock
source
Pullup resistor per
PCI specification
Pullup resistor per
I2C specification
(value depends on
EEPROM,
typically 2.7 kΩ)
Pullup resistor per
I2C specification
(value depends on
EEPROM,
typically 2.7 kΩ)
10-kΩ to 47-kΩ
pulldown resistor
10-kΩ to 47-kΩ
pullup resistor
(IF UNUSED)
10-kΩ to 47-kΩ
pullup resistor
10-kΩ to 47-kΩ
pullup resistor
10-kΩ to 47-kΩ
pullup resistor
10-kΩ to 47-kΩ
pullup resistor
10-kΩ to 47-kΩ
pullup resistor
10-kΩ to 47-kΩ
pullup resistor
10-kΩ to 47-kΩ
pullup resistor
Float
NA
Tie to GND if not
using EEPROM
Tie to GND if not
using EEPROM
10-kΩ to 47-kΩ
pulldown resistor
10-kΩ to 47-kΩ
pullup resistor
2−18
Table 2−10. 16-Bit PC Card Address and Data Terminals
I/O
POWER
I/O
POWER
External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Card
address and data terminal is unused, then the terminal may be left floating.
H14
G17
G19
H17
H19
J17
J19
K15
K17
H18
J13
J18
K13
G18
L17
M17
K18
K14
H15
F18
G15
E19
E17
D18
C19
D17
M14
N17
N19
N15
P18
B15
A16
A17
M15
N18
M13
P17
P19
A15
B16
C16
†
DESCRIPTION
PC Card address. 16-bit PC Card address lines. A25 is the most significant
bit.
PC Card data. 16-bit PC Card data lines. D15 is the most significant bit. I/O
TYPE
O
V
V
V
V
RAIL
CCA
CCB
CCA
CCB
/
/
SOCKET A TERMINAL SOCKET B TERMINAL
NAME NO. NAME NO.
A_A25
A_A24
A_A23
A_A22
A_A21
A_A20
A_A19
A_A18
A_A17
A_A16
A_A15
A_A14
A_A13
A_A12
A_A11
A_A10
A_A9
A_A8
A_A7
A_A6
A_A5
A_A4
A_A3
A_A2
A_A1
A_A0
A_D15
A_D14
A_D13
A_D12
A_D11
A_D10
A_D9
A_D8
A_D7
A_D6
A_D5
A_D4
A_D3
A_D2
A_D1
A_D0
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.
C07
A07
C08
A08
C09
A09
E10
C10
A10
E09
B08
F10
G10
F09
B11
A12
G11
B10
B07
G09
B06
C06
B05
E06
A04
B04
E12
B13
F12
C14
A14
D01
C01
C02
C13
A13
E13
B14
E14
D02
D03
B01
B_A25
B_A24
B_A23
B_A22
B_A21
B_A20
B_A19
B_A18
B_A17
B_A16
B_A15
B_A14
B_A13
B_A12
B_A11
B_A10
B_A9
B_A8
B_A7
B_A6
B_A5
B_A4
B_A3
B_A2
B_A1
B_A0
B_D15
B_D14
B_D13
B_D12
B_D11
B_D10
B_D9
B_D8
B_D7
B_D6
B_D5
B_D4
B_D3
B_D2
B_D1
B_D0
2−19
Table 2−11. 16-Bit PC Card Interface Control Terminals
I/O
POWER
I/O
POWER
External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card
interface control terminal is unused, then the terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL
NAME NO. NAME NO.
A_BVD1
(STSCHG
A_BVD2
(SPKR
A_CD1
A_CD2
A_CE1
A_CE2
A_INPACK E07 B_INPACK E18
A_IORD
A_IOWR
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.
/RI)
)
B02
A02
C15
E05
G12
B12
C11
E11
B_BVD1
(STSCHG
B_BVD2
(SPKR
B_CD1
B_CD2
B_CE1
B_CE2
B_IORD
B_IOWR
/RI)
)
†
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that
include batteries. BVD1 is used with BVD2 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and must be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt
F14
Configuration Register, for enable bits. See Section 5.5, ExCA Card
Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
status bits for this signal.
Status change. STSCHG
protect, or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that
include batteries. BVD2 is used with BVD1 as an indication of the condition of the
batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery
is good. When BVD2 is low and BVD1 is high, the battery is weak and must be
replaced. When BVD1 is low, the battery is no longer serviceable and the data in
the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt
Configuration Register, for enable bits. See Section 5.5, ExCA Card
Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the
C17
status bits for this signal.
Speaker. SPKR
socket have been configured for the 16-bit I/O interface. The audio signals from
cards A and B are combined by the controller and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA
operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to
indicate a request for a DMA operation.
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground
N13
on the PC Card. When a PC Card is inserted into a socket, CD1
B17
pulled low. For signal status, see Section 5.2, ExCA Interface Status Register.
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered
M18
address bytes. CE1
L19
odd-numbered address bytes.
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an
I/O read cycle at the current address.
DMA request. INPACK
operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then
the PC Card asserts this signal to indicate a request for a DMA operation.
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data
output during host I/O read cycles.
L15
DMA write. IORD
16-bit PC Card that supports DMA. The controller asserts IORD
transfers from the PC Card to host memory.
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O
PC Cards during host I/O write cycles.
L13
DMA read. IOWR
16-bit PC Card that supports DMA. The controller asserts IOWR
from host memory to the PC Card.
is used by 16-bit modem cards to indicate a ring detection.
is an optional binary audio signal available only when the card and
enables even-numbered address bytes, and CE2 enables
can be used as the DMA request signal during DMA
is used as the DMA write strobe during DMA operations from a
is used as the DMA write strobe during DMA operations from a
DESCRIPTION
alerts the system to a change in the READY, write
and CD2 are
during DMA
during transfers
TYPE
I
I
I
O
I
O
O
V
V
V
V
V
V
V
V
V
V
V
V
RAIL
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
/
/
/
/
/
/
2−20
Table 2−11. 16-Bit PC Card Interface Control Terminals (Continued)
I/O
POWER
I/O
POWER
SKT A TERMINAL SKT B TERMINAL
NAME NO. NAME NO.
A_OE C12 B_OE L18
A_READY
(IREQ
)
A_REG
A_RESET A06 B_RESET F17 PC Card reset. RESET forces a hard reset to a 16-bit PC Card. O
A_VS1
A_VS2
A_WAIT
A_WE B09 B_WE J15
A_WP
(IOIS16
)
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.
C04
C05
A03
E08
B03
C03
B_READY
(IREQ
B_REG
B_VS1
B_VS2
B_WAIT
B_WP
(IOIS16
)
†
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card
data output during host memory read cycles.
DMA terminal count. OE
16-bit PC Card that supports DMA. The controller asserts OE
write operation.
Ready. The ready function is provided when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by 16-bit memory PC
Cards to indicate that the memory card circuits are busy processing a previous write
command. READY is driven high when the 16-bit memory PC Card is ready to accept a
B19
new data transfer command.
Interrupt request. IREQ
controller on the 16-bit I/O PC Card requires service by the host software. IREQ
(deasserted) when no interrupt is requested.
Attribute memory select. REG remains high for all common memory accesses. When
REG
is asserted, access is limited to attribute memory (OE or WE active) and to the I/O
space (IORD
card memory and is generally used to record card capacity and other configuration and
attribute information.
F15
DMA acknowledge. REG
operations to a 16-bit PC Card that supports DMA. The controller asserts REG
indicate a DMA operation. REG
DMA write (IORD
C18
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with
F19
each other, determine the operating voltage of the PC Card.
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the
B18
memory or I/O cycle in progress.
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards.
WE
technologies.
DMA terminal count. WE
that supports DMA. The controller asserts WE
operation.
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the
write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for
the 16-bit port (IOIS16
I/O is 16 bits. IOIS16
PC Card when the address on the bus corresponds to an address to which the 16-bit
A18
)
PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations to a
16-bit PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a
request for a DMA operation.
or IOWR active). Attribute memory is a separately accessed section of
is also used for memory PC Cards that employ programmable memory
is used as terminal count (TC) during DMA operations to a
is asserted by a 16-bit I/O PC Card to indicate to the host that a
is used as a DMA acknowledge (DACK) during DMA
) strobes to transfer data.
is used as a TC during DMA operations to a 16-bit PC Card
) function.
applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit
DESCRIPTION
to indicate TC for a DMA
is high
to
is used in conjunction with the DMA read (IOWR) or
to indicate the TC for a DMA read
TYPE
O
I
O
I/O
I
O
I
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RAIL
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
/
/
/
/
/
/
/
/
2−21
Table 2−12. CardBus PC Card Interface System Terminals
I/O
PU/
POWER
I/O
PU/PDPOWER
A 33-Ω to 47-Ω series damping resistor (per PC Card specification) is the only external component needed for
terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then the
terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL
NAME NO. NAME NO.
A_CCLK E09 B_CCLK H18
A_CCLKRUN
A_CRST
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.
C03
A06
B_CCLKRUN
B_CRST
†
CardBus clock. CCLK provides synchronous timing
for all transactions on the CardBus interface. All
signals except CRST
CAUDIO, CCD2
sampled on the rising edge of CCLK, and all timing
parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock
frequency , but it can be stopped in the low state or
slowed down for power savings.
CardBus clock run. CCLKRUN is used by a CardBus
PC Card to request an increase in the CCLK
A18
frequency , and by the controller to indicate that the
CCLK frequency is going to be decreased.
CardBus reset. CRST brings CardBus PC
Card-specific registers, sequencers, and signals to a
known state. When CRST
F17
PC Card signals are placed in a high-impedance
state, and the controller drives these signals to a valid
logic level. Assertion can be asynchronous to CCLK,
but deassertion must be synchronous to CCLK.
DESCRIPTION
, CCLKRUN, CINT, CSTSCHG,
, CCD1, CVS2, and CVS1 are
is asserted, all CardBus
INPUT OUTPUT
TYPE
O PCIO3
I/O PCII4 PCIO4 PU3
O PCII4 PCIO4 PU3
V
V
V
V
V
V
RAIL
CCA
CCB
CCA
CCB
CCA
CCB
/
/
/
2−22
Table 2−13. CardBus PC Card Address and Data Terminals
I/O
POWER
I/O
POWER
External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card
address and data terminal is unused, then the terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL
NAME NO. NAME NO.
A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0
A_CC/BE3
A_CC/BE2
A_CC/BE1
A_CC/BE0
A_CPAR G10 B_CPAR K13
D01
C01
D03
C02
B01
B04
A04
E06
B05
C06
B06
G09
C07
B07
A07
A10
E11
G11
C11
B11
C12
B12
A12
E12
C13
F12
A13
C14
E13
A14
B14
E14
C05
F09
B10
G12
B_CAD31
B_CAD30
B_CAD29
B_CAD28
B_CAD27
B_CAD26
B_CAD25
B_CAD24
B_CAD23
B_CAD22
B_CAD21
B_CAD20
B_CAD19
B_CAD18
B_CAD17
B_CAD16
B_CAD15
B_CAD14
B_CAD13
B_CAD12
B_CAD11
B_CAD10
B_CAD9
B_CAD8
B_CAD7
B_CAD6
B_CAD5
B_CAD4
B_CAD3
B_CAD2
B_CAD1
B_CAD0
B_CC/BE3
B_CC/BE2
B_CC/BE1
B_CC/BE0
†
B15
A16
B16
A17
C16
D17
C19
D18
E17
E19
G15
F18
H14
H15
CardBus address and data. These signals make up the multiplexed
G17
CardBus address and data bus on the CardBus interface. During
K17
the address phase of a CardBus cycle, CAD31−CAD0 contain a
L13
32-bit address. During the data phase of a CardBus cycle,
CAD31−CAD0 contain data. CAD31 is the most significant bit.
K18
L15
L17
L18
L19
M17
M14
M15
N19
N18
N15
M13
P18
P17
P19
CardBus bus commands and byte enables. CC/BE3−CC/BE0 are
multiplexed on the same CardBus terminals. During the address
F15
phase of a CardBus cycle, CC/BE3
command. During the data phase, this 4-bit bus is used as byte
G18
enables. The byte enables determine which byte paths of the full
K14
32-bit data bus carry meaningful data. CC/BE0
M18
(CAD7−CAD0), CC/BE1
CC/BE2
applies to byte 2 (CAD23−CAD16), and CC/BE3 applies to
byte 3 (CAD31−CAD24).
CardBus parity. In all CardBus read and write cycles, the controller
calculates even parity across the CAD and CC/BE
initiator during CardBus cycles, the controller outputs CPAR with a
one-CCLK delay. As a target during CardBus cycles, the controller
compares its calculated parity to the parity indicator of the initiator;
a compare error results in a parity error assertion.
DESCRIPTION
−CC/BE0 define the bus
applies to byte 1 (CAD15−CAD8),
applies to byte 0
buses. As an
TYPE
I/O
I/O
I/O
INPUT OUTPUT
PCII7 PCIO7
PCII7 PCIO7
PCII7 PCIO7
V
V
V
V
V
V
RAIL
CCA
CCB
CCA
CCB
CCA
CCB
/
/
/
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.
2−23
Table 2−14. CardBus PC Card Interface Control Terminals
I/O
PU/
POWER
I/O
PU/PDPOWER
A_CCD1
C15
B_CCD1
N13
CCD2 are used in conjunction with CVS1 and CVS2
A_CCD1
C15
B_CCD1
N13
CCD2 are used in conjunction with CVS1 and CVS2
If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL
NAME NO. NAME NO.
A_CAUDIO A02 B_CAUDIO C17
A_CBLOCK
A_CCD2
A_CDEVSEL
A_CFRAME
A_CGNT
A_CINT
A_CIRDY
A_CPERR
A_CREQ
A_CSERR
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.
E10
E05
C09
C08
B09
C04
B08
F10
E07
B03
B_CBLOCK
B_CCD2
B_CDEVSEL
B_CFRAME
B_CGNT
B_CINT
B_CIRDY
B_CPERR
B_CREQ
B_CSERR
†
CardBus audio. CAUDIO is a digital input signal from
a PC Card to the system speaker. The controller
supports the binary audio mode and outputs a binary
signal from the card to SPKROUT.
CardBus lock. CBLOCK is used to gain exclusive
J19
access to a target.
CardBus detect 1 and CardBus detect 2. CCD1 and
B17
to identify card insertion and interrogate cards to
determine the operating voltage and card type.
CardBus device select. The controller asserts
CDEVSEL
device. As a CardBus initiator on the bus, the
H19
controller monitors CDEVSEL
If no target responds before timeout occurs, then the
controller terminates the cycle with an initiator abort.
CardBus cycle frame. CFRAME is driven by the
initiator of a CardBus bus cycle. CFRAME
to indicate that a bus transaction is beginning, and
G19
data transfers continue while this signal is asserted.
When CFRAME
transaction is in the final data phase.
CardBus bus grant. CGNT is driven by the controller
to grant a CardBus PC Card access to the CardBus
J15
bus after the current data transaction has been
completed.
CardBus interrupt. CINT is asserted low by a CardBus
B19
PC Card to request interrupt servicing from the host.
CardBus initiator ready. CIRDY indicates the ability of
the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed
J13
on a rising edge of CCLK when both CIRDY
CTRDY
are asserted. Until CIRDY and CTRDY are
both sampled asserted, wait states are inserted.
CardBus parity error. CPERR reports parity errors
during CardBus transactions, except during special
J18
cycles. It is driven low by a target two clocks following
the data cycle during which a parity error is detected.
CardBus request. CREQ indicates to the arbiter that
E18
the CardBus PC Card desires use of the CardBus bus
as an initiator.
CardBus system error. CSERR reports address parity
errors and other system errors that could lead to
catastrophic results. CSERR
B18
synchronous to CCLK, but deasserted by a weak
pullup; deassertion may take several CCLK periods.
The controller can report CSERR
assertion of SERR
DESCRIPTION
to claim a CardBus cycle as the target
until a target responds.
is deasserted, the CardBus bus
is driven by the card
to the system by
on the PCI interface.
is asserted
and
INPUT OUTPUT
TYPE
I PCII4 PCIO4 PU3
I/O PCII4 PCIO4 PU3
I TTLI2 PU4
I/O PCII4 PCIO4 PU3
I/O PCII7 PCIO7
O PCII7 PCIO7
I PCII4 PCIO4 PU3
I/O PCII4 PCIO4 PU3
I/O PCII4 PCIO4 PU3
I PCII4 PCIO4 PU3
I PCII4 PCIO4 PU3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RAIL
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
/
/
/
/
/
/
/
/
/
/
2−24
Table 2−14. CardBus PC Card Interface Control Terminals (Continued)
I/O
PU/
POWER
I/O
PU/PDPOWER
SKT A TERMINAL SKT B TERMINAL
NAME NO. NAME NO.
A_CSTOP
A_CSTSCHG
A_CTRDY
A_CVS1
A_CVS2
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.
A09
B02
A08
A03
E08
B_CSTOP
B_CSTSCHG
B_CTRDY
B_CVS1
B_CVS2
†
CardBus stop. CSTOP is driven by a CardBus target
to request the initiator to stop the current CardBus
J17
transaction. CSTOP
and is commonly asserted by target devices that do
not support burst data transfers.
CardBus status change. CSTSCHG alerts the system
to a change in the card status, and is used as a
F14
wake-up mechanism.
CardBus target ready. CTRDY indicates the ability of
the CardBus target to complete the current data
phase of the transaction. A data phase is completed
H17
on a rising edge of CCLK, when both CIRDY
CTRDY
are asserted; until this time, wait states are
inserted.
CardBus voltage sense 1 and CardBus voltage sense
2. CVS1 and CVS2 are used in conjunction with
C18
CCD1
F19
and CCD2 to identify card insertion and
interrogate cards to determine the operating voltage
and card type.
DESCRIPTION
is used for target disconnects,
and
INPUT OUTPUT
TYPE
I/O PCII4 PCIO4 PU3
I PCII6 SW1
I/O PCII1 PCIO1 PU5
I/O TTLI2 TTLO1 PU4
V
V
V
V
V
V
V
V
RAIL
CCA
CCB
CCA
CCB
CCA
CCB
CCA
CCB
/
/
/
/
2−25
TERMINAL
I/O
EXTERNAL
PIN STRAPPING
I/O
EXTERNAL
PIN STRAPPING
signal pins must be matched and as short as possible to the
signal pins must be matched and as short as possible to the
NAME NO.
CNA P15
CPS M11
PC0
PC1
PC2
R0
R1
TPA0P
TPA0N
TPA1P
TPA1N
TPBIAS0
TPBIAS1
TPB0P
TPB0N
TPB1P
TPB1N
XI
XO
R12
U13
V13
U18
U19
V15
W15
V18
W18
U15
U17
V14
W14
V16
W16
R18
R19
Table 2−15. IEEE 1394 Physical Layer Terminals
DESCRIPTION
Cable not active. This terminal is asserted high when there
are no ports receiving incoming bias voltage. If it is not used,
then this terminal must be strapped either to DVDD or GND
through a resistor. The CNA terminal can be disabled by
setting bit 7 (CNAOUT) of the PCI PHY control register at
offset ECh in the PCI configuration space (see Section 7.22,
PCI PHY Control Register). This bit is loaded by the serial
EEPROM. If an EEPROM is implemented and CNA
functionality is needed, then the appropriate bit in the serial
EEPROM must be cleared as defined in Table 3−9.
Cable power status input. This terminal is normally
connected to cable power through a 400-kΩ resistor. This
circuit drives an internal comparator that is used to detect
the presence of cable power. If CPS is not used to detect
cable power, then this terminal must be pulled to GND.
Power class programming inputs. On hardware reset, these
inputs set the default value of the power class indicated
during self-ID. Programming is done by tying these terminals
high or low.
Current-setting resistor terminals. These terminals are
connected to an external resistance to set the internal
operating currents and cable driver output currents. A
resistance of 6.34 kΩ ±1% is required to meet the IEEE Std
1394-1995 output voltage limits.
Twisted-pair cable A differential signal terminals. Board trace
lengths from each pair of positive and negative differential
external load resistors and to the cable connector. For an
unused port, TPA+ and TPA− can be left open.
Twisted-pair bias output. This provides the 1.86-V nominal
bias voltage needed for proper operation of the twisted-pair
cable drivers and receivers and for signaling to the remote
nodes that there is an active cable connection. Each of
these pins must be decoupled with a 1.0-µF capacitor to
ground.
Twisted-pair cable B differential signal terminals. Board trace
lengths from each pair of positive and negative differential
external load resistors and to the cable connector. For an
unused port, TPB+ and TPB− must be pulled to ground.
Crystal oscillator inputs. These pins connect to a
24.576-MHz parallel resonant fundamental mode crystal.
The optimum values for the external shunt capacitors are
dependent on the specifications of the crystal used (see
Section 3.9.2, Crystal Selection). An external clock input can
be connected to the XI terminal. When using an external
clock input, the XO terminal must be left unconnected, and
the clock must be supplied before the controller is taken out
of reset. Refer to Section 3.9.2 for the operating
characteristics of the XI terminal.
INPUT OUTPUT
TYPE
I/O LVCO1 Tie to GND
FT FT
I LVCI1
—
I/O
I/O
I/O
I/O
I/O
—
COMPONENTS
390-kΩ series
resistor to
BUSPOWER if
providing power
through the 1394
port
Pullup resistors if
high. Can be tied
directly to ground
if set to low.
6.34-kΩ ±1%
resistor between
R0 and R1 per
1394 specification
1394 termination
(see reference
schematics)
1394 termination
(see reference
schematics)
1394 termination
(see reference
schematics)
1394 termination
(see reference
schematics)
1394 termination
(see reference
schematics)
24.576-MHz
oscillator (see
implementation
guide)
(IF USED)
Pullup to V
through 1-kΩ
resistor
Tie to GND
Float
Pull directly to
V
CC
Float
Float
Float
Tie to GND
Tie to GND
Tie to GND
Float
CC
2−26
Table 2−16. SD/MMC Terminals
I/O
PU/
POWER
EXTERNAL
I/O
PU/PDPOWER
EXTERNAL
I/O
PU/
POWER
EXTERNAL
I/O
PU/PDPOWER
EXTERNAL
If any SD/MMC terminal is unused, then the terminal may be left floating.
TERMINAL
NAME NO.
MC_PWR_CTRL_0
MC_PWR_CTRL_1
SD_CD E03
SD_CLK J05, G05
SD_CMD J03, F03
SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
SD_WP H07
F01
F02
J02, H05
J01, G03
J06, G02
H03, G01
Media card power control for flash media sockets. O LVCO1
SD/MMC card detect. This input is asserted when
SD/MMC cards are inserted.
SD flash clock. This output provides the SD/MMC
clock, which operates at 16 MHz.
SD flash command. This signal provides the SD
command per the SD Memory Card Specifications.
SD flash data [3:0]. These signals provide the SD
data path per the SD Memory Card Specifications.
SD write protect data. This signal indicates that the
media inserted in the socket is write protected.
DESCRIPTION
INPUT OUTPUT
TYPE
I LVCI1 PU2 V
I/O TTLO2 SW2 V
I/O TTLI2 TTLO2 SW2 V
I/O TTLI2 TTLO2 SW2 V
I TTLI2 SW2 V
Table 2−17. Memory Stick/PRO Terminals
If any Memory Stick/PRO terminal is unused, then the terminal may be left floating.
TERMINAL
NAME NO.
MC_PWR_CTRL_0
MC_PWR_CTRL_1
MS_BS F03
MS_CD F05
MS_CLK G05
MS_DATA3
MS_DATA2
MS_DATA1
MS_SDIO (DATA0) G01
F01
F02
H05
G03
G02
Media card power control for flash media sockets. O LVCO1
Memory Stick bus state. This signal provides Memory
Stick bus state information.
Media Card detect. This input is asserted when a
Memory Stick or Memory Stick Pro media is inserted.
Memory Stick clock. This output provides the MS clock,
which operates at 16 MHz.
Memory Stick data [3:1]. These signals provide the
Memory Stick data path.
Memory Stick serial data I/O. This signal provides
Memory Stick data input/output. Memory Stick data 0.
DESCRIPTION
INPUT OUTPUT
TYPE
I/O TTLO2 SW2 V
I LVCI1 PU2 V
I/O TTLO2 SW2 V
I/O TTLI2 TTLO2 SW2 V
I/O TTLI2 TTLO2 SW2 V
RAIL
CC
CC
CC
CC
CC
RAIL
CC
CC
CC
CC
CC
COMPONENTS
Power switch or
FET to turn power
on to FM socket
COMPONENTS
Power switch or
FET to turn power
on to FM socket
2−27
Table 2−18. Smart Media/XD Terminals
I/O
PU/
POWER
EXTERNAL
I/O
PU/PDPOWER
EXTERNAL
If any Smart Media/XD terminal is unused, then the terminal may be left floating.
TERMINAL
NAME NO.
MC_PWR_CTRL_0
MC_PWR_CTRL_1
SM_ALE J03
SM_CD F06
SM_CE H07
SM_CLE J07
SM_D7
SM_D6
SM_D5
SM_D4
SM_D3
SM_D2
SM_D1
SM_D0
SM_EL_WP G05 SmartMedia electrical write protect. O TTLO2 SW2 V
SM_PHYS_WP K02
SM_RE J05
SM_R/B K01
SM_WE F03
F01
Media card power control for flash media sockets. O LVCO1
F02
SmartMedia address latch enable. This signal
functions as specified in the SmartMedia
specification, and is used to latch addresses
passed over SM_D7−SM_D0.
SmartMedia card detect. This input is asserted
when SmartMedia cards are inserted.
SmartMedia card enable. This signal functions as
specified in the SmartMedia specification, and is
used to enable the media for a pending
transaction.
SmartMedia command latch enable. This signal
functions as specified in the SmartMedia
specification, and is used to latch commands
passed over SM_D7−SM_D0.
J02
J01
J06
SmartMedia data terminals. These signals pass
H03
data to and from the SmartMedia, and functions
H05
as specified in the SmartMedia specifications.
G03
G02
G01
SmartMedia physical write protect. This input
comes from the write protect tab of the
SmartMedia card.
SmartMedia read enable. This signal functions as
specified in the SmartMedia specification, and is
used to latch a read transfer from the card.
SmartMedia read/busy. This signal functions as
specified in the SmartMedia specification, and is
used to pace data transfers to the card.
SmartMedia write enable. This signal functions as
specified in the SmartMedia specification, and is
used to latch a write transfer to the card.
DESCRIPTION
INPUT OUTPUT
TYPE
O TTLO2 SW2 V
I LVCI1 PU2 V
O TTLO2 SW2 V
O TTLO2 SW2 V
I/O TTLI2 TTLO2 SW2 V
I PCII5 PCIO5 SW3
O TTLO2 SW2 V
I PCII5 PCIO5 SW3 V
O TTLO2 SW2 V
RAIL
CC
CC
CC
CC
CC
CC
CC
CC
CC
PARTS
Power switch or
FET to turn power
on to FM socket
2−28
Table 2−19. Smart Card Terminals
I/O
PU/
POWER
EXTERNAL
I/O
PU/PDPOWER
EXTERNAL
†
If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be
connected to 5 V.
TERMINAL
NAME NO.
SC_CD L02
SC_CLK K05
SC_DATA L01 Smart Card data input/output I/O PCII5 PCIO5 SW3
SC_OC L03
SC_PWR_CTRL L05 Smart Card power control for the Smart Card socket. O LVCO1
SC_FCB K02
SC_GPIO6
SC_GPIO5
SC_GPIO4
SC_GPIO3
SC_GPIO2
SC_GPIO1
SC_GPIO0
SC_RFU K01
SC_RST K03
SC_VCC_5V K07 Smart Card power terminal PWR
†
These terminals are reserved for the PCI7421 and PCI7411 controllers.
Smart Card card detect. This input is asserted when Smart
Cards are inserted.
Smart Card clock. The controller drives a 3-MHz clock to the
Smart Card interface when enabled.
Smart Card overcurrent. This input comes from the Smart
Card power switch.
Smart Card function code. The controller does not support
synchronous Smart Cards as specified in ISO/IEC 7816-10,
and this terminal is in a high-impedance state.
H03
J06
Smart Card general-purpose I/O terminals. These signals
J01
can be controlled by firmware and are used as control
J02
signals for an external Smart Card interface chip or level
J03
shifter.
J05
J07
Smart Card reserved. This terminal is in a high-impedance
state.
Smart Card This signal starts and stops the Smart Card
reset sequence. The controller asserts this reset when
requested by the host.
DESCRIPTION
INPUT OUTPUT
TYPE
I TTLI2 SW2 VCC
O PCIO8
I LVCI1 PU2 5 V
I PCII5 PCIO5 SW3
I/O TTLI2 TTLO2 SW2 5 V
I PCII5 PCIO5 SW3 5 V
O PCIO6
RAIL
PARTS
22 kΩ resistor to
GND
68 pF capacitor
to GND
Power switch or
FET to turn on
power to FM
socket
1 kΩ resistor to
5 V
2−29
2−30
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI7x21/PCI7x11 controller. Figure 3−1 shows the connections to the
PCI7x21/PCI7x11 controller. The PCI interface includes all address/data and control signals for PCI protocol. The
interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
PCI Bus
EEPROM
1394a
Socket
PC
Card/
UltraMedia
Card
PCI7x21/
PCI7x11
Power
Switch
SD/MMC
MS/MSPRO
SM/xD
SD/MMC
PC
Card/
UltraMedia
Card
Power Switch
Power Switch
Figure 3−1. PCI7x21/PCI7x11 System Block Diagram
3.1 Power Supply Sequencing
The PCI7x21/PCI7x11 controller contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and
clamp voltages. The core power supply is always 1.5 V. The clamp voltages can be either 3.3 V or 5 V, depending
on the interface. The following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Power core 1.5 V.
2. Apply the I/O voltage.
3. Apply the analog voltage.
4. Apply the clamp voltage.
The power-down sequence is:
1. Remove the clamp voltage.
2. Remove the analog voltage.
3. Remove the I/O voltage.
4. Remove power from the core.
NOTE: If the voltage regulator is enabled, then steps 2, 3, and 4 of the power-up sequence
and steps 1, 2, and 3 of the power-down sequence all occur simultaneously.
3−1
3.2 I/O Characteristics
The PCI7x21/PCI7x11 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local
Bus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 14.2, Recommended Operating
Conditions, provides the electrical characteristics of the inputs and outputs.
V
Tied for Open Drain
OE
CCP
Pad
Figure 3−2. 3-State Bidirectional Buffer
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI7x21/PCI7x11 controller is interfaced
with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from
external signals. The core power supply is 1.5 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI7x21/PCI7x11 controller must reliably accommodate both voltage
levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage
applied. If a system designer desires a 5-V PCI bus, then V
can be connected to a 5-V power supply.
CCP
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI7x21/PCI7x11 controller is fully compliant with the PCI Local Bus Specification. The PCI7x21/PCI7x11
controller provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V
signaling environment by connecting the V
PCI signals, the PCI7x21/PCI7x11 controller provides the optional interrupt signals INTA
terminals to the desired voltage level. In addition to the mandatory
CCP
, INTB, INTC, and INTD.
3.4.1 1394 PCI Bus Master
As a bus master, the 1394 function of the PCI7x21/PCI7x11 controller supports the memory commands specified in
Table 3−1. The PCI m a s t er s u pp o rts the memory read, memory read line, and memory read multiple commands. The
read command usage for read transactions of greater than two data phases are determined by the selection in bits
9−8 (MR_ENHANCE field) of the PCI miscellaneous configuration register (refer to Section 7.23 for details). For read
transactions of one or two data phases, a memory read command is used.
Table 3−1. PCI Bus Support
PCI
Memory read 0110 DMA read from memory
Memory write 0111 DMA write to memory
Memory read multiple 1100 DMA read from memory
Memory read line 1110 DMA read from memory
Memory write and invalidate 1111 DMA write to memory
COMMAND
C/BE3
−C/BE0
OHCI MASTER FUNCTION
3−2
3.4.2 Device Resets
The following are the requirements for proper reset of the PCI7x21/PCI7x11 controller:
1. GRST
2. GRST
3. PRST
4. PCLK must be stable for 100 µs before PRST
VCC
GRST
PRST
and PRST must both be asserted at power on.
must be asserted for at least 2 ms at power on
must be deasserted either at the same time or after GRST is asserted
is deasserted.
> 2 ms > 0 ns
PCLK
> 100 ms
Figure 3−3. PCI Reset Requirement
3.4.3 Serial EEPROM I2C Bus
The PCI7x21/PCI7x11 controller offers many choices for modes of operation, and these choices are selected by
programming several configuration registers. For system board applications, these registers are normally
programmed through the BIOS routine. For add-in card and docking-station/port-replicator applications, the
PCI7x21/PCI7x11 controller provides a two-wire inter-integrated circuit (IIC or I
serial EEPROM.
The PCI7x21/PCI7x1 1 controller is always the bus master, and the EEPROM is always the slave. Either device can
drive the bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors
on the SCL and SDA signal lines. The PCI7x21/PCI7x11 controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and
SDA terminals. If the PCI7x21/PCI7x11 controller detects a logic-high level on the SCL terminal at the end of GRST
then it initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I
can be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the PCI7x21/PCI7x11
controller. Figure 3−3 shows a serial EEPROM application.
In addition to loading configuration data from an EEPROM, the PCI7x21/PCI7x11 I
write from other I
2
C serial devices. A system designer can control the I2C bus, using the PCI7x21/PCI7x1 1 controller
2
C) serial bus for use with an external
2
C limit of 16 Kbits
2
C bus can be used to read and
,
3−3
as bus master, by reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus
control/status register (PCI offset B3h, see Section 4.50) causes the PCI7x21/PCI7x11 controller to route the SDA
and SCL signals to the SDA and SCL terminals, respectively. The read/write data, slave address, and byte addresses
are manipulated by accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets
B0h, B1h, and B2h; see Sections 4.47, 4.48, and 4.49, respectively).
EEPROM interface status information is communicated through the serial bus control and status register (PCI offset
B3h, see Section 4.50). Bit 3 (SBDETECT) in this register indicates whether or not the PCI7x21/PCI7x11 serial ROM
circuitry detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit
0 (ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface
is busy).
The subsystem vendor ID for functions 2 and 3 is also loaded through EEPROM. The EEPROM load data goes to
all four functions from the serial EEPROM loader.
V
CC
Serial
ROM
A0
A1A2SCL
SDA
SCL
SDA
PCI7x21/PCI7x11
Figure 3−4. Serial ROM Application
3.4.4 Functions 0 and 1 (CardBus) Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see
Section 4.27) make up a doubleword of PCI configuration space for functions 0 and 1. This doubleword register is
used for system and option card (mobile dock) identification purposes and is required by some operating systems.
Implementation of this unique identifier register is a PC 99/PC 2001 requirement.
The PCI7x21/PCI7x11 controller of fers two mechanisms to load a read-only value into the subsystem registers. The
first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control
register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification
value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor
ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of
implementing the serial electrically erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The PCI7x21/PCI7x11 controller loads the data from
the serial EEPROM after a reset of the primary bus. Note that the SUSPEND
PCI7x21/PCI7x11 core, including the serial-bus state machine (see Section 3.8.6, Suspend Mode, for details on
using SUSPEND
).
The PCI7x21/PCI7x11 controller provides a two-line serial-bus host controller that can interface to a serial EEPROM.
See Section 3.6, Serial EEPROM Interface,
for details on the two-wire serial-bus controller and applications.
input gates the PCI reset from the entire
3−4
3.4.5 Function 2 (OHCI 1394) Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI
configuration space (see Section 7.25, Subsystem Access Register). See Table 7−22 for a complete description of
the register contents.
Write access to the subsystem access register updates the subsystem identification registers identically to
OHCI-Lynx. The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem
ID registers at Function 2 PCI offsets 2Ch and 2Eh, respectively. The system ID value written to this register may also
be read back from this register. See Table 7−22 for a complete description of the register contents.
3.4.6 Function 3 (Flash Media) Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI
configuration space (see Section 11.22, Subsystem Access Register). See Table 11−15 for a complete description
of the register contents.
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at Function 3 PCI offsets 2Ch and 2Eh, respectively. See Table 11−15 for a complete description of the register
contents.
3.4.7 Function 4 (SD Host) Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset 8Ch in the PCI
configuration space (see Section 12.23, Subsystem Access Register). See Table 12−16 for a complete description
of the register contents.
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at Function 4 PCI offsets 2Ch and 2Eh, respectively. See Table 12−16 for a complete description of the register
contents.
3.4.8 Function 5 (Smart Card) Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI
configuration space (see Section 13.23, Subsystem ID Alias Register). See Table 13−14 for a complete description
of the register contents.
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at Function 5 PCI offsets 2Ch and 2Eh, respectively. See Table 13−14 for a complete description of the register
contents.
3.5 PC Card Applications
The PCI7x21/PCI7x11 controller supports all the PC Card features and applications as described below.
• Card insertion/removal and recognition per the PC Card Standard (release 8.1)
• Speaker and audio applications
• LED socket activity indicators
• PC Card controller programming model
• CardBus socket registers
3−5
3.5.1 PC Card Insertion/Removal and Recognition
The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface.
3.5.2 Low Voltage CardBus Card Detection
The card detection logic of the PCI7x21/PCI7x11 controller includes the detection of Cardbus cards with VCC = 3.3
V and V
present state register as follows based on bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see
Section 4.31):
= 1.8 V. The reporting of the 1.8-V CardBus card (VCC = 3.3 V , VPP = 1.8 V) is reported through the socket
PP
• If the 12V_SW_SEL bit is 0 (TPS2228 is used), then the 1.8-V CardBus card causes the 3VCARD bit in the
socket present state register to be set.
• If the 12V_SW_SEL bit is 1 (TPS2226 is used), then the 1.8-V CardBus card causes the XVCARD bit in
the socket present state register to be set.
3.5.3 UltraMedia Card Detection
The PCI7x21/PCI7x11 controller is capable of detecting all the UltraMedia devices defined by the PCMCIA Proposal
0262 – MultiMedia Cards, Secure Digital, Memory Stick devices, and Smart Card devices. The detection of these
devices is made possible through circuitry included in the PCI7x21/PCI7x11 controller and the adapters used to
interface these devices with the PC Card/CardBus sockets. No additional hardware requirements are placed on the
system designer in order to support these devices.
The PC Card Standard addresses the card detection and recognition process through an interrogation procedure that
the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage
requirements and interface type (16-bit vs. CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2
signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four terminals in a certain
configuration to indicate the type of card and its supply voltage requirements. The encoding scheme for this, defined
in the PC Card Standard, is shown in Table 3−2.
3−6
Table 3−2. PC Card—Card Detect and Voltage Sense Connections
CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface V
Ground Ground Open Open 5 V 16-bit PC Card 5 V Per CIS (VPP)
Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Per CIS (VPP)
Ground Ground Ground Ground 5 V 16-bit PC Card
Ground Ground Open Ground LV 16-bit PC Card 3.3 V Per CIS (VPP)
Ground
Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Per CIS (VPP)
Connect to
CVS2
Connect to
CVS1
Ground Ground Ground Open LV 16-bit PC Card X.X V Per CIS (VPP)
Connect to
CVS2
Ground
Connect to
CVS1
Ground
Ground
Connect to
CVS1
Ground
Ground Ground
Ground
Connect to
CVS2
Ground Open
Connect to
CVS1
Connect to
CVS2
Open
Connect to
CCD2
Connect to
CCD2
Connect to
CCD1
Ground
Connect to
CCD1
Connect to
CCD1
Ground LV CardBus PC Card 3.3 V and X.X V Per CIS (VPP)
Connect to
CCD2
Open LV CardBus PC Card 3.3 V 1.8 V (V
Open LV CardBus PC Card X.X V and Y.Y V Per CIS (VPP)
Connect to
CCD2
Connect to
CCD1
Ground Reserved Reserved
LV CardBus PC Card 3.3 V Per CIS (VPP)
LV CardBus PC Card
LV CardBus PC Card Y.Y V Per CIS (VPP)
LV UltraMedia Per query terminals
CC
5 V, 3.3 V, and
X.X V
3.3 V, X.X V,
and Y.Y V
VPP/V
CORE
Per CIS (VPP)
Per CIS (VPP)
CORE
)
3.5.4 Flash Media Card Detection
The PCI7x21/PCI7x11 controller detects an MMC/SD card insertion through the MC_CD_0 terminal. When this
terminal is 0, an MMC/SD card is inserted in the socket. The PCI7x21/PCI7x1 1 controller debounces the MC_CD_0
signal such that instability of the signal does not cause false card insertions. The debounce time is approximately 50
ms. The MC_CD_0
card detection and power control logic.
The MMC/SD card detection and power control logic contains three main states:
• Socket empty, power off
• Card inserted, power off
• Card inserted, power on
The PCI7x21/PCI7x11 controller detects a Memory Stick card insertion through the MC_CD_1
terminal is 0, a Memory Stick card is inserted in the socket. The PCI7x21/PCI7x11 controller debounces the
MC_CD_1
signal such that instability of the signal does not cause false card insertions. The debounce time is
approximately 50 ms. The MC_CD_1
in the Memory Stick card detection and power control logic.
The Memory Stick card detection and power control logic contains three main states:
• Socket empty, power off
• Card inserted, power off
• Card inserted, power on
signal is not debounced on card removals. The filtered MC_CD_0 signal is used in the MMC/SD
terminal. When this
signal is not debounced on card removals. The filtered MC_CD_1 signal is used
3−7
3.5.5 Power Switch Interface
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
The power switch interface of the PCI7x21/PCI7x11 controller is a 3-pin serial interface. This 3-pin interface is
implemented such that the PCI7x21/PCI7x11 controller can connect to both the TPS2226 and TPS2228 power
switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.31) selects the power
switch that is implemented. The PCI7x21/PCI7x1 1 controller defaults to use the control logic for the TPS2228 power
switch. See Table 3−3 and Table 3−6 below for the power switch control logic.
Table 3−3. TPS2228 Control Logic—xVPP/VCORE
AVPP/VCORE CONTROL SIGNALS
D8(SHDN) D0 D1 D9
1 0 0 X 0 V 1 0 0 X 0 V
1 0 1 0 3.3 V 1 0 1 0 3.3 V
1 0 1 1 5 V 1 0 1 1 5 V
1 1 0 X Hi-Z 1 1 0 X Hi-Z
1 1 1 0 Hi-Z 1 1 1 0 Hi-Z
1 1 1 1 1.8 V 1 1 1 1 1.8 V
0 X X X Hi-Z 0 X X X Hi-Z
OUTPUT
V_AVPP/VCORE
BVPP/VCORE CONTROL SIGNALS
D8(SHDN) D4 D5 D10
Table 3−4. TPS2228 Control Logic—xVCC
AVCC CONTROL SIGNALS
D8(SHDN) D3 D2
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z
OUTPUT
V_AVCC
BVCC CONTROL SIGNALS
D8(SHDN) D6 D7
Table 3−5. TPS2226 Control Logic—xVPP
AVPP CONTROL SIGNALS
D8(SHDN) D0 D1 D9
1 0 0 X 0 V 1 0 0 X 0 V
1 0 1 0 3.3 V 1 0 1 0 3.3 V
1 0 1 1 5 V 1 0 1 1 5 V
1 1 0 X 12 V 1 1 0 X 12 V
1 1 1 X Hi-Z 1 1 1 X Hi-Z
0 X X X Hi-Z 0 X X X Hi-Z
OUTPUT
V_AVPP
BVPP CONTROL SIGNALS
D8(SHDN) D4 D5 D10
Table 3−6. TPS2226 Control Logic—xVCC
AVCC CONTROL SIGNALS
D8(SHDN) D3 D2
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi-Z 0 X X Hi-Z
OUTPUT
V_AVCC
BVCC CONTROL SIGNALS
D8(SHDN) D6 D7
OUTPUT
V_BVPP/VCORE
OUTPUT
V_BVCC
OUTPUT
V_BVPP
OUTPUT
V_BVCC
3.5.6 Internal Ring Oscillator
The internal ring oscillator provides an internal clock source for the PCI7x21/PCI7x11 controller so that neither the
PCI clock nor an external clock is required in order for the PCI7x21/PCI7x11 controller to power down a socket or
interrogate a PC Card. This internal oscillator, operating nominally at 16 kHz, is always enabled.
3−8
3.5.7 Integrated Pullup Resistors for PC Card Interface
The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card
configurations. The PCI7x21/PCI7x11 controller has integrated all of these pullup resistors and requires no additional
external components. The I/O buffer on the BVD1(STSCHG
)/CSTSCHG terminal has the capability to switch to an
internal pullup resistor when a 16-bit PC Card is inserted, or switch to an internal pulldown resistor when a CardBus
card is inserted. This prevents inadvertent CSTSCHG events. The pullup resistor requirements for the various
UltraMedia interfaces are either included in the UltraMedia cards (or the UltraMedia adapter) or are part of the existing
PCMCIA architecture. The PCI7x21/PCI7x11 controller does not require any additional components for UltraMedia
support.
3.5.8 SPKROUT and CAUDPWM Usage
The SPKROUT terminal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is
configured for I/O mode, the BVD2 terminal becomes the SPKR
CardBus applications, is referred to as CAUDIO. SPKR
PCI7x21/PCI7x11 controller. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform as well
as a PWM signal. The binary audio signal from each PC Card sockets is enabled by bit 1 (SPKROUTEN) of the card
control register (PCI offset 91h, see Section 4.38).
Older controllers support CAUDIO in binary or PWM mode, but use the same output terminal (SPKROUT). Some
audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM.
The PCI7x21/PCI7x11 implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC
terminal. Bit 2 (AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM
terminal to CAUDPWM. See Section 4.36, Multifunction Routing Register, for details on configuring the MFUNC
terminals.
input terminal from the card. This terminal, in
passes a TTL-level binary audio signal to the
Figure 3−5 illustrates the SPKROUT connection.
System
Core Logic
BINARY_SPKR
Speaker
Subsystem
PWM_SPKR
PCI7x21/
PCI7x11
SPKROUT
CAUDPWM
Figure 3−5. SPKROUT Connection to Speaker Driver
3.5.9 LED Socket Activity Indicators
The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LEDA1 and LEDA2 signals
can be routed to the multifunction terminals. When configured for LED outputs, these terminals output an active high
signal to indicate socket activity . LEDA1 indicates socket A (card A) activity, and LEDA2 indicates socket B (card B)
activity. The LED_SKT output indicates socket activity to either socket A or socket B. See Section 4.36, Multifunction
Routing Status Register,
The active-high LED signal is driven for 64 ms. When the LED is not being driven high, it is driven to a low state. Either
of the two circuits shown in Figure 3−6 can be implemented to provide LED signaling, and the board designer must
implement the circuit that best fits the application.
The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signals are pulsed when READY(IREQ
IRDY
, or CREQ are active.
for details on configuring the multifunction terminals.
) is low. For CardBus cards, the LED activity signals are pulsed if CFRAME,
3−9
Current Limiting
R ≈ 150 Ω
Socket A
LED
Socket B
LED
PCI7x21/
PCI7x11
MFUNCx
Current Limiting
R ≈ 150 Ω
MFUNCy
Figure 3−6. Two Sample LED Circuits
As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND
signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.
3.5.10 CardBus Socket Registers
The PCI7x21/PCI7x1 1 controller contains all registers for compatibility with the PCI Local Bus Specification and the
PC Card Standard. These registers, which exist as the CardBus socket registers, are listed in Table 3−7.
Table 3−7. CardBus Socket Registers
REGISTER NAME OFFSET
Socket event 00h
Socket mask 04h
Socket present state 08h
Socket force event 0Ch
Socket control 10h
Reserved 14h−1Ch
Socket power management 20h
3.5.11 48-MHz Clock Requirements
The PCI7x21/PCI7x11 controller is designed to use an external 48-MHz clock connected to the CLK_48 terminal to
provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the
various clocks required for the flash media function (Function 3) of the PCI7x21/PCI7x11 controller.
The 48-MHz clock is needed as follows in the designated states:
• Power−up Follow the power-up sequence
• D0: Clock must not be stopped
• D1/D2/D3: Clock can be stopped
• D1/D2/D3
• D3
cold
The 48-MHz clock must maintain a frequency of 48 MHz ± 0.8% over normal operating conditions. This clock must
maintain a duty cycle of 40% − 60%. The PCI7x21/PCI7x11 controller requires that the 48-MHz clock be running and
stable (a minimum of 10 clock pulses) before a GRST
The following are typical specifications for crystals used with the PCI7x21/PCI7x11 controller in order to achieve the
required frequency accuracy and stability.
• Crystal mode of operation: Fundamental
• Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with
±30 ppm frequency tolerance is recommended for adequate margin.
to D0: Need 10 clocks before D0 state
hot
to D0: Need 10 clocks before PRST de-assert
deassertion.
3−10
• Frequency stability (overtemperature and age): A crystal with ±30 ppm frequency stability is recommended
for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between frequency
tolerance and stability may be made as long as the total frequency variation is less than
±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and
the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible
variation due to the crystal alone. Crystal aging also contributes to the frequency variation.
3.6 Serial EEPROM Interface
The PCI7x21/PCI7x11 controller has a dedicated serial bus interface that can be used with an EEPROM to load
certain registers in the PCI7x21/PCI7x11 controller. The EEPROM is detected by a pullup resistor on the SCL
terminal. See Table 3−9 for the EEPROM loading map.
3.6.1 Serial-Bus Interface Implementation
The PCI7x21/PCI7x11 controller drives SCL at nearly 100 kHz during data transfers, which is the maximum specified
frequency for standard mode I
2
C. The serial EEPROM must be located at address A0h.
Some serial device applications may include PC Card power switches, card ejectors, or other devices that may
enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed
in the sections that follow.
3.6.2 Accessing Serial-Bus Devices Through Software
The PCI7x21/PCI7x11 controller provides a programming mechanism to control serial bus devices through software.
The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−8 lists
the registers used to program a serial-bus device through software.
Table 3−8. PCI7x21/PCI7x11 Registers Used to Program Serial-Bus Devices
PCI OFFSET REGISTER NAME DESCRIPTION
B0h Serial-bus data Contains the data byte to send on write commands or the received data byte on read commands.
B1h Serial-bus index
B2h
B3h
Serial-bus slave
address
Serial-bus control
and status
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
Write transactions to this register initiate a serial-bus transaction. The slave device address and the
R/W
command selector are programmed through this register.
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol-select bit is programmed through this register.
3.6.3 Serial-Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−4.
The PCI7x21/PCI7x11 controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode
2
I
C using 7-bit addressing.
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as shown
in Figure 3−7. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high
transition of SDA while SCL is in the high state, as shown in Figure 3−7. Data on SDA must remain stable during the
high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control
signals, that is, a start or a stop condition.
3−11
SDA
SCL
Start
Condition
Stop
Condition
Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 3−7. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−8
illustrates the acknowledge protocol.
SCL From
Master
SDA Output
By Transmitter
SDA Output
By Receiver
123 789
Figure 3−8. Serial-Bus Protocol Acknowledge
The PCI7x21/PCI7x11 controller is a serial bus master; all other devices connected to the serial bus external to the
PCI7x21/PCI7x11 controller are slave devices. As the bus master, the PCI7x21/PCI7x11 controller drives the SCL
clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle
states.
Typically, the PCI7x21/PCI7x11 controller masters byte reads and byte writes under software control. Doubleword
reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under
software control. See Section 3.6.4, Serial-Bus EEPROM Application, for details on how the PCI7x21/PCI7x11
controller automatically loads the subsystem identification and other register defaults through a serial-bus EEPROM.
Figure 3−9 illustrates a byte write. The PCI7x21/PCI7x11 controller issues a start condition and sends the 7-bit slave
device address and the command bit zero. A 0 in the R/W
command bit indicates that the data transfer is a write. The
slave device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI7x21/PCI7x1 1
controller, then an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see
Section 4.50). The word address byte is then sent by the PCI7x21/PCI7x11 controller, and another slave
acknowledgment is expected. Then the PCI7x21/PCI7x11 controller delivers the data byte MSB first and expects a
final acknowledgment before issuing the stop condition.
Slave Address Word Address
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
R/W
S/P = Start/Stop ConditionA = Slave Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 A P
Data Byte
Figure 3−9. Serial-Bus Protocol—Byte Write
3−12
Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command
bit must be set to 1 to indicate a read-data transfer. In addition, the PCI7x21/PCI7x11 master must acknowledge
reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data
transfers. The SCL signal remains driven by the PCI7x21/PCI7x11 master.
Slave Address Word Address
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Start
A = Slave Acknowledgement
R/W
Sb6 b4b5 b3 b2 b1 b0 1 A
Restart R/W
b7 b6 b4b5 b3 b2 b1 b0 M P
S/P = Start/Stop ConditionM = Master Acknowledgement
Slave Address
Data Byte
Figure 3−10. Serial-Bus Protocol—Byte Read
Figure 3−11 illustrates EEPROM interface doubleword data collection protocol.
Slave Address Word Address
S1 10 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Start
Data Byte 3 M
R/W
Data Byte 2 Data Byte 1 Data Byte 0 M PMM
M = Master Acknowledgement S/P = Start/Stop ConditionA = Slave Acknowledgement
S1 10 00001A
Restart
Slave Address
Stop
R/W
Figure 3−11. EEPROM Interface Doubleword Data Collection
3.6.4 Serial-Bus EEPROM Application
When the PCI bus is reset and the serial-bus interface is detected, the PCI7x21/PCI7x1 1 controller attempts to read
the subsystem identification and other register defaults from a serial EEPROM.
This format must be followed for the PCI7x21/PCI7x1 1 controller to load initializations from a serial EEPROM. All bit
fields must be considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the PCI7x21/PCI7x11 controller. All hardware
address bits for the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip
in the sample application (Figure 3−11) assumes the 1010b high-address nibble. The lower three address bits are
terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.
3−13
Table 3−9. EEPROM Loading Map
SERIAL ROM
OFFSET
00h CardBus function indicator (00h)
01h Number of bytes (20h)
PCI 04h, command register, function 0, bits 8, 6−5, 2−0
02h [7]
Command
register, bit 8
03h [7]
Command
register, bit 8
04h PCI 40h, subsystem vendor ID, byte 0
05h PCI 41h, subsystem vendor ID, byte 1
06h PCI 42h, subsystem ID, byte 0
07h PCI 43h, subsystem ID, byte 1
08h PCI 44h, PC Card 16-bit I/F legacy mode base address register, byte 0, bits 7−1
09h PCI 45h, PC Card 16-bit I/F legacy mode base address register, byte 1
0Ah PCI 46h, PC Card 16-bit I/F legacy mode base address register, byte 2
0Bh PCI 47h, PC Card 16-bit I/F legacy mode base address register, byte 3
0Ch PCI 80h, system control, function 0, byte 0, bits 6−0
0Dh PCI 80h, system control, function 1, byte 0, bit 2
0Eh PCI 81h, system control, byte 1, bits 7,6
0Fh Reserved nonloadable (PCI 82h, system control, byte 2)
10h PCI 83h, system control, byte 3, bits 7−2, 0
11h PCI 8Ch, MFUNC routing, byte 0
12h PCI 8Dh, MFUNC routing, byte 1
13h PCI 8Eh, MFUNC routing, byte 2
14h PCI 8Fh, MFUNC routing, byte 3
15h PCI 90h, retry status, bits 7, 6
16h PCI 91h, card control, bit 7
17h PCI 92h, device control, bits 6, 5, 3−0 (bit 0 must be programmed to 0)
18h PCI 93h, diagnostic, bits 4−0
19h PCI A2h, power-management capabilities, function 0, bit 15 (bit 7 of EEPROM offset 16h corresponds to bit 15)
1Ah PCI A2h, power-management capabilities, function 1, bit 15 (bit 7 of EEPROM offset 16h corresponds to bit 15)
1Bh CB Socket + 0Ch, function 0 socket force event, bit 27 (bit 3 of EEPROM offset 17h corresponds to bit 27)
1Ch CB Socket + 0Ch, function 1 socket force event, bit 27 (bit 3 of EEPROM offset 18h corresponds to bit 27)
1Dh ExCA 00h, ExCA identification and revision, bits 7−0
1Eh PCI 86h, general control, byte 0, bits 7−0
1Fh PCI 87h, general control, byte 1, bits 7, 6 (can only be set to 1 if bits 1:0 = 01), 4−0
20h PCI 89h, GPE enable, bits 7, 6, 4−0
21h PCI 8Bh, general-purpose output, bits 4−0
22h 1394 OHCI function indicator (02h)
23h Number of bytes (17h)
24h PCI 3Fh, maximum latency bits 7−4 PCI 3Eh, minimum grant, bits 3−0
[6]
Command
register, bit 6
[6]
Command
register, bit 6
Command
register, bit 5
PCI 04h, command register, function 1, bits 8, 6−5, 2−0
Command
register, bit 5
BYTE DESCRIPTION
[5]
[5]
[4:3]
RSVD
[4:3]
RSVD
[2]
Command
register, bit 2
[2]
Command
register, bit 2
[1]
Command
register, bit 1
[1]
Command
register, bit 1
[0]
Command
register, bit 0
[0]
Command
register, bit 0
3−14
Table 3−9. EEPROM Loading Map (Continued)
SERIAL ROM
OFFSET
25h PCI 2Ch, subsystem vendor ID, byte 0
26h PCI 2Dh, subsystem vendor ID, byte 1
27h PCI 2Eh, subsystem ID, byte 0
28h PCI 2Fh, subsystem ID, byte 1
29h PCI F4h, Link_Enh, byte 0, bits 7, 2, 1
OHCI 50h, host controller control, bit 23
[7]
Link_Enh.
enab_unfair
2Ah Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM
2Bh OHCI 24h, GUIDHi, byte 0
2Ch OHCI 25h, GUIDHi, byte 1
2Dh OHCI 26h, GUIDHi, byte 2
2Eh OHCI 27h, GUIDHi, byte 3
2Fh OHCI 28h, GUIDLo, byte 0
30h OHCI 29h, GUIDLo, byte 1
31h OHCI 2Ah, GUIDLo, byte 2
32h OHCI 2Bh, GUIDLo, byte 3
33h Checksum (Reserved—no bit loaded)
34h PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4
35h PCI F0h, PCI miscellaneous, byte 0, bits 5, 4, 2, 1, 0
36h PCI F1h, PCI miscellaneous, byte 1, bits 7, 3, 2, 1, 0
37h Reserved
38h Reserved (CardBus CIS pointer)
39h Reserved
3Ah PCI ECh, PCI PHY control, bits 7, 3, 1
3Bh Flash media core function indicator (03h)
3Ch Number of bytes (05h)
3Dh PCI 2Ch, subsystem vendor ID, byte 0
3Eh PCI 2Dh, subsystem vendor ID, byte 1
3Fh PCI 2Eh, subsystem ID, byte 0
40h PCI 2Fh, subsystem ID, byte 1
41h PCI 4Ch, general control, bits 6−4, 2−0
42h SD host controller function indicator (03h)
43h Number of bytes (0Bh)
44h PCI 2Ch, subsystem vendor ID, byte 0
45h PCI 2Dh, subsystem vendor ID, byte 1
46h PCI 2Eh, subsystem ID, byte 0
47h PCI 2Fh, subsystem ID, byte 1
48h PCI 88h, general control bits 6−4, 0
HCControl.Program Phy Enable
[6]
BYTE DESCRIPTION
[5:3]
RSVD
00h = No MINI ROM
Other Values = MINI ROM offset
Link_Enh, bit 2
[2]
[1]
Link_Enh.
enab_accel
[0]
RSVD
3−15
Table 3−9. EEPROM Loading Map (Continued)
SERIAL ROM
OFFSET
49h PCI 94h, slot 0 3.3 V maximum current
4Ah PCI 98h, slot 1 3.3 V maximum current
4Bh PCI 9Ch, slot 2 3.3 V maximum current
4Ch Reserved (PCI A0h, slot 3 3.3 V maximum current)
4Dh Reserved (PCI A4h, slot 4 3.3 V maximum current)
4Eh Reserved (PCI A8h, slot 5 3.3 V maximum current)
4Fh PCI Smart Card function indicator (05h)
50h Number of bytes (0Eh)
51h PCI 09h, class code, byte 0
52h PCI 0Ah, class code, byte 1
53h PCI 0Bh, class code, byte 2
54h PCI 2Ch, subsystem vendor ID, byte 0
55h PCI 2Dh, subsystem vendor ID, byte 1
56h PCI 2Eh, subsystem ID, byte 0
57h PCI 2Fh, subsystem ID, byte 1
58h PCI 4Ch, general control bits 6−4
59h PCI 58h, Smart Card configuration 1, byte 0, bits 6−4, 2−0
5Ah PCI 59h, Smart Card configuration 1, byte 1, bits 6−4, 2−0
5Bh PCI 5Ah, Smart Card configuration 1, byte 2, bits 6−4, 2−0
5Ch PCI 5Bh, Smart Card configuration 1, byte 3, bits 7−4, 2−0
5Dh PCI 5Ch, Smart Card configuration 2, byte 0
5Eh PCI 5Dh, Smart Card configuration 2, byte 1
5Fh End-of-list indicator (80h)
BYTE DESCRIPTION
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI7x21/PCI7x11 controller. The PCI7x21/PCI7x11 controller provides several interrupt signaling schemes to
accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this
controller are based on various specifications and industry standards. The ExCA register set provides interrupt
control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the
CardBus PC Card functions. The PCI7x21/PCI7x11 controller is, therefore, backward compatible with existing
interrupt control register definitions, and new registers have been defined where required.
The PCI7x21/PCI7x11 controller detects PC Card interrupts and events at the PC Card interface and notifies the host
controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the
PCI7x21/PCI7x11 controller, PC Card interrupts are classified either as card status change (CSC) or as functional
interrupts.
The method by which any type of PCI7x21/PCI7x11 interrupt is communicated to the host interrupt controller varies
from system to system. The PCI7x21/PCI7x11 controller offers system designers the choice of using parallel PCI
interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt
protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs,
as detailed in the sections that follow. All interrupt signaling is provided through the seven multifunction terminals,
MFUNC0−MFUNC6.
3−16
3.7.1 PC Card Functional and Card Status Change Interrupts
CardBus
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
PCI7x21/PCI7x11 controller and may warrant notification of host card and socket services software for service. CSC
events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card
signals.
Table 3−10 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The four types of cards
that can be inserted into any PC Card socket are:
• 16-bit memory card
• 16-bit I/O card
• CardBus cards
• UltraMedia card
Table 3−10. Interrupt Mask and Flag Registers
CARD TYPE EVENT MASK FLAG
16-bit memory
16-bit I/O Change in card status (STSCHG) ExCA offset 05h/45h/805h bit 0 ExCA offset 04h/44h/804h bit 0
16-bit I/O/
UltraMedia
All 16-bit PC
Cards/
Smart Card
adapters/
UltraMedia/
Flash Media
Battery conditions (BVD1, BVD2) ExCA offset 05h/45h/805h bits 1 and 0 ExCA offset 04h/44h/804h bits 1 and 0
Wait states (READY) ExCA offset 05h/45h/805h bit 2 ExCA offset 04h/44h/804h bit 2
Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0
Power cycle complete ExCA offset 05h/45h/805h bit 3 ExCA offset 04h/44h/804h bit 3
Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0
Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0
Power cycle complete Socket mask bit 3 Socket event bit 3
Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the
card type.
3−17
Table 3−11. PC Card Interrupt Events and Description
Battery conditions
Battery conditions
memory
/
adapters/
CARD TYPE EVENT TYPE SIGNAL DESCRIPTION
A transition on BVD1 indicates a change in the
PC Card battery conditions.
A transition on BVD2 indicates a change in the
PC Card battery conditions.
A transition on READY indicates a change in the
ability of the memory PC Card to accept or provide
data.
The assertion of STSCHG indicates a status change
on the PC Card.
The assertion of IREQ indicates an interrupt request
from the PC Card.
The assertion of CSTSCHG indicates a status
change on the PC Card.
The assertion of CINT indicates an interrupt request
from the PC Card.
A transition on either CD1//CCD1 or CD2//CCD2
indicates an insertion or removal of a 16-bit or
CardBus PC Card.
An interrupt is generated when a PC Card power-up
cycle has completed.
16-bit
16-bit I/O
16-bit I/O/
UltraMedia
CardBus
All PC Cards
Smart Card
adapters/
UltraMedia/
Flash Media
(BVD1, BVD2)
Wait states
(READY)
Change in card
status (STSCHG
Interrupt request
(IREQ
)
Change in card
status (CSTSCHG)
Interrupt request
(CINT
)
Card insertion
or removal
Power cycle
complete
BVD1(STSCHG)//CSTSCHG
CSC
BVD2(SPKR)//CAUDIO
CSC READY(IREQ)//CINT
CSC BVD1(STSCHG)//CSTSCHG
)
Functional READY(IREQ)//CINT
CSC BVD1(STSCHG)//CSTSCHG
Functional READY(IREQ)//CINT
CSC
CSC N/A
CD1//CCD1,
CD2
//CCD2
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For
example, READY(IREQ
)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for
CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in
parentheses. The CardBus signal name follows after a double slash (//).
The 1997 PC Card Standard describes the power-up sequence that must be followed by the PCI7x21/PCI7x11
controller when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon
completion of this power-up sequence, the PCI7x21/PCI7x11 interrupt scheme can be used to notify the host system
(see Table 3−11), denoted by the power cycle complete event. This interrupt source is considered a PCI7x21/PCI7x11
internal event, because it depends on the completion of applying power to the socket rather than on a signal change
at the PC Card interface.
3.7.2 Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−11 by setting
the appropriate bits in the PCI7x21/PCI7x11 controller. By individually masking the interrupt sources listed, software
can control those events that cause a PCI7x21/PCI7x11 interrupt. Host software has some control over the system
interrupt the PCI7x21/PCI7x11 controller asserts by programming the appropriate routing registers. The
PCI7x21/PCI7x11 controller allows host software to route PC Card CSC and PC Card functional interrupts to separate
system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more
detail in the following sections.
When an interrupt is signaled by the PCI7x21/PCI7x1 1 controller, the interrupt service routine must determine which
of the events listed in Table 3−10 caused the interrupt. Internal registers in the PCI7x21/PCI7x11 controller provide
flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine
the action to be taken.
Table 3−10 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Notice that there is not a mask bit to stop the PCI7x21/PCI7x11 controller from passing PC Card functional interrupts
through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and
there must never be a card interrupt that does not require service after proper initialization.
3−18
Table 3−10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the
flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by
bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20), and defaults to
the flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event
register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software must not program the chip through both register sets when a CardBus card is functioning.
3.7.3 Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the PCI7x21/PCI7x11 controller can be
routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions.
To use the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset
92h, see Section 4.39), to select the parallel IRQ signaling scheme. See Section 4.36, Multifunction Routing Status
Register, for details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA
is dictated by certain card and socket-services software. The INT A
for INTA
signaling. The INTRTIE bit is used, in this case, to route socket interrupt events to INTA. This leaves (at a
requirement calls for routing the MFUNC0 terminal
maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ9, IRQ10,
and IRQ15. The multifunction routing status register must be programmed to a value of 0A9F 5432h. This value
routes the MFUNC0 terminal to INT A
shown is that INTA
must also be routed to the programmable interrupt controller (PIC), or to some circuitry that
signaling and routes the remaining terminals as illustrated in Figure 3−12. Not
provides parallel PCI interrupts to the host.
, to signal CSC events. This requirement
PCI7x21/PCI7x11
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IRQ3
IRQ4
IRQ5
IRQ15
IRQ9
IRQ10
PIC
Figure 3−12. IRQ Implementation
Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ
configuration of a system implementing the PCI7x21/PCI7x1 1 controller. The multifunction routing status register is
a global register that is shared between the four PCI7x21/PCI7x11 functions. See Section 4.36, Multifunction Routing
Status Register,
for details on configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the PCI7x21/PCI7x11 controller
makes available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. The INTA
terminals (MFUNC0, MFUNC1, MFUNC2, and MFUNC4). If bit 29 (INTRTIE) is set in the system control register (PCI
offset 80h, see Section 4.29), then INTA
and INTB are tied internally. When the TIEALL bit is set, all four functions
return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts.
, INTB, INTC, and INTD can be routed to MFUNC
3−19
The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI
flash media general
SD host general
Smart Card general
offset 3Dh, see Section 4.24). Table 3−12 summarizes the interrupt signaling modes.
Table 3−12. Interrupt Pin Register Cross Reference
INTRTIE
Bit
TIEALL
Bit
0 0 0x01 (INTA) 0x02 (INTB) 0x03 (INTC)
INTPIN
Function 0
(CardBus)
INTPIN
Function 1
(CardBus)
INTPIN
Function 2
(1394 OHCI)
INTPIN
Function 3
(Flash Media)
Determined by bits
6−5 (INT_SEL field) in
INTPIN
Function 4
(SD Host)
Determined by bits
6−5 (INT_SEL field) in
INTPIN
Function 5
(Smart Card)
Determined by bits
6−5 (INT_SEL field) in
1 0 0x01 (INTA) 0x01 (INTA) 0x03 (INTC)
X 1 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) 0x01 (INTA)
control register (see
Section 11.21)
control register (see
Section 12.22)
control register (see
Section 13.22)
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI7x21/PCI7x11 controller uses a single terminal to
communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of
a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI
clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA
INTD
. For details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
, INTB, INTC, and
3.7.6 SMI Support in the PCI7x21/PCI7x11 Controller
The PCI7x21/PCI7x11 controller provides a mechanism for interrupting the system when power changes have been
made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance
interrupt (SMI) scheme. SMI interrupts are generated by the PCI7x21/PCI7x11 controller, when enabled, after a write
cycle to either the socket control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA
power control register (ExCA offset 02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be
sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−13 describes the SMI control
bits function.
Table 3−13. SMI Control
BIT NAME FUNCTION
SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
SMISTAT This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
SMIENB When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt
can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset
1Eh/5Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.36).
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI7x21/PCI7x11 controller, various features
are designed into the controller to allow implementation of popular power-saving techniques. These features and
techniques are as follows:
• Clock run protocol
• Cardbus PC Card power management
• 16-bit PC Card power management
• Suspend mode
3−20
• Ring indicate
• PCI power management
• Cardbus bridge power management
• ACPI support
EEPROM
PCI7x21/P
1394a
Socket
PC
Card/
UltraMedia
Card
PCI Bus
CI7x11
Power
Switch
PC
Card/
UltraMedia
Card
SD/MMC
MS/MSPRO
SM/xD
SD/MMC
Power Switch
Power Switch
†
The system connection to GRST
must be asserted for subsequent warm resets.
is implementation-specific. GRST must be asserted on initial power up of the PCI7x21/PCI7x11 controller. PRST
Figure 3−13. System Diagram Implementing CardBus Device Class Power Management
3.8.1 1394 Power Management (Function 2)
The PCI7x21/PCI7x11 controller complies with PCI Bus Power Management Interface Specification. The controller
supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management
definition in the 1394 Open Host Controller Interface Specification, Appendix A.4 and PCI Bus Power Management
Specification. PME
PMCSR.PME_STS in the D0 state due to unmasked interrupt events. In previous OHCI implementations, unmasked
interrupt events were interpreted as (IntEvent.n && IntMask.n && IntMask.masterIntEnable), where n represents a
specific interrupt event. Based on feedback from Microsoft this implementation may cause problems with the existing
Windows power-management arcitecture as a PME
from the D1 to D0 state where interrupts were enabled to generate wake events. If bit 10
(ignore_mstrIntEna_for_pme) in the PCI miscellaneous configuration register (OHCI offset F0h, see Section 7.23)
is set, then the PCI7x21/PCI7x11 controller implements the preferred behavior as (IntEvent.n && IntMask.n).
Otherwise, the PCI7x21/PCI7x11 controller implements the preferred behavior as (IntEvent.n && IntMask.n &&
IntMask.masterIntEnable). In addition, when the ignore_mstrIntEna_for_pme bit is set, it causes bit 26 of the OHCI
vendor ID register (OHCI offset 40h, see Section 8.15) to read 1, otherwise, bit 26 reads 0. An open drain buffer is
used for PME
then insertion of a PC Card causes the PCI7x21/PCI7x11 controller to assert PME
low power state (D3, D2, or D1). The OS services PME and takes the PCI7x21/PCI7x11 controller to the D0 state.
is supported to provide notification of wake events. Per Section A.4.2, the 1394 OHCI sets
and an interrupt could be simultaneously signaled on a transition
. If PME is enabled in the power management control/status register (PCI offset A4h, see Section 4.44),
, which wakes the system from a
3−21
3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR)
The PCI7x21/PCI7x11 controller requires 1.5-V core voltage. The core power can be supplied by the
PCI7x21/PCI7x11 controller itself using the internal
LDO-VR. The core power can alternatively be supplied by an
external power supply through the VR_PORT terminal. Table 3−14 lists the requirements for both the internal core
power supply and the external core power supply.
Table 3−14. Requirements for Internal/External 1.5-V Core Power Supply
SUPPLY V
Internal 3.3 V GND 1.5-V output
External 3.3 V V
VR_EN VR_PORT NOTE
CC
CC
1.5-V input
Internal 1.5-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT
terminal for decoupling. This output is not for external use.
Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA
capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required.
3.8.3 CardBus (Functions 0 and 1) Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI7x21/PCI7x11
controller. CLKRUN
CLKRUN
, this is not always available to the system designer, and alternate power-saving features are provided. For
details on the CLKRUN
The PCI7x21/PCI7x11 controller does not permit the central resource to stop the PCI clock under any of the following
conditions:
• Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
• The 16-bit PC Card resource manager is busy.
• The PCI7x21/PCI7x11 CardBus master state machine is busy. A cycle may be in progress on CardBus.
• The PCI7x21/PCI7x11 master is busy. There may be posted data from CardBus to PCI in the
PCI7x21/PCI7x11 controller.
• Interrupts are pending.
• The CardBus CCLK for the socket has not been stopped by the PCI7x21/PCI7x11 CCLKRUN
• Bit 0 (KEEP_PCLK) in the miscellaneous configuration register (PCI offset F0h, see Section 7.23) is set.
• The 1394 resource manager is busy.
• The PCI7x21/PCI7x11 1394 master state machine is busy. A cycle may be in progress on 1394.
• The PCI7x21/PCI7x11 master is busy. There may be posted data from the 1394 bus to PCI in the
PCI7x21/PCI7x11 controller.
• PC Card interrogation is in progress.
• The 1394 bus is not idle.
The PCI7x21/PCI7x11 controller restarts the PCI clock using the CLKRUN
conditions:
• A 16-bit PC Card IREQ
• A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG
• A CardBus attempts to start the CCLK using CCLKRUN
• A CardBus card arbitrates for the CardBus bus using CREQ
• A 1394 device changes the status of the twisted pair lines from idle to active.
• Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.
• Data is in any of the FIFOs (receive or transmit).
• The master state machine is busy.
• There are pending interrupts.
signaling is provided through the MFUNC6 terminal. Since some chip sets do not implement
protocol see the PCI Mobile Design Guide.
manager.
protocol under any of the following
or a CardBus CINT has been asserted by either card.
/RI event occurs in the socket.
.
.
3.8.4 CardBus PC Card Power Management
The PCI7x21/PCI7x11 controller implements its own card power-management engine that can turn off the CCLK to
a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus
CCLKRUN
3−22
interface to control this clock management.
3.8.5 16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN
bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) are provided for 16-bit
PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The
power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN
bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function
when there is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3.8.6 Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI7x21/PCI7x11 controller. Besides gating PRST
inside the PCI7x21/PCI7x11 controller in order to minimize power consumption.
and GRST, SUSPEND also gates PCLK
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT
, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor
an external clock is routed to the serial-interrupt state machine. Figure 3−14 is a signal diagram of the suspend
function.
RESET
GNT
SUSPEND
PCLK
External Terminals
Internal Signals
RESETIN
SUSPENDIN
PCLKIN
Figure 3−14. Signal Diagram of Suspend Function
3.8.7 Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which
would require the reconfiguration of the PCI7x21/PCI7x11 controller by software. Asserting the SUSPEND
signal
3−23
places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the
controller unless a PCI transaction is currently in process (GNT
parked on the PCI7x21/PCI7x11 controller when SUSPEND
is asserted). It is important that the PCI bus not be
is asserted because the outputs are in a high-impedance
state.
The GPIOs, MFUNC signals, and RI_OUT
signal are all active during SUSPEND, unless they are disabled in the
appropriate PCI7x21/PCI7x11 registers.
3.8.8 Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode
and wake-up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform
requirements. RI_OUT
• A 16-bit PC Card modem in a powered socket asserts RI
incoming call.
• A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up.
• A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery
voltage levels.
Figure 3−15 shows various enable bits for the PCI7x21/PCI7x11 RI_OUT
masking of CSC events. See Table 3−10 for a detailed description of CSC interrupt masks and flags.
PC Card
Socket A
PC Card
Socket B
on the PCI7x21/PCI7x11 controller can be asserted under any of the following conditions:
to indicate to the system the presence of an
function; however, it does not show the
RI_OUT Function
Card
I/F
CSTSMASK
CSC
RINGEN
RI
CDRESUME
CSC
RIENB
RI_OUT
Figure 3−15. RI_OUT Functional Diagram
RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register
(ExCA of fset 03h/43h/803h, see Section 5.4). This is programmed on a per-socket basis and is only applicable when
a 16-bit card is powered in the socket.
The CBWAKE signaling to RI_OUT
is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the
CardBus socket registers.
RI_OUT
can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT
function is enabled by setting bit 7 (RIENB) in the card control register (PCI offset 91h, see Section 4.38). The PME
function is enabled by setting bit 8 (PME_ENABLE) in the power-management control/status register (PCI offset A4h,
see Section 4.44). When bit 0 (RIMUX) in the system control register (PCI offset 80h, see Section 4.29) is set to 0,
both the RI_OUT
and RIMUX is set to 0, then the RI_OUT
Therefore, in a system using both the RI_OUT
function and the PME function are routed to the RI_OUT/PME terminal. If both functions are enabled
/PME terminal becomes RI_OUT only and PME assertions are never seen.
function and the PME function, RIMUX must be set to 1 and RI_OUT
must be routed to either MFUNC2 or MFUNC4.
3−24
3.8.9 PCI Power Management
3.8.9.1 CardBus Power Management (Functions 0 and 1)
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure
required to let the operating system control the power of PCI functions. This is done by defining a standard PCI
interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can
be assigned one of seven power-management states, resulting in varying levels of power savings.
The seven power-management states of PCI functions are:
• D0-uninitialized − Before controller configuration, controller not fully functional
• D0-active − Fully functional state
• D1 − Low-power state
• D2 − Low-power state
• D3
• D3
• D3
NOTE 1: In the D0-uninitialized state, the PCI7x21/PCI7x11 controller does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1
NOTE 2: The PWR_STATE bits (bits 1−0) of the power-management control/status register (PCI offset A4h, see Section 4.44) only code for four
Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power
state of the originating bridge device.
− Low-power state. Transition state before D3
hot
− PME signal-generation capable. Main power is removed and VAUX is available.
cold
− No power and completely nonfunctional
off
(MEM_EN) of the command register (PCI offset 04h, see Section 4.4) are both set, the PCI7x21/PCI7x11 controller switches the state
to D0-active. Transition from D3
the controller to the D0-uninitialized state immediately.
power states, D0, D1, D2, and D3
is not accessible in the D3
cold
to the D0-uninitialized state happens at the deassertion of PRST
cold
. The differences between the three D3 states is invisible to the software because the controller
hot
or D3
off
state.
cold
. The assertion of GRST forces
For the operating system (OS) to manage the controller power states on the PCI bus, the PCI function must support
four power-management operations. These operations are:
• Capabilities reporting
• Power status reporting
• Setting the power state
• System wake-up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI
offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI7x21/PCI7x11
controller, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an of fset
of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power
management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of
capabilities. If there are no more items in the list, then the next item pointer must be set to 0. The registers following
the next item pointer are specific to the capability of the function. The PCI power-management capability implements
the register block outlined in Table 3−15.
Table 3−15. Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID A0h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) A4h
The power-management capabilities register (PCI offset A2h, see Section 4.43) provides information on the
capabilities of the function related to power management. The power-management control/status register (PCI offset
A4h, see Section 4.44) enables control of power-management states and enables/monitors power-management
events. The data register is an optional register that can provide dynamic data.
3−25
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges.
3.8.9.2 OHCI 1394 (Function 2) Power Management
The PCI7x21/PCI7x11 controller complies with the PCI Bus Power Management Interface Specification. The
controller supports the D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power
management definition in the 1394 Open Host Controller Interface Specification, Appendix A4.
Table 3−16. Function 2 Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID 44h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h
3.8.9.3 Flash Media (Function 3) Power Management
The PCI Bus Power Management Interface Specification is applicable for the flash media dedicated sockets. This
function supports the D0 and D3 power states.
Table 3−17. Function 3 Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID 44h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h
3.8.9.4 SD Host (Function 4) Power Management
The PCI Bus Power Management Interface Specification is applicable for the SD host dedicated sockets. This
function supports the D0 and D3 power states.
Table 3−18. Function 4 Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID 80h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 84h
3.8.9.5 Smart Card (Function 5) Power Management
The PCI Bus Power Management Interface Specification is applicable for the Smart Card dedicated sockets. This
function supports the D0 and D3 power states.
Table 3−19. Function 5 Power-Management Registers
REGISTER NAME OFFSET
Power-management capabilities Next item pointer Capability ID 44h
Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h
3.8.10 CardBus Bridge Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed
in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3
without losing wake-up context (also called PME context).
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake-up are as follows:
• Preservation of device context. The specification states that a reset must occur during the transition from
D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME
• Power source in D3
context registers.
if wake-up support is required from this state.
cold
hot
or D3
cold
3−26
The Texas Instruments PCI7x21/PCI7x11 controller addresses these D3 wake-up issues in the following manner:
• Two resets are provided to handle preservation of PME
− Global reset (GRST
) is used only on the initial boot up of the system after power up. It places the
context bits:
PCI7x21/PCI7x11 controller in its default state and requires BIOS to configure the controller before
becoming fully functional.
− PCI reset (PRST
then PME
context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.
Please see the master list of PME
• Power source in D3
auxiliary power source must be supplied to the PCI7x21/PCI7x11 V
) has dual functionality based on whether PME is enabled or not. If PME is enabled,
context bits in Section 3.8.12.
if wake-up support is required from this state. Since VCC is removed in D3
cold
terminals. Consult the PCI14xx
CC
cold
, an
Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to
CardBus Bridges for further information.
3.8.11 ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The PCI7x21/PCI7x11 controller offers a generic interface that
is compliant with ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI7x21/PCI7x11 PCI configuration space
at offset 88h. The programming model is broken into status and control functions. In compliance with ACPI, the top
level event status and enable bits reside in the general-purpose event status register (PCI offset 88h, see
Section 4.32) and general-purpose event enable register (PCI offset 89h, see Section 4.33). The status and enable
bits are implemented as defined by ACPI and illustrated in Figure 3−16.
Status Bit
Event Input
Enable Bit
Event Output
Figure 3−16. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3.8.12 Master List of PME Context Bits and Global Reset-Only Bits
PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit, bit 8 of the
power management control/status register (PCI offset A4h, see Section 4.44) is set. If PME
bits are cleared when either PRST
The PME
context bits (functions 0 and 1) are:
or GRST is asserted.
• Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6
• System control register (PCI offset 80h, see Section 4.29): bits 10−8
• Power management control/status register (PCI offset A4h, see Section 4.44): bit 15
• ExCA power control register (ExCA 802h/842h, see Section 5.3): bits 7, 5 (82365SL mode only), 4, 3, 1,
0
• ExCA interrupt and general control (ExCA 803h/843h, see Section 5.4): bits 6, 5
• ExCA card status-change register (ExCA 804h/844h, see Section 5.5): bits 3−0
is not enabled, then these
3−27
• ExCA card status-change interrupt configuration register (ExCA 805h/845h, see Section 5.6): bits 3−0
• ExCA card detect and general control register (ExCA 816h/856h, see Section 5.19): bits 7, 6
• Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0
• Socket mask register (CardBus offset 04h, see Section 6.2): bits 3−0
• Socket present state register (CardBus offset 08h, see Section 6.3): bits 13−7, 5−1
• Socket control register (CardBus offset 10h, see Section 6.5): bits 6−4, 2−0
Global reset-only bits, as the name implies, are cleared only by GRST
. These bits are never cleared by PRST,
regardless of the setting of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means
that assertion of SUSPEND
a diagram showing the application of GRST
blocks the GRST signal internally, thus preserving all register contents. Figure 3−13 is
and PRST.
The global reset-only bits (functions 0 and 1) are:
• Status register (PCI offset 06h, see Section 4.5): bits 15−11, 8
• Secondary status register (PCI offset 16h, see Section 4.14): bits 15−11, 8
• Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15–0
• Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15–0
• PC Card 16-bit I/F legacy-mode base-address register (PCI offset 44h, see Section 4.28): bits 31−0
• System control register (PCI offset 80h, see Section 4.29): bits 31−24, 22−13, 11, 6−0
• MC_CD debounce register (PCI offset 84h, see Section 4.30): bits 7−0
• General control register (PCI offset 86h, see Section 4.31): bits 13−10, 7, 5−3, 1, 0
• General-purpose event status register (PCI offset 88h, see Section 4.32): bits 7, 6, 4−0
• General-purpose event enable register (PCI offset 89h, see Section 4.33): bits 7, 6, 4−0
• General-purpose output register (PCI offset 8Bh, see Section 4.35): bits 4−0
• Multifunction routing register (PCI offset 8Ch, see Section 4.36): bits 31−0
• Retry status register (PCI offset 90h, see Section 4.37): bits 7−5, 3, 1
• Card control register (PCI offset 91h, see Section 4.38): bits 7, 2−0
• Device control register (PCI offset 92h, see Section 4.39): bits 7−5, 3−0
• Diagnostic register (PCI offset 93h, see Section 4.40): bits 7−0
• Power management capabilities register (PCI offset A2h, see Section 4.43): bit 15
• Power management CSR register (PCI offset A4h, see Section 4.44): bits 15, 8
• Serial bus data register (PCI offset B0h, see Section 4.47): bits 7−0
• Serial bus index register (PCI offset B1h, see Section 4.48): bits 7−0
• Serial bus slave address register (PCI offset B2h, see Section 4.49): bits 7−0
• Serial bus control/status register (PCI offset B3h, see Section 4.50): bits 7, 3−0
• ExCA identification and revision register (ExCA 800h/840h, see Section 5.1): bits 7−0
• ExCA global control register (ExCA 81Eh/85Eh, see Section 5.20): bits 2−0
• CardBus socket power management register (CardBus 20h, see Section 6.6): bits 25, 24
The global reset-only bit (function 2) is:
• Subsystem vendor ID register (PCI offset 2Ch, see Section 7.12): bits 15−0
• Subsystem ID register (PCI offset 2Eh, see Section 7.12): bits 31−16
• Minimum grant and maximum latency register (PCI offset 3Eh, see Section 7.16): bits 15−0
• Power management control and status register (PCI offset 48h, see Section 7.20): bits 15, 8, 1, 0
• Miscellaneous configuration register (PCI offset F0h, see Section 7.23): bits 15, 11−8, 5−0
• Link enhancement control register (PCI offset F4h, see Section 7.24): bits 15−12, 10, 8, 7, 2, 1
• Bus options register (OHCI offset 20h, see Section 8.9): bits 15−12
• GUID high register (OHCI offset 24h, see Section 8.10): bits 31−0
• GUID low register (OHCI offset 28h, see Section 8.11): bits 31−0
• Host controller control register (OHCI offset 50h/54h, see Section 8.16): bit 23
• Link control register (OHCI offset E0h/E4h, see Section 8.31): bit 6
• PHY-link loopback test register (Local offset C14h): bits 6−4, 0
• Link test control register (Local offset C00h): bits 12−8
3−28
The global reset-only (function 3) register bits:
• Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15–0
• Subsystem ID register (PCI offset 2Eh, see Section 11.10): bits 15–0
• Power management control and status register (PCI offset 48h, see Section 11.18): bits 15, 8, 1, 0
• General control register (PCI offset 4Ch, see Section 11.21): bits 6−4, 2–0
• Diagnostic register (PCI offset 54h, see Section 11.23): bits 31–0
The global reset-only (function 4) register bits:
• Subsystem vendor ID register (PCI offset 2Ch, see Section 12.9): bits 15–0
• Subsystem ID register (PCI offset 2Eh, see Section 12.10): bits 15–0
• Power management control and status register (PCI offset 84h, see Section 12.19): bits 15, 8, 1, 0
• General control register (PCI offset 88h, see Section 12.22): bits 6−4, 0
• Diagnostic register (PCI offset 90h, see Section 12.24): bits 31–0
The global reset-only (function 5) register bits:
• Subsystem vendor ID register (PCI offset 2Ch, see Section 13.10): bits 15–0
• Subsystem ID register (PCI offset 2Eh, see Section 13.11): bits 15–0
• Power management control and status register (PCI offset 48h, see Section 13.19): bits 15, 8, 1, 0
• General control register (PCI offset 4Ch, see Section 13.22): bits 6−4, 0
3−29
3.9 IEEE 1394 Application Information
3.9.1 PHY Port Cable Connection
PCI7x21/
PCI7x11
Cable Port
CPS
TPBIAS
TPA+
TPA−
TPB+
TPB−
220 pF
(see Note A)
400 kΩ
1 µF
56 Ω56 Ω
56 Ω56 Ω
5 kΩ
Cable
Power
Pair
Cable
Pair
A
Cable
Pair
B
Outer Shield
Termination
NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended.
Figure 3−17. TP Cable Connections
Outer Cable Shield
1 MΩ
Chassis Ground
0.01 µF
0.001 µF
Figure 3−18. Typical Compliant DC Isolated Outer Shield Termination
3−30
Outer Cable Shield
Chassis Ground
Figure 3−19. Non-DC Isolated Outer Shield Termination
3.9.2 Crystal Selection
The PCI7x21/PCI7x11 controller is designed to use an external 24.576-MHz crystal connected between the XI and
XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that
generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media
data rates.
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995. Adjacent
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHY devices
must be able to compensate for this difference over the maximum packet length. Large clock variations may cause
resynchronization overflows or underflows, resulting in corrupted packet data.
The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required
frequency accuracy and stability:
• Crystal mode of operation: Fundamental
• Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with
±30 ppm frequency tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended
for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between frequency
tolerance and stability may be made as long as the total frequency variation is less than
±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and
the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible
variation due to the crystal alone. Crystal aging also contributes to the frequency variation.
• Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (C
) is a function of not only the
L
discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a
maximum of ±5% tolerance be used.
For example, load capacitors (C9 and C10 in Figure 3−20) of 16 pF each were appropriate for the layout of the
PCI7x21/PCI7x11 evaluation module (EVM), which uses a crystal specified for 12-pF loading. The load specified for
the crystal includes the load capacitors (C9 and C10), the loading of the PHY pins (C
itself (C
). The value of C
BD
is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical
PHY
), and the loading of the board
PHY
board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the
total load capacitance is:
+
L
C9 C10
C9 ) C10
) C
PHY
) C
BD
C
3−31
C9
X1
C10
X1
I
S
24.576 MHz
C
PHY
+ C
BD
X0
Figure 3−20. Load Capacitance for the PCI7x21/PCI7x11 PHY
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise
introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load
capacitors must be considered as a unit during layout. The crystal and the load capacitors must be placed as close
as possible to one another while minimizing the loop area created by the combination of the three components.
Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant
current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as
close as possible to the PHY X1 and X0 terminals to minimize etch lengths, as shown in Figure 3−21.
C9 C10
X1
For more details on crystal selection, see application report SLLA051 available from the TI website:
http://www.ti.com/sc/1394.
Figure 3−21. Recommended Crystal and Capacitor Layout
3.9.3 Bus Reset
In the PCI7x21/PCI7x11 controller, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and
initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and Gap_Count
field, as required by IEEE Std 1394a-2000. Therefore, whenever the IBR bit is written, the RHB and Gap_Count are
also written.
The RHB and Gap_Count may also be updated by PHY-config packets. The PCI7x21/PCI7x11 controller is IEEE
1394a-2000 compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and
Gap_Count to be loaded, unlike older IEEE 1394-1995 compliant PHY devices which decode only received
PHY-config packets.
The gap-count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the
Gap_Count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config
packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their
RHBs and Gap_Count values, without having the Gap_Count set back to 63 by the bus reset. The subsequent
connection of a new node to the bus, which initiates a bus reset, then causes the Gap_Count of each node to be set
to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all
other nodes on the bus have their Gap_Count values set to 63, while this node Gap_Count remains set to the value
just loaded by the write to PHY register 1.
3−32
Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the
IBR bit, RHB, and Gap_Count in PHY register 1:
• Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all
nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new
connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus. If this bus reset is
initiated by setting the IBR bit to 1, then the RHB and Gap_Count field must also be loaded with the correct
values consistent with the just transmitted PHY-config packet. In the PCI7x21/PCI7x11 controller, the RHB
and Gap_Count are updated to their correct values upon the transmission of the PHY-config packet, so
these values may first be read from register 1 and then rewritten.
• Other than to initiate the bus reset, which must follow the transmission of a PHY-config packet, whenever
the IBR bit is set to 1 in order to initiate a bus reset, the Gap_Count value must also be set to 63 so as to
be consistent with other nodes on the bus, and the RHB must be maintained with its current value.
• The PHY register 1 must not be written to except to set the IBR bit. The RHB and Gap_Count must not be
written without also setting the IBR bit to 1.
3−33
3−34
4 PC Card Controller Programming Model
This chapter describes the PCI7x21/PCI7x11 PCI configuration registers that make up the 256-byte PCI configuration
header for each PCI7x21/PCI7x11 function. There are some bits which affect both CardBus functions, but which, in
order to work properly, must be accessed only through function 0. These are called global bits. Registers containing
one or more global bits are denoted by § in Table 4−2.
Any bit followed by a † is not cleared by the assertion of PRST
Section 3.8.10, for more details) if PME
GRST
. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes referred to
as PME context bits and are implemented to allow PME
D3
to D0.
cold
If a bit is followed by a ‡, then this bit is cleared only by GRST
is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared only by
context to be preserved during the transition from D3
in all cases (not conditional on PME being enabled).
(see CardBus Bridge Power Management,
or
hot
These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm
resets.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
Table 4−1. Bit Field Access Tag Descriptions
ACCESS TAG NAME MEANING
R Read Field can be read by software.
W Write Field can be written by software to any value.
S Set Field can be set by a write of 1. Writes of 0 have no effect.
C Clear Field can be cleared by a write of 1. Writes of 0 have no effect.
U Update Field can be autonomously updated by the PCI7x21/PCI7x11 controller.
4.1 PCI Configuration Register Map (Functions 0 and 1)
The PCI7x21/PCI7x11 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and
1. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is
PC99/PC2001 compliant as well. Table 4−2 illustrates the PCI configuration register map, which includes both the
predefined portion of the configuration space and the user-definable registers.
Table 4−2. Functions 0 and 1 PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status ‡ Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
CardBus socket registers/ExCA base address register 10h
Secondary status ‡ Reserved Capability pointer 14h
CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h
CardBus memory base register 0 1Ch
CardBus memory limit register 0 20h
CardBus memory base register 1 24h
CardBus memory limit register 1 28h
‡
One or more bits in this register are cleared only by the assertion of GRST
.
4−1
Table 4−2. Functions 0 and 1 PCI Configuration Register Map (Continued)
REGISTER NAME OFFSET
CardBus I/O base register 0 2Ch
CardBus I/O limit register 0 30h
CardBus I/O base register 1 34h
CardBus I/O limit register 1 38h
Bridge control † Interrupt pin Interrupt line 3Ch
Subsystem ID ‡ Subsystem vendor ID ‡ 40h
PC Card 16-bit I/F legacy-mode base-address ‡ 44h
Reserved 48h−7Ch
System control †‡§ 80h
General control ‡§ Reserved MC_CD debounce ‡ 84h
General-purpose output ‡ General-purpose input
Multifunction routing status ‡ 8Ch
Diagnostic ठDevice control ठCard control ठRetry status ठ90h
Reserved 94h−9Ch
Power management capabilities ‡ Next item pointer Capability ID A0h
Power management data
(Reserved)
Serial bus control/status ‡ Serial bus slave address ‡ Serial bus index ‡ Serial bus data ‡ B0h
†
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST
enabled, then this bit is cleared by the assertion of PRST
‡
One or more bits in this register are cleared only by the assertion of GRST
§
One or more bits in this register are global in nature and must be accessed only through function 0.
Power management
control/status bridge support
extensions
Reserved A8h−ACh
Reserved B4h−FCh
or GRST.
General-purpose event
enable ‡
Power management control/status †‡
.
General-purpose event
status ‡
when PME is enabled. If PME is not
88h
A4h
4.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Vendor ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0
Register: Vendor ID
Offset: 00h (Functions 0, 1)
Type: Read-only
Default: 104Ch
4−2
4.3 Device ID Register Functions 0 and 1
This read-only register contains the device ID assigned by TI to the PCI7x21/PCI7x11 CardBus controller functions
(PCI functions 0 and 1).
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Device ID—Smart Card enabled
Type R R R R R R R R R R R R R R R R
Default 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
Register: Device ID
Offset: 02h (Functions 0 and 1)
Type: Read-only
Default: 8031h
4−3
4.4 Command Register
The PCI command register provides control over the PCI7x21/PCI7x11 interface to the PCI bus. All bit functions
adhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this register
are shared among the PCI7x21/PCI7x11 PCI functions. Three command registers exist in the PCI7x21/PCI7x11
controller, one for each function. Software manipulates the PCI7x21/PCI7x11 functions as separate entities when
enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are
internally wired OR between the three functions, and these control bits appear to software to be separate for each
function.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Command
Type R R R R R RW R RW R RW RW R R RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Command
Offset: 04h
Type: Read-only, Read/Write
Default: 0000h
Table 4−3. Command Register Description
BIT
15−11 RSVD R Reserved. Bits 15−11 return 0s when read.
10 INT_DISABLE RW
9 FBB_EN R
8 SERR_EN RW
7 RSVD R Reserved. Bit 7 returns 0 when read.
6 PERR_EN RW
5 VGA_EN RW
4 MWI_EN R
3 SPECIAL R
2 MAST_EN RW
SIGNAL TYPE FUNCTION
INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx
1 = INTx
Fast back-to-back enable. The PCI7x21/PCI7x11 controller does not generate fast back-to-back
transactions; therefore, this bit is read-only . This bit returns a 0 when read.
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI7x21/PCI7x11 controller to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR
Parity error response enable. This bit controls the PCI7x21/PCI7x11 response to parity errors through the
PERR
by asserting SERR
0 = PCI7x21/PCI7x11 controller ignores detected parity errors (default).
1 = PCI7x21/PCI7x11 controller responds to detected parity errors.
VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI7x21/PCI7x11 controller does
not respond to palette register writes and snoops the data). When the bit is 0, the PCI7x21/PCI7x11
controller treats all palette accesses like all other accesses.
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI7x21/PCI7x11 controller does not support memory
write-and-invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired
to 0. This bit returns 0 when read. Writes to this bit have no effect.
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The
PCI7x21/PCI7x11 controller does not respond to special cycle operations; therefore, this bit is hardwired
to 0. This bit returns 0 when read. Writes to this bit have no effect.
Bus master control. This bit controls whether or not the PCI7x21/PCI7x11 controller can act as a PCI bus
initiator (master). The PCI7x21/PCI7x11 controller can take control of the PCI bus only when this bit is set.
0 = Disables the PCI7x21/PCI7x11 ability to generate PCI bus accesses (default)
1 = Enables the PCI7x21/PCI7x11 ability to generate PCI bus accesses
assertion is enabled (default)
assertion is disabled
output driver
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated
.
4−4
Table 4−3. Command Register Description (continued)
BIT
1 MEM_EN RW
0 IO_EN RW
SIGNAL TYPE FUNCTION
Memory space enable. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles
in PCI memory space.
0 = Disables the PCI7x21/PCI7x11 response to memory space accesses (default)
1 = Enables the PCI7x21/PCI7x11 response to memory space accesses
I/O space control. This bit controls whether or not the PCI7x21/PCI7x11 controller can claim cycles in PCI
I/O space.
0 = Disables the PCI7x21/PCI7x11 controller from responding to I/O space accesses (default)
1 = Enables the PCI7x21/PCI7x11 controller to respond to I/O space accesses
4.5 Status Register
The status register provides device information to the host system. Bits in this register can be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown
through each function. See Table 4−4 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Status
Type RW RW RW RW RW R R RW R R R R RU R R R
Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Register: Status
Offset: 06h (Functions 0, 1)
Type: Read-only, Read/Write
Default: 0210h
Table 4−4. Status Register Description
BIT SIGNAL TYPE FUNCTION
15 ‡ PAR_ERR RW
14 ‡ SYS_ERR RW
13 ‡ MABORT RW
12 ‡ TABT_REC RW
11 ‡ TABT_SIG RW
10−9 PCI_SPEED R
8 ‡ DATAPAR RW
7 FBB_CAP R
6 UDF R
5 66MHZ R
‡
This bit is cleared only by the assertion of GRST
Detected parity error. This bit is set when a parity error is detected, either an address or data parity error.
Write a 1 to clear this bit.
Signaled system error. This bit is set when SERR is enabled and the PCI7x21/PCI7x11 controller signaled
a system error to the host. Write a 1 to clear this bit.
Received master abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI
bus has been terminated by a master abort. Write a 1 to clear this bit.
Received target abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the PCI
bus was terminated by a target abort. Write a 1 to clear this bit.
Signaled target abort. This bit is set by the PCI7x21/PCI7x11 controller when it terminates a transaction on
the PCI bus with a target abort. Write a 1 to clear this bit.
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the
PCI7x21/PCI7x1 1 controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
Data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. PERR
b. The PCI7x21/PCI7x11 controller was the bus master during the data parity error.
c. The parity error response bit is set in the command register.
Fast back-to-back capable. The PCI7x21/PCI7x11 controller cannot accept fast back-to-back transactions;
thus, this bit is hardwired to 0.
UDF supported. The PCI7x21/PCI7x11 controller does not support user-definable features; therefore, this
bit is hardwired to 0.
66-MHz capable. The PCI7x21/PCI7x11 controller operates at a maximum PCLK frequency of 33 MHz;
therefore, this bit is hardwired to 0.
was asserted by any PCI device including the PCI7x21/PCI7x11 controller.
.
4−5
Table 4−4. Status Register Description (continued)
BIT SIGNAL TYPE FUNCTION
Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI
4 CAPLIST R
3 INT_STATUS RU
2−0 RSVD R Reserved. These bits return 0s when read.
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the
command register (PCI offset 04h, see Section 4.4) is a 0 and this bit is a 1, is the function’s INTx
asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit.
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI7x21/PCI7x11 controller.
Bit 7 6 5 4 3 2 1 0
Name Revision ID
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: Revision ID
Offset: 08h (functions 0, 1)
Type: Read-only
Default: 00h
4.7 Class Code Register
signal
The class code register recognizes PCI7x21/PCI7x11 functions 0 and 1 as a bridge device (06h) and a CardBus
bridge device (07h), with a 00h programming interface.
Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI class code
Base class Subclass Programming interface
Type R R R R R R R R R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0
Register: PCI class code
Offset: 09h (functions 0, 1)
Type: Read-only
Default: 06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit 7 6 5 4 3 2 1 0
Name Cache line size
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Cache line size
Offset: 0Ch (Functions 0, 1)
Type: Read/Write
Default: 00h
4−6
4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI7x21/PCI7x11 controller, in units of PCI clock cycles.
When the PCI7x21/PCI7x11 controller is a PCI bus initiator and asserts FRAME
, the latency timer begins counting
from zero. If the latency timer expires before the PCI7x21/PCI7x11 transaction has terminated, then the
PCI7x21/PCI7x11 controller terminates the transaction when its GNT
Bit 7 6 5 4 3 2 1 0
Name Latency timer
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
is deasserted.
Register: Latency timer
Offset: 0Dh
Type: Read/Write
Default: 00h
4.10 Header Type Register
The header type register returns 82h when read, indicating that the PCI7x21/PCI7x11 functions 0 and 1 configuration
spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers
00h−7Fh, and 80h−FFh is user-definable extension registers.
Bit 7 6 5 4 3 2 1 0
Name Header type
Type R R R R R R R R
Default 1 0 0 0 0 0 1 0
Register: Header type
Offset: 0Eh (Functions 0, 1)
Type: Read-only
Default: 82h
4.11 BIST Register
Because the PCI7x21/PCI7x11 controller does not support a built-in self-test (BIST), this register returns the value
of 00h when read.
Bit 7 6 5 4 3 2 1 0
Name BIST
Type R R R R R R R R
Default 0 0 0 0 0 0 0 0
Register: BIST
Offset: 0Fh (Functions 0, 1)
Type: Read-only
Default: 00h
4−7
4.12 CardBus Socket Registers/ExCA Base Address Register
This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped
ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI
memory address space on a 4-Kbyte boundary. Bits 11−0 are read-only, returning 0s when read. When software
writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address
space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at
offset 800h. This register is not shared by functions 0 and 1, so the system maps each socket control register
separately.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CardBus socket registers/ExCA base address
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CardBus socket registers/ExCA base address
Type RW RW RW RW R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: CardBus socket registers/ExCA base address
Offset: 10h
Type: Read-only, Read/Write
Default: 0000 0000h
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management
register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each
socket has its own capability pointer register. This register is read-only and returns A0h when read.
Bit 7 6 5 4 3 2 1 0
Name Capability pointer
Type R R R R R R R R
Default 1 0 1 0 0 0 0 0
Register: Capability pointer
Offset: 14h
Type: Read-only
Default: A0h
4−8
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates
CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI
offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket
functions, but is accessed on a per-socket basis. See Table 4−5 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Secondary status
Type RC RC RC RC RC R R RC R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Register: Secondary status
Offset: 16h
Type: Read-only, Read/Clear
Default: 0200h
Table 4−5. Secondary Status Register Description
BIT SIGNAL TYPE FUNCTION
15 ‡ CBPARITY RC
14 ‡ CBSERR RC
13 ‡ CBMABORT RC
12 ‡ REC_CBTA RC
11 ‡ SIG_CBTA RC
10−9 CB_SPEED R
8 ‡ CB_DPAR RC
7 CBFBB_CAP R
6 CB_UDF R
5 CB66MHZ R
4−0 RSVD R These bits return 0s when read.
‡
This bit is cleared only by the assertion of GRST
Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data
parity error. W rite a 1 to clear this bit.
Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI7x21/PCI7x11
controller does not assert the CSERR
Received master abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the
CardBus bus is terminated by a master abort. Write a 1 to clear this bit.
Received target abort. This bit is set when a cycle initiated by the PCI7x21/PCI7x11 controller on the
CardBus bus is terminated by a target abort. Write a 1 to clear this bit.
Signaled target abort. This bit is set by the PCI7x21/PCI7x11 controller when it terminates a transaction
on the CardBus bus with a target abort. Write a 1 to clear this bit.
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the
PCI7x21/PCI7x1 1 controller asserts this signal at a medium speed.
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR
b. The PCI7x21/PCI7x11 controller was the bus master during the data parity error.
c. The parity error response enable bit (bit 0) is set in the bridge control register (PCI offset 3Eh,
see Section 4.25).
Fast back-to-back capable. The PCI7x21/PCI7x11 controller cannot accept fast back-to-back
transactions; therefore, this bit is hardwired to 0.
User-definable feature support. The PCI7x21/PCI7x11 controller does not support user-definable
features; therefore, this bit is hardwired to 0.
66-MHz capable. The PCI7x21/PCI7x11 CardBus interface operates at a maximum CCLK frequency of
33 MHz; therefore, this bit is hardwired to 0.
was asserted on the CardBus interface.
.
signal. Write a 1 to clear this bit.
4−9
4.15 PCI Bus Number Register
The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which
the PCI7x21/PCI7x11 controller is connected. The PCI7x21/PCI7x11 controller uses this register in conjunction with
the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration
cycles to its secondary buses.
Bit 7 6 5 4 3 2 1 0
Name PCI bus number
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: PCI bus number
Offset: 18h (Functions 0, 1)
Type: Read/Write
Default: 00h
4.16 CardBus Bus Number Register
The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus
to which the PCI7x21/PCI7x11 controller is connected. The PCI7x21/PCI7x11 controller uses this register in
conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI
configuration cycles to its secondary buses. This register is separate for each PCI7x21/PCI7x11 controller function.
Bit 7 6 5 4 3 2 1 0
Name CardBus bus number
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: CardBus bus number
Offset: 19h
Type: Read/Write
Default: 00h
4.17 Subordinate Bus Number Register
The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below
the CardBus bus. The PCI7x21/PCI7x11 controller uses this register in conjunction with the PCI bus number and
CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This
register is separate for each CardBus controller function.
Bit 7 6 5 4 3 2 1 0
Name Subordinate bus number
Type RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0
Register: Subordinate bus number
Offset: 1Ah
Type: Read/Write
Default: 00h
4−10
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