Texas Instruments PCI4410APDV, PCI4410GHK, PCI4410PDV Datasheet
2000 PCIBus Solutions
Data Manual
Printed in U.S.A., 01/00 SCPS052
PCI4410 GHK/PDV
Data Manual
PC Card and OHCI Controller
Literature Number: SCPS052
January 2000
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
iii
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Power Supply Sequencing 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 I/O Characteristics 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Clamping Voltages 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Component Interconnect (PCI) Interface 3–2. . . . . . . . . . . . . .
3.4.1 PCI Bus Lock (LOCK
) 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Loading Subsystem Identification 3–3. . . . . . . . . . . . . . . . . . . . .
3.5 PC Card Applications 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 PC Card Insertion/Removal and Recognition 3–3. . . . . . . . . . .
3.5.2 P
2
C Power-Switch Interface (TPS2211) 3–4. . . . . . . . . . . . . . .
3.5.3 Zoomed Video Support 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Ultra Zoomed Video 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 D3_ST A T
Terminal 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Internal Ring Oscillator 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 Integrated Pullup Resistors for PC Card Interface 3–6. . . . . . .
3.5.8 SPKROUT and CAUDPWM Usage 3–7. . . . . . . . . . . . . . . . . . .
3.5.9 LED Socket Activity Indicators 3–7. . . . . . . . . . . . . . . . . . . . . . . .
3.5.10 PC Card-16 Distributed DMA Support 3–8. . . . . . . . . . . . . . . . .
3.5.11 PC Card-16 PC/PCI DMA 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.12 CardBus Socket Registers 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Serial Bus Interface 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Serial Bus Interface Implementation 3–11. . . . . . . . . . . . . . . . . . .
3.6.2 Serial Bus Interface Protocol 3–11. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Serial Bus EEPROM Application 3–13. . . . . . . . . . . . . . . . . . . . . .
3.6.4 Accessing Serial Bus Devices Through Software 3–15. . . . . . . .
3.7 Programmable Interrupt Subsystem 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 PC Card Functional and Card Status Change Interrupts 3–16.
3.7.2 Interrupt Masks and Flags 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Using Parallel IRQ Interrupts 3–18. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Using Parallel PCI Interrupts 3–18. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Using Serialized IRQSER Interrupts 3–18. . . . . . . . . . . . . . . . . . .
iv
3.7.6 SMI Support in the PCI4410 3–19. . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Power Management Overview 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Clock Run Protocol 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 CardBus PC Card Power Management 3–19. . . . . . . . . . . . . . . .
3.8.3 16-Bit PC Card Power Management 3–20. . . . . . . . . . . . . . . . . . .
3.8.4 Suspend Mode 3–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.5 Requirements for Suspend Mode 3–21. . . . . . . . . . . . . . . . . . . . .
3.8.6 Ring Indicate 3–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.7 PCI Power Management 3–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8 CardBus Bridge Power Management 3–23. . . . . . . . . . . . . . . . . .
3.8.9 ACPI Support 3–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.10 Master List of PME
Context Bits and Global Reset Only
Bits 3–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PC Card Controller Programming Model 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Configuration Registers (Functions 0 and 1) 4–1. . . . . . . . . . . . . . . . .
4.2 Vendor ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Device ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Revision ID Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 PCI Class Code Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Cache Line Size Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Latency Timer Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket/ExCA Base-Address Register 4–7. . . . . . . . . . . . . . . . . .
4.13 Capability Pointer Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Base Registers 0, 1 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Limit Registers 0, 1 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 I/O Base Registers 0, 1 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 I/O Limit Registers 0, 1 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register 4–15. . . . . . . . .
4.29 System Control Register 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 General Status Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
4.31 General Control Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Multifunction Routing Register 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 Retry Status Register 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 Card Control Register 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 Device Control Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.36 Diagnostic Register 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 Socket DMA Register 0 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 Socket DMA Register 1 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 Capability ID Register 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 Next-Item Pointer Register 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 Power Management Capabilities Register 4–28. . . . . . . . . . . . . . . . . . . . . .
4.42 Power Management Control/Status Register 4–29. . . . . . . . . . . . . . . . . . . .
4.43 Power Management Control/Status Register Bridge Support
Extensions 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.44 Power Management Data Register 4–30. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.45 General-Purpose Event Status Register 4–31. . . . . . . . . . . . . . . . . . . . . . . .
4.46 General-Purpose Event Enable Register 4–32. . . . . . . . . . . . . . . . . . . . . . .
4.47 General-Purpose Input Register 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 General-Purpose Output Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 ExCA Compatibility Registers 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 ExCA Identification and Revision Register 5–4. . . . . . . . . . . . . . . . . . . . . .
5.2 ExCA Interface Status Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 ExCA Power Control Register 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ExCA Interrupt and General Control Register 5–7. . . . . . . . . . . . . . . . . . .
5.5 ExCA Card Status-Change Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ExCA Card Status-Change-Interrupt Configuration Register 5–9. . . . . . .
5.7 ExCA Address Window Enable Register 5–10. . . . . . . . . . . . . . . . . . . . . . . .
5.8 ExCA I/O Window Control Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5–12. . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5–12. . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5–13. . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5–13. . . .
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers 5–14. . .
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers 5–15. . .
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers 5–16. . . .
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers 5–17. . .
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers 5–18. .
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers 5–19.
5.19 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5–20. . .
5.20 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5–20. . .
5.21 ExCA Card Detect and General Control Register 5–21. . . . . . . . . . . . . . . .
5.22 ExCA Global Control Register 5–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.23 ExCA Memory Windows 0–4 Page Register 5–22. . . . . . . . . . . . . . . . . . . .
6 CardBus Socket Registers 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
6.1 Socket Event Register 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Socket Mask Register 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Socket Present State Register 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Socket Force Event Register 6–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Socket Control Register 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Socket Power Management Register 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Distributed DMA (DDMA) Registers 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 DDMA Current Address/Base-Address Register 7–1. . . . . . . . . . . . . . . . .
7.2 DDMA Page Register 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 DDMA Current Count/Base Count Register 7–2. . . . . . . . . . . . . . . . . . . . .
7.4 DDMA Command Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 DDMA Status Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 DDMA Request Register 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 DDMA Mode Register 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 DDMA Master Clear Register 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 DDMA Multichannel/Mask Register 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 OHCI-Lynx Controller Programming Model 8–1. . . . . . . . . . . . . . . . . . . . . . . . .
8.1 PCI Configuration Registers 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Vendor ID Register 8–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Device ID Register 8–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 PCI Command Register 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 PCI Status Register 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6 Class Code and Revision ID Register 8–5. . . . . . . . . . . . . . . . . . . . . . . . . .
8.7 Latency Timer and Class Cache Line Size Register 8–5. . . . . . . . . . . . . .
8.8 Header Type and BIST Register 8–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9 Open HCI Registers Base Address Register 8–6. . . . . . . . . . . . . . . . . . . .
8.10 TI Extension Base-Address Register 8–7. . . . . . . . . . . . . . . . . . . . . . . . . . .
8.11 PCI Subsystem Identification Register 8–8. . . . . . . . . . . . . . . . . . . . . . . . . .
8.12 PCI Power Management Capabilities Pointer Register 8–8. . . . . . . . . . . .
8.13 Interrupt Line and Interrupt Pin Registers 8–9. . . . . . . . . . . . . . . . . . . . . . .
8.14 MIN_GNT and MAX_LAT Registers 8–9. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.15 PCI OHCI Control Register 8–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.16 Capability ID and Next Item Pointer Registers 8–10. . . . . . . . . . . . . . . . . . .
8.17 Power Management Capabilities Register 8–11. . . . . . . . . . . . . . . . . . . . . .
8.18 Power Management Control and Status Register 8–12. . . . . . . . . . . . . . . .
8.19 Power Management Extension Register 8–13. . . . . . . . . . . . . . . . . . . . . . . .
8.20 PCI Miscellaneous Configuration Register 8–14. . . . . . . . . . . . . . . . . . . . . .
8.21 Link Enhancement Control Register 8–15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.22 Subsystem Access Identification Register 8–16. . . . . . . . . . . . . . . . . . . . . .
8.23 GPIO Control Register 8–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Open HCI Registers 9–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 OHCI Version Register 9–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 GUID ROM Register 9–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 Asynchronous Transmit Retries Register 9–6. . . . . . . . . . . . . . . . . . . . . . .
vii
9.4 CSR Data Register 9–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5 CSR Compare Register 9–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6 CSR Control Register 9–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.7 Configuration ROM Header Register 9–9. . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8 Bus Identification Register 9–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.9 Bus Options Register 9–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.10 GUID High Register 9–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.11 GUID Low Register 9–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.12 Configuration ROM Mapping Register 9–12. . . . . . . . . . . . . . . . . . . . . . . . . .
9.13 Posted Write Address Low Register 9–12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.14 Posted Write Address High Register 9–13. . . . . . . . . . . . . . . . . . . . . . . . . . .
9.15 Vendor ID Register 9–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.16 Host Controller Control Register 9–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.17 Self ID Buffer Pointer Register 9–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.18 Self ID Count Register 9–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.19 ISO Receive Channel Mask High Register 9–16. . . . . . . . . . . . . . . . . . . . . .
9.20 ISO Receive Channel Mask Low Register 9–17. . . . . . . . . . . . . . . . . . . . . .
9.21 Interrupt Event Register 9–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.22 Interrupt Mask Register 9–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.23 Isochronous Transmit Interrupt Event Register 9–20. . . . . . . . . . . . . . . . . .
9.24 Isochronous Transmit Interrupt Mask Register 9–21. . . . . . . . . . . . . . . . . . .
9.25 Isochronous Receive Interrupt Event Register 9–21. . . . . . . . . . . . . . . . . . .
9.26 Isochronous Receive Interrupt Mask Register 9–22. . . . . . . . . . . . . . . . . . .
9.27 Fairness Control Register (Optional Register) 9–22. . . . . . . . . . . . . . . . . . .
9.28 Link Control Register 9–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.29 Node Identification Register 9–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.30 PHY Control Register 9–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.31 Isochronous Cycle Timer Register 9–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.32 Asynchronous Request Filter High Register 9–27. . . . . . . . . . . . . . . . . . . . .
9.33 Asynchronous Request Filter Low Register 9–29. . . . . . . . . . . . . . . . . . . . .
9.34 Physical Request Filter High Register 9–30. . . . . . . . . . . . . . . . . . . . . . . . . .
9.35 Physical Request Filter Low Register 9–32. . . . . . . . . . . . . . . . . . . . . . . . . .
9.36 Physical Upper Bound Register (Optional Register) 9–32. . . . . . . . . . . . . .
9.37 Asynchronous Context Control Register 9–33. . . . . . . . . . . . . . . . . . . . . . . .
9.38 Asynchronous Context Command Pointer Register 9–34. . . . . . . . . . . . . .
9.39 Isochronous Transmit Context Control Register 9–35. . . . . . . . . . . . . . . . . .
9.40 Isochronous Transmit Context Command Pointer Register 9–36. . . . . . . .
9.41 Isochronous Receive Context Control Register 9–37. . . . . . . . . . . . . . . . . .
9.42 Isochronous Receive Context Command Pointer Register 9–38. . . . . . . .
9.43 Isochronous Receive Context Match Register 9–39. . . . . . . . . . . . . . . . . . .
10 Electrical Characteristics 10–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1 Absolute Maximum Ratings Over Operating Temperature Ranges 10–1.
10.2 Recommended Operating Conditions 10–2. . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Electrical Characteristics Over Recommended Operating Conditions
(unless otherwise noted) 10–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
10.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges
of Supply Voltage and Operating Free-Air Temperature 10–4. . . . . . . . . . .
10.5 PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature 10–4. . . . . . . . . . . . . . . . . . . .
11 Mechanical Information 11–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
List of Illustrations
Figure Title Page
2–1 PCI-to-CardBus Terminal Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 PCI-to-PC Card (16-Bit) Terminal Diagram 2–2. . . . . . . . . . . . . . . . . . . . . . . . .
2–3 MicroStar BGA Ball Diagram 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PCI4410 System Block Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 3-State Bidirectional Buffer 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 TPS2211 Terminal Assignments 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 TPS2211 Typical Application 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Zoomed Video Subsystem 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Sample Application of SPKROUT and CAUDPWM 3–7. . . . . . . . . . . . . . . . . .
3–7 Two Sample LED Circuits 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Serial EEPROM Application 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 Serial Bus Start/Stop Conditions and Bit Transfers 3–12. . . . . . . . . . . . . . . . . .
3–10 Serial Bus Protocol Acknowledge 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Serial Bus Protocol – Byte Write 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Serial Bus Protocol – Byte Read 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 EEPROM Interface Doubleword Data Collection 3–13. . . . . . . . . . . . . . . . . . . .
3–14 EEPROM Data Format 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–15 IRQ Implementation 3–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 Suspend Functional Implementation 3–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Signal Diagram of Suspend Function 3–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 RI_OUT
Functional Diagram 3–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 ExCA Register Access Through I/O 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 ExCA Register Access Through Memory 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Accessing CardBus Socket Registers Through PCI Memory 6–1. . . . . . . . . .
x
List of Tables
Table Title Page
2–1 CardBus And 16-Bit PC Card Signal Names by PDV Terminal Number 2–4
2–2 CardBus And 16-Bit PC Card Signal Names by GHK Terminal Number 2–6
2–3 CardBus PC Card Signal Names Sorted Alphabetically to GHK/PDV
Terminal Number 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 16-Bit PC Card Signal Names Sorted Alphabetically to GHK/PDV
Terminal Number 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Power Supply Terminals 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 PC Card Power Switch Terminals 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 PCI System Terminals 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 PCI Address and Data Terminals 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 PCI Interface Control Terminals 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Multifunction and Miscellaneous Terminals 2–15. . . . . . . . . . . . . . . . . . . . . . . . .
2–11 16-Bit PC Card Address and Data Terminals 2–16. . . . . . . . . . . . . . . . . . . . . . .
2–12 16-Bit PC Card Interface Control Terminals 2–17. . . . . . . . . . . . . . . . . . . . . . . . .
2–13 CardBus PC Card Interface System Terminals 2–18. . . . . . . . . . . . . . . . . . . . . .
2–14 CardBus PC Card Address and Data Terminals 2–19. . . . . . . . . . . . . . . . . . . . .
2–15 CardBus PC Card Interface Control Terminals 2–20. . . . . . . . . . . . . . . . . . . . . .
2–16 IEEE1394 PHY/Link Interface Terminals 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . .
2–17 Zoomed Video Interface Terminals 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PC Card Card-Detect and Voltage-Sense Connections 3–4. . . . . . . . . . . . . .
3–2 Distributed DMA Registers 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 PC/PCI Channel Assignments 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 I/O Addresses Used for PC/PCI DMA 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 CardBus Socket Registers 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Registers and Bits Loadable Through Serial EEPROM 3–14. . . . . . . . . . . . . . .
3–7 Interrupt Mask and Flag Registers 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 PC Card Interrupt Events and Description 3–17. . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 SMI Control 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 Power Management Registers 3–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 PCI Configuration Registers (Functions 0 and 1) 4–1. . . . . . . . . . . . . . . . . . . .
4–2 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Secondary Status Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Bridge Control Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 System Control Register 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 General Status Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 General Control Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Multifunction Routing Register 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
4–10 Retry Status Register 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–11 Card Control Register 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–12 Device Control Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–13 Diagnostic Register 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–14 Socket DMA Register 0 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–15 Socket DMA Register 1 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–16 Power Management Capabilities Register 4–28. . . . . . . . . . . . . . . . . . . . . . . . . .
4–17 Power Management Control/Status Register 4–29. . . . . . . . . . . . . . . . . . . . . . .
4–18 Power Management Control/Status Register Bridge Support Extensions 4–30
4–19 General-Purpose Event Status Register 4–31. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–20 General-Purpose Event Enable Register 4–32. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–21 General-Purpose Input Register 4–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–22 General-Purpose Output Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 ExCA Registers and Offsets 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 ExCA Identification and Revision Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . .
5–3 ExCA Interface Status Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 ExCA Power Control Register 82365SL Support 5–6. . . . . . . . . . . . . . . . . . . .
5–5 ExCA Power Control Register 82365SL-DF Support 5–6. . . . . . . . . . . . . . . . .
5–6 ExCA Interrupt and General Control Register 5–7. . . . . . . . . . . . . . . . . . . . . . .
5–7 ExCA Card Status-Change Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 ExCA Card Status-Change-Interrupt Configuration Register 5–9. . . . . . . . . .
5–9 ExCA Address Window Enable Register 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 ExCA I/O Window Control Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 ExCA Memory Windows 0–4 Start-Address High-Byte Registers 5–15. . . . . .
5–12 ExCA Memory Windows 0–4 End-Address High-Byte Registers 5–17. . . . . . .
5–13 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers 5–19. . . . .
5–14 ExCA I/O Card Detect and General Control Register 5–21. . . . . . . . . . . . . . . .
5–15 ExCA Global Control Register 5–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 CardBus Socket Registers 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Socket Event Register 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Socket Mask Register 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Socket Present State Register 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Socket Force Event Register 6–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Socket Control Register 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7 Socket Power Management Register 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1 Distributed DMA Registers 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 DDMA Command Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 DDMA Status Register 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–4 DDMA Mode Register 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–5 DDMA Multichannel/Mask Register 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1 Bit Field Access Tag Descriptions 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–2 PCI Configuration Register Map 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–3 PCI Command Register 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–4 PCI Status Register 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
8–5 Class Code and Revision ID Register 8–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–6 Latency Timer and Class Cache Line Size Register 8–5. . . . . . . . . . . . . . . . .
8–7 Header Type and BIST Register 8–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–8 Open HCI Registers Base-Address Register 8–6. . . . . . . . . . . . . . . . . . . . . . .
8–9 TI Extension Base-Address Register 8–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–10 PCI Subsystem Identification Register 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–11 Interrupt Line and Interrupt Pin Registers 8–9. . . . . . . . . . . . . . . . . . . . . . . . . .
8–12 MIN_GNT and MAX_LAT Registers 8–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–13 Capability ID and Next Item Pointer Registers 8–10. . . . . . . . . . . . . . . . . . . . . .
8–14 Power Management Capabilities Register 8–11. . . . . . . . . . . . . . . . . . . . . . . . . .
8–15 Power Management Control and Status Register 8–12. . . . . . . . . . . . . . . . . . .
8–16 Power Management Extension Register 8–13. . . . . . . . . . . . . . . . . . . . . . . . . . .
8–17 PCI Miscellaneous Configuration Register 8–14. . . . . . . . . . . . . . . . . . . . . . . . .
8–18 Link Enhancement Control Register 8–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–19 Subsystem Access Identification Register 8–16. . . . . . . . . . . . . . . . . . . . . . . . . .
8–20 GPIO Control Register 8–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–1 Open HCI Register Map 9–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–2 OHCI Version Register 9–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–3 GUID ROM Register 9–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–4 Asynchronous Transmit Retries Register 9–6. . . . . . . . . . . . . . . . . . . . . . . . . . .
9–5 CSR Control Register 9–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–6 Configuration ROM Header Register 9–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–7 Bus Options Register 9–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–8 Configuration ROM Mapping Register 9–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–9 Posted Write Address Low Register 9–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–10 Posted Write Address High Register 9–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–11 Host Controller Control Register 9–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–12 Self ID Count Register 9–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–13 ISO Receive Channel Mask High Register 9–16. . . . . . . . . . . . . . . . . . . . . . . . .
9–14 ISO Receive Channel Mask Low Register 9–17. . . . . . . . . . . . . . . . . . . . . . . . . .
9–15 Interrupt Event Register 9–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–16 Interrupt Mask Register 9–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–17 Isochronous Transmit Interrupt Event Register 9–20. . . . . . . . . . . . . . . . . . . . . .
9–18 Isochronous Receive Interrupt Event Register 9–21. . . . . . . . . . . . . . . . . . . . . .
9–19 Fairness Control Register 9–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–20 Link Control Register 9–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–21 Node Identification Register 9–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–22 PHY Control Register 9–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–23 Isochronous Cycle Timer Register 9–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–24 Asynchronous Request Filter High Register 9–27. . . . . . . . . . . . . . . . . . . . . . . .
9–25 Asynchronous Request Filter Low Register 9–29. . . . . . . . . . . . . . . . . . . . . . . . .
9–26 Physical Request Filter High Register 9–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–27 Physical Request Filter Low Register 9–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–28 Asynchronous Context Control Register 9–33. . . . . . . . . . . . . . . . . . . . . . . . . . .
xiii
9–29 Asynchronous Context Command Pointer Register 9–34. . . . . . . . . . . . . . . . . .
9–30 Isochronous Transmit Context Control Register 9–35. . . . . . . . . . . . . . . . . . . . .
9–31 Isochronous Receive Context Control Register 9–37. . . . . . . . . . . . . . . . . . . . .
9–32 Isochronous Receive Context Match Register 9–39. . . . . . . . . . . . . . . . . . . . . .
xiv
1–1
1 Introduction
The Texas Instruments PCI4410 is an integrated single-socket PC Card controller and IEEE 1394 Open HCI host
controller. This high-performance integrated solution provides the latest in both PC Card and IEEE 1394 technology .
1.1 Description
The PCI4410 is a dual-function PCI device compliant with
PCI Local Bus Specification 2.2
. Function 0 provides the
independent PC Card socket controller compliant with the
1997 PC Card Standard
. The PCI4410 provides features
that make it the best choice for bridging between the PCI bus and PC Cards, and supports either 16-bit or CardBus
PC Cards in the socket, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI4410 is
register compatible with the Intel 82365SL–DF and 82365SL ExCA controllers. The PCI4410 internal data path
logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.
Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting.
The PCI4410 can be programmed to accept posted writes to improve bus utilization.
Function 1 of the PCI4410 is compatible with IEEE1394A and the latest 1394 open host controller interface (OHCI)
specifications. The chip provides the IEEE1394 link function and is compatible with data rates of 100, 200, and 400
Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The
PCI4410 provides physical write posting and a highly tuned physical data path for SBP-2 performance. Multiple cache
line burst transfers, advanced internal arbitration, and bus holding buffers on the PHY/Link interface are other
features that make the PCI4410 the best-in-class 1394 Open HCI solution.
The PCI4410 provides an internally buffered zoomed video (ZV) path. This reduces the design effort of PC board
manufacturers to add a ZV-compatible solution and ensures compliance with the CardBus loading specifications.
Various implementation-specific functions and general-purpose inputs and outputs are provided through eight
multifunction terminals. These terminals present a system with options in PC/PCI DMA, PCI LOCK
and parallel
interrupts, PC Card activity indicator LEDs, and other platform-specific signals. ACPI-compliant general-purpose
events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming
interface is included for the general-purpose inputs and outputs.
The PCI4410 is compliant with the latest
PCI Bus Power Management Specification
, and provides several low-power
modes which enable the host power system to further reduce power consumption. The
PC Card (CardBus) Controller
and
IEEE 1394 Host Controller Device Class Specifications
required for Microsoft OnNowt power management are
supported. Furthermore, an advanced complementary metal-oxide semiconductor (CMOS) process achieves low
system power consumption.
Unused PCI4410 inputs must be pulled to a valid logic level using a 43-kΩ resistor.
1.2 Features
The PCI4410 supports the following features:
• Ability to wake from D3
hot
and D3
cold
• Fully compatible with the Intel 430TX (Mobile Triton II) chipset
• A 208-pin low-profile QFP (PDV) or 209-ball MICROSTAR BGA ball grid array (GHK) package
Intel is a trademark of Intel Corporation.
Microsoft OnNow is a trademark of Microsoft Corporation.
MicroStar BGA is a trademark of Texas Instruments Incorporated
1–2
• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
• Single PC Card or CardBus slot with hot insertion and removal
• Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
• Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI
interrupts, and serial ISA IRQ and PCI interrupts
• Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
• Pipelined architecture allows greater than 130M bps sustained throughput from CardBus-to-PCI and from
PCI-to-CardBus
• Interface to parallel single-slot PC Card power interface switches like the TI TPS2211
• Up to five general-purpose I/Os
• Programmable output select for CLKRUN
• Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
• Two I/O windows and two memory windows available to the CardBus socket
• Exchangeable Card Architecture (ExCA) compatible registers are mapped in memory and I/O space
• Intel 82365SL-DF and 82365SL register compatible
• Distributed DMA (DDMA) and PC/PCI DMA
• 16-Bit DMA on the PC Card socket
• Ring indicate, SUSPEND
, PCI CLKRUN, and CardBus CLKRUN
• Socket activity LED pins
• PCI bus lock (LOCK
)
• Advanced submicron, low-power CMOS technology
• Internal ring oscillator
• OHCI link function designed to
IEEE 1394 Open Host Controller Interface (OHCI) Specification
• Implements PCI burst transfers and deep FIFOs to tolerate large host latency
• Supports physical write posting of up to 3 outstanding transactions
• OHCI link function is IEEE 1394-1995 compliant and compatible with Proposal 1394a
• Supports serial bus data rates of 100, 200, and 400 Mbits/second
• Provides bus-hold buffers on the PHY-Link I/F for low-cost single-capacitor isolation
TI is a trademark of Texas Instruments Incorporated
1–3
1.3 Related Documents
•
Advanced Configuration and Power Interface (ACPI) Specification
(Revision 2.0)
•
PCI Bus Power Management Interface Specification
(Revision 1.1)
•
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
(Revision 1.)
•
PCI Local Bus Specification
(Revision 2.2)
•
PCI Mobile Design Guide
(Revision 1.0)
•
PCI14xx Implemenation Guide for D3 Wake-Up
•
1997 PC Card Standard
•
PC 98/99
•
Serialized IRQ Support for PCI Systems
(Revision 6)
1.4 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI4410 PC Card controller 3.3-V, 5-V tolerant I/Os 208-pin LQFP
209-ball PBGA
1–4
2–1
2 Terminal Descriptions
The PCI4410 is packaged in either a 209-ball GHK MICROSTAR BGA or a 208-terminal PDV package. The PCI4410
is a single-socket CardBus bridge with integrated OHCI link. Figure 2–1 is a terminal diagram of the PDV package
with PCI-to-CardBus signal names. Figure 2–2 is a terminal diagram of the PDV package with PCI-to-PC Card signal
names. Figure 2–3 is a terminal diagram of the GHK package.
CTRDY
CIRDY
CFRAME
CC/BE2
CAD17
GND
CAD18
CAD19
CVS2
CAD20
CRST
CAD21
CAD22
VCC
CREQ
CAD23
CC/BE3
VCCCB
CAD24
CAD25
CAD26
GND
CVS1
CINT
CSERR
CAUDIO
CSTSCHG
CCLKRUN
CCD2
VCC
CAD27
CAD28
CAD29
CAD30
CRSVD
CAD31
LPS
PHY_LREQ
VCC
PHY_CLK
PHY_CTL(0)
PHY_CTL(1)
LINKON
PHY_DATA0
VCCL
PHY_DATA1
GND
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
123456789101112131415161718192021
22
2324252627282930313233343536373839404142434445464748495051
PHY_DATA6
CCLK
CDEVSEL
CGNT
CSTOP
CPERR
CBLOCK
VCC
CPAR
CRSVD
CC/BE1
CAD16
CAD14
CAD15
CAD12
GND
CAD13
CAD11
CAD10
VCCCB
CAD9
CC/BE0
CAD8
VCC
CAD7
CRSVD
CAD5
CAD6
CAD3
CAD4
CAD1
GND
CAD2
CAD0
CCD1
VCCD1
VCCD0
ZV_PCLK
ZV_SDATA
ZV_LRCLK
ZV_MCLK
ZV_UV(7)
VCC
ZV_SCLK
ZV_UV(5)
ZV_UV(6)
ZV_UV(3)
GND
ZV_UV(4)
ZV_UV(1)
ZV_UV(2)
ZV_UV(0)
ZV_Y(7)
ZV_Y(6)
ZV_Y(5)
ZV_Y(4)
ZV_Y(3)
GND
ZV_Y(2)
ZV_Y(1)
ZV_Y(0)
ZV_VSYNC
ZV_HREF
RSVD
INTB
INTA
VCC
LED_SKT
RSVD
VPPD1
VPPD0
SUSPEND
MFUNC6
MFUNC5
MFUNC4
GRST
MFUNC3
MFUNC2
VCCI
SPKROUT
MFUNC1
MFUNC0
RI_OUT/PME
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VCC
AD7
C/BE0
AD8
AD9
AD10
VCCP
AD11
GND
AD12
AD13
AD14
AD15
C/BE1
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
PHY_DATA7
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
GND
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
VCC
PHY_RSVD
PHY_RSVD
REQ
GNT
AD31
AD30
AD29
GND
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
VCC
AD23
AD22
AD21
VCCP
AD20
PRST
PCLK
GND
AD19
AD18
AD17
AD16
C/BE2
FRAME
IRDY
VCC
TRDY
DEVSEL
STOP
PERR
SERR
PAR
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Figure 2–1. PCI-to-CardBus Terminal Diagram
2–2
ADDR22
ADDR15
ADDR23
ADDR12
ADDR24
GND
ADDR7
ADDR25
VS2
ADDR6
RESET
ADDR5
ADDR4
VCC
INPACK
ADDR3
REG
VCCCB
ADDR2
ADDR1
ADDR0
GND
VS1
READY(IREQ)
WAIT
BVD2(SPKR)
BVD1(STSCHG/RI)
WP(IOIS16)
CD2
VCC
DATA0
DATA8
DATA1
DATA9
DATA2
DATA10
LPS
PHY_LREQ
VCC
PHY_CLK
PHY_CTL(0)
PHY_CTL(1)
LINKON
PHY_DATA0
VCCL
PHY_DATA1
GND
PHY_DATA2
PHY_DATA3
PHY_DATA4
PHY_DATA5
123456789101112131415
16
1718192021222324252627282930313233343536373839404142434445464748495051
PHY_DATA6
ADDR16
ADDR21WEADDR20
ADDR14
ADDR19
VCC
ADDR13
ADDR18
ADDR8
ADDR17
ADDR9
IOWR
ADDR11
GND
IORDOECE2
VCCCB
ADDR10
CE1
DATA15
VCC
DATA7
DATA14
DATA6
DATA13
DATA5
DATA12
DATA4
GND
DATA11
DATA3
CD1
VCCD1
VCCD0
ZV_PCLK
ZV_SDATA
ZV_LRCLKZV_MCLK
ZV_UV(7)
VCC
ZV_SCLK
ZV_UV(5)
ZV_UV(6)
ZV_UV(3)
GND
ZV_UV(4)
ZV_UV(1)
ZV_UV(2)
ZV_UV(0)
ZV_Y(7)
ZV_Y(6)
ZV_Y(5)
ZV_Y(4)
ZV_Y(3)
GND
ZV_Y(2)
ZV_Y(1)
ZV_Y(0)
ZV_VSYNC
ZV_HREF
RSVD
INTB
INTA
VCC
LED_SKT
RSVD
VPPD1
VPPD0
SUSPEND
MFUNC6
MFUNC5
MFUNC4
GRST
MFUNC3
MFUNC2
VCCI
SPKROUT
MFUNC1
MFUNC0
RI_OUT/PME
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VCC
AD7
C/BE0
AD8
AD9
AD10
VCCP
AD11
GND
AD12
AD13
AD14
AD15
C/BE1
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
PHY_DATA7
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
GND
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
PHY_RSVD
VCC
PHY_RSVD
PHY_RSVD
REQ
GNT
AD31
AD30
AD29
GND
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
VCC
AD23
AD22
AD21
VCCP
AD20
PRST
PCLK
GND
AD19
AD18
AD17
AD16
C/BE2
FRAME
IRDY
VCC
TRDY
DEVSEL
STOP
PERR
SERR
PAR
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Figure 2–2. PCI-to-PC Card (16-Bit) Terminal Diagram
2–3
1917
16
13141511
12
9
810
V
U
W
R
N
P
L
M
K
T
75
6
3
4
H
F
G
E
C
D
1
A
B
2
J
18
Figure 2–3. MICROSTAR BGA Ball Diagram
Table 2–1 shows the terminal assignments for the 208-terminal PDV CardBus and 16-bit PC Card signal names.
Table 2–2 shows the terminal assignments for the 209-ball GHK CardBus and 16-bit PC Card signal names.
Table 2–3 shows the CardBus PC Card signal names sorted alphabetically to the GHK/PDV terminal numbers.
Table 2–4 shows the 16-bit PC Card signal names sorted alphabetically to the GHK/PDV terminal numbers.
2–4
Table 2–1. CardBus and 16-Bit PC Card Signal Names by PDV Terminal Number
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
NO.
CARDBUS 16-BIT
NO.
CARDBUS 16-BIT
NO.
CARDBUS 16-BIT
1 PHY_DATA7 PHY_DATA7 44 FRAME FRAME 87 VPPD0 VPPD0
2 PHY_RSVD PHY_RSVD 45 IRDY IRDY 88 VPPD1 VPPD1
3 PHY_RSVD PHY_RSVD 46 V
CC
V
CC
89 RSVD RSVD
4 PHY_RSVD PHY_RSVD 47 TRDY TRDY 90 LED_SKT LED_SKT
5 PHY_RSVD PHY_RSVD 48 DEVSEL DEVSEL 91 V
CC
V
CC
6 GND GND 49 STOP STOP 92 INTA INTA
7 PHY_RSVD PHY_RSVD 50 PERR PERR 93 INTB INTB
8 PHY_RSVD PHY_RSVD 51 SERR SERR 94 RSVD RSVD
9 PHY_RSVD PHY_RSVD 52 PAR PAR 95 ZV_HREF ZV_HREF
10 PHY_RSVD PHY_RSVD 53 C/BE1 C/BE1 96 ZV_VSYNC ZV_VSYNC
11 PHY_RSVD PHY_RSVD 54 AD15 AD15 97 ZV_Y(0) ZV_Y(0)
12 PHY_RSVD PHY_RSVD 55 AD14 AD14 98 ZV_Y(1) ZV_Y(1)
13 PHY_RSVD PHY_RSVD 56 AD13 AD13 99 ZV_Y(2) ZV_Y(2)
14 V
CC
V
CC
57 AD12 AD12 100 GND GND
15 PHY_RSVD PHY_RSVD 58 GND GND 101 ZV_Y(3) ZV_Y(3)
16 PHY_RSVD PHY_RSVD 59 AD11 AD11 102 ZV_Y(4) ZV_Y(4)
17 REQ REQ 60 V
CCP
V
CCP
103 ZV_Y(5) ZV_Y(5)
18 GNT GNT 61 AD10 AD10 104 ZV_Y(6) ZV_Y(6)
19 AD31 AD31 62 AD9 AD9 105 ZV_Y(7) ZV_Y(7)
20 AD30 AD30 63 AD8 AD8 106 ZV_UV(0) ZV_UV(0)
21 AD29 AD29 64 C/BE0 C/BE0 107 ZV_UV(2) ZV_UV(2)
22 GND GND 65 AD7 AD7 108 ZV_UV(1) ZV_UV(1)
23 AD28 AD28 66 V
CC
V
CC
109 ZV_UV(4) ZV_UV(4)
24 AD27 AD27 67 AD6 AD6 110 GND GND
25 AD26 AD26 68 AD5 AD5 111 ZV_UV(3) ZV_UV(3)
26 AD25 AD25 69 AD4 AD4 112 ZV_UV(6) ZV_UV(6)
27 AD24 AD24 70 AD3 AD3 113 ZV_UV(5) ZV_UV(5)
28 C/BE3 C/BE3 71 AD2 AD2 114 ZV_SCLK ZV_SCLK
29 IDSEL IDSEL 72 AD1 AD1 115 V
CC
V
CC
30 V
CC
V
CC
73 AD0 AD0 116 ZV_UV(7) ZV_UV(7)
31 AD23 AD23 74 GND GND 117 ZV_MCLK ZV_MCLK
32 AD22 AD22 75 RI_OUT/PME RI_OUT/PME 118 ZV_LRCLK ZV_LRCLK
33 AD21 AD21 76 MFUNC0 MFUNC0 119 ZV_SDATA ZV_SDATA
34 V
CCP
V
CCP
77 MFUNC1 MFUNC1 120 ZV_PCLK ZV_PCLK
35 AD20 AD20 78 SPKROUT SPKROUT 121 VCCD0 VCCD0
36 PRST PRST 79 V
CCI
V
CCI
122 VCCD1 VCCD1
37 PCLK PCLK 80 MFUNC2 MFUNC2 123 CCD1 CD1
38 GND GND 81 MFUNC3 MFUNC3 124 CAD0 DATA3
39 AD19 AD19 82 GRST GRST 125 CAD2 DATA11
40 AD18 AD18 83 MFUNC4 MFUNC4 126 GND GND
41 AD17 AD17 84 MFUNC5 MFUNC5 127 CAD1 DATA4
42 AD16 AD16 85 MFUNC6 MFUNC6 128 CAD4 DATA12
43 C/BE2 C/BE2 86 SUSPEND SUSPEND 129 CAD3 DATA5
2–5
Table 2–1. CardBus and 16-Bit PC Card Signal Names by PDV Terminal Number (Continued)
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
NO.
CARDBUS 16-BIT
NO.
CARDBUS 16-BIT
NO.
CARDBUS 16-BIT
130 CAD6 DATA13 157 CTRDY ADDR22 184 CCLKRUN WP(IOIS16)
131 CAD5 DATA6 158 CIRDY ADDR15 185 CCD2 CD2
132 CRSVD DATA14 159 CFRAME ADDR23 186 V
CC
V
CC
133 CAD7 DATA7 160 CC/BE2 ADDR12 187 CAD27 DATA0
134 V
CC
V
CC
161 CAD17 ADDR24 188 CAD28 DATA8
135 CAD8 DATA15 162 GND GND 189 CAD29 DATA1
136 CC/BE0 CE1 163 CAD18 ADDR7 190 CAD30 DATA9
137 CAD9 ADDR10 164 CAD19 ADDR25 191 CRSVD DATA2
138 V
CCCB
V
CCCB
165 CVS2 VS2 192 CAD31 DATA10
139 CAD10 CE2 166 CAD20 ADDR6 193 LPS LPS
140 CAD11 OE 167 CRST RESET 194 PHY_LREQ PHY_LREQ
141 CAD13 IORD 168 CAD21 ADDR5 195 V
CC
V
CC
142 GND GND 169 CAD22 ADDR4 196 PHY_CLK PHY_CLK
143 CAD12 ADDR11 170 V
CC
V
CC
197 PHY_CTL(0) PHY_CTL(0)
144 CAD15 IOWR 171 CREQ INPACK 198 PHY_CTL(1) PHY_CTL(1)
145 CAD14 ADDR9 172 CAD23 ADDR3 199 LINKON LINKON
146 CAD16 ADDR17 173 CC/BE3 REG 200 PHY_DATA0 PHY_DATA0
147 CC/BE1 ADDR8 174 V
CCCB
V
CCCB
201 V
CCL
V
CCL
148 CRSVD ADDR18 175 CAD24 ADDR2 202 PHY_DATA1 PHY_DATA1
149 CPAR ADDR13 176 CAD25 ADDR1 203 GND GND
150 V
CC
V
CC
177 CAD26 ADDR0 204 PHY_DATA2 PHY_DATA2
151 CBLOCK ADDR19 178 GND GND 205 PHY_DATA3 PHY_DATA3
152 CPERR ADDR14 179 CVS1 VS1 206 PHY_DATA4 PHY_DATA4
153 CSTOP ADDR20 180 CINT READY(IREQ) 207 PHY_DATA5 PHY_DATA5
154 CGNT WE 181 CSERR WAIT 208 PHY_DATA6 PHY_DATA6
155 CDEVSEL ADDR21 182 CAUDIO BVD2(SPKR)
156 CCLK ADDR16 183 CSTSCHG BVD1
(STSCHG
/RI)
2–6
Table 2–2. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
TERM
.
NO.
CARDBUS 16-BIT
TERM
.
NO.
CARDBUS 16-BIT
TERM
.
NO.
CARDBUS 16-BIT
A4 PHY_DATA6 PHY_DATA6 E8 PHY_LREQ PHY_LREQ H14 CAD13 IORD
A5 GND GND E9 CAD29 DATA1 H15 GND GND
A6 LINKON LINKON E10 CSTSCHG BVD1
(STSCHG
/RI)
H17 CAD11 OE
A7 V
CC
V
CC
E11 GND GND H18 CAD10 CE2
A8 CAD30 DATA9 E12 CREQ INPACK H19 V
CCCB
V
CCCB
A9 CCD2 CD2 E13 CVS2 VS2 J1 AD31 AD31
A10 CINT READY(IREQ) E14 CFRAME ADDR23 J2 AD30 AD30
A11 CAD24 ADDR2 E17 CDEVSEL ADDR21 J3 AD29 AD29
A12 V
CCCB
V
CCCB
E18 CSTOP ADDR20 J5 GND GND
A13 V
CC
V
CC
E19 CBLOCK ADDR19 J6 AD28 AD28
A14 CAD20 ADDR6 F1 PHY_RSVD PHY_RSVD J14 CC/BE0 CE1
A15 GND GND F2 PHY_RSVD PHY_RSVD J15 CAD9 ADDR10
A16 CTRDY ADDR22 F3 PHY_RSVD PHY_RSVD J17 CAD8 DATA15
B5 PHY_DATA3 PHY_DATA3 F5 PHY_RSVD PHY_RSVD J18 V
CC
V
CC
B6 PHY_DATA0 PHY_DATA0 F6 PHY_DATA2 PHY_DATA2 J19 CAD7 DATA7
B7 PHY_CLK PHY_CLK F7 PHY_CTL(1) PHY_CTL(1) K1 AD27 AD27
B8 CRSVD DATA2 F8 LPS LPS K2 AD26 AD26
B9 V
CC
V
CC
F9 CAD28 DATA8 K3 AD25 AD25
B10 CSERR WAIT F10 CCLKRUN WP(IOIS16) K5 AD24 AD24
B11 CAD25 ADDR1 F11 CVS1 VS1 K6 C/BE3 C/BE3
B12 CC/BE3 REG F12 CRST RESET K14 CRSVD DATA14
B13 CAD22 ADDR4 F13 CC/BE2 ADDR12 K15 CAD5 DATA6
B14 CAD19 ADDR25 F14 CPERR ADDR14 K17 CAD6 DATA13
B15 CAD17 ADDR24 F15 CGNT WE K18 CAD3 DATA5
C5 PHY_DATA5 PHY_DATA5 F17 V
CC
V
CC
K19 CAD4 DATA12
C6 PHY_DATA1 PHY_DATA1 F18 CRSVD ADDR18 L1 IDSEL IDSEL
C7 PHY_CTL(0) PHY_CTL(0) F19 CC/BE1 ADDR8 L2 V
CC
V
CC
C8 CAD31 DATA10 G1 V
CC
V
CC
L3 AD23 AD23
C9 CAD27 DATA0 G2 PHY_RSVD PHY_RSVD L5 AD21 AD21
C10 CAUDIO BVD2(SPKR) G3 PHY_RSVD PHY_RSVD L6 AD22 AD22
C11 CAD26 ADDR0 G5 PHY_RSVD PHY_RSVD L14 CAD1 DATA4
C12 CAD23 ADDR3 G6 PHY_RSVD PHY_RSVD L15 GND GND
C13 CAD21 ADDR5 G14 CAD16 ADDR17 L17 CAD2 DATA11
C14 CAD18 ADDR7 G15 CPAR ADDR13 L18 CAD0 DATA3
C15 CIRDY ADDR15 G17 CAD14 ADDR9 L19 CCD1 CD1
D1 PHY_DATA7 PHY_DATA7 G18 CAD15 IOWR M1 V
CCP
V
CCP
D19 CCLK ADDR16 G19 CAD12 ADDR11 M2 AD20 AD20
E1 GND GND H1 GNT GNT M3 PRST PRST
E2 PHY_RSVD PHY_RSVD H2 REQ REQ M5 GND GND
E3 PHY_RSVD PHY_RSVD H3 PHY_RSVD PHY_RSVD M6 PCLK PCLK
E6 PHY_DATA4 PHY_DATA4 H5 PHY_RSVD PHY_RSVD M14 V
CC
V
CC
E7 V
CCL
V
CCL
H6 PHY_RSVD PHY_RSVD M15 ZV_SDATA ZV_SDATA
2–7
Table 2–2. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number (Continued)
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
TERM.
SIGNAL NAME
TERM
.
NO.
CARDBUS 16-BIT
TERM
.
NO.
CARDBUS 16-BIT
TERM
.
NO.
CARDBUS 16-BIT
M17 ZV_PCLK ZV_PCLK P18 ZV_UV(6) ZV_UV(6) U14 ZV_Y(1) ZV_Y(1)
M18 VCCD0 VCCD0 P19 ZV_SCLK ZV_SCLK U15 ZV_Y(5) ZV_Y(5)
M19 VCCD1 VCCD1 R1 TRDY TRDY V5 AD12 AD12
N1 AD19 AD19 R2 STOP STOP V6 V
CCP
V
CCP
N2 AD18 AD18 R3 SERR SERR V7 AD7 AD7
N3 AD17 AD17 R6 AD14 AD14 V8 AD4 AD4
N5 IRDY IRDY R7 AD10 AD10 V9 AD1 AD1
N6 AD16 AD16 R8 AD6 AD6 V10 MFUNC1 MFUNC1
N14 ZV_UV(1) ZV_UV(1) R9 GND GND V11 GRST GRST
N15 ZV_UV(5) ZV_UV(5) R10 V
CCI
V
CCI
V12 VPPD0 VPPD0
N17 ZV_UV(7) ZV_UV(7) R11 MFUNC6 MFUNC6 V13 INTA INTA
N18 ZV_MCLK ZV_MCLK R12 LED_SKT LED_SKT V14 ZV_VSYNC ZV_VSYNC
N19 ZV_LRCLK ZV_LRCLK R13 ZV_Y(0) ZV_Y(0) V15 ZV_Y(3) ZV_Y(3)
P1 C/BE2 C/BE2 R14 ZV_Y(4) ZV_Y(4) W4 C/BE1 C/BE1
P2 FRAME FRAME R17 ZV_UV(0) ZV_UV(0) W5 GND GND
P3 V
CC
V
CC
R18 ZV_UV(4) ZV_UV(4) W6 AD9 AD9
P5 PERR PERR R19 GND GND W7 V
CC
V
CC
P6 DEVSEL DEVSEL T1 PAR PAR W8 AD3 AD3
P7 AD13 AD13 T19 ZV_Y(7) ZV_Y(7) W9 AD2 AD2
P8 AD8 AD8 U5 AD15 AD15 W10 MFUNC0 MFUNC0
P9 RI_OUT/PME RI_OUT/PME U6 AD11 AD11 W11 MFUNC3 MFUNC3
P10 MFUNC2 MFUNC2 U7 C/BE0 C/BE0 W12 SUSPEND SUSPEND
P11 MFUNC5 MFUNC5 U8 AD5 AD5 W13 V
CC
V
CC
P12 RSVD RSVD U9 AD0 AD0 W14 ZV_HREF ZV_HREF
P13 RSVD RSVD U10 SPKROUT SPKROUT W15 ZV_Y(2) ZV_Y(2)
P14 GND GND U11 MFUNC4 MFUNC4 W16 ZV_Y(6) ZV_Y(6)
P15 ZV_UV(2) ZV_UV(2) U12 VPPD1 VPPD1
P17 ZV_UV(3) ZV_UV(3) U13 INTB INTB
2–8
Table 2–3. CardBus PC Card Signal Names Sorted Alphabetically to GHK/PDV Terminal Number
TERM. NO.
TERM. NO.
TERM. NO.
TERM. NO.
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
AD0 73 U9 CAD11 140 H17 CRST 167 F12 PHY_CLK 196 B7
AD1 72 V9 CAD12 143 G19 CRSVD 132 K14 PHY_CTL(0) 197 C7
AD2 71 W9 CAD13 141 H14 CRSVD 148 F18 PHY_CTL(1) 198 F7
AD3 70 W8 CAD14 145 G17 CRSVD 191 B8 PHY_DATA0 200 B6
AD4 69 V8 CAD15 144 G18 CSERR 181 B10 PHY_DATA1 202 C6
AD5 68 U8 CAD16 146 G14 CSTOP 153 E18 PHY_DATA2 204 F6
AD6 67 R8 CAD17 161 B15 CSTSCHG 183 E10 PHY_DATA3 205 B5
AD7 65 V7 CAD18 163 C14 CTRDY 157 A16 PHY_DATA4 206 E6
AD8 63 P8 CAD19 164 B14 CVS1 179 F11 PHY_DATA5 207 C5
AD9 62 W6 CAD20 166 A14 CVS2 165 E13 PHY_DATA6 208 A4
AD10 61 R7 CAD21 168 C13 DEVSEL 48 P6 PHY_DATA7 1 D1
AD11 59 U6 CAD22 169 B13 FRAME 44 P2 PHY_LREQ 194 E8
AD12 57 V5 CAD23 172 C12 GND 6 E1 PHY_RSVD 2 E3
AD13 56 P7 CAD24 175 A11 GND 22 J5 PHY_RSVD 3 F5
AD14 55 R6 CAD25 176 B11 GND 38 M5 PHY_RSVD 4 G6
AD15 54 U5 CAD26 177 C11 GND 58 W5 PHY_RSVD 5 E2
AD16 42 N6 CAD27 187 C9 GND 74 R9 PHY_RSVD 7 F3
AD17 41 N3 CAD28 188 F9 GND 100 P14 PHY_RSVD 8 F2
AD18 40 N2 CAD29 189 E9 GND 110 R19 PHY_RSVD 9 G5
AD19 39 N1 CAD30 190 A8 GND 126 L15 PHY_RSVD 10 F1
AD20 35 M2 CAD31 192 C8 GND 142 H15 PHY_RSVD 11 H6
AD21 33 L5 CAUDIO 182 C10 GND 162 A15 PHY_RSVD 12 G3
AD22 32 L6 C/BE0 64 U7 GND 178 E11 PHY_RSVD 13 G2
AD23 31 L3 C/BE1 53 W4 GND 203 A5 PHY_RSVD 15 H5
AD24 27 K5 C/BE2 43 P1 GNT 18 H1 PHY_RSVD 16 H3
AD25 26 K3 C/BE3 28 K6 GRST 82 V11 PRST 36 M3
AD26 25 K2 CBLOCK 151 E19 IDSEL 29 L1 REQ 17 H2
AD27 24 K1 CC/BE0 136 J14 INTA 92 V13 RI_OUT/PME 75 P9
AD28 23 J6 CC/BE1 147 F19 INTB 93 U13 RSVD 89 P12
AD29 21 J3 CC/BE2 160 F13 IRDY 45 N5 RSVD 94 P13
AD30 20 J2 CC/BE3 173 B12 LED_SKT 90 R12 SERR 51 R3
AD31 19 J1 CCD1 123 L19 LINKON 199 A6 SPKROUT 78 U10
CAD0 124 L18 CCD2 185 A9 LPS 193 F8 STOP 49 R2
CAD1 127 L14 CCLK 156 D19 MFUNC0 76 W10 SUSPEND 86 W12
CAD2 125 L17 CCLKRUN 184 F10 MFUNC1 77 V10 TRDY 47 R1
CAD3 129 K18 CDEVSEL 155 E17 MFUNC2 80 P10 V
CC
14 G1
CAD4 128 K19 CFRAME 159 E14 MFUNC3 81 W11 V
CC
30 L2
CAD5 131 K15 CGNT 154 F15 MFUNC4 83 U11 V
CC
46 P3
CAD6 130 K17 CINT 180 A10 MFUNC5 84 P11 V
CC
66 W7
CAD7 133 J19 CIRDY 158 C15 MFUNC6 85 R11 V
CC
91 W13
CAD8 135 J17 CPAR 149 G15 PAR 52 T1 V
CC
115 M14
CAD9 137 J15 CPERR 152 F14 PCLK 37 M6 V
CC
134 J18
CAD10 139 H18 CREQ 171 E12 PERR 50 P5 V
CC
150 F17
2–9
Table 2–3. CardBus PC Card Signal Names Sorted Alphabetically to GHK/PDV Terminal Number
(Continued)
TERM. NO.
TERM. NO.
TERM. NO.
TERM. NO.
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
V
CC
170 A13 V
CCP
34 M1 ZV_SDATA 119 M15 ZV_VSYNC 96 V14
V
CC
186 B9 V
CCP
60 V6 ZV_UV(0) 106 R17 ZV_Y(0) 97 R13
V
CC
195 A7 VPPD0 87 V12 ZV_UV(1) 108 N14 ZV_Y(1) 98 U14
V
CCCB
138 H19 VPPD1 88 U12 ZV_UV(2) 107 P15 ZV_Y(2) 99 W15
V
CCCB
174 A12 ZV_HREF 95 W14 ZV_UV(3) 111 P17 ZV_Y(3) 101 V15
VCCD0 121 M18 ZV_LRCLK 118 N19 ZV_UV(4) 109 R18 ZV_Y(4) 102 R14
VCCD1 122 M19 ZV_MCLK 117 N18 ZV_UV(5) 113 N15 ZV_Y(5) 103 U15
V
CCI
79 R10 ZV_PCLK 120 M17 ZV_UV(6) 112 P18 ZV_Y(6) 104 W16
V
CCL
201 E7 ZV_SCLK 114 P19 ZV_UV(7) 116 N17 ZV_Y(7) 105 T19
2–10
Table 2–4. 16-Bit PC Card Signal Names Sorted Alphabetically to GHK/PDV Terminal Number
TERM. NO.
TERM. NO.
TERM. NO.
TERM. NO.
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
SIGNAL NAME
PDV GHK
AD0 73 U9 ADDR10 137 J15 DEVSEL 48 P6 PHY_DATA2 204 F6
AD1 72 V9 ADDR11 143 G19 FRAME 44 P2 PHY_DATA3 205 B5
AD2 71 W9 ADDR12 160 F13 GND 6 E1 PHY_DATA4 206 E6
AD3 70 W8 ADDR13 149 G15 GND 22 J5 PHY_DATA5 207 C5
AD4 69 V8 ADDR14 152 F14 GND 38 M5 PHY_DATA6 208 A4
AD5 68 U8 ADDR15 158 C15 GND 58 W5 PHY_DATA7 1 D1
AD6 67 R8 ADDR16 156 D19 GND 74 R9 PHY_LREQ 194 E8
AD7 65 V7 ADDR17 146 G14 GND 100 P14 PHY_RSVD 2 E3
AD8 63 P8 ADDR18 148 F18 GND 110 R19 PHY_RSVD 3 F5
AD9 62 W6 ADDR19 151 E19 GND 126 L15 PHY_RSVD 4 G6
AD10 61 R7 ADDR20 153 E18 GND 142 H15 PHY_RSVD 5 E2
AD11 59 U6 ADDR21 155 E17 GND 162 A15 PHY_RSVD 7 F3
AD12 57 V5 ADDR22 157 A16 GND 178 E11 PHY_RSVD 8 F2
AD13 56 P7 ADDR23 159 E14 GND 203 A5 PHY_RSVD 9 G5
AD14 55 R6 ADDR24 161 B15 GNT 18 H1 PHY_RSVD 10 F1
AD15 54 U5 ADDR25 164 B14 GRST 82 V11 PHY_RSVD 11 H6
AD16 42 N6 BVD1
(STSCHG
/RI)
183 E10 IDSEL 29 L1 PHY_RSVD 12 G3
AD17 41 N3 BVD2(SPKR) 182 C10 INPACK 171 E12 PHY_RSVD 13 G2
AD18 40 N2 C/BE0 64 U7 INTA 92 V13 PHY_RSVD 15 H5
AD19 39 N1 C/BE1 53 W4 INTB 93 U13 PHY_RSVD 16 H3
AD20 35 M2 C/BE2 43 P1 IRDY 45 N5 PRST 36 M3
AD21 33 L5 C/BE3 28 K6 IORD 141 H14 READY(IREQ) 180 A10
AD22 32 L6 CD1 123 L19 IOWR 144 G18 REG 173 B12
AD23 31 L3 CD2 185 A9 LED_SKT 90 R12 REQ 17 H2
AD24 27 K5 CE1 136 J14 LINKON 199 A6 RESET 167 F12
AD25 26 K3 CE2 139 H18 LPS 193 F8 RI_OUT/PME 75 P9
AD26 25 K2 DATA0 187 C9 MFUNC0 76 W10 RSVD 89 P12
AD27 24 K1 DATA1 189 E9 MFUNC1 77 V10 RSVD 94 P13
AD28 23 J6 DATA2 191 B8 MFUNC2 80 P10 SERR 51 R3
AD29 21 J3 DATA3 124 L18 MFUNC3 81 W11 SPKROUT 78 U10
AD30 20 J2 DATA4 127 L14 MFUNC4 83 U11 STOP 49 R2
AD31 19 J1 DATA5 129 K18 MFUNC5 84 P11 SUSPEND 86 W12
ADDR0 177 C11 DATA6 131 K15 MFUNC6 85 R11 TRDY 47 R1
ADDR1 176 B11 DATA7 133 J19 OE 140 H17 V
CC
14 G1
ADDR2 175 A11 DATA8 188 F9 PAR 52 T1 V
CC
30 L2
ADDR3 172 C12 DATA9 190 A8 PCLK 37 M6 V
CC
46 P3
ADDR4 169 B13 DATA10 192 C8 PERR 50 P5 V
CC
66 W7
ADDR5 168 C13 DATA11 125 L17 PHY_CLK 196 B7 V
CC
91 W13
ADDR6 166 A14 DATA12 128 K19 PHY_CTL(0) 197 C7 V
CC
115 M14
ADDR7 163 C14 DATA13 130 K17 PHY_CTL(1) 198 F7 V
CC
134 J18
ADDR8 147 F19 DATA14 132 K14 PHY_DATA0 200 B6 V
CC
150 F17
ADDR9 145 G17 DATA15 135 J17 PHY_DATA1 202 C6 V
CC
170 A13
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