TEXAS INSTRUMENTS PCI2050B Technical data
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查询PCI2050B供应商
Data M anua
October 2005 Connectivity Solutions
SCPS076F
IMPORTANT NOTICE
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Contents
Section Title Page
1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Related Documents 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Trademarks 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction to the PCI2050B Bridge 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Write Combining 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 66-MHz Operation 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 PCI Commands 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Configuration Cycles 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Special Cycle Generation 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Secondary Clocks 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Bus Arbitration 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Primary Bus Arbitration 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Internal Secondary Bus Arbitration 3−6. . . . . . . . . . . . . . . . . . . .
3.6.3 External Secondary Bus Arbitration 3−7. . . . . . . . . . . . . . . . . . .
3.7 Decode Options 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 System Error Handling 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Posted Write Parity Error 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Posted Write Time-Out 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 Target Abort on Posted Writes 3−7. . . . . . . . . . . . . . . . . . . . . . . .
3.8.4 Master Abort on Posted Writes 3−8. . . . . . . . . . . . . . . . . . . . . . .
3.8.5 Master Delayed Write Time-Out 3−8. . . . . . . . . . . . . . . . . . . . . .
3.8.6 Master Delayed Read Time-Out 3−8. . . . . . . . . . . . . . . . . . . . . .
3.8.7 Secondary SERR
3.9 Parity Handling and Parity Error Reporting 3−8. . . . . . . . . . . . . . . . . . . . . .
3.9.1 Address Parity Error 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Data Parity Error 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Master and Target Abort Handling 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Discard Timer 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Delayed Transactions 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Mode Selection 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 CompactPCI Hot-Swap Support 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 JTAG Support 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1 Test Port Instructions 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
Section Title Page
3.16 GPIO Interface 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16.1 Secondary Clock Mask 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16.2 Transaction Forwarding Control 3−15. . . . . . . . . . . . . . . . . . . . . . .
3.17 PCI Power Management 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 Behavior in Low-Power States 3−16. . . . . . . . . . . . . . . . . . . . . . . .
4 Bridge Configuration Header 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Vendor ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Device ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Command Register 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Status Register 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Revision ID Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Class Code Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Cache Line Size Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Primary Latency Timer Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Header Type Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 BIST Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 Base Address Register 0 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Base Address Register 1 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Primary Bus Number Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Bus Number Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Subordinate Bus Number Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Secondary Bus Latency Timer Register 4−8. . . . . . . . . . . . . . . . . . . . . . . .
4.17 I/O Base Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 I/O Limit Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Secondary Status Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Base Register 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 Memory Limit Register 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Prefetchable Memory Base Register 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Prefetchable Memory Limit Register 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Prefetchable Base Upper 32 Bits Register 4−12. . . . . . . . . . . . . . . . . . . . . .
4.25 Prefetchable Limit Upper 32 Bits Register 4−13. . . . . . . . . . . . . . . . . . . . . .
4.26 I/O Base Upper 16 Bits Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 I/O Limit Upper 16 Bits Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 Capability Pointer Register 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.29 Expansion ROM Base Address Register 4−14. . . . . . . . . . . . . . . . . . . . . . . .
4.30 Interrupt Line Register 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Interrupt Pin Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Bridge Control Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Extension Registers 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Chip Control Register 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Extended Diagnostic Register 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Arbiter Control Register 5−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Section Title Page
5.4 P_SERR Event Disable Register 5−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 GPIO Output Data Register 5−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 GPIO Output Enable Register 5−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 GPIO Input Data Register 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Secondary Clock Control Register 5−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 P_SERR Status Register 5−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Power-Management Capability ID Register 5−8. . . . . . . . . . . . . . . . . . . . .
5.11 Power-Management Next-Item Pointer Register 5−9. . . . . . . . . . . . . . . . .
5.12 Power-Management Capabilities Register 5−9. . . . . . . . . . . . . . . . . . . . . .
5.13 Power-Management Control/Status Register 5−10. . . . . . . . . . . . . . . . . . . .
5.14 PMCSR Bridge Support Register 5−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15 Data Register 5−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 HS Capability ID Register 5−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.17 HS Next-Item Pointer Register 5−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.18 Hot-Swap Control Status Register 5−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.19 Diagnostics Register 5−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Electrical Characteristics 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Absolute Maximum Ratings Over Operating Temperature Ranges 6−1.
6.2 Recommended Operating Conditions 6−2. . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Electrical Characteristics Over Recommended Operating
Conditions 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 66-MHz PCI Clock Signal AC Parameters 6−4. . . . . . . . . . . . . . . . . . . . . .
6.5 66-MHz PCI Signal Timing 6−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Parameter Measurement Information 6−6. . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 PCI Bus Parameter Measurement Information 6−7. . . . . . . . . . . . . . . . . . .
7 Mechanical Data 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
List of Illustrations
Figure Title Page
2−1 PCI2050B GHK/ZHK Terminal Diagram 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 PCI2050B PDV Terminal Diagram 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 PCI2050B PPM Terminal Diagram 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 System Block Diagram 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 PCI AD31−AD0 During Address Phase of a Type 0 Configuration
Cycle 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 PCI AD31−AD0 During Address Phase of a Type 1 Configuration
Cycle 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Bus Hierarchy and Numbering 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Secondary Clock Block Diagram 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Clock Mask Read Timing After Reset 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 PCI Clock Signal AC Parameter Measurements 6−4. . . . . . . . . . . . . . . . . . . .
6−3 Load Circuit and Voltage Waveforms 6−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 RSTIN
Timing Waveforms 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Tables
Table Title Page
2−1 208-Terminal PDV Signal Names Sorted by Terminal Number 2−4. . . . . . . .
2−2 208-Terminal PPM Signal Names Sorted by Terminal Number 2−5. . . . . . . .
2−3 257-Terminal GHK/ZHK Signal Names Sorted by Terminal Number 2−6. . .
2−4 208-Terminal PDV Signal Names Sorted Alphabetically 2−8. . . . . . . . . . . . . .
2−5 208-Terminal PPM Signal Names Sorted Alphabetically 2−9. . . . . . . . . . . . . .
2−6 257-Terminal GHK/ZHK Signal Names Sorted Alphabetically 2−10. . . . . . . . .
2−7 Primary PCI System Terminals 2−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Primary PCI Address and Data Terminals 2−12. . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Primary PCI Interface Control Terminals 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Secondary PCI System Terminals 2−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Secondary PCI Address and Data Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . .
2−12 Secondary PCI Interface Control Terminals 2−16. . . . . . . . . . . . . . . . . . . . . . . . .
2−13 JTAG Interface Terminals 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 Miscellaneous Terminals 2−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−15 Power Supply Terminals 2−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PCI Command Definitions 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 PCI S_AD31−S_AD16 During the Address Phase of a Type 0 Configuration
Cycle 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Configuration via MS0 and MS1 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 JTAG Instructions and Op Codes 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Boundary Scan Terminal Order 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Clock Mask Data Format 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Bridge Configuration Header 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Command Register Description 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Status Register Description 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Secondary Status Register Description 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Bridge Control Register Description 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 Chip Control Register Description 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Extended Diagnostic Register Description 5−2. . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 Arbiter Control Register Description 5−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 P_SERR Event Disable Register Description 5−4. . . . . . . . . . . . . . . . . . . . . . .
5−5 GPIO Output Data Register Description 5−5. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 GPIO Output Enable Register Description 5−5. . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 GPIO Input Data Register Description 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 Secondary Clock Control Register Description 5−7. . . . . . . . . . . . . . . . . . . . . .
5−9 P_SERR Status Register Description 5−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 Power-Management Capabilities Register Description 5−9. . . . . . . . . . . . . . .
5−11 Power-Management Control/Status Register 5−10. . . . . . . . . . . . . . . . . . . . . . .
vii
Table Title Page
5−12 PMCSR Bridge Support Register Description 5−11. . . . . . . . . . . . . . . . . . . . . . .
5−13 Hot-Swap Control Status Register Description 5−13. . . . . . . . . . . . . . . . . . . . . .
5−14 Diagnostics Register Description 5−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
1 Introduction
The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two
peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions
occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions
to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the
two bus traffic paths through the bridge act independently.
The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical
loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The
PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with
an external bus arbiter.
The CompactPCI hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction
compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge
provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge
has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process
achieves low system power consumption while operating at PCI clock rates up to 66-MHz.
1.1 Features
The PCI2050B bridge supports the following features:
• Two 32-bit, 66-MHz PCI buses
• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus
arbiter
• Ten secondary PCI clock outputs
• Independent read and write buffers for each direction
• Burst data transfers with pipeline architecture to maximize data throughput in both directions
• Supports write combing for enhanced data throughput
• Up to three delayed transactions in both directions
• Supports the frame-to-frame delay of only four PCI clocks from one bus to another
• Bus locking propagation
• Predictable latency per PCI Local Bus Specification
• Architecture configurable for PCI Bus Power Management Interface Specification
• CompactPCI hot-swap functionality
• Secondary bus is driven low during reset
• VGA/palette memory and I/O decoding options
• Advanced submicron, low-power CMOS technology
• 208-terminal PDV, 208-terminal PPM, or 257-terminal MicroStar BGA package
1−1
1.2 Related Documents
• Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0)
• IEEE Standard Test Access Port and Boundary-Scan Architecture
• PCI Local Bus Specification (Revision 2.2)
• PCI-to-PCI Bridge Specification (Revision 1.1)
• PCI Bus Power Management Interface Specification (Revision 1.1)
• PICMG CompactPCI Hot-Swap Specification (Revision 1.0)
1.3 Trademarks
CompactPCI is a trademark of PICMG − PCI Industrial Computer Manufacturers Group, Inc.
Intel is a trademark of Intel Corporation.
MicroStar BGA and TI are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
1.4 Ordering Information
ORDERING NUMBER VOLTAGE TEMPERATURE PACKAGE
PCI2050BPDV 3.3-V, 5-V Tolerant I/Os 0°C to 70°C 208 QFP
PCI2050BPPM 3.3-V, 5-V Tolerant I/Os 0°C to 70°C 208 QFP
PCI2050BGHK 3.3-V, 5-V Tolerant I/Os 0°C to 70°C 257 BGA
PCI2050BZHK 3.3-V, 5-V Tolerant I/Os 0°C to 70°C 257 RoHS BGA
PCI2050BIPDV 3.3-V, 5-V Tolerant I/Os −40°C to 85°C 208 QFP
PCI2050BIGHK 3.3-V, 5-V Tolerant I/Os −40°C to 85°C 257 BGA
PCI2050BIZHK 3.3-V, 5-V Tolerant I/Os −40°C to 85°C 257 RoHS BGA
1−2
2 Terminal Descriptions
The PCI2050B device is available in four packages, a 257-terminal GHK MicroStar BGA package, a 257-terminal
RoHS-compliant ZHK MicroStar BGA package, a 208-terminal PDV package, or a 208-terminal PPM package. The
GHK and ZHK packages are mechanically and electrically identical, but the ZHK is a RoHS-compliant design.
Throughout the remainder of this manual, only the GHK package designator is used for either the GHK or the ZHK
package. Figure 2−1 is the GHK-package terminal diagram. Figure 2−2 is the PDV-package terminal diagram.
Figure 2−3 is the PPM-package terminal diagram. Table 2−1 lists terminals on the PDV packaged device in
increasing numerical order with the signal name for each. Table 2−2 lists terminals on the PPM packaged device in
increasing alphanumerical order with the signal name for each. Table 2−3 lists terminals on the GHK packaged device
in increasing alphanumerical order with the signal name for each. Table 2−4, Table 2−5, and Table 2−6 list the signal
names in alphabetical order, with corresponding terminal numbers for each package type.
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2436
7
5
11 15
128910
1413161718
19
Figure 2−1. PCI2050B GHK/ZHK Terminal Diagram
2−1
PDV LOW-PROFILE QUAD FLAT PACKAGE
TOP VIEW
V
CC
GND
S_AD11
GND
S_AD12
S_AD13
V
CC
S_AD14
S_AD15
GND
S_C/BE1
S_PAR
S_SERR
V
CC
S_PERR
S_LOCK
S_STOP
GND
S_DEVSEL
S_TRDY
S_IRDY
V
CC
S_FRAME
S_C/BE2
GND
S_AD16
S_AD17
V
CC
S_AD18
S_AD19
GND
S_AD20
S_AD21
V
CC
S_AD22
S_AD23
GND
S_C/BE3
S_AD24
V
CC
S_AD25
S_AD26
GND
S_AD27
S_AD28
V
CC
S_AD29
S_AD30
GND
S_AD31
S_REQ0
V
CC
CONFIG66
MSK_IN
HSENUM
126
125
127
CCP
P_V
124
GND
123
P_AD1
P_AD0
122
121
CC
V
120
P_AD2
P_AD3
118
119
GND
117
P_AD4
P_AD5
116
115
CC
V
114
P_AD6
P_AD7
112
113
CCP
GND
148
S_AD7
S_AD6
146
147
V
145
CC
S_AD4
S_AD5
144
143
CC
V
S_M66ENA
S_AD10
S_AD9
S_C/BE0
154
153
152
151
S_AD8
150
149
MS0
155
214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
156
GND
142
S_AD2
S_AD3
140
141
CC
V
139
S_AD0
S_AD1
138
137
GND
136
S_V
135
TMS
TCK
TRST
132
134
133
PCI2050B
V
131
CC
TDO
130
TDI
129
HSLED
128
GND
P_C/BE0
111
110
CC
V
P_AD8
108
109
P_AD9
MS1
107
51 106
CC
V
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
GND
V
CC
P_M66ENA
P_AD10
GND
P_AD11
P_AD12
V
CC
P_AD13
P_AD14
GND
P_AD15
P_C/BE1
V
CC
P_PAR
P_SERR
P_PERR
P_LOCK
GND
P_STOP
P_DEVSEL
P_TRDY
P_IRDY
V
CC
P_FRAME
P_C/BE2
GND
P_AD16
P_AD17
V
CC
P_AD18
P_AD19
GND
P_AD20
P_AD21
V
CC
P_AD22
P_AD23
GND
P_IDSEL
P_C/BE3
P_AD24
V
CC
P_AD25
P_AD26
GND
P_AD27
P_AD28
V
CC
P_AD29
GND
V
CC
2−2
CC
V
S_REQ1
S_REQ2
S_REQ3
S_REQ4
S_REQ6
S_REQ5
CC
V
GPIO2
S_RST
S_CFN
HSSWITCH/GPIO3
GPIO0
GPIO1
GND
S_CLKOUT0
S_CLKOUT1
S_CLKOUT2
S_GNT0
S_REQ7
S_REQ8
GND
S_GNT1
S_GNT2
S_GNT5
S_GNT3
S_GNT4
S_GNT8
S_GNT6
S_GNT7
GND
S_CLK
Figure 2−2. PCI2050B PDV Terminal Diagram
CC
V
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
GND
S_CLKOUT6
S_CLKOUT7
CC
V
S_CLKOUT8
S_CLKOUT9
P_RST
BPCCE
P_CLK
P_GNT
GND
P_REQ
V
P_AD30
P_AD31
CC
GND
PPM QUAD FLAT PACKAGE
TOP VIEW
V
CC
GND
S_AD11
GND
S_AD12
S_AD13
V
CC
S_AD14
S_AD15
GND
S_C/BE1
S_PAR
S_SERR
V
CC
S_PERR
S_LOCK
S_STOP
GND
S_DEVSEL
S_TRDY
S_IRDY
V
CC
S_FRAME
S_C/BE2
GND
S_AD16
S_AD17
V
CC
S_AD18
S_AD19
GND
S_AD20
S_AD21
V
CC
S_AD22
S_AD23
GND
S_C/BE3
S_AD24
V
CC
S_AD25
S_AD26
GND
S_AD27
S_AD28
V
CC
S_AD29
S_AD30
GND
S_AD31
S_REQ0
V
CC
CONFIG66
MSK_IN
HSENUM
126
125
127
CCP
P_V
124
GND
123
P_AD1
P_AD0
122
121
V
120
CC
P_AD2
P_AD3
118
119
GND
117
P_AD4
P_AD5
116
115
CC
V
114
P_AD6
P_AD7
112
113
CCP
GND
148
S_AD7
S_AD6
146
147
V
145
CC
S_AD4
S_AD5
144
143
CC
V
S_M66ENA
S_AD10
S_AD9
S_C/BE0
154
153
152
151
S_AD8
150
149
MS0
155
214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
156
GND
142
S_AD2
S_AD3
140
141
CC
V
139
S_AD0
S_AD1
138
137
GND
136
S_V
135
TMS
TCK
TRST
132
134
133
PCI2050B
V
131
CC
TDO
130
TDI
129
HSLED
128
GND
P_C/BE0
111
110
CC
V
P_AD8
108
109
P_AD9
MS1
107
51 106
CC
V
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
GND
V
CC
P_M66ENA
P_AD10
GND
P_AD11
P_AD12
V
CC
P_AD13
P_AD14
GND
P_AD15
P_C/BE1
V
CC
P_PAR
P_SERR
P_PERR
P_LOCK
GND
P_STOP
P_DEVSEL
P_TRDY
P_IRDY
V
CC
P_FRAME
P_C/BE2
GND
P_AD16
P_AD17
V
CC
P_AD18
P_AD19
GND
P_AD20
P_AD21
V
CC
P_AD22
P_AD23
GND
P_IDSEL
P_C/BE3
P_AD24
V
CC
P_AD25
P_AD26
GND
P_AD27
P_AD28
V
CC
P_AD29
GND
V
CC
CC
V
S_REQ1
S_REQ2
S_REQ3
S_REQ4
S_REQ6
S_REQ5
CC
V
GPIO2
S_RST
S_CFN
HSSWITCH/GPIO3
GPIO0
GPIO1
GND
S_CLKOUT0
S_CLKOUT1
S_CLKOUT2
S_GNT0
S_REQ7
S_REQ8
GND
S_GNT1
S_GNT2
S_GNT5
S_GNT3
S_GNT4
S_GNT8
S_GNT6
S_GNT7
GND
S_CLK
Figure 2−3. PCI2050B PPM Terminal Diagram
CC
V
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
GND
S_CLKOUT6
S_CLKOUT7
CC
V
S_CLKOUT8
S_CLKOUT9
P_RST
BPCCE
P_CLK
P_GNT
GND
P_REQ
V
P_AD30
P_AD31
CC
GND
2−3
Table 2−1. 208-Terminal PDV Signal Names Sorted by Terminal Number
PDV
NO.
10 S_GNT0 52 GND 94 GND 136 GND 178 V
11 S_GNT1 53 V
12 GND 54 GND 96 P_AD13 138 S_AD1 180 S_C/BE2
13 S_GNT2 55 P_AD29 97 V
14 S_GNT3 56 V
15 S_GNT4 57 P_AD28 99 P_AD11 141 S_AD3 183 S_AD17
16 S_GNT5 58 P_AD27 100 GND 142 GND 184 V
17 S_GNT6 59 GND 101 P_AD10 143 S_AD4 185 S_AD18
18 S_GNT7 60 P_AD26 102 P_M66ENA 144 S_AD5 186 S_AD19
19 S_GNT8 61 P_AD25 103 V
20 GND 62 V
21 S_CLK 63 P_AD24 105 V
22 S_RST 64 P_C/BE3 106 MS1 148 GND 190 V
23 S_CFN 65 P_IDSEL 107 P_AD9 149 S_C/BE0 191 S_AD22
24 HS_SWITCH/GPIO3 66 GND 108 V
25 GPIO2 67 P_AD23 109 P_AD8 151 V
26 V
27 GPIO1 69 V
28 GPIO0 70 P_AD21 112 P_AD7 154 S_AD10 196 V
29 S_CLKOUT0 71 P_AD20 113 P_AD6 155 MS0 197 S_AD25
30 S_CLKOUT1 72 GND 114 V
31 GND 73 P_AD19 115 P_AD5 157 V
32 S_CLKOUT2 74 P_AD18 116 P_AD4 158 GND 200 S_AD27
33 S_CLKOUT3 75 V
34 V
35 S_CLKOUT4 77 P_AD16 119 P_AD2 161 S_AD12 203 S_AD29
36 S_CLKOUT5 78 GND 120 V
37 GND 79 P_C/BE2 121 P_AD1 163 V
38 S_CLKOUT6 80 P_FRAME 122 P_AD0 164 S_AD14 206 S_AD31
39 S_CLKOUT7 81 V
40 V
41 S_CLKOUT8 83 P_TRDY 125 CONFIG66 167 S_C/BE1
42 S_CLKOUT9 84 P_DEVSEL 126 MSK_IN 168 S_PAR
SIGNAL NAME
1 V
CC
2 S_REQ1 44 BPCCE 86 GND 128 HS_LED 170 V
3 S_REQ2 45 P_CLK 87 P_LOCK 129 TDI 171 S_PERR
4 S_REQ3 46 P_GNT 88 P_PERR 130 TDO 172 S_LOCK
5 S_REQ4 47 P_REQ 89 P_SERR 131 V
6 S_REQ5 48 GND 90 P_PAR 132 TMS 174 GND
7 S_REQ6 49 P_AD31 91 V
8 S_REQ7 50 P_AD30 92 P_C/BE1 134 TRST 176 S_TRDY
9 S_REQ8 51 V
CC
CC
CC
PDV
SIGNAL NAME
NO.
43 P_RST 85 P_STOP 127 HS_ENUM 169 S_SERR
CC
CC
CC
CC
68 P_AD22 110 P_C/BE0 152 S_AD9 194 S_C/BE3
CC
CC
76 P_AD17 118 P_AD3 160 GND 202 V
CC
82 P_IRDY 124 P_V
PDV
SIGNAL NAME
NO.
CC
93 P_AD15 135 S_V
95 P_AD14 137 S_AD0 179 S_FRAME
CC
98 P_AD12 140 S_AD2 182 S_AD16
CC
104 GND 146 S_AD6 188 S_AD20
CC
CC
111 GND 153 S_M66ENA 195 S_AD24
CC
117 GND 159 S_AD11 201 S_AD28
CC
123 GND 165 S_AD15 207 S_REQ0
CCP
PDV
SIGNAL NAME
NO.
CC
133 TCK 175 S_DEVSEL
CCP
139 V
CC
145 V
CC
147 S_AD7 189 S_AD21
150 S_AD8 192 S_AD23
CC
156 GND 198 S_AD26
CC
162 S_AD13 204 S_AD30
CC
166 GND 208 V
PDV
SIGNAL NAME
NO.
CC
173 S_STOP
177 S_IRDY
CC
181 GND
CC
187 GND
CC
193 GND
CC
199 GND
CC
205 GND
CC
2−4
Table 2−2. 208-Terminal PPM Signal Names Sorted by Terminal Number
PPM
NO.
10 S_GNT0 52 GND 94 GND 136 GND 178 V
11 S_GNT1 53 V
12 GND 54 GND 96 P_AD13 138 S_AD1 180 S_C/BE2
13 S_GNT2 55 P_AD29 97 V
14 S_GNT3 56 V
15 S_GNT4 57 P_AD28 99 P_AD11 141 S_AD3 183 S_AD17
16 S_GNT5 58 P_AD27 100 GND 142 GND 184 V
17 S_GNT6 59 GND 101 P_AD10 143 S_AD4 185 S_AD18
18 S_GNT7 60 P_AD26 102 P_M66ENA 144 S_AD5 186 S_AD19
19 S_GNT8 61 P_AD25 103 V
20 GND 62 V
21 S_CLK 63 P_AD24 105 V
22 S_RST 64 P_C/BE3 106 MS1 148 GND 190 V
23 S_CFN 65 P_IDSEL 107 P_AD9 149 S_C/BE0 191 S_AD22
24 HS_SWITCH/GPIO3 66 GND 108 V
25 GPIO2 67 P_AD23 109 P_AD8 151 V
26 V
27 GPIO1 69 V
28 GPIO0 70 P_AD21 112 P_AD7 154 S_AD10 196 V
29 S_CLKOUT0 71 P_AD20 113 P_AD6 155 MS0 197 S_AD25
30 S_CLKOUT1 72 GND 114 V
31 GND 73 P_AD19 115 P_AD5 157 V
32 S_CLKOUT2 74 P_AD18 116 P_AD4 158 GND 200 S_AD27
33 S_CLKOUT3 75 V
34 V
35 S_CLKOUT4 77 P_AD16 119 P_AD2 161 S_AD12 203 S_AD29
36 S_CLKOUT5 78 GND 120 V
37 GND 79 P_C/BE2 121 P_AD1 163 V
38 S_CLKOUT6 80 P_FRAME 122 P_AD0 164 S_AD14 206 S_AD31
39 S_CLKOUT7 81 V
40 V
41 S_CLKOUT8 83 P_TRDY 125 CONFIG66 167 S_C/BE1
42 S_CLKOUT9 84 P_DEVSEL 126 MSK_IN 168 S_PAR
SIGNAL NAME
1 V
CC
2 S_REQ1 44 BPCCE 86 GND 128 HS_LED 170 V
3 S_REQ2 45 P_CLK 87 P_LOCK 129 TDI 171 S_PERR
4 S_REQ3 46 P_GNT 88 P_PERR 130 TDO 172 S_LOCK
5 S_REQ4 47 P_REQ 89 P_SERR 131 V
6 S_REQ5 48 GND 90 P_PAR 132 TMS 174 GND
7 S_REQ6 49 P_AD31 91 V
8 S_REQ7 50 P_AD30 92 P_C/BE1 134 TRST 176 S_TRDY
9 S_REQ8 51 V
CC
CC
CC
PPM
SIGNAL NAME
NO.
43 P_RST 85 P_STOP 127 HS_ENUM 169 S_SERR
CC
CC
CC
CC
68 P_AD22 110 P_C/BE0 152 S_AD9 194 S_C/BE3
CC
CC
76 P_AD17 118 P_AD3 160 GND 202 V
CC
82 P_IRDY 124 P_V
PPM
SIGNAL NAME
NO.
CC
93 P_AD15 135 S_V
95 P_AD14 137 S_AD0 179 S_FRAME
CC
98 P_AD12 140 S_AD2 182 S_AD16
CC
104 GND 146 S_AD6 188 S_AD20
CC
CC
111 GND 153 S_M66ENA 195 S_AD24
CC
117 GND 159 S_AD11 201 S_AD28
CC
123 GND 165 S_AD15 207 S_REQ0
CCP
PPM
SIGNAL NAME
NO.
CC
133 TCK 175 S_DEVSEL
CCP
139 V
CC
145 V
CC
147 S_AD7 189 S_AD21
150 S_AD8 192 S_AD23
CC
156 GND 198 S_AD26
CC
162 S_AD13 204 S_AD30
CC
166 GND 208 V
PPM
SIGNAL NAME
NO.
CC
173 S_STOP
177 S_IRDY
CC
181 GND
CC
187 GND
CC
193 GND
CC
199 GND
CC
205 GND
CC
2−5
Table 2−3. 257-Terminal GHK/ZHK Signal Names Sorted by Terminal Number
GHK
SIGNAL NAME
NO.
A2 NC C8 V
A3 V
CC
A4 S_AD31 C10 NC F13 GND K17 TDO P12 P_LOCK
A5 S_AD28 C11 S_IRDY F14 S_AD9 K18 TDI P13 P_C/BE1
A6 S_AD25 C12 S_LOCK F15 S_AD10 K19 NC P14 P_AD12
A7 GND C13 S_PAR F17 S_AD8 L1 S_CLKOUT0 P15 V
A8 S_AD20 C14 V
A9 V
CC
A10 S_C/BE2 C16 NC G1 S_GNT3 L5 S_CLKOUT2 P19 P_AD5
A11 S_DEVSEL C17 NC G2 S_GNT2 L6 GND R1 P_GNT
A12 GND C18 NC G3 GND L14 HS_LED R2 NC
A13 V
CC
A14 GND D1 NC G6 S_REQ3 L17 MSK_IN R6 P_AD29
A15 S_AD13 D2 V
A16 V
CC
A17 NC D17 NC G17 V
A18 NC D18 NC G18 S_AD5 M2 V
B1 NC D19 GND G19 S_AD4 M3 S_CLKOUT4 R11 P_DEVSEL
B2 NC E1 S_REQ5 H1 S_GNT7 M5 GND R12 P_PERR
B3 NC E2 S_REQ4 H2 S_GNT6 M6 S_CLKOUT5 R13 P_AD14
B4 S_REQ0 E3 S_REQ1 H3 S_GNT5 M14 P_AD4 R14 GND
B5 S_AD29 E5†NC H5 S_GNT4 M15 V
B6 S_AD26 E6 S_AD30 H6 S_GNT1 M17 P_AD1 R18 P_C/BE0
B7 S_C/BE3 E7 GND H14 S_AD3 M18 P_AD0 R19 GND
B8 S_AD21 E8 S_AD23 H15 GND M19 GND T1 P_AD30
B9 NC E9 GND H17 S_AD2 N1 S_CLKOUT6 T2 V
B10 GND E10 S_AD16 H18 V
B11 S_TRDY E11 V
B12 S_STOP E12 S_PERR J1 S_GNT8 N5 BPCCE T18 V
B13 S_SERR E13 S_AD15 J2 GND N6 S_CLKOUT8 T19 MS1
B14 S_AD14 E14 S_AD11 J3 S_CLK N14 P_AD8 U1 GND
B15 S_AD12 E17 MS0 J5 S_RST N15 V
B16 NC E18 S_M66ENA J6 S_CFN N17 GND U3 NC
B17 NC E19 V
B18 NC F1 S_GNT0 J15 S_AD0 N19 P_AD2 U5 GND
B19 NC F2 S_REQ7 J17 S_V
C1 NC F3 S_REQ6 J18 TRST P2 P_RST U7 P_AD24
C2 NC F5 S_REQ2 J19 TCK P3 P_CLK U8 P_AD23
C3 NC F6 V
C4 NC F7 V
C5 GND F8 S_AD22 K3 V
C6 S_AD27 F9 S_AD19 K5 GPIO1 P8 V
C7 S_AD24 F10 S_AD17 K6 GPIO0 P9 P_AD18 U13 V
†
Terminal E5 is used as a key to indicate the location of the A1 corner. It is a no-connect terminal.
GHK
SIGNAL NAME
NO.
CC
C9 S_AD18 F12 S_C/BE1 K15 V
CC
C15 GND F19 S_AD7 L3 NC P18 P_AD6
C19 NC G5 S_REQ8 L15 HS_ENUM R3 P_AD31
CC
D3 NC G15 S_C/BE0 L19 P_V
CC
CC
CC
CC
GHK
NO.
F11 S_FRAME K14 TMS P10 P_C/BE2
F18 GND L2 S_CLKOUT1 P17 P_AD7
G14 S_AD6 L18 CONFIG66 R7 P_AD26
H19 S_AD1 N3 V
J14 GND N18 P_AD3 U4 NC
K1 HS_SWITCH/GPIO3 P5 GND U9 GND
K2 GPIO2 P6 P_REQ U10 P_AD16
SIGNAL NAME
CC
CC
CCP
CC
GHK
SIGNAL NAME
NO.
CC
CCP
M1 S_CLKOUT3 R9 P_AD19
CC
CC
N2 S_CLKOUT7 T3 NC
CC
CC
P1 S_CLKOUT9 U6 P_AD27
P7 V
CC
CC
GHK
SIGNAL NAME
NO.
P11 P_TRDY
CC
R8 GND
R10 GND
R17 P_AD9
CC
T17 NC
CC
U2 NC
U11 P_IRDY
U12 GND
CC
2−6
Table 2−3. 257-Terminal GHK/ZHK Signal Names Sorted by Terminal Number (Continued)
GHK
SIGNAL NAME
NO.
U14 P_AD13 V4 NC V13 P_PAR W4 V
U15 P_AD10 V5 NC V14 GND W5 P_AD28 W14 P_AD15
U16 NC V6 GND V15 P_AD11 W6 P_AD25 W15 V
U17 NC V7 P_C/BE3 V16 V
U18 NC V8 P_AD22 V17 NC W8 V
U19 NC V9 P_AD20 V18 NC W9 P_AD21 W18 NC
V1 NC V10 P_AD17 V19 NC W10 V
V2 NC V11 V
V3 NC V12 NC W3 NC W12 P_STOP
GHK
NO.
SIGNAL NAME
CC
GHK
SIGNAL NAME
NO.
CC
W2 NC W11 P_FRAME
GHK
SIGNAL NAME
NO.
CC
W7 P_IDSEL W16 P_M66ENA
CC
CC
GHK
SIGNAL NAME
NO.
W13 P_SERR
CC
W17 NC
2−7
Table 2−4. 208-Terminal PDV Signal Names Sorted Alphabetically
SIGNAL NAME
BPCCE 44 P_AD0 122 P_LOCK 87 S_C/BE0 149 S_SERR 169
CONFIG66 125 P_AD1 121 P_M66ENA 102 S_C/BE1 167 S_STOP 173
GND 12 P_AD2 119 P_PAR 90 S_C/BE2 180 S_TRDY 176
GND 20 P_AD3 118 P_PERR 88 S_C/BE3 194 S_V
GND 31 P_AD4 116 P_REQ 47 S_CFN 23 TCK 133
GND 37 P_AD5 115 P_RST 43 S_CLK 21 TDI 129
GND 48 P_AD6 113 P_SERR 89 S_CLKOUT0 29 TDO 130
GND 52 P_AD7 112 P_STOP 85 S_CLKOUT1 30 TMS 132
GND 54 P_AD8 109 P_TRDY 83 S_CLKOUT2 32 TRST 134
GND 59 P_AD9 107 P_V
GND 66 P_AD10 101 S_AD0 137 S_CLKOUT4 35 V
GND 72 P_AD11 99 S_AD1 138 S_CLKOUT5 36 V
GND 78 P_AD12 98 S_AD2 140 S_CLKOUT6 38 V
GND 86 P_AD13 96 S_AD3 141 S_CLKOUT7 39 V
GND 94 P_AD14 95 S_AD4 143 S_CLKOUT8 41 V
GND 100 P_AD15 93 S_AD5 144 S_CLKOUT9 42 V
GND 104 P_AD16 77 S_AD6 146 S_DEVSEL 175 V
GND 111 P_AD17 76 S_AD7 147 S_FRAME 179 V
GND 117 P_AD18 74 S_AD8 150 S_GNT0 10 V
GND 123 P_AD19 73 S_AD9 152 S_GNT1 11 V
GND 136 P_AD20 71 S_AD10 154 S_GNT2 13 V
GND 142 P_AD21 70 S_AD11 159 S_GNT3 14 V
GND 148 P_AD22 68 S_AD12 161 S_GNT4 15 V
GND 156 P_AD23 67 S_AD13 162 S_GNT5 16 V
GND 158 P_AD24 63 S_AD14 164 S_GNT6 17 V
GND 160 P_AD25 61 S_AD15 165 S_GNT7 18 V
GND 166 P_AD26 60 S_AD16 182 S_GNT8 19 V
GND 174 P_AD27 58 S_AD17 183 S_IRDY 177 V
GND 181 P_AD28 57 S_AD18 185 S_LOCK 172 V
GND 187 P_AD29 55 S_AD19 186 S_M66ENA 153 V
GND 193 P_AD30 50 S_AD20 188 S_PAR 168 V
GND 199 P_AD31 49 S_AD21 189 S_PERR 171 V
GND 205 P_C/BE0 110 S_AD22 191 S_REQ0 207 V
GPIO0 28 P_C/BE1 92 S_AD23 192 S_REQ1 2 V
GPIO1 27 P_C/BE2 79 S_AD24 195 S_REQ2 3 V
GPIO2 25 P_C/BE3 64 S_AD25 197 S_REQ3 4 V
HS_ENUM 127 P_CLK 45 S_AD26 198 S_REQ4 5 V
HS_LED 128 P_DEVSEL 84 S_AD27 200 S_REQ5 6 V
HS_SWITCH/GPIO3 24 P_FRAME 80 S_AD28 201 S_REQ6 7 V
MS0 155 P_GNT 46 S_AD29 203 S_REQ7 8 V
MS1 106 P_IDSEL 65 S_AD30 204 S_REQ8 9
MSK_IN 126 P_IRDY 82 S_AD31 206 S_RST 22
PDV
NO.
SIGNAL NAME
PDV
NO.
SIGNAL NAME
CCP
PDV
SIGNAL NAME
NO.
124 S_CLKOUT3 33 V
PDV
NO.
SIGNAL NAME
CCP
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
PDV
NO.
135
1
26
34
40
51
53
56
62
69
75
81
91
97
103
105
108
114
120
131
139
145
151
202
208
157
163
170
178
184
190
196
2−8
Table 2−5. 208-Terminal PPM Signal Names Sorted Alphabetically
SIGNAL NAME
BPCCE 44 P_AD0 122 P_LOCK 87 S_C/BE0 149 S_SERR 169
CONFIG66 125 P_AD1 121 P_M66ENA 102 S_C/BE1 167 S_STOP 173
GND 12 P_AD2 119 P_PAR 90 S_C/BE2 180 S_TRDY 176
GND 20 P_AD3 118 P_PERR 88 S_C/BE3 194 S_V
GND 31 P_AD4 116 P_REQ 47 S_CFN 23 TCK 133
GND 37 P_AD5 115 P_RST 43 S_CLK 21 TDI 129
GND 48 P_AD6 113 P_SERR 89 S_CLKOUT0 29 TDO 130
GND 52 P_AD7 112 P_STOP 85 S_CLKOUT1 30 TMS 132
GND 54 P_AD8 109 P_TRDY 83 S_CLKOUT2 32 TRST 134
GND 59 P_AD9 107 P_V
GND 66 P_AD10 101 S_AD0 137 S_CLKOUT4 35 V
GND 72 P_AD11 99 S_AD1 138 S_CLKOUT5 36 V
GND 78 P_AD12 98 S_AD2 140 S_CLKOUT6 38 V
GND 86 P_AD13 96 S_AD3 141 S_CLKOUT7 39 V
GND 94 P_AD14 95 S_AD4 143 S_CLKOUT8 41 V
GND 100 P_AD15 93 S_AD5 144 S_CLKOUT9 42 V
GND 104 P_AD16 77 S_AD6 146 S_DEVSEL 175 V
GND 111 P_AD17 76 S_AD7 147 S_FRAME 179 V
GND 117 P_AD18 74 S_AD8 150 S_GNT0 10 V
GND 123 P_AD19 73 S_AD9 152 S_GNT1 11 V
GND 136 P_AD20 71 S_AD10 154 S_GNT2 13 V
GND 142 P_AD21 70 S_AD11 159 S_GNT3 14 V
GND 148 P_AD22 68 S_AD12 161 S_GNT4 15 V
GND 156 P_AD23 67 S_AD13 162 S_GNT5 16 V
GND 158 P_AD24 63 S_AD14 164 S_GNT6 17 V
GND 160 P_AD25 61 S_AD15 165 S_GNT7 18 V
GND 166 P_AD26 60 S_AD16 182 S_GNT8 19 V
GND 174 P_AD27 58 S_AD17 183 S_IRDY 177 V
GND 181 P_AD28 57 S_AD18 185 S_LOCK 172 V
GND 187 P_AD29 55 S_AD19 186 S_M66ENA 153 V
GND 193 P_AD30 50 S_AD20 188 S_PAR 168 V
GND 199 P_AD31 49 S_AD21 189 S_PERR 171 V
GND 205 P_C/BE0 110 S_AD22 191 S_REQ0 207 V
GPIO0 28 P_C/BE1 92 S_AD23 192 S_REQ1 2 V
GPIO1 27 P_C/BE2 79 S_AD24 195 S_REQ2 3 V
GPIO2 25 P_C/BE3 64 S_AD25 197 S_REQ3 4 V
HS_ENUM 127 P_CLK 45 S_AD26 198 S_REQ4 5 V
HS_LED 128 P_DEVSEL 84 S_AD27 200 S_REQ5 6 V
HS_SWITCH/GPIO3 24 P_FRAME 80 S_AD28 201 S_REQ6 7 V
MS0 155 P_GNT 46 S_AD29 203 S_REQ7 8 V
MS1 106 P_IDSEL 65 S_AD30 204 S_REQ8 9
MSK_IN 126 P_IRDY 82 S_AD31 206 S_RST 22
PPM
NO.
SIGNAL NAME
PPM
NO.
SIGNAL NAME
CCP
PPM
SIGNAL NAME
NO.
124 S_CLKOUT3 33 V
PPM
NO.
SIGNAL NAME
CCP
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
PPM
NO.
135
1
26
34
40
51
53
56
62
69
75
81
91
97
103
105
108
114
120
131
139
145
151
202
208
157
163
170
178
184
190
196
2−9
Table 2−6. 257-Terminal GHK/ZHK Signal Names Sorted Alphabetically
SIGNAL NAME
BPCCE N5 NC A18 NC V19 P_FRAME W11 S_AD29 B5
CONFIG66 L18 NC B1 NC W2 P_GNT R1 S_AD30 E6
GND A7 NC B2 NC W3 P_IDSEL W7 S_AD31 A4
GND A12 NC B3 NC W17 P_IRDY U11 S_CFN J6
GND A14 NC B9 NC W18 P_LOCK P12 S_CLK J3
GND B10 NC B16 P_AD0 M18 P_M66ENA W16 S_CLKOUT0 L1
GND C5 NC B17 P_AD1 M17 P_PAR V13 S_CLKOUT1 L2
GND C15 NC B18 P_AD2 N19 P_PERR R12 S_CLKOUT2 L5
GND D19 NC B19 P_AD3 N18 P_REQ P6 S_CLKOUT3 M1
GND E7 NC C1 P_AD4 M14 P_RST P2 S_CLKOUT4 M3
GND E9 NC C2 P_AD5 P19 P_SERR W13 S_CLKOUT5 M6
GND F13 NC C3 P_AD6 P18 P_STOP W12 S_CLKOUT6 N1
GND F18 NC C4 P_AD7 P17 P_TRDY P11 S_CLKOUT7 N2
GND G3 NC C10 P_AD8 N14 P_V
GND H15 NC C16 P_AD9 R17 S_AD0 J15 S_CLKOUT9 P1
GND J2 NC C17 P_AD10 U15 S_AD1 H19 S_C/BE0 G15
GND J14 NC C18 P_AD11 V15 S_AD2 H17 S_C/BE1 F12
GND L6 NC C19 P_AD12 P14 S_AD3 H14 S_C/BE2 A10
GND M5 NC D1 P_AD13 U14 S_AD4 G19 S_C/BE3 B7
GND M19 NC D3 P_AD14 R13 S_AD5 G18 S_DEVSEL A11
GND N17 NC D17 P_AD15 W14 S_AD6 G14 S_FRAME F11
GND P5 NC D18 P_AD16 U10 S_AD7 F19 S_GNT0 F1
GND R8 NC E5 P_AD17 V10 S_AD8 F17 S_GNT1 H6
GND R10 NC K19 P_AD18 P9 S_AD9 F14 S_GNT2 G2
GND R14 NC L3 P_AD19 R9 S_AD10 F15 S_GNT3 G1
GND R19 NC R2 P_AD20 V9 S_AD11 E14 S_GNT4 H5
GND U1 NC T3 P_AD21 W9 S_AD12 B15 S_GNT5 H3
GND U5 NC T17 P_AD22 V8 S_AD13 A15 S_GNT6 H2
GND U9 NC U2 P_AD23 U8 S_AD14 B14 S_GNT7 H1
GND U12 NC U3 P_AD24 U7 S_AD15 E13 S_GNT8 J1
GND V6 NC U4 P_AD25 W6 S_AD16 E10 S_IRDY C11
GND V14 NC U16 P_AD26 R7 S_AD17 F10 S_LOCK C12
GPIO0 K6 NC U17 P_AD27 U6 S_AD18 C9 S_M66ENA E18
GPIO1 K5 NC U18 P_AD28 W5 S_AD19 F9 S_PAR C13
GPIO2 K2 NC U19 P_AD29 R6 S_AD20 A8 S_PERR E12
HS_ENUM L15 NC V1 P_AD30 T1 S_AD21 B8 S_REQ0 B4
HS_LED L14 NC V2 P_AD31 R3 S_AD22 F8 S_REQ1 E3
HS_SWITCH/GPIO3 K1 NC V3 P_CLK P3 S_AD23 E8 S_REQ2 F5
MSK_IN L17 NC V4 P_C/BE0 R18 S_AD24 C7 S_REQ3 G6
MS0 E17 NC V5 P_C/BE1 P13 S_AD25 A6 S_REQ4 E2
MS1 T19 NC V12 P_C/BE2 P10 S_AD26 B6 S_REQ5 E1
NC A2 NC V17 P_C/BE3 V7 S_AD27 C6 S_REQ6 F3
NC A17 NC V18 P_DEVSEL R11 S_AD28 A5 S_REQ7 F2
GHK
NO.
SIGNAL NAME
GHK
NO.
SIGNAL NAME
GHK
NO.
SIGNAL NAME
CCP
GHK
SIGNAL NAME
NO.
L19 S_CLKOUT8 N6
GHK
NO.
2−10
Table 2−6. 257-Terminal GHK/ZHK Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
S_REQ8 G5 TMS K14 V
S_RST J5 TRST J18 V
S_SERR B13 V
S_STOP B12 V
S_TRDY B11 V
S_V
CCP
TCK J19 V
TDI K18 V
TDO K17 V
GHK
NO.
J17 V
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
GHK
NO.
A3 V
A9 V
A13 V
A16 V
C8 V
C14 V
D2 V
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
CC
CC
GHK
NO.
E11 V
E19 V
F6 V
F7 V
M15 V
G17 V
H18 V
K3 V
K15 V
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
CC
CC
GHK
NO.
M2 V
N3 V
N15 V
P7 V
P8 V
P15 V
T2
T18
U13
SIGNAL NAME
CC
CC
CC
CC
CC
CC
GHK
NO.
V11
V16
W4
W8
W10
W15
2−11
The terminals are grouped in tables by functionality, such as PCI system function and power-supply function (see
Table 2−7 through Table 2−15). The terminal numbers also are listed for convenient reference.
Table 2−7. Primary PCI System Terminals
TERMINAL
PDV/
GHK/
NAME
P_CLK 45 P3 I
P_RST
PPM
ZHK
NO.
NO.
43 P2 I
I/O DESCRIPTION
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI
signals are sampled at rising edge of P_CLK.
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers
in a high-impedance state and reset all internal registers. When asserted, the device is completely
nonfunctional. During P_RST, the secondary interface is driven low. After P_RST is deasserted, the bridge
is in its default state.
Table 2−8. Primary PCI Address and Data Terminals
TERMINAL
PDV/
NAME
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
PPM
NO.
49
50
55
57
58
60
61
63
67
68
70
71
73
74
76
77
93
95
96
98
99
101
107
109
112
113
115
116
118
119
121
122
64
79
92
110
GHK/
ZHK
NO.
W5
W6
W9
V10
U10
W14
R13
U14
P14
V15
U15
R17
N14
P17
P18
P19
M14
N18
N19
M17
M18
P10
P13
R18
I/O DESCRIPTION
R3
T1
R6
U6
R7
U7
U8
V8
V9
R9
P9
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, P_AD31−P_AD0 contain a
I/O
32-bit address or other destination information. During the data phase, P_AD31−P_AD0 contain data.
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
V7
During the address phase of a primary bus PCI cycle, P_C/BE3
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte
I/O
paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7−P_AD0),
P_C/BE1
P_C/BE3
applies to byte 1 (P_AD15−P_AD8), P_C/BE2 applies to byte 2 (P_AD23−P_AD16), and
applies to byte 3 (P_AD31−P_AD24).
−P_C/BE0 define the bus command.
2−12
Table 2−9. Primary PCI Interface Control Terminals
TERMINAL
PDV/
GHK/
PPM
NAME
P_DEVSEL 84 R11 I/O
P_FRAME
P_GNT
P_IDSEL 65 W7 I
P_IRDY 82 U11 I/O
P_LOCK 87 P12 I/O
P_PAR 90 V13 I/O
P_PERR
P_REQ 47 P6 O Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as a master.
P_SERR 89 W13 O
P_STOP 85 W12 I/O
P_TRDY 83 P11 I/O
ZHK
NO.
NO.
80 W11 I/O
46 R1 I
88 R12 I/O
I/O DESCRIPTION
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As
a PCI master on the primary bus, the bridge monitors P_DEVSEL
responds before time-out occurs, then the bridge terminates the cycle with a master abort.
Primary cycle frame. P_FRAME is driven by the master of a primary bus cycle. P_FRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When P_FRAME is deasserted, the primary bus transaction is in the final data phase.
Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access
to the primary PCI bus after the current data transaction has completed. P_GNT
a primary bus request, depending on the primary bus arbitration algorithm.
Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.
P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus.
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space
of the bridge can only be accessed from the primary bus.
Primary initiator ready . P_IRDY indicates ability of the primary bus master to complete the current data
phase of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY
and P_TRDY are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are
inserted.
Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as a bus
master.
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the
P_AD and P_C/BE
indicator with a one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared
to the parity indicator of the master; a miscompare can result in a parity error assertion (P_PERR).
Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated
parity does not match P_PAR when P_PERR
offset 04h, see Section 4.3).
Primary system error. Output pulsed from the bridge when enabled through bit 8 of the command
register (PCI offset 04h, see Section 4.3) indicating a system error has occurred. The bridge needs
not be the target of the primary PCI cycle to assert this signal. When bit 6 is enabled in the bridge control
register (PCI offset 3Eh, see Section 4.32), this signal also pulses, indicating that a system error has
occurred on one of the subordinate buses downstream from the bridge.
Primary cycle stop signal. This signal is driven by a PCI target to request that the master stop the
current primary bus transaction. This signal is used for target disconnects and is commonly asserted
by target devices which do not support burst data transfers.
Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current
data phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both
P_IRDY and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are
inserted.
buses. As a bus master during PCI write cycles, the bridge outputs this parity
is enabled through bit 6 of the command register (PCI
until a target responds. If no target
may or may not follow
2−13
TERMINAL
PDV/
GHK/
NAME
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
S_CLK
S_CFN 23 J6 I
S_RST 22 J5 O
PPM
ZHK
NO.
NO.
42
P1
41
N6
39
N2
38
N1
36
M6
35
M3
33
M1
32
L5
30
L2
29
L1
21 J3 I
Table 2−10. Secondary PCI System Terminals
I/O DESCRIPTION
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each
secondary bus device samples all secondary PCI signals at the rising edge of its corresponding
O
S_CLKOUT input.
Secondary PCI bus clock input. This input synchronizes the PCI2050B device to the secondary bus
clocks.
Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled.
When the external arbiter is enabled, the PCI2050B S_REQ0
bus grant input to the bridge and S_GNT0
external arbiter on the secondary bus.
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit
(bit 6) of the bridge control register (PCI offset 3Eh, see Section 4.32). S_RST
respect to the state of the secondary interface CLK signal.
is reconfigured as a secondary bus master request to the
terminal is reconfigured as a secondary
is asynchronous with
2−14
NAME
TERMINAL
PDV/
PPM
NO.
Table 2−11. Secondary PCI Address and Data Terminals
GHK/
ZHK
NO.
I/O DESCRIPTION
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
206
204
203
201
200
198
197
195
192
191
189
188
186
185
183
182
165
164
162
161
159
154
152
150
147
146
144
143
141
140
138
137
A4
E6
B5
A5
C6
B6
A6
C7
E8
F8
B8
A8
F9
C9
F10
E10
E13
B14
A15
B15
E14
F15
F14
F17
F19
G14
G18
G19
H14
H17
H19
J15
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on
the secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31−S_AD0
I/O
contain a 32-bit address or other destination information. During the data phase, S_AD31−S_AD0
contain data.
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
S_DEVSEL 175 A11 I/O
S_FRAME 179 F11 I/O
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
194
180
167
149
19
18
17
16
15
14
13
11
10
B7
A10
F12
G15
J1
H1
H2
H3
H5
G1
G2
H6
F1
I/O
O
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a secondary bus PCI cycle, S_C/BE3
command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine
which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0
(S_AD7−S_AD0), S_C/BE1
(S_AD23−S_AD16), and S_C/BE3
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As
a PCI master on the secondary bus, the bridge monitors S_DEVSEL
responds before time-out occurs, then the bridge terminates the cycle with a master abort.
Secondary cycle frame. S_FRAME is driven by the master of a secondary bus cycle. S_FRAME is
asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME
is asserted. When S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used
to grant potential secondary PCI bus masters access to the bus. Ten potential masters (including the
bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, S_GNT0
signal for the bridge.
applies to byte 1 (S_AD15−S_AD8), S_C/BE2 applies to byte 2
applies to byte 3 (S_AD31−S_AD24).
is reconfigured as an external secondary bus request
−S_C/BE0 define the bus
applies to byte 0
until a target responds. If no target
2−15
TERMINAL
PDV/
GHK/
NAME
S_IRDY 177 C11 I/O
S_LOCK 172 C12 I/O
S_PAR 168 C13 I/O
S_PERR
S_REQ8
S_REQ7
S_REQ6
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
S_SERR
S_STOP 173 B12 I/O
S_TRDY 176 B11 I/O
PPM
ZHK
NO.
NO.
171 E12 I/O
9
G5
8
7
6
E1
5
E2
4
G6
3
2
207
169 B13 I
E3
B4
I/O DESCRIPTION
F2
F3
F5
Table 2−12. Secondary PCI Interface Control Terminals
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as a
master.
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across
the S_AD and S_C/BE
with a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the
master parity indicator. A miscompare can result in a parity error assertion (S_PERR).
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that
calculated parity does not match S_P AR when enabled through the command register (PCI offset 04h,
see Section 4.3).
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used
as inputs from secondary PCI bus masters requesting the bus. Ten potential masters (including the
bridge) can be located on the secondary PCI bus.
I
When the internal arbiter is disabled, the S_REQ0
grant for the bridge.
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled
through the bridge control register (PCI offset 3Eh, see Section 4.32). S_SERR
bridge.
Secondary cycle stop signal. S_STOP is driven by a PCI target to request that the master stop the current
secondary bus transaction. S_STOP
devices that do not support burst data transfers.
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY
and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
buses. As a master during PCI write cycles, the bridge outputs this parity indicator
signal is reconfigured as an external secondary bus
is never asserted by the
is used for target disconnects and is commonly asserted by target
Table 2−13. JTAG Interface Terminals
TERMINAL
PDV/
GHK/
NAME
TCK 133 J19 I JTAG boundary-scan clock. TCK is the clock controlling the JTAG logic.
TDI 129 K18 I
TDO 130 K17 O
TMS 132 K14 I JTAG test mode select. TMS causes state transitions in the test access port controller.
TRST 134 J18 I
2−16
PPM
NO.
ZHK
NO.
I/O DESCRIPTION
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG
interface. The new data on TDI is sampled on the rising edge of TCK.
JTAG serial data out. TDO is the serial output through which test instructions and data from the test logic
leave the PCI2050B device.
JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a
reset state and initialize the test logic.
Table 2−14. Miscellaneous Terminals
DESCRIPTION
TERMINAL
PDV/
NAME
BPCCE 44 N5 I
CONFIG66 125 L18 I
GPIO3/HS_SWITCH
GPIO2
GPIO1
GPIO0
HS_ENUM 127 L15 O Hot-swap ENUM
HS_LED 128 L14 O Hot-swap LED output
MS0
MS1
P_M66ENA 102 W16 I
S_M66ENA 153 E18 I/O
GHK/
PPM
ZHK
NO.
NO.
24
25
27
28
155 E17 I Mode select 0
106 T19 I Mode select 1
I/O DESCRIPTION
Bus/power clock control management terminal. When this terminal is tied high and the
PCI2050B device is placed in the D3 power state, it enables the PCI2050B device to place the
secondary bus in the B2 power state. The PCI2050Bdevice disables the secondary clocks and
drives them to 0. When tied low, placing the PCI2050B device in the D3 power state has no
effect on the secondary bus clocks.
Configure 66 MHz operation. This input-only terminal is used to specify if the PCI2050B device
is capable of running at 66 MHz. If this terminal is tied high, then device can be run at 66 MHz.
If this terminal is tied low, then the PCI2050B device can only function under the 33-MHz PCI
configuration.
K1
K2
K5
K6
General-purpose I/O terminals
GPIO3 is HS_SWITCH
I
HS_SWITCH
Primary interface 66 MHz enable. This input-only signal designates the primary interface bus
speed. This terminal must be pulled low for 33-MHz operation on the primary bus. In this case,
S_M66ENA signal will be driven low by the PCI2050B device, forcing the secondary bus to
run at 33 MHz. For 66-MHz operation, this terminal must be pulled high.
Secondary 66 MHz enable. This signal designates the secondary bus speed. If the
P_M66ENA is driven low, then this signal is driven low by the PCI2050B device, forcing
secondary bus to run at 33 MHz. If the primary bus is running at 66 MHz (P_M66ENA is high),
then S_M66ENA is an input and must be externally pulled high for the secondary bus to
operate at 6 6 MHz or pulled low for secondary bus to operate at 33 MHz. Note that S_M66ENA
is an open drained output.
in cPCI mode.
provides the status of the ejector handle switch to the cPCI logic.
Table 2−15. Power Supply Terminals
TERMINAL
NAME PDV/PPM NO. GHK NO.
12, 20, 31, 37, 48, 52, 54,
59, 66, 72, 78, 86, 94, 100,
GND
V
CC
P_V
CCP
S_V
CCP
NOTE 1: TI recommends that P_V
104, 111, 117, 123, 136,
142, 148, 156, 158, 160,
166, 174, 181, 187, 193,
199, 205
1, 26, 34, 40, 51, 53, 56, 62,
69, 75, 81, 91, 97, 103, 105,
108, 114, 120, 131, 139,
145, 151, 157, 163, 170,
178, 184, 190, 196, 202,
(1)
(1)
208
124 L19
135 J17
CCP
A7, A12, A14, B10, C5,
C15, D19, E7, E9, F13,
F18, G3, H15, J2, J14, L6,
M5, M19, N17, P5, R8,
R10, R14, R19, U1, U5, U9,
U12, V6, V14
A3, A9, A13, A16, C8, C14,
D2, E11, E19, F6, F7, M15,
G17, H18, K3, K15, M2, N3,
N15, P7, P8, P15, T2, T18,
U13, V11, V16, W4, W8,
W10, W15
and S_V
be powered up first before applying power to VCC.
CCP
Device ground terminals
Power-supply terminal for core logic (3.3 V)
Primary bus-signaling environment supply. P_V
protection circuitry on primary bus I/O signals.
Secondary bus-signaling environment supply. S_V
protection circuitry on secondary bus I/O signals.
CCP
CCP
is used in
is used in
2−17
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