TEXAS INSTRUMENTS PCI2050 Technical data
查询PCI2050供应商
Data Manual
1999 PCIBus Solutions
Printed in U.S.A., 12/99 SCPS053
PCI2050
PCI-to-PCI Bridge
Data Manual
Literature Number: SCPS053
December 1999
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify , before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
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or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction to the PCI2050 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 PCI Commands 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Configuration Cycles 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Special Cycle Generation 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Secondary Clocks 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Primary Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Internal Secondary Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . .
3.6.3 External Secondary Bus Arbitration 3–6. . . . . . . . . . . . . . . . . . .
3.7 Decode Options 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 System Error Handling 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Posted Write Parity Error 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Posted Write Timeout 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 Target Abort on Posted Writes 3–6. . . . . . . . . . . . . . . . . . . . . . . .
3.8.4 Master Abort on Posted Writes 3–7. . . . . . . . . . . . . . . . . . . . . . .
3.8.5 Master Delayed Write Timeout 3–7. . . . . . . . . . . . . . . . . . . . . . . .
3.8.6 Master Delayed Read Timeout 3–7. . . . . . . . . . . . . . . . . . . . . . .
3.8.7 Secondary SERR 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Parity Handling and Parity Error Reporting 3–7. . . . . . . . . . . . . . . . . . . . . .
3.9.1 Address Parity Error 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Data Parity Error 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Master and Target Abort Handling 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Discard Timer 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Delayed Transactions 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Mode Selection 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 Compact PCI Hot-Swap Support 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 JTAG Support 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1 Test Port Instructions 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16 GPIO Interface 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16.1 Secondary Clock Mask 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
3.16.2 Transaction Forwarding Control 3–15. . . . . . . . . . . . . . . . . . . . . . .
3.17 PCI Power Management 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 Behavior in Low Power States 3–15. . . . . . . . . . . . . . . . . . . . . . . .
4 Bridge Configuration Header 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Vendor ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Device ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Revision ID Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Class Code Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Cache Line Size Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Primary Latency Timer Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Header Type Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 BIST Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 Base Address Register 0 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Base Address Register 1 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Primary Bus Number Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Bus Number Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Subordinate Bus Number Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Secondary Bus Latency Timer Register 4–8. . . . . . . . . . . . . . . . . . . . . . . .
4.17 I/O Base Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 I/O Limit Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Secondary Status Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Base Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 Memory Limit Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Prefetchable Memory Base Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Prefetchable Memory Limit Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Prefetchable Base Upper 32 Bits Register 4–12. . . . . . . . . . . . . . . . . . . . . .
4.25 Prefetchable Limit Upper 32 Bits Register 4–13. . . . . . . . . . . . . . . . . . . . . .
4.26 I/O Base Upper 16 Bits Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 I/O Limit Upper 16 Bits Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 Capability Pointer Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.29 Expansion ROM Base Address Register 4–14. . . . . . . . . . . . . . . . . . . . . . . .
4.30 Interrupt Line Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Interrupt Pin Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Bridge Control Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Extension Registers 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Chip Control Register 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Extended Diagnostic Register 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Arbiter Control Register 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 P_SERR Event Disable Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 GPIO Output Data Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 GPIO Output Enable Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 GPIO Input Data Register 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
5.8 Secondary Clock Control Register 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 P_SERR Status Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 PM Capability ID Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 PM Next Item Pointer Register 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Power Management Capabilities Register 5–9. . . . . . . . . . . . . . . . . . . . . .
5.13 Power Management Control/Status Register 5–10. . . . . . . . . . . . . . . . . . . .
5.14 PMCSR Bridge Support Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15 Data Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 HS Capability ID Register 5–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.17 HS Next Item Pointer Register 5–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.18 Hot Swap Control Status Register 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Absolute Maximum Ratings Over Operating Temperature Ranges 6–1.
6.2 Recommended Operating Conditions 6–2. . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Recommended Operating Conditions for PCI Interface 6–2. . . . . . . . . . .
6.4 Electrical Characteristics Over Recommended Operating Conditions 6–3
6.5 PCI Clock/Reset Timing Requirements Over Recommended
Ranges Of Supply Voltage And Operating Free-Air Temperature 6–4. . .
6.6 PCI Timing Requirements Over Recommended Ranges Of
Supply Voltage And Operating Free-Air Temperature 6–5. . . . . . . . . . . . .
6.7 Parameter Measurement Information 6–6. . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 PCI Bus Parameter Measurement Information 6–7. . . . . . . . . . . . . . . . . . .
7 Mechanical Data 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
List of Illustrations
Figure Title Page
2–1 PCI2050 Terminal Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 System Block Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle 3–2
3–3 PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle 3–3
3–4 Bus Hierarchy and Numbering 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Secondary Clock Block Diagram 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Clock Mask Read Timing After Reset 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Load Circuit and Voltage Waveforms 6–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 PCLK Timing Waveform 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 RSTIN
6–4 Shared-Signals Timing Waveforms 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Waveforms 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Tables
Table Title Page
2–1 208-Terminal PDV Signal Names Sorted by Terminal Number 2–2. . . . . . . .
2–2 Signal Names Sorted Alphabetically 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 208-Terminal GHK Signal Names Sorted by Terminal Number 2–6. . . . . . . .
2–4 Primary PCI System 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Primary PCI Address and Data 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Primary PCI Interface Control 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Secondary PCI System 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Secondary PCI Address and Data 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Secondary PCI Interface Control 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Miscellaneous Terminals 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 JTAG Interface Terminals 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 Power Supply 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PCI Command Definition 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI S_AD31–S_AD16 During the Address Phase of a Type 0
Configuration Cycle 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Configuration Via MS0 and MS1 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 JTAG Instructions and Op Codes 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Boundary Scan Terminal Order 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Clock Mask Data Format 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Bridge Configuration Header 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Secondary Status Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Bridge Control Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Chip Control Register 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Extended Diagnostic Register 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Arbiter Control Register 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 P_SERR Event Disable Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 GPIO Output Data Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 GPIO Output Enable Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 GPIO Input Data Register 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 Secondary Clock Control Register 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 P_SERR Status Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Power Management Capabilities Register 5–9. . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 Power Management Control/Status Register 5–10. . . . . . . . . . . . . . . . . . . . . . .
5–12 PMCSR Bridge Support Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 Hot Swap Control Status Register 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
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1 Introduction
1.1 Description
The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high performance connection path between two
peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets
on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge
supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act
independently.
The PCI2050 bridge is compliant with the
loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The
PCI2050 provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with
an external secondary PCI bus arbiter.
The compact-PCI hot-swap extended PCI capability is provided which makes the PCI2050 an ideal solution for
multifunction compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050 bridge is compliant with the
for
PCI Power Management 1.0 and 1.1
An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates
up to 33 MHz.
PCI Local Bus Specification
PCI-to-PCI Bridge Specification 1.1
. The PCI2050 has been designed to lead the industry in power conservation.
, and can be used to overcome the electrical
. The PCI 2050 provides compliance
1.2 Features
The PCI2050 supports the following features:
• Configurable for
• Provides compact PCI hot-swap functionality
• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Two 32-bit, 33-MHz PCI buses
• Provides internal two-tier arbitration for up to nine secondary bus masters and supports an external
secondary bus arbiter
PCI Bus Power Management Interface Specification
• Burst data transfers with pipeline architecture to maximize data throughput in both directions
• Independent read and write buffers for each direction
• Up to three delayed transactions in both directions
• Provides 10 secondary PCI clock outputs
• Predictable latency per
• Propagates bus locking
• Secondary bus is driven low during reset
• Provides VGA/palette memory and I/O, and subtractive decoding options
• Advanced submicron, low-power CMOS technology
• Packaged in 208-terminal QFP or 209-terminal MicroStar BGA
PCI Local Bus Specification
1–1
1.3 Related Documents
•
Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0)
•
PCI Local Bus Specification (Revision 2.2)
•
PCI-to-PCI Bridge Architecture Specification (Revision 1.1)
•
PCI Bus Power Management Interface Specification (Revision 1.1)
•
PICMG Compact-PCI Hot Swap Specification (Revision 1.0)
1.4 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI2050 PCI–PCI Bridge 3.3 V, 5-V Tolerant I/Os 208-terminal QFP
209-terminal MicroStar BGA
1–2
2 Terminal Descriptions
PDV LOW-PROFILE QUAD FLAT PACKAGE
TOP VIEW
V
CC
GND
S_AD11
GND
S_AD12
S_AD13
V
CC
S_AD14
S_AD15
GND
S_C/BE1
S_PAR
S_SERR
V
CC
S_PERR
S_LOCK
S_STOP
GND
S_DEVSEL
S_TRDY
S_IRDY
V
CC
S_FRAME
S_C/BE2
GND
S_AD16
S_AD17
V
CC
S_AD18
S_AD19
GND
S_AD20
S_AD21
V
CC
S_AD22
S_AD23
GND
S_C/BE3
S_AD24
V
CC
S_AD25
S_AD26
GND
S_AD27
S_AD28
V
CC
S_AD29
S_AD30
GND
S_AD31
S_REQ0
V
CC
NC
MSK_IN
HSENUM
126
125
127
CCP
P_V
124
GND
123
P_AD1
P_AD0
122
121
CC
V
120
P_AD2
P_AD3
118
119
GND
117
P_AD4
P_AD5
116
115
CC
V
114
P_AD6
P_AD7
112
113
CCP
GND
148
S_AD7
S_AD6
146
147
CC
V
145
S_AD4
S_AD5
144
143
CC
V
S_M66ENA
S_AD10
S_AD9
S_C/BE0
154
153
152
151
S_AD8
150
149
MS0
155
214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
156
GND
142
S_AD2
S_AD3
140
141
CC
V
139
S_AD0
S_AD1
138
137
GND
136
S_V
135
TCLK
TRST
134
133
CC
TMS
V
TDO
130
132
131
PCI2050
TDI
129
HSLED
128
GND
P_C/BE0
111
110
CC
V
P_AD8
108
109
P_AD9
MS1
107
51 106
CC
V
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
GND
V
CC
NC
P_AD10
GND
P_AD11
P_AD12
V
CC
P_AD13
P_AD14
GND
P_AD15
P_C/BE1
V
CC
P_PAR
P_SERR
P_PERR
P_LOCK
GND
P_STOP
P_DEVSEL
P_TRDY
P_IRDY
V
CC
P_FRAME
P_C/BE2
GND
P_AD16
P_AD17
V
CC
P_AD18
P_AD19
GND
P_AD20
P_AD21
V
CC
P_AD22
P_AD23
GND
P_IDSEL
P_C/BE3
P_AD24
V
CC
P_AD25
P_AD26
GND
P_AD27
P_AD28
V
CC
P_AD29
GND
V
CC
CC
V
S_REQ1
S_REQ2
S_REQ3
S_REQ5
S_REQ6
S_REQ4
S_GNT0
S_REQ8
S_REQ7
CC
GND
S_GNT1
S_GNT2
S_GNT5
S_GNT3
S_GNT4
S_GNT8
S_GNT6
S_GNT7
GND
S_CLK
V
GPIO2
S_RST
S_CFN
HSSWITCH/GPIO3
GPIO0
GPIO1
GND
S_CLKOUT1
S_CLKOUT2
S_CLKOUT0
Figure 2–1. PCI2050 Terminal Diagram
CC
V
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
GND
S_CLKOUT7
S_CLKOUT6
CC
V
S_CLKOUT8
S_CLKOUT9
P_RST
BPCCE
P_CLK
P_GNT
GND
P_REQ
V
P_AD30
P_AD31
CC
GND
2–1
Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number
PDV
GHK
NO.
NO.
1 D1 V
2 E3 S_REQ1 45 N5 P_CLK 88 U12 P_PERR 131 K15 V
3 F5 S_REQ2 46 P3 P_GNT 89 P12 P_SERR 132 K14 TMS
4 G6 S_REQ3 47 R1 P_REQ 90 R12 P_PAR 133 J19 TCLK
5 E2 S_REQ4 48 P6 GND 91 W13 V
6 E1 S_REQ5 49 R2 P_AD31 92 V13 P_C/BE1 135 J17 S_V
7 F3 S_REQ6 50 P5 P_AD30 93 U13 P_AD15 136 J14 GND
8 F2 S_REQ7 51 R3 V
9 G5 S_REQ8 52 T1 GND 95 W14 P_AD14 138 H19 S_AD1
10 F1 S_GNT0 53 W4 V
11 H6 S_GNT1 54 U5 GND 97 R13 V
12 G3 GND 55 R6 P_AD29 98 U14 P_AD12 141 H14 S_AD3
13 G2 S_GNT2 56 P7 V
14 G1 S_GNT3 57 V5 P_AD28 100 P14 GND 143 G19 S_AD4
15 H5 S_GNT4 58 W5 P_AD27 101 V15 P_AD10 144 G18 S_AD5
16 H3 S_GNT5 59 U6 GND 102 R14 NC 145 G17 V
17 H2 S_GNT6 60 V6 P_AD26 103 U15 V
18 H1 S_GNT7 61 R7 P_AD25 104 W16 GND 147 F19 S_AD7
19 J1 S_GNT8 62 W6 V
20 J2 GND 63 P8 P_AD24 106 R17 MS1 149 G15 S_C/BE0
21 J3 S_CLK 64 U7 P_C/BE3 107 P15 P_AD9 150 F17 S_AD8
22 J5 S_RST 65 V7 P_IDSEL 108 N14 V
23 J6 S_CFN 66 W7 GND 109 R18 P_AD8 152 F14 S_AD9
24 K1 HSSWITCH/GPIO3 67 R8 P_AD23 110 R19 P_C/BE0 153 E18 S_M66ENA
25 K2 GPIO2 68 U8 P_AD22 111 P17 GND 154 F15 S_AD10
26 K3 V
27 K5 GPIO1 70 W8 P_AD21 113 N15 P_AD6 156 D19 GND
28 K6 GPIO0 71 W9 P_AD20 114 P19 V
29 L1 S_CLKOUT0 72 V9 GND 115 M14 P_AD5 158 C15 GND
30 L2 S_CLKOUT1 73 U9 P_AD19 116 N17 P_AD4 159 E14 S_AD11
31 L3 GND 74 R9 P_AD18 117 N18 GND 160 F13 GND
32 L6 S_CLKOUT2 75 P9 V
33 L5 S_CLKOUT3 76 W10 P_AD17 119 M15 P_AD2 162 A15 S_AD13
34 M1 V
35 M2 S_CLKOUT4 78 U10 GND 121 M18 P_AD1 164 B14 S_AD14
36 M3 S_CLKOUT5 79 R10 P_C/BE2 122 M19 P_AD0 165 E13 S_AD15
37 M6 GND 80 P10 P_FRAME 123 L19 GND 166 A14 GND
38 M5 S_CLKOUT6 81 W11 V
39 N1 S_CLKOUT7 82 V11 P_IRDY 125 L17 NC 168 C13 S_PAR
40 N2 V
41 N3 S_CLKOUT8 84 P11 P_DEVSEL 127 L14 HSENUM 170 A13 V
42 N6 S_CLKOUT9 85 R11 P_STOP 128 K19 HSLED 171 E12 S_PERR
43 P1 P_RST 86 W12 GND 129 K18 TDI 172 C12 S_LOCK
SIGNAL NAME
CC
CC
CC
CC
PDV
GHK
NO.
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
NO.
44 P2 BPCCE 87 V12 P_LOCK 130 K17 TDO
69 V8 V
77 V10 P_AD16 120 M17 V
83 U11 P_TRDY 126 L15 MSK_IN 169 B13 S_SERR
PDV
GHK
NO.
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
CCP
NO.
94 P13 GND 137 J15 S_AD0
96 V14 P_AD13 139 H18 V
99 W15 P_AD11 142 H15 GND
105 T19 V
112 P18 P_AD7 155 E17 MS0
118 N19 P_AD3 161 B15 S_AD12
124 L18 P_V
PDV
GHK
NO.
SIGNAL NAME
CC
CCP
CC
CC
CC
CC
CC
CC
NO.
134 J18 TRST
140 H17 S_AD2
146 G14 S_AD6
148 F18 GND
151 E19 V
157 A16 V
163 C14 V
167 F12 S_C/BE1
2–2
Table 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number (continued)
PDV
GHK
NO.
SIGNAL NAME
CC
NO.
173 B12 S_STOP 182 C10 S_AD16 191 B8 S_AD22 200 B6 S_AD27
174 A12 GND 183 E10 S_AD17 192 C8 S_AD23 201 E7 S_AD28
175 A11 S_DEVSEL 184 F10 V
176 B11 S_TRDY 185 A9 S_AD18 194 E8 S_C/BE3 203 A5 S_AD29
177 C11 S_IRDY 186 B9 S_AD19 195 A7 S_AD24 204 F6 S_AD30
178 E11 V
179 F11 S_FRAME 188 F9 S_AD20 197 C7 S_AD25 206 E6 S_AD31
180 A10 S_C/BE2 189 E9 S_AD21 198 F7 S_AD26 207 C5 S_REQ0
181 B10 GND 190 A8 V
PDV
GHK
NO.
SIGNAL NAME
CC
CC
NO.
187 C9 GND 196 B7 V
PDV
GHK
NO.
NO.
193 F8 GND 202 C6 V
199 A6 GND 208 A4 V
SIGNAL NAME
CC
PDV
GHK
NO.
SIGNAL NAME
CC
CC
NO.
205 B5 GND
2–3
Table 2–2. Signal Names Sorted Alphabetically
PDV
SIGNAL NAME
BPCCE 44 P2 P_AD0 122 M19 P_PAR 90 R12 S_C/BE3 194 E8
GND 12 G3 P_AD1 121 M18 P_PERR 88 U12 S_CFN 23 J6
GND 20 J2 P_AD2 119 M15 P_REQ 47 R1 S_CLK 21 J3
GND 31 L3 P_AD3 118 N19 P_RST 43 P1 S_CLKOUT0 29 L1
GND 37 M6 P_AD4 116 N17 P_SERR 89 P12 S_CLKOUT1 30 L2
GND 48 P6 P_AD5 115 M14 P_STOP 85 R11 S_CLKOUT2 32 L6
GND 52 T1 P_AD6 113 N15 P_TRDY 83 U11 S_CLKOUT3 33 L5
GND 54 U5 P_AD7 112 P18 P_V
GND 59 U6 P_AD8 109 R18 S_AD0 137 J15 S_CLKOUT5 36 M3
GND 66 W7 P_AD9 107 P15 S_AD1 138 H19 S_CLKOUT6 38 M5
GND 72 V9 P_AD10 101 V15 S_AD2 140 H17 S_CLKOUT7 39 N1
GND 78 U10 P_AD11 99 W15 S_AD3 141 H14 S_CLKOUT8 41 N3
GND 86 W12 P_AD12 98 U14 S_AD4 143 G19 S_CLKOUT9 42 N6
GND 94 P13 P_AD13 96 V14 S_AD5 144 G18 S_DEVSEL 175 A11
GND 100 P14 P_AD14 95 W14 S_AD6 146 G14 S_FRAME 179 F11
GND 104 W16 P_AD15 93 U13 S_AD7 147 F19 S_GNT0 10 F1
GND 111 P17 P_AD16 77 V10 S_AD8 150 F17 S_GNT1 11 H6
GND 117 N18 P_AD17 76 W10 S_AD9 152 F14 S_GNT2 13 G2
GND 123 L19 P_AD18 74 R9 S_AD10 154 F15 S_GNT3 14 G1
GND 136 J14 P_AD19 73 U9 S_AD11 159 E14 S_GNT4 15 H5
GND 142 H15 P_AD20 71 W9 S_AD12 161 B15 S_GNT5 16 H3
GND 148 F18 P_AD21 70 W8 S_AD13 162 A15 S_GNT6 17 H2
GND 156 D19 P_AD22 68 U8 S_AD14 164 B14 S_GNT7 18 H1
GND 158 C15 P_AD23 67 R8 S_AD15 165 E13 S_GNT8 19 J1
GND 160 F13 P_AD24 63 P8 S_AD16 182 C10 S_IRDY 177 C11
GND 166 A14 P_AD25 61 R7 S_AD17 183 E10 S_LOCK 172 C12
GND 174 A12 P_AD26 60 V6 S_AD18 185 A9 S_M66ENA 153 E18
GND 181 B10 P_AD27 58 W5 S_AD19 186 B9 S_PAR 168 C13
GND 187 C9 P_AD28 57 V5 S_AD20 188 F9 S_PERR 171 E12
GND 193 F8 P_AD29 55 R6 S_AD21 189 E9 S_REQ0 207 C5
GND 199 A6 P_AD30 50 P5 S_AD22 191 B8 S_REQ1 2 E3
GND 205 B5 P_AD31 49 R2 S_AD23 192 C8 S_REQ2 3 F5
GPIO0 28 K6 P_C/BE0 110 R19 S_AD24 195 A7 S_REQ3 4 G6
GPIO1 27 K5 P_C/BE1 92 V13 S_AD25 197 C7 S_REQ4 5 E2
GPIO2 25 K2 P_C/BE2 79 R10 S_AD26 198 F7 S_REQ5 6 E1
HSENUM 127 L14 P_C/BE3 64 U7 S_AD27 200 B6 S_REQ6 7 F3
HSLED 128 K19 P_CLK 45 N5 S_AD28 201 E7 S_REQ7 8 F2
HSSWITCH/GPIO3 24 K1 P_DEVSEL 84 P11 S_AD29 203 A5 S_REQ8 9 G5
MS0 155 E17 P_FRAME 80 P10 S_AD30 204 F6 S_RST 22 J5
MS1 106 R17 P_GNT 46 P3 S_AD31 206 E6 S_SERR 169 B13
MSK_IN 126 L15 P_IDSEL 65 V7 S_C/BE0 149 G15 S_STOP 173 B12
NC 102 R14 P_IRDY 82 V11 S_C/BE1 167 F12 S_TRDY 176 B11
NC 125 L17 P_LOCK 87 V12 S_C/BE2 180 A10 S_V
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
CCP
PDV
GHK
NO.
SIGNAL NAME
CCP
NO.
124 L18 S_CLKOUT4 35 M2
PDV
GHK
NO.
NO.
135 J17
2–4
Table 2–2. Signal Names Sorted Alphabetically (continued)
PDV
SIGNAL NAME
TCLK 133 J19 V
TDI 129 K18 V
TDO 130 K17 V
TMS 132 K14 V
TRST 134 J18 V
V
CC
V
CC
V
CC
V
CC
GHK
NO.
NO.
1 D1 V
26 K3 V
34 M1 V
40 N2 V
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
CC
CC
PDV
GHK
NO.
NO.
51 R3 V
53 W4 V
56 P7 V
62 W6 V
69 V8 V
75 P9 V
81 W11 V
91 W13 V
97 R13 V
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
CC
CC
PDV
GHK
NO.
NO.
103 U15 V
105 T19 V
108 N14 V
114 P19 V
120 M17 V
131 K15 V
139 H18 V
145 G17 V
151 E19 V
SIGNAL NAME
CC
CC
CC
CC
CC
CC
CC
CC
CC
PDV
GHK
NO.
NO.
157 A16
163 C14
170 A13
178 E11
184 F10
190 A8
196 B7
202 C6
208 A4
2–5
Table 2–3. 209-Terminal GHK Signal Names Sorted by Terminal Number
GHK
SIGNAL NAME
NO.
A4 V
CC
A5 S_AD29 E10 S_AD17 H18 V
A6 GND E11 V
A7 S_AD24 E12 S_PERR J1 S_GNT8 N5 P_CLK U7 P_C/BE3
A8 V
CC
A9 S_AD18 E14 S_AD11 J3 S_CLK N14 V
A10 S_C/BE2 E17 MS0 J5 S_RST N15 P_AD6 U10 GND
A11 S_DEVSEL E18 S_M66ENA J6 S_CFN N17 P_AD4 U11 P_TRDY
A12 GND E19 V
A13 V
CC
A14 GND F2 S_REQ7 J17 S_V
A15 S_AD13 F3 S_REQ6 J18 TRST P2 BPCCE U15 V
A16 V
CC
B5 GND F6 S_AD30 K1 HSSWITCH/GPIO3 P5 P_AD30 V6 P_AD26
B6 S_AD27 F7 S_AD26 K2 GPIO2 P6 GND V7 P_IDSEL
B7 V
CC
B8 S_AD22 F9 S_AD20 K5 GPIO1 P8 P_AD24 V9 GND
B9 S_AD19 F10 V
B10 GND F11 S_FRAME K14 TMS P10 P_FRAME V11 P_IRDY
B11 S_TRDY F12 S_C/BE1 K15 V
B12 S_STOP F13 GND K17 TDO P12 P_SERR V13 P_C/BE1
B13 S_SERR F14 S_AD9 K18 TDI P13 GND V14 P_AD13
B14 S_AD14 F15 S_AD10 K19 HSLED P14 GND V15 P_AD10
B15 S_AD12 F17 S_AD8 L1 S_CLKOUT0 P15 P_AD9 W4 V
C5 S_REQ0 F18 GND L2 S_CLKOUT1 P17 GND W5 P_AD27
C6 V
CC
C7 S_AD25 G1 S_GNT3 L5 S_CLKOUT3 P19 V
C8 S_AD23 G2 S_GNT2 L6 S_CLKOUT2 R1 P_REQ W8 P_AD21
C9 GND G3 GND L14 HSENUM R2 P_AD31 W9 P_AD20
C10 S_AD16 G5 S_REQ8 L15 MSK_IN R3 V
C11 S_IRDY G6 S_REQ3 L17 NC R6 P_AD29 W11 V
C12 S_LOCK G14 S_AD6 L18 P_V
C13 S_PAR G15 S_C/BE0 L19 GND R8 P_AD23 W13 V
C14 V
CC
C15 GND G18 S_AD5 M2 S_CLKOUT4 R10 V
D1 V
CC
D19 GND H1 S_GNT7 M5 S_CLKOUT6 R12 P_PAR
E1 S_REQ5 H2 S_GNT6 M6 GND R13 V
E2 S_REQ4 H3 S_GNT5 M14 P_AD5 R14 NC
E3 S_REQ1 H5 S_GNT4 M15 P_AD2 R17 MS1
E6 S_AD31 H6 S_GNT1 M17 V
E7 S_AD28 H14 S_AD3 M18 P_AD1 R19 P_C/BE0
E8 S_C/BE3 H15 GND M19 P_AD0 T1 GND
GHK
SIGNAL NAME
NO.
E9 S_AD21 H17 S_AD2 N1 S_CLKOUT7 T19 V
CC
E13 S_AD15 J2 GND N6 S_CLKOUT9 U8 P_AD22
CC
F1 S_GNT0 J15 S_AD0 N19 P_AD3 U13 P_AD15
F5 S_REQ2 J19 TCLK P3 P_GNT V5 P_AD28
F8 GND K3 V
CC
F19 S_AD7 L3 GND P18 P_AD7 W6 V
G17 V
CC
G19 S_AD4 M3 S_CLKOUT5 R11 P_STOP W16 GND
GHK
NO.
H19 S_AD1 N3 S_CLKOUT8 U6 GND
J14 GND N18 GND U12 P_PERR
K6 GPIO0 P9 V
M1 V
SIGNAL NAME
CC
CCP
CC
CC
CCP
CC
CC
GHK
SIGNAL NAME
NO.
N2 V
CC
CC
P1 P_RST U14 P_AD12
P7 V
CC
CC
P11 P_DEVSEL V12 P_LOCK
CC
CC
R7 P_AD25 W12 GND
R9 P_AD18 W14 P_AD14
CC
CC
R18 P_AD8
GHK
SIGNAL NAME
NO.
CC
U5 GND
U9 P_AD19
CC
V8 V
CC
V10 P_AD16
CC
CC
W7 GND
W10 P_AD17
CC
CC
W15 P_AD11
2–6
TERMINAL
PDV
NAME
P_CLK 45 N5 I
P_RST
TERMINAL
NAME
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
GHK
NO.
NO.
43 P1 I
PDV
GHK
NO.
49
50
55
57
58
60
61
63
67
68
70
71
73
74
76
77
93
95
96
98
99
101
107
109
112
113
115
116
118
119
121
122
64
79
92
110
NO.
R2
P5
R6
V5
W5
V6
R7
P8
R8
U8
W8
W9
U9
R9
W10
V10
U13
W14
V14
U14
W15
V15
P15
R18
P18
N15
M14
N17
N19
M15
M18
M19
U7
R10
V13
R19
T able 2–4. Primary PCI System
I/O DESCRIPTION
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI
signals are sampled at rising edge of P_CLK.
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers
in a high–impedance state and reset all internal registers. When asserted, the device is completely
nonfunctional. During P_RST
is in its default state.
, the secondary interface is driven low. After P_RST is deasserted, the bridge
Table 2–5. Primary PCI Address and Data
I/O DESCRIPTION
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, P_AD31–P_AD0 contain a
I/O
32-bit address or other destination information. During the data phase, P_AD31–P_AD0 contain data.
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, P_C/BE3
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte
I/O
paths of the full 32-bit data bus carry meaningful data. P_C/BE0
P_C/BE1
P_C/BE3
applies to byte 1 (P_AD15–P_AD8), P_C/BE2 applies to byte 2 (P_AD23–P_AD16), and
applies to byte 3 (P_AD31–P_AD24).
–P_C/BE0 define the bus command.
applies to byte 0 (P_AD7–P_AD0),
2–7
Table 2–6. Primary PCI Interface Control
TERMINAL
PDV
NAME
P_DEVSEL 84 P11 I/O
P_FRAME
P_GNT
P_IDSEL 65 V7 I
P_IRDY 82 V11 I/O
P_LOCK 87 V12 I/O Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as an initiator.
P_PAR 90 R12 I/O
P_PERR
P_REQ 47 R1 O
P_SERR 89 P12 O
P_STOP 85 R11 I/O
P_TRDY 83 U11 I/O
GHK
NO.
NO.
80 P10 I/O
46 P3 I
88 U12 I/O
I/O DESCRIPTION
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As
a PCI initiator on the primary bus, the bridge monitors P_DEVSEL
responds before time-out occurs, then the bridge terminates the cycle with an initiator abort.
Primary cycle frame. P_FRAME is driven by the initiator of a primary bus cycle. P_FRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When P_FRAME
Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access
to the primary PCI bus after the current data transaction has completed. P_GNT
a primary bus request, depending on the primary bus parking algorithm.
Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.
P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus.
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space
of the bridge can only be accessed from the primary bus.
Primary initiator ready. P_IRDY indicates ability of the primary bus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY
and P_TRDY are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are
inserted.
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the
P_AD and P_C/BE
with a one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the
parity indicator of the initiator; a miscompare can result in a parity error assertion (P_PERR
Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated
parity does not match P_PAR when P_PERR
Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as an
initiator.
Primary system error. Output pulsed from the bridge when enabled through the command register
indicating a system error has occurred. The bridge needs not be the target of the primary PCI cycle
to assert this signal. When bit 6 is enabled in the bridge control register (offset 3Eh, see Section 4.32),
this signal also pulses indicating that a system error has occurred on one of the subordinate buses
downstream from the bridge.
Primary cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current
primary bus transaction. This signal is used for target disconnects and is commonly asserted by target
devices which do not support burst data transfers.
Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current
data phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both
and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are
P_IRDY
inserted.
is deasserted, the primary bus transaction is in the final data phase.
buses. As an initiator during PCI write cycles, the bridge outputs this parity indicator
is enabled through bit 6 of the command register.
until a target responds. If no target
may or may not follow
).
2–8
TERMINAL
PDV
NAME
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
S_CLK
S_CFN 23 J6 I
S_RST 22 J5 O
GHK
NO.
NO.
42
N6
41
N3
39
N1
38
M5
36
M3
35
M2
33
L5
32
L6
30
L2
29
L1
21 J3 I Secondary PCI bus clock input. This input syncronizes the PCI2050 to the secondary bus clocks.
T able 2–7. Secondary PCI System
I/O DESCRIPTION
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each
secondary bus device samples all secondary PCI signals at the rising edge of its corresponding
O
S_CLKOUT input.
Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled.
When the external arbiter is enabled, the PCI2050 S_REQ0
grant input to the bridge and S_GNT0
external arbiter on the secondary bus.
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit
(bit 6) of the bridge control register (offset 3Eh, see Section 4.32). S_RST
respect to the state of the secondary interface CLK signal.
is reconfigured as a secondary bus master request to the
pin is reconfigured as a secondary bus
is asynchronous with
2–9
TERMINAL
PDV
NAME
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
S_DEVSEL 175 A11 I/O
S_FRAME 179 F11 I/O
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
NO.
206
204
203
201
200
198
197
195
192
191
189
188
186
185
183
182
165
164
162
161
159
154
152
150
147
146
144
143
141
140
138
137
194
180
167
149
19
18
17
16
15
14
13
11
10
GHK
NO.
E10
C10
E13
B14
A15
B15
E14
F15
F14
F17
F19
G14
G18
G19
H14
H17
H19
J15
A10
F12
G15
I/O DESCRIPTION
E6
F6
A5
E7
B6
F7
C7
A7
C8
B8
E9
F9
B9
A9
I/O
E8
I/O
J1
H1
H2
H3
H5
G1
G2
H6
F1
O
Table 2–8. Secondary PCI Address and Data
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on
the secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31–S_AD0
contain a 32-bit address or other destination information. During the data phase, S_AD31–S_AD0
contain data.
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a secondary bus PCI cycle, S_C/BE3
command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine
which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0
(S_AD7–S_AD0), S_C/BE1
(S_AD23–S_AD16), and S_C/BE3
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As
a PCI initiator on the secondary bus, the bridge monitors S_DEVSEL
responds before timeout occurs, then the bridge terminates the cycle with an initiator abort.
Secondary cycle frame. S_FRAME is driven by the initiator of a secondary bus cycle. S_FRAME is
asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME
is asserted. When S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used
to grant potential secondary PCI bus masters access to the bus. T en potential initiators (including the
bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, S_GNT0
signal for the bridge.
applies to byte 1 (S_AD15–S_AD8), S_C/BE2 applies to byte 2
applies to byte 3 (S_AD31–S_AD24).
until a target responds. If no target
is reconfigured as an external secondary bus request
–S_C/BE0 define the bus
applies to byte 0
2–10
TERMINAL
PDV
NAME
S_IRDY 177 C11 I/O
S_LOCK 172 C12 I/O
S_PAR 168 C13 I/O
S_PERR
S_REQ8
S_REQ7
S_REQ6
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
S_SERR
S_STOP 173 B12 I/O
S_TRDY 176 B11 I/O
GHK
NO.
NO.
171 E12 I/O
9
G5
8
7
6
5
4
G6
3
2
207
169 B13 I
I/O DESCRIPTION
F2
F3
E1
E2
F5
E3
C5
Table 2–9. Secondary PCI Interface Control
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus initiator to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_PCLKn where
both S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are
inserted.
Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as an
initiator.
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across
the S_AD and S_C/BE
indicator with a one-S_CLK delay . As a target during PCI read cycles, the calculated parity is compared
to the initiator parity indicator. A miscompare can result in a parity error assertion (S_PERR
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that
calculated parity does not match S_PAR when enabled through the command register.
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used
as inputs from secondary PCI bus initiators requesting the bus. Ten potential initiators (including the
bridge) can be located on the secondary PCI bus.
I
When the internal arbiter is disabled, the S_REQ0
grant for the bridge.
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled
through the bridge control register. S_SERR
Secondary cycle stop signal. S_STOP is driven by a PCI target to request the initiator to stop the current
secondary bus transaction. S_STOP
devices that do not support burst data transfers.
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_IRDY
buses. As an initiator during PCI write cycles, the bridge outputs this parity
signal is reconfigures as an external secondary bus
is never asserted by the bridge.
is used for target disconnects and is commonly asserted by target
).
Table 2–10. Miscellaneous Terminals
TERMINAL
PDV
NAME
BPCCE 44 P2 I
GPIO3/HSSWITCH
GPIO2
GPIO1
GPIO0
HSENUM 127 L14 O Hot swap ENUM
HSLED 128 K19 O Hot swap LED output
MS0
MS1
NC
S_M66ENA 153 E18 O
GHK
NO.
NO.
24
25
27
28
155 E17 I Mode select 0
106 R17 I Mode select 1
102
R14
125
L17
I/O DESCRIPTION
Bus/power clock control management terminal. When signal BPCCE is tied high, and when the
PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary bus
in the B2 power state. The PCI2050 disables the secondary clocks and drives them to 0. When
tied low, placing the PCI2050 in the D3 power state has no ef fect on the secondary bus clocks.
K1
K2
K5
K6
General-purpose I/O pins
GPIO3 is HSSWITCH
I
HSSWITCH
NC These terminals have no function on the PCI2050.
Secondary bus 66-MHz enable pin. This pin is always driven low to incicate that the secondary
bus speed is 33 MHz.
in CPCI mode.
provides the status of the ejector handle switch to the CPCI logic.
2–11
Table 2–11. JTAG Interface Terminals
TERMINAL
PDV
NAME
TCLK 133 J19 I JTAG boundary-scan clock. TCLK is the clock controlling the JTAG logic.
TDI 129 K18 I
TDO 130 K17 O
TMS 132 K14 I JTAG test mode select. TMS causes state transitions in the test access port controller.
TRST 134 J18 I
NO.
GHK
NO.
I/O DESCRIPTION
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the
JTAG interface. The new data on TDI is sampled on the rising edge of TCLK.
JTAG serial data out. TDO is the serial output through which test instructions and data from the test
logic leave the PCI2050.
JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter
a reset state and initialize the test logic.
Table 2–12. Power Supply
TERMINAL
NAME PDV NO. GHK NO.
GND
P_V
S_V
V
12, 20, 31, 37, 48, 52, 54,
59, 66, 72, 78, 86, 94, 100,
104, 111, 117, 123, 136,
142, 148, 156, 158, 160,
166, 174, 181, 187, 193,
199, 205
1, 26, 34, 40, 51, 53, 56, 62,
69, 75, 81, 91, 97, 103, 105,
CC
CCP
CCP
108, 114, 120, 131, 139,
145, 151, 157, 163, 170,
178, 184, 190, 196, 202,
208
124 L18
135 J17
A6, A12, A14, B5, B10, C9,
C15, D19, F8, F13, F18,
G3, H15, J2, J14, L3, L19,
M6, N18, P6, P13, P14,
P17, T1, U5, U6, U10, V9,
W7, W12, W16
A4, A8, A13, A16, B7, C6,
C14, D1, E11, E19, F10,
G17, H18, K3, K15, M1,
M17, N2, N14, P7, P9, P19,
R3, R13, T19, U15, V8, W4,
W6, W11, W13
Device ground terminals
Power-supply terminal for core logic (3.3 V)
Primary bus-signaling environment supply. P_V
protection circuitry on primary bus I/O signals.
Secondary bus-signaling environment supply. S_V
protection circuitry on secondary bus I/O signals.
DESCRIPTION
is used in
CCP
CCP
is used in
2–12
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI2050 PCI-to-PCI bridge features and functionality. Figure 3–1
shows a simplified block diagram of a typical system implementation using the PCI2050.
CPU
Host Bus
PCI Bus 0
PCI2050
PCI Bus 1
Host
Bridge
Memory
PCI
Device
PCI Bus 2
PCI2050
PCI Option Slot
PCI
Device
PCI
Device
Figure 3–1. System Block Diagram
PCI
Device
PCI Option Card
PCI Option Card
(Option)
3.1 Introduction to the PCI2050
The PCI2050 is a bridge between two PCI buses and is compliant with both the
PCI-to-PCI Bridge Specification
. The bridge supports two 32-bit PCI buses operating at a maximum of 33 MHz. The
primary and secondary buses operate independently in either a 3.3-V or 5-V signaling environment. The core logic
of the bridge, however, is powered at 3.3 V to reduce power consumption.
Host software interacts with the bridge through internal registers. These internal registers provide the standard PCI
status and control for both the primary and secondary buses. Many vendor-specific features that exist in the TI
extension register set are included in the bridge. The PCI configuration header of the bridge is only accessible from
the primary PCI interface.
The bridge provides internal arbitration for the nine possible secondary bus masters, and provides each with a
dedicated active low request/grant pair (REQ
/GNT). The arbiter features a two-tier rotational scheme with the
PCI2050 bridge defaulting to the highest priority tier.
Upon system power up, power-on self-test (POST) software configures the bridge according to the devices that exist
on subordinate buses, and enables performance-enhancing features of the PCI2050. In a typical system, this is the
only communication with the bridge internal register set.
PCI Local Bus Specification
and the
3–1
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