Texas Instruments PCI2040GGU, PCI2040PGE Datasheet




1999 PCIBus Solutions

Data Manual

Printed in U.S.A.
07/99

SCPS048

PCI2040 PCI-DSP Bridge Controller

Data Manual

Literature Number: SCPS048

July 1999

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.

TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated

iii

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Related Documents 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 PCI2040 Functional Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 PCI Interface 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Accessing Internal PCI2040 Registers 3–2. . . . . . . . . . . . . . . . . . . . . . . . .

3.3 PCI_LOCK

3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Serial ROM Interface 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 PCI2040 Host Port Interface 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Identifying Implemented Ports and DSP Types 3–3. . . . . . . . . .

3.5.2 DSP Chip Selects 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3 HPI Register Access Control 3–4. . . . . . . . . . . . . . . . . . . . . . . . .

3.5.4 Mapping HPI DSP Memory to the Host 3–4. . . . . . . . . . . . . . . .

3.5.5 Read/Write Procedure 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.6 HPI Interface Specific Notes 3–5. . . . . . . . . . . . . . . . . . . . . . . . .

3.6 General-Purpose I/O Interface 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Interrupts 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 Interrupt Event and Interrupt Mask Registers 3–6. . . . . . . . . . .

3.7.2 DSP-to-Host Interrupts 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3 HPI Error Interrupts and HPI Error Reporting 3–7. . . . . . . . . . .

3.7.4 General-Purpose Interrupts 3–7. . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.5 Interrupts Versus PME

3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 PCI2040 Power Management 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 PCI Power Management Register Interface 3–8. . . . . . . . . . . .

3.8.2 PCI Power Management Device States and Transitions 3–8. .

3.9 Compact PCI Hot-Swap 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 General-Purpose Bus 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 Example Transactions on the General-Purpose Bus 3–11. . . . . . . . . . . . .

3.11.1 General-Purpose Bus Word Write 3–11. . . . . . . . . . . . . . . . . . . .

3.11.2 General-Purpose Bus Word Read 3–11. . . . . . . . . . . . . . . . . . . .

4 PCI2040 Programming Model 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 PCI Configuration Registers 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Vendor and Device ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 PCI Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

4.4 PCI Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Revision ID 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Class Code 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Cache Line Size Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Latency Timer Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Header Type Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 BIST Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 HPI CSR Memory Base Address Register 4–7. . . . . . . . . . . . . . . . . . . . . .

4.12 Control Space Base Address Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . .

4.13 GP Bus Base Address Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Subsystem Vendor ID Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 Subsystem ID Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 Capability Pointer Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Interrupt Line Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18 Interrupt Pin Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 MIN_GNT Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.20 MAX_LAT Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.21 GPIO Select Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 GPIO Input Data Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 GPIO Direction Control Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.24 GPIO Output Data Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.25 GPIO Interrupt Event Type Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.26 Miscellaneous Control Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.27 Diagnostic Register 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.28 PM Capability ID Register 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.29 PM Next-Item Pointer Register 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.30 Power Management Capabilities Register 4–17. . . . . . . . . . . . . . . . . . . . . .

4.31 Power Management Control/Status Register 4–18. . . . . . . . . . . . . . . . . . . .

4.32 HPI CSR I/O Base Address Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.33 HS Capability ID Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.34 HS Next-Item Pointer Register 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.35 CPCI Hot Swap Control and Status Register 4–20. . . . . . . . . . . . . . . . . . . .

5 HPI Control and Status Registers (HPI CSR) 5–1. . . . . . . . . . . . . . . . . . . . . . . .

5.1 Interrupt Event Register 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Interrupt Mask Register 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 HPI Error Report Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 HPI Reset Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 HPI DSP Implementation Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 HPI Data Width Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 DSP HPI Overview 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 C54X Host Port Interface 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 Modes of Operation 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2 HPI Functional Description 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.3 HPI Registers 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

6.2 C54X HPI Control Register 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 Auto Increment Feature 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.2 Interrupts 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.3 Four Strobes (HDS1

, HDS2, HR/W, HAS) 6–4. . . . . . . . . . . . . .

6.2.4 Wait States 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.5 Host Read/Write Access to HPI 6–4. . . . . . . . . . . . . . . . . . . . . . .

6.2.6 HPI Memory Access During Reset 6–5. . . . . . . . . . . . . . . . . . . .

6.2.7 Examples of Transactions Targeting the C54X 6–5. . . . . . . . . .

6.2.7.1 PCI Word Write 6–5. . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.7.2 PCI Word Read 6–6. . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.7.3 PCI Double Word Write 6–7. . . . . . . . . . . . . . . . . . .

6.2.7.4 PCI Double Word Read 6–8. . . . . . . . . . . . . . . . . . .

6.3 C6X HPI Interface 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1 No SAM or HOM Modes 6–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.2 Address/Data Bus 6–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.3 Byte Enables (HBE0

and HBE1) 6–9. . . . . . . . . . . . . . . . . . . . . .

6.3.4 Wait States 6–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.5 C6X HPI Registers 6–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.6 Software Handshaking Using HRDY and FETCH 6–11. . . . . . .

6.3.7 Host Access Sequence 6–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.8 Single Half-Word Cycles 6–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.9 Memory Access Through HPI During Reset 6–12. . . . . . . . . . . .

6.3.10 Examples of Transactions Targeting the C6X 6–12. . . . . . . . . . .

7 Electrical Characteristics 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Absolute Maximum Ratings Over Operating Temperature Ranges 7–1.

7.2 Recommended Operating Conditions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Electrical Characteristics Over Recommended Operating Conditions 7–3

8 Mechanical Information 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Illustrations

Figure Title Page

2–1 PCI2040 Pin Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 PCI2040 System Block Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 PCI2040 Serial ROM Data Format 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 PCI2040 Reset Illustration 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 General-Purpose Bus Word Write 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 General-Purpose Bus Word Read 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 C54X Select Input Logic 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Word Write To HPID Without Auto-Increment Enabled 6–6. . . . . . . . . . . . . . .

6–3 Word Write From HPID Without Auto-Increment Enabled 6–7. . . . . . . . . . . .

6–4 Doubleword Write To HPID Without Auto-Increment Enabled 6–8. . . . . . . . .

6–5 Doubleword Read Trom HPID Without Auto-Increment Enabled 6–8. . . . . .

6–6 Double Word Write To HPID Without Auto-Increment Selected 6–13. . . . . . . .

6–7 Double Word Read From HPID Without Auto-Increment Selected 6–13. . . . .

vii

List of Tables

Table Title Page

2–1 Card Signal Names by GGU/PGE Pin Number 2–2. . . . . . . . . . . . . . . . . . . . .

2–2 Card Signal Names Sorted Alphabetically 2–3. . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Power Supply 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 PCI System Terminal Functions 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Miscellaneous Terminal Functions 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Host Port Interface Terminal Functions 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Compact PCI Hot Swap Interface 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 General-Purpose Bus Interface 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 PCI2040 Chip Select Decoding 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 HPI Interface Features 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 PMC Changes for PCI PM 1.1 Register Model 3–8. . . . . . . . . . . . . . . . . . . . . .

3–4 General-Purpose Bus Signals 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 PCI Configuration Registers 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Bit Field Access Tag Descriptions 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 PCI Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 PCI Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 HPI CSR Memory Base Address Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Control Space Base Address Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 General-Purpose Bus Base Address Register 4–9. . . . . . . . . . . . . . . . . . . . . .

4–8 GPIO Select Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 GPIO Input Data Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 GPIO Direction Control Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 GPIO Output Data Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–12 GPIO Interrupt Event Type Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–13 Miscellaneous Control Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–14 Diagnostic Register 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–15 Power Management Capabilities Register 4–17. . . . . . . . . . . . . . . . . . . . . . . . . .

4–16 Power Management Control/Status Register 4–18. . . . . . . . . . . . . . . . . . . . . . .

4–17 HPI CSR I/O Base Address Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–18 CPCI Hot Swap Control and Status Register 4–20. . . . . . . . . . . . . . . . . . . . . . .

5–1 HPI Configuration Register Map 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Interrupt Event Register 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Interrupt Mask Register 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 HPI Error Report Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 HPI Reset Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 HPI DSP Implementation Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 HPI Data Width Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

6–1 C54X HPI Registers Access Control 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 C54X HPI Control Register Description 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 HCNTL0 and HCNTL1 in C6X 6–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 C6X HPI Control Register 6–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–1

1 Introduction

1.1 Description

The TI PCI2040 is a PCI-DSP bridge that provides a glueless connection between the 8-bit host port interface (HPI)
port on the TMS320C54X or the 16-bit HPI port on TMS320C6X to the high performance PCI bus. It provides a PCI
bus target interface compliant with the

PCI Local Bus Specification

.

The PCI2040 provides several external interfaces: the PCI bus interface with compact PCI support, the HPI port
interface with support for up to four DSPs, a serial ROM interface, a general-purpose input/output interface (GPIOs),
and a 16-bit general-purpose bus to provide a glueless interface to TI JT AG test bus controller (TBC). The PCI2040
universal target-only PCI interface is compatible with 3.3-V or 5-V signaling environments.

The PCI2040 interfaces with DSPs via a data bus (HPI port). The PCI2040 also provides a serial ROM interface for
preloading several registers including the subsystem ID and subsystem vendor ID.

The PCI2040, compliant with the latest

PCI Bus Power Management Interface Specification

, provides several
low-power features that reduce power consumption. Furthermore, an advanced CMOS process achieves low system
power consumption.

Unused PCI2040 inputs must be pulled to a valid logic level using a pullup resistor.

1.2 Features

The PCI2040 supports the following features:

• PCI bus target only, supporting both single-word reads and writes

• Write transaction posting for improved PCI bus performance

• Provides glueless interface to host port interface (HPI) port of C54x and/or C6x

• Up to four DSP devices on HPI

• Allows direct access to program and control external devices connected to PCI2040

• Serial ROM interface for loading subsystem ID and subsystem vendor ID

• A 16-bit general-purpose bus (GPB) that provides glueless interface to TI JTAG TBC

• 3.3-V core logic with universal PCI interface compatible with 3.3-V or 5-V signaling environments

• Advanced submicron, low-power CMOS technology

• 144-pin device and choice of surface mount packaging: TQFP or 12 mm x 12 mm MicroStar BGA

• Up to 33 MHz PCI bus frequency

1.3 Related Documents

•

Compact PCI Hot Swap Specification PICMG 2.1

(Revision 1.0)

•

PCI Bus Power Management Interface Specification

(Revision 1.1)

•

PCI Local Bus Specification

(Revision 2.2)

•

PC 98/99

1.4 Ordering Information

ORDERING NUMBER NAME VOLTAGE PACKAGE

PCI2040 PCI-DSP Bridge Controller 3.3 V, 5-V Tolerant I/Os 144-pin LQFP

144-ball PBGA

1–2

2–1

2 Terminal Descriptions

PCI_STOP

PCI_TRDY

PCI_IRDY

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

3738394041424344454647484950515253545556575859606162636465666768697071

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

PCI_AD30

GND
PCI_C/BE3
PCI_IDSEL

GND

GRST

PCI_RST

GND

RSVD

GND

RSVD

RSVD

HRST3

HRDY5x1/HRDY6x1

HRDY5x2/HRDY6x2

GPIO0

GPIO1

GPIO2

GPIO5

GPIO3

GPIO4

RSVD

RSVD

RSVD

RSVD

RSVD

CCP

V

CCH

V

CC

V

PCI_AD31

PCI_AD29
PCI_AD28

CC

V

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

CC

V

PCI_AD23
PCI_AD22

PCI_AD21
PCI_AD20

PCI_PCLK

PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16

CC

V

PCI_C/BE2

PCI_FRAME

PCI_DEVSEL

RSVD

HBE1/GPA1

HBE0/GPA0

HDS/GP_CS

HRST0

HRST1

HRST2

HWIL/GPA2

RSVD

HRDY5x0/HRDY6x0

CC

V

RSVD

RSVD

RSVD

RSVD

RSVD

GP_RST

PME

PCI_AD0

PCI_SERR

PCI_AD13

PCI_AD12

PCI_AD11

GND

PCI_C/BE0

PCI_AD7

HSENUM

CCP

V

PCI_PERR

PCI_C/BE1

PCI_LOCK

CC

V

PCI_PAR

GND

PCI_AD15

PCI_AD14

CC

V

PCI_INTA

GND

PCI_AD10

PCI_AD9

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

CC

V

PCI_AD2

PCI_AD1

RSVD

HSLED

GND

HCNTL1/GPA4

HCNTL0/GPA3

HAD0/GPD0

HAD2/GPD2

HAD3/GPD3

HAD4/GPD4

HAD5/GPD5

HAD6/GPD6

HAD7/GPD7

HAD8/GPD8

HAD10/GPD10

GND

HAD9/GPD9

HAD11/GPD11

HAD12/GPD12

HAD13/GPD13

HAD14/GPD14

HAD15/GPD15

CCH

V

CC

V

GP_INT

GP_RDY

HINT0

HINT1

HINT2

HINT3

HSSWITCH

HR/W/GPA5

HAD1/GPD1

CC

V

GND

HCS0

HCS1

HCS2

HCS3

PCI_AD8

CC

V

HRDY5x3/HRDY6x3

RSVD

Figure 2–1. PCI2040 Pin Diagram

2–2

Table 2–1 shows the card signal names and their terminal assignments sorted alphanumerically by the associated
GGU package terminal number. Table 2–2 shows the card signal names sorted alphabetically by the signal name
and its associated terminal numbers.

T able 2–1. Card Signal Names by GGU/PGE Pin Number

PIN NO.

PIN NO.

PIN NO.

SIGNAL

PIN NO.

SIGNAL

GGU PGE

SIGNAL NAME

GGU PGE

SIGNAL NAME

GGU PGE

SIGNAL

NAME

GGU PGE

SIGNAL

NAME

A1 1 PCI_AD31 C11 106 HR/W/GPA5 G10 92 HAD8/GPD8 L4 42 PCI_C/BE1
A2 143 RSVD C12 105 HCS3 G11 91 V

CCH

L5 46 PCI_AD13
A3 140 RSVD C13 104 HCS2 G12 89 HAD6/GPD6 L6 50 PCI_INTA
A4 137 RSVD D1 8 PCI_AD25 G13 90 HAD7/GPD7 L7 55 V

CCP

A5 133 RSVD D2 7 PCI_AD26 H1 21 PCI_PCLK L8 59 PCI_AD6
A6 129 GPIO4 D3 6 PCI_AD27 H2 22 GND L9 63 GND
A7 126 GPIO2 D4 5 V

CC

H3 23 PCI_AD19 L10 67 V

CC

A8 124 GPIO0 D5 136 RSVD H4 24 PCI_AD18 L11 70 GP_RST
A9 120 HRDY5x1/HRDY6x1 D6 132 RSVD H10 85 HAD3/GPD3 L12 75 GP_RDY

A10 116 HRST2 D7 128 V

CC

H11 86 HAD4/GPD4 L13 76 HINT0
A11 112 HDS/GP_CS D8 121 HRDY5x2/HRDY6x2 H12 87 GND M1 35 RSVD
A12 110 HBE1/GPA1 D9 117 HRST3 H13 88 HAD5/GPD5 M2 36 RSVD
A13 109 HWIL/GPA2 D10 113 V

CC

J1 25 PCI_AD17 M3 39 PCI_PAR
B1 2 PCI_AD30 D11 103 HCS1 J2 26 PCI_AD16 M4 43 GND
B2 144 RSVD D12 102 HCS0 J3 27 V

CC

M5 47 PCI_AD12
B3 141 RSVD D13 101 GND J4 28 PCI_C/BE2 M6 51 GND
B4 138 RSVD E1 12 PCI_IDSEL J10 81 V

CC

M7 53 PCI_AD9
B5 134 RSVD E2 11 PCI_C/BE3 J11 82 HAD0/GPD0 M8 58 PCI_AD7
B6 130 GPIO5 E3 10 GND J12 83 HAD1/GPD1 M9 62 PCI_AD3
B7 125 GPIO1 E4 9 PCI_AD24 J13 84 HAD2/GPD2 M10 66 PCI_AD0
B8 123 V

CCH

E10 100 HAD15/GPD15 K1 29 PCI_FRAME M11 69 RSVD

B9 119 HRDY5x0/HRDY6x0 E11 99 HAD14/GPD14 K2 30 PCI_IRDY M12 72 HSLED

B10 115 HRST1 E12 98 HAD13/GPD13 K3 31 GND M13 74 GP_INT
B11 111 HBE0/GPA0 E13 97 HAD12/GPD12 K4 41 PCI_LOCK N1 37 PCI_PERR
B12 108 HCNTL0/GPA3 F1 16 PCI_AD21 K5 45 PCI_AD14 N2 38 PCI_SERR
B13 107 HCNTL1/GPA4 F2 15 PCI_AD22 K6 49 V

CC

N3 40 V

CC

C1 4 PCI_AD28 F3 14 PCI_AD23 K7 56 PCI_C/BE0 N4 44 PCI_AD15
C2 3 PCI_AD29 F4 13 V

CC

K8 60 PCI_AD5 N5 48 PCI_AD11
C3 142 RSVD F10 96 HAD11/GPD11 K9 64 PCI_AD2 N6 52 PCI_AD10
C4 139 RSVD F11 95 V

CC

K10 77 GND N7 54 PCI_AD8

C5 135 RSVD F12 94 HAD10/GPD10 K11 78 HINT1 N8 57 V

CC

C6 131 RSVD F13 93 HAD9/GPD9 K12 79 HINT2 N9 61 PCI_AD4
C7 127 GPIO3 G1 18 V

CCP

K13 80 HINT3 N10 65 PCI_AD1
C8 122 HRDY5x3/HRDY6x3 G2 17 PCI_AD20 L1 32 PCI_TRDY N11 68 PME
C9 118 GND G3 19 PCI_RST L2 33 PCI_DEVSEL N12 71 HSENUM

C10 114 HRST0 G4 20 GRST L3 34 PCI_STOP N13 73 HSSWITCH

2–3

Table 2–2. Card Signal Names Sorted Alphabetically

PIN NO.

PIN NO.

PIN NO.

PIN NO.

SIGNAL NAME

GGU PGE

SIGNAL NAME

GGU PGE

SIGNAL NAME

GGU PGE

SIGNAL NAME

GGU PGE

GRST G4 20 HBE0/GPA0 B11 111 PCI_AD10 N6 52 PCI_SERR N2 38
GND E3 10 HBE1/GPA1 A12 110 PCI_AD11 N5 48 PCI_STOP L3 34
GND H2 22 HCNTL0/GPA3 B12 108 PCI_AD12 M5 47 PCI_TRDY L1 32
GND K3 31 HCNTL1/GPA4 B13 107 PCI_AD13 L5 46 PME N11 68
GND M4 43 HCS0 D12 102 PCI_AD14 K5 45 RSVD M1 35
GND M6 51 HCS1 D11 103 PCI_AD15 N4 44 RSVD M2 36
GND L9 63 HCS2 C13 104 PCI_AD16 J2 26 RSVD M11 69
GND K10 77 HCS3 C12 105 PCI_AD17 J1 25 RSVD C6 131
GND H12 87 HDS/GP_CS A11 112 PCI_AD18 H4 24 RSVD D6 132
GND D13 101 HINT0 L13 76 PCI_AD19 H3 23 RSVD A5 133
GND C9 118 HINT1 K11 78 PCI_AD20 G2 17 RSVD B5 134
GP_INT M13 74 HINT2 K12 79 PCI_AD21 F1 16 RSVD C5 135
GP_RDY L12 75 HINT3 K13 80 PCI_AD22 F2 15 RSVD D5 136
GP_RST L11 70 HR/W/GPA5 C11 106 PCI_AD23 F3 14 RSVD A4 137
GPIO0 A8 124 HRDY5x0/HRDY6x0 B9 119 PCI_AD24 E4 9 RSVD B4 138
GPIO1 B7 125 HRDY5x1/HRDY6x1 A9 120 PCI_AD25 D1 8 RSVD C4 139
GPIO2 A7 126 HRDY5x2/HRDY6x2 D8 121 PCI_AD26 D2 7 RSVD A3 140
GPIO3 C7 127 HRDY5x3/HRDY6x3 C8 122 PCI_AD27 D3 6 RSVD B3 141
GPIO4 A6 129 HRST0 C10 114 PCI_AD28 C1 4 RSVD C3 142
GPIO5 B6 130 HRST1 B10 115 PCI_AD29 C2 3 RSVD A2 143
HAD0/GPD0 J11 82 HRST2 A10 116 PCI_AD30 B1 2 RSVD B2 144
HAD1/GPD1 J12 83 HRST3 D9 117 PCI_AD31 A1 1 V

CC

D4 5

HAD2/GPD2 J13 84 HSENUM N12 71 PCI_C/BE0 K7 56 V

CC

F4 13

HAD3/GPD3 H10 85 HSLED M12 72 PCI_C/BE1 L4 42 V

CC

J3 27

HAD4/GPD4 H11 86 HSSWITCH N13 73 PCI_C/BE2 J4 28 V

CC

N3 40

HAD5/GPD5 H13 88 HWIL/GPA2 A13 109 PCI_C/BE3 E2 11 V

CC

K6 49

HAD6/GPD6 G12 89 PCI_AD0 M10 66 PCI_DEVSEL L2 33 V

CC

N8 57

HAD7/GPD7 G13 90 PCI_AD1 N10 65 PCI_FRAME K1 29 V

CC

L10 67

HAD8/GPD8 G10 92 PCI_AD2 K9 64 PCI_IDSEL E1 12 V

CC

J10 81

HAD9/GPD9 F13 93 PCI_AD3 M9 62 PCI_INTA L6 50 V

CC

F11 95

HAD10/GPD10 F12 94 PCI_AD4 N9 61 PCI_IRDY K2 30 V

CC

D10 113

HAD11/GPD11 F10 96 PCI_AD5 K8 60 PCI_LOCK K4 41 V

CC

D7 128

HAD12/GPD12 E13 97 PCI_AD6 L8 59 PCI_PAR M3 39 V

CCH

G11 91

HAD13/GPD13 E12 98 PCI_AD7 M8 58 PCI_PCLK H1 21 V

CCH

B8 123

HAD14/GPD14 E11 99 PCI_AD8 N7 54 PCI_PERR N1 37 V

CCP

G1 18

HAD15/GPD15 E10 100 PCI_AD9 M7 53 PCI_RST G3 19 V

CCP

L7 55

2–4

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.

Table 2–3. Power Supply

TERMINAL

NO.

DESCRIPTION

NAME

PGE GGU

DESCRIPTION

GND

10, 22, 31, 43,
51, 63, 77, 87,

101, 118

C9, D13, E3,
H2, H12, K3,
K10, L9, M4,

M6

Device ground terminals

V

CC

5, 13, 27, 40,

49, 57, 67, 81,

95, 113, 128

D4, D7, D10,

F4, F11, J3,

J10, K6, L10,

N3, N8

Power supply terminal for core logic (3.3 V)

V

CCH

91, 123 G11, B8

HPI interface signaling voltage. The V

CCH

input indicates the signaling level for the HPI interface

and is nominally either 3.3 V or 5 V.

V

CCP

18, 55 G1, L7

PCI interface signaling voltage. The V

CCP

input indicates the signaling level for the PCI interface

and is nominally either 3.3 V or 5 V.

2–5

Table 2–4. PCI System Terminal Functions

TERMINAL

NO.

I/O DESCRIPTION

NAME

PGE GGU

I/O

DESCRIPTION

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10

PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

1
2
3
4
6
7
8

9
14
15
16
17
23
24
25
26
44
45
46
47
48
52
53
54
58
59
60
61
62
64
65
66

A1
B1
C2
C1
D3
D2
D1
E4
F3
F2
F1

G2

H3
H4
J1
J2
N4
K5
L5

M5

N5
N6

M7

N7

M8

L8
K8
N9

M9

K9

N10

M10

I/O 32-bit multiplexed address/data bus

PCI_C/BE3
PCI_C/BE2
PCI_C/BE1
PCI_C/BE0

11
28
42
56

E2
J4
L4
K7

I PCI command and byte enable

PCI_PCLK 21 H1 I PCI clock. Provides timing for all PCI transactions with a maximum frequency of 33 MHz.

PCI_DEVSEL 33 L2 O Device select

PCI_FRAME 29 K1 I PCI cycle frame

PCI_IDSEL 12 E1 I Initialization and device select

PCI_INTA 50 L6 O Interrupt A. INTA indicates to the host that PCI2040 requires attention.

PCI_IRDY 30 K2 I Initiator ready

PCI_LOCK 41 K4 I PCI lock

PCI_PAR 39 M3 I/O PCI parity

PCI_PERR 37 N1 I/O Parity error

PCI_RST 19 G3 I PCI reset. Assertion forces PCI2040 non-PME context to a predetermined state.

PCI_SERR 38 N2 O System error

PCI_STOP 34 L3 O PCI stop

PCI_TRDY 32 L1 O Target ready

2–6

Table 2–5. Miscellaneous Terminal Functions

TERMINAL

NO.

I/O DESCRIPTION

NAME

PGE GGU

I/O

DESCRIPTION

GRST 20 G4 I

Global reset. This is a power-on reset to PCI2040 that indicates that a power has been applied to
the VCC terminals. GRST

resets all register bits in PCI2040.

PME

68 N11 O

Power management event. This output indicates PCI power management wake-up events to the
host, and requires open-drain, fail-safe signaling per the

PCI Bus Power Management Interface

Specification

.

GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0

130
129
127
126
125
124

B6
A6

C7

A7
B7
A8

I/O

General-purpose inputs/output. With some exceptions, these terminals provide basic general­purpose input and output functionality programmable through the PCI2040.

The GPIO3 and GPIO2 inputs may be programmed to generate generic interrupt events. See
Section 3.7.4,

General-Purpose Interrupts

, for details.

GPIO0 is sampled on GRST

to determine if a serial ROM is implemented. If GPIO0 is sampled high

on GRST

assertions, then the serial ROM clock (SCL) is routed to the GPIO0 terminal and the serial

ROM data line (SDA) is routed to the GPIO1 terminal.
GPIO4. GP write strobe. This active low signal is used to indicate a read from a device on the bus.

The data on the bus is valid on the rising edge of WR

.

GPIO5. GP read strobe. This active low signal is used to indicate a write to a device on the bus. The
data on the bus is valid on the rising edge of RD

.

RSVD

35, 36,

69,

131–144

A2–A5,

B2–B5,
C3–C6,
D5, D6,
M1, M2,

M11

NC Reserved. These terminals are not connected in PCI2040 implementations.

2–7

Table 2–6. Host Port Interface Terminal Functions

TERMINAL

NO.

I/O DESCRIPTION

NAME

PGE GGU

I/O

DESCRIPTION

HAD15
HAD14
HAD13
HAD12
HAD11
HAD10

HAD9
HAD8
HAD7
HAD6
HAD5
HAD4
HAD3
HAD2
HAD1
HAD0

100

99
98
97
96
94
93
92
90
89
88
86
85
84
83
82

E10
E11
E12
E13
F10
F12
F13
G10
G13
G12
H13
H11
H10

J13
J12
J11

I/O

Data. A 16-bit parallel, bidirectional, and 3-state data bus used to access registers on external
devices controlled by PCI2040. HAD15 is MSB and HAD0 is LSB.

HR/W/GPA5

106 C11 O

Read/Write. The PCI2040 drives this signal to 0 on a host port interface for a write and to 1
on a host port interface for a read.

HDS/GP_CS

112 A11 O

Read strobe/data strobe. Active low signal that controls the transfer of data during an HPI
cycle, and indicates to the DSP that the data on HAD15–HAD0 is valid. This signal must be
connected to HDS1 or HDS2 on the DSP. Unused DSP HDSx inputs must be tied high.

HINT3
HINT2
HINT1
HINT0

80
79
78
76

K13
K12
K11

L13

I

HPI Interrupts. These four interrupts from the DSPs are connected point-to-point between
PCI2040 and each implemented DSP. The PCI2040 may be programmed to assert a PCI
interrupt when the DSPs assert any HINT3

–HINT0. From the DSP perspective, these signals
are controlled by the HINT bit in the HPI control register and are driven high when the DSPs
are being reset (and placed in high impedance when EMU1/OFF

is asserted).

HBE1/GPA1
HBE0

/GPA0

110
111

A12
B11

O

Byte enables. These active low signals are only used when communicating with the C6x DSP .
They indicate which bytes of the data bus are valid when writing to the C6x HPI data register
and are not meaningful in any other conditions.

HWIL/GPA2 109 A13 O

Half-word identification select. Identifies first or second half-word of transfer. HWIL is low for
the first half-word and high for the second half-word. This is not to be confused with the BOB
bit in the DSP HPI control register which controls MSB/LSB from the DSP perspective.

HCNTL1/GPA4
HCNTL0/GPA3

107
108

B13
B12

O

Control signals for DSP access mode. Selects an access to DSP HPI address register, HPI
control register, or HPI data register (and controls auto-increment). The HCNTL1 and HCNTL0
combinations are different for C54x and C6x DSPs.

HCS3
HCS2
HCS1
HCS0

105
104
103
102

C12
C13
D11
D12

O

Chip selects. These four chip selects to the DSPs are connected point-to-point between
PCI2040 and each implemented DSP. The input to the DSP serves as an enable input for the
HPI and must be low during an access and may stay low between accesses.

HRDY5x3/HRDY6x3
HRDY5x2/HRDY6x2
HRDY5x1/HRDY6x1
HRDY5x0/HRDY6x0

122
121
120
119

C8
D8
A9
B9

I

Host ready signals. These ready signals from the DSPs are connected point-to-point between
PCI2040 and each implemented DSP. This ready signal is active high for C54x DSPs and
active low for C6x DSPs. When asserted, it indicates that the DSP is ready for a transfer to
be performed, and is deasserted when the DSP is busy completing the internal portion of the
previous transaction. HCS

enables HRDY for the DSP; that is, HRDY is always asserted when
the chip selects are deasserted. The DSP places this ready signal in high impedance when
EMU1/OFF

is active (low).

HRST3
HRST2
HRST1
HRST0

117
116
115
114

D9
A10
B10
C10

O

Host-to-DSP resets. These active low reset signals to the DSPs are connected point-to-point
between PCI2040 and each implemented DSP. The PCI2040 resets the DSPs when GRST
is asserted. It is software’s responsibility to deassert HRSTn.

2–8

Table 2–7. Compact PCI Hot Swap Interface

TERMINAL

NO.

I/O DESCRIPTION

NAME

PGE GGU

I/O

DESCRIPTION

HSENUM

71 N12 O

Hot swap ENUM. This is an active low open drain signaling output that is asserted when either bit 7 (INS)
or bit 6 (EXT) are set and bit 1 (EIM) is cleared in the CPCI hot swap control and status register (see
Section 4.35). This output indicates to the system that an insertion event occurred or that a removal event
is about to occur.

HSLED

72 M12 O

Hot swap LED. This output is controlled via bit 3 (LOO) in the CPCI hot swap control and status register
(see Section 4.35) and is provided to indicate when a hot-swap device is about to be removed. When
PCI_RST

is asserted to PCI2040, it drives this LED output until the serial ROM has completed preload

and the ejector switch has been closed indicated by the HSSWITCH input.

HSSWITCH

73 N13 I

Hot swap handle switch. This input provides status of the ejector handle state and is used in the bit 7 (INS)
and bit 6 (EXT) logic in the CPCI hot swap control and status register (see Section 4.35). The status of
HSSWITCH is not directly read via CPCI hot swap control and status register but can be read through bit 8
(HSSWITCH_STS) in the miscellaneous control register (see Section 4.26).

Table 2–8. General-Purpose Bus Interface

TERMINAL

NO.

I/O DESCRIPTION

NAME

PGE GGU

I/O

DESCRIPTION

GPD15
GPD14
GPD13
GPD12
GPD11
GPD10

GPD9
GPD8
GPD7
GPD6
GPD5
GPD4
GPD3
GPD2
GPD1
GPD0

100

99
98
97
96
94
93
92
90
89
88
86
85
84
83
82

E10
E11
E12
E13
F10
F12

F13
G10
G13
G12
H13
H11
H10

J13

J12

J11

I/O GP data bus. 16-bit data bus.

GPA5
GPA4
GPA3
GPA2
GPA1
GPA0

106
107
108
109
110
111

C11
B13
B12
A13
A12

B11

I/O GP address lines. 6-bit address bus.

GP_CS 112 A11 O GP chip select
GP_INT 74 M13 I/O GP interrupt. Interrupt from a device on the GP bus.
GP_RD 130 B6 I/O GP read.

GP_RDY 75 L12 I/O

GP ready. Whenever the device on the GP bus is ready to accept a read or write from PCI2040, GP_RDY
is asserted. GP_RDY is deasserted when the device is in recovery from a read or write operation.

GP_RST 70 L11 O GP reset. An active low output that will follow the state of GRST.

GP_WR 129 A6 I/O GP write.

3–1

3 PCI2040 Functional Description

This section covers the functional description for PCI2040. The PCI2040 provides a 32-bit PCI host interface and an
interface for 8-bit and 16-bit host port interface (HPI) ports for TI’s C54x and C6x families of DSP processors. The
following conventions are used in this document:

• DSP C54x or C6x

• Word 16 bits for PCI, 16 bits for C54x, 32 bits for C6x

• Half-word 8 bits for C54x, 16 bits for C6x

• Double-word 32 bits for PCI

Figure 3–1 shows a simplified block diagram of the PCI2040.

PCI Host Bus Interface

Miscellaneous

Interface

CPCI Hot-Swap

PCI Power

Management

Serial ROM

GPIO

Interrupt

PCI

Target

SM

HPI

Interface

Registers

&

PCI

Registers

C6x

Host

Port

Extensions

C54x
Host

Port

SM

HPI Interface

GP BUS

Interface

Figure 3–1. PCI2040 System Block Diagram

3.1 PCI Interface

PCI2040 provides an integrated 32-bit PCI bus interface compliant with the

PCI Local Bus Specification

. The PCI2040
incorporates a PCI target interface for configuration cycles, accesses to internal registers, and access to the HPI
interface via memory-mapped space. The PCI2040 does not provide PCI mastering.

As a PCI bus target, PCI2040 incorporates the following features:

• Supports the memory read, memory write, configuration read, and configuration write

• Aliases the memory read multiple, memory read line, and memory write and invalidate to the basic

memory commands (i.e., memory read and memory write)

• Supports PCI_LOCK

3–2

3.2 Accessing Internal PCI2040 Registers

PCI configuration space is accessed via PCI configuration read and PCI configuration write cycles. These registers
may be accessed using byte, word, or double-word transfers.

The PCI2040 provides a set of registers specifically for interfacing with the HPI port. These registers are called the
HPI control and status registers (HPI CSRs) (see Section 5), and they may be memory- and I/O-mapped. The HPI
CSR memory base address register (see Section 4.11) provides the mechanism for mapping the HPI CSRs into
memory space. When mapped into memory space, the HPI CSRs may be accessed using bytes, words, or
double-word transfers. Memory mapping the HPI CSR registers is recommended.

The HPI control and status registers may also be mapped into I/O space via the HPI CSR I/O base address register
(see Section 4.32). When this register is programmed to a nonzero value, PCI2040 maps the HPI CSRs into I/O
space, and the index/data access scheme is used to access the registers using byte transfers.

The HPI CSR I/O base address register identifies the I/O address of the index port. I/O address index + 1 is the data
port. To access a HPI CSR register, software writes the of fset of the HPI CSR register into the index port. I/O reads
from the data port provide the contents of the indexed register and writes to the data port result in PCI2040 updating
the indexed register.

3.3 PCI_LOCK

PCI2040 supports exclusive access via the LOCK protocol defined by PCI and the PCI_LOCK terminal. As a PCI
target, PCI2040 locks all DSP access and internal resources to a particular master when PCI_LOCK

is sampled
deasserted during the address phase of a PCI cycle that it claims. Once LOCK is established, the PCI2040 remains
locked until both FRAME and LOCK are sampled deasserted or bit 30 (HPIError) is set in the interrupt event register
(see Section 5.1).

The master that owns the exclusive access lock on PCI2040 drives PCI_LOCK while the lock is established and
deasserts PCI_LOCK (and asserts FRAME) when addressing the PCI2040. The PCI2040 claims and retries cycles
addressed to it when PCI_LOCK

is asserted. Other masters will not be able to force the PCI_LOCK signal high when

addressing a locked PCI2040 and will be retried.
Note that when the PCI2040 is not locked, it can claim and complete data transfers even if PCI_LOCK is sampled

asserted in the address phase.

3.4 Serial ROM Interface

The PCI2040 provides a two-wire serial ROM interface that may be used to preload PCI2040 registers following a
power-on reset (GRST

). The serial ROM interface includes a serial clock (SCL) output and a serial data (SDA)
input/output. The SCL signal maps to the GPIO0 terminal and the SDA signal maps to the GPIO1 terminal. The
two-wire serial ROM interface is enabled by pulling up both GPIO0 and GPIO1 terminals to VCC with resistors. The
PCI2040 will only sense GPIO0 on GRST to identify the serial ROM; thus, only GPIO0 must be tied low to disable
the serial ROM interface.

The registers that may be preloaded are given in the following list, and only write accessible bits in these registers
may be preloaded. Figure 3–2 illustrates the PCI2040 serial ROM data format.

• Class code register : SubClass – SubClass

• Class code register : BaseClass – BaseClass

• Subsystem vendor ID register – SubSys Byte 0 & SubSys Byte 1

• Subsystem ID register – SubSys Byte 2 & SubSys Byte 3

• GPIO select register – GPIO select register

• Miscellaneous control register – Misc Ctrl Byte 0 & Misc Ctrl Byte 1

3–3

• Diagnostic register – Diagnostic

• HPI DSP implementation register – HPI_Imp Byte 0

• HPI data width register – HPI_DW Byte 0

SubClass

BaseClass
SubSys Byte 0
SubSys Byte 1
SubSys Byte 2
SubSys Byte 3

GPIO Select

RSVD

RSVD
Misc Ctrl Byte 0
Misc Ctrl Byte 1

Diagnostic

HPI_Imp Byte 0

RSVD

HPI_DW Byte 0

RSVD

Word Address 0
Word Address 1
Word Address 2
Word Address 3
Word Address 4
Word Address 5
Word Address 6
Word Address 7
Word Address 8
Word Address 9
Word Address 10
Word Address 11
Word Address 12
Word Address 13
Word Address 14
Word Address 15

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

RSVD_DIAG

Word Address 16 (10h)
Word Address 17
Word Address 18
Word Address 19
Word Address 20
Word Address 21
Word Address 22
Word Address 23
Word Address 24
Word Address 25
Word Address 26
Word Address 27
Word Address 28
Word Address 29
Word Address 30
Word Address 31

...AVAIL...

Figure 3–2. PCI2040 Serial ROM Data Format

When PCI2040 accesses an implemented serial ROM, it always addresses the serial ROM at slave address
8’b10100000. The serial ROM data format described above utilizes 32 bytes of address space, some of which are
reserved for future generations of the PCI2040. A byte at address 31 is reserved for diagnostic software purposes
and will not be allocated to future generations of the PCI2040. Serial ROM addresses above word address 31 are
available for use by PCI2040 applications. If the data at word address 0 is FFh, then the PCI2040 will stop reading
from the serial ROM. This feature prevents the uninitialized data from being loaded into the PCI2040’s registers.

3.5 PCI2040 Host Port Interface

The PCI2040 HPI interface is used to access TI’s TMS320C54X or TMS320C6X DSP chips. The devices connected
to the HPI interface are memory-mapped in host memory. The host system processor accesses the HPI interface
via slave accesses to PCI2040. The DSP devices can generate interrupts, and the PCI2040 passes these interrupt
requests to the PCI bus via INTA

. See Section 3.7,

Interrupts

, for more information on PCI2040 interrupts.

The HPI port on DSP devices is a parallel port that allows access to the DSP’s memory space and internal registers.
The PCI2040 has to configure the HPI interface on the DSP by accessing the DSP’s HPI control register (HPIC). Other
DSP HPI registers include the HPI data register (HPID) and the HPI address register (HPIA). See Section 6,

DSP

HPI Overview

for more information on DSP registers.

3.5.1 Identifying Implemented Ports and DSP Types

The PCI2040 supports up to four DSPs of both the C54x and C6x types. It may be useful for generic software to
discover what number and type of DSPs are connected to the PCI2040. This is accomplished by using the HPI DSP
implementation register (see Section 5.5) and HPI data width register (see Section 5.6) in the HPI control and status
register space. The HPI DSP implementation register identifies how many DSPs are implemented and what HCSn
outputs are connected, and the HPI data width register identifies whether the HPI port per connected DSP is 8 bits
(C54x) or 16 bits (C6x).

3–4

The HPI DSP implementation register and HPI data width register may be loaded from a serial ROM. Also, these
registers are implemented as read/write so intelligent software can load them with the proper values.

3.5.2 DSP Chip Selects

The PCI2040 provides four chip select outputs (HCS3–HCS0) that uniquely select each HPI port DSP (or other HPI
peripheral) per transaction. This section describes how software encodes the chip select in the PCI address to access
a particular DSP interfacing with PCI2040.

The PCI2040’s control space base address register (see Section 4.12) is a standard PCI base address register
requesting 32K bytes of control space nonprefetchable memory to access up to four DSPs. The PCI2040 claims PCI
memory access transactions that fall within the 32-Kbyte memory window by comparing the upper 17 bits of the PCI
address (PCI_AD31–PCI_AD15) to bits 31–15 (A V AIL_ADD field) in the control space base address register . When
a cycle is claimed, the chip select is determined by decoding bits 14 and 13 of the PCI address. PCI_AD14 and
PCI_AD13 determine the chip select according to Table 3–1.

Only when the PCI cycle is claimed (by decoding PCI_AD31–PCI_AD15) is the chip select asserted.

Table 3–1. PCI2040 Chip Select Decoding

PCI_AD(14–13) CHIP SELECT ASSERTED

2’b00 HCS0
2’b01 HCS1
2’b10 HCS2
2’b11 HCS3

3.5.3 HPI Register Access Control

The HCNTL1 and HCNTL0 terminals are driven by the PCI2040 to select the DSP HPI register and access mode
on a cycle-by-cycle basis. The PCI2040 determines the type of DSP register access from the PCI address, similarly
to the chip select decode as described in Section 3.5.2,

DSP Chip Selects

.

When a cycle is claimed by decoding PCI_AD31–PCI_AD15, the HCNTL1 and HCNTL0 control signals are
determined by decoding bits 12 and 11 of PCI address. PCI_AD12 maps to HCNTL1 and PCI_AD11 maps to
HCNTL0, and the selected HCNTL1 and HCNTL0 are driven to the HPI interface when the cycle is forwarded.

Table 6–1 and Table 6–3 provides more information on the usage of HCNTL1 and HCNTL0 for both C54x and C6x
DSPs.

3.5.4 Mapping HPI DSP Memory to the Host

The PCI address bits PCI_AD10–PCI_AD0 are not forwarded to the HPI interface, and these address bits are not
decoded by PCI2040 for any purpose. This 2-Kbyte of addressable space per DSP (and control) allows the host to
directly map 2K bytes of host memory to the HPI interface for each DSP. This allows for fast memory block copies
rather than an I/O port mechanism.

The PCI2040 does not automatically generate accesses to the HPI address registers based upon
PCI_AD10–PCI_AD0, and it is left to software to synchronize the HPI address register with copies to and from HPI
memory space.

3.5.5 Read/Write Procedure

The following procedure illustrates how to read and write HPI space, and covers some of the initialization that must
be done to successfully transfer data to and from DSP memory via the HPI data register.

After a power-on reset (GRST):

• PCI2040 preloads several registers if a serial ROM is implemented, and this rewrites the HPI
implementation and HPI data width registers (software can also rewrite these registers).