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The TI PCI2040 is a PCI-DSP bridge that provides a glueless connection between the 8-bit host port interface (HPI)
port on the TMS320C54X or the 16-bit HPI port on TMS320C6X to the high performance PCI bus. It provides a PCI
bus target interface compliant with the PCI Local Bus Specification.
The PCI2040 provides several external interfaces: the PCI bus interface with compact PCI support, the HPI port
interface with support for up to four DSPs, a serial ROM interface, a general-purpose input/output interface (GPIOs),
and a 16-bit general-purpose bus to provide a glueless interface to TI JTAG test bus controller (TBC). The PCI2040
universal target-only PCI interface is compatible with 3.3-V or 5-V signaling environments.
The PCI2040 interfaces with DSPs via a data bus (HPI port). The PCI2040 also provides a serial ROM interface for
preloading several registers including the subsystem ID and subsystem vendor ID.
The PCI2040, compliant with the latest PCI Bus Power Management Interface Specification, provides several
low-power features that reduce power consumption. Furthermore, an advanced CMOS process achieves low system
power consumption.
Unused PCI2040 inputs must be pulled to a valid logic level using a pullup resistor.
1.2Features
The PCI2040 supports the following features:
•PCI bus target only, supporting both single-word reads and writes
•Write transaction posting for improved PCI bus performance
•Provides glueless interface to host port interface (HPI) port of C54x and/or C6x
•Up to four DSP devices on HPI
•Allows direct access to program and control external devices connected to PCI2040
•Serial ROM interface for loading subsystem ID and subsystem vendor ID
•A 16-bit general-purpose bus (GPB) that provides glueless interface to TI JTAG TBC
•3.3-V core logic with universal PCI interface compatible with 3.3-V or 5-V signaling environments
•Advanced submicron, low-power CMOS technology
•144-pin device and choice of surface mount packaging: TQFP or 12 mm x 12 mm MicroStar BGA
•Up to 33 MHz PCI bus frequency
1.3Related Documents
•Compact PCI Hot Swap Specification PICMG 2.1 (Revision 1.0)
•PCI Bus Power Management Interface Specification (Revision 1.1)
Global reset. This is a power-on reset to PCI2040 that indicates that a power has been applied to
the VCC terminals. GRST
Power management event. This output indicates PCI power management wake-up events to the
host, and requires open-drain, fail-safe signaling per the PCI Bus Power Management InterfaceSpecification.
General-purpose inputs/output. With some exceptions, these terminals provide basic generalpurpose input and output functionality programmable through the PCI2040.
The GPIO3 and GPIO2 inputs may be programmed to generate generic interrupt events. See
Section 3.7.4, General-Purpose Interrupts, for details.
GPIO0 is sampled on GRST
I/O
on GRST
ROM data line (SDA) is routed to the GPIO1 terminal.
GPIO4. GP write strobe. This active low signal is used to indicate a read from a device on the bus.
The data on the bus is valid on the rising edge of WR
GPIO5. GP read strobe. This active low signal is used to indicate a write to a device on the bus. The
data on the bus is valid on the rising edge of RD
NCReserved. These terminals are not connected in PCI2040 implementations.
assertions, then the serial ROM clock (SCL) is routed to the GPIO0 terminal and the serial
resets all register bits in PCI2040.
to determine if a serial ROM is implemented. If GPIO0 is sampled high
Data. A 16-bit parallel, bidirectional, and 3-state data bus used to access registers on external
I/O
devices controlled by PCI2040. HAD15 is MSB and HAD0 is LSB.
Read/Write. The PCI2040 drives this signal to 0 on a host port interface for a write and to 1
on a host port interface for a read.
Read strobe/data strobe. Active low signal that controls the transfer of data during an HPI
cycle, and indicates to the DSP that the data on HAD15−HAD0 is valid. This signal must be
connected to HDS1 or HDS2 on the DSP. Unused DSP HDSx inputs must be tied high.
HPI Interrupts. These four interrupts from the DSPs are connected point-to-point between
PCI2040 and each implemented DSP. The PCI2040 may be programmed to assert a PCI
interrupt when the DSPs assert any HINT3−HINT0. From the DSP perspective, these signals
I
are controlled by the HINT bit in the HPI control register and are driven high when the DSPs
are being reset (and placed in high impedance when EMU1/OFF
Byte enables. These active low signals are only used when communicating with the C6x DSP.
They indicate which bytes of the data bus are valid when writing to the C6x HPI data register
O
and are not meaningful in any other conditions.
Half-word identification select. Identifies first or second half-word of transfer. HWIL is low for
the first half-word and high for the second half-word. This is not to be confused with the BOB
bit in the DSP HPI control register which controls MSB/LSB from the DSP perspective.
Control signals for DSP access mode. Selects an access to DSP HPI address register, HPI
control register, or HPI data register (and controls auto-increment). The HCNTL1 and HCNTL0
O
combinations are different for C54x and C6x DSPs.
Chip selects. These four chip selects to the DSPs are connected point-to-point between
PCI2040 and each implemented DSP. The input to the DSP serves as an enable input for the
O
HPI and must be low during an access and may stay low between accesses.
Host ready signals. These ready signals from the DSPs are connected point-to-point between
C8
D8
A9
B9
D9
PCI2040 and each implemented DSP. This ready signal is active high for C54x DSPs and
active low for C6x DSPs. When asserted, it indicates that the DSP is ready for a transfer to
be performed, and is deasserted when the DSP is busy completing the internal portion of the
I
previous transaction. HCS
the chip selects are deasserted. The DSP places this ready signal in high impedance when
EMU1/OFF
Host-to-DSP resets. These active low reset signals to the DSPs are connected point-to-point
between PCI2040 and each implemented DSP. The PCI2040 resets the DSPs when GRST
O
is asserted. It is software’s responsibility to deassert HRSTn.
is active (low).
enables HRDY for the DSP; that is, HRDY is always asserted when
is asserted).
2−7
Table 2−7. Compact PCI Hot Swap Interface
NAME
I/O
DESCRIPTION
NAME
I/O
DESCRIPTION
TERMINAL
HSENUM
HSLED
HSSWITCH
NO.
PGE GGU
71N12O
72M12O
73N13I
I/ODESCRIPTION
Hot swap ENUM. This is an active low open drain signaling output that is asserted when either bit 7 (INS)
or bit 6 (EXT) are set and bit 1 (EIM) is cleared in the CPCI hot swap control and status register (see
Section 4.35). This output indicates to the system that an insertion event occurred or that a removal event
is about to occur.
Hot swap LED. This output is controlled via bit 3 (LOO) in the CPCI hot swap control and status register
(see Section 4.35) and is provided to indicate when a hot-swap device is about to be removed. When
PCI_RST
and the ejector switch has been closed indicated by the HSSWITCH input.
Hot swap handle switch. This input provides status of the ejector handle state and is used in the bit 7 (INS)
and bit 6 (EXT) logic in the CPCI hot swap control and status register (see Section 4.35). The status of
HSSWITCH is not directly read via CPCI hot swap control and status register but can be read through bit 8
(HSSWITCH_STS) in the miscellaneous control register (see Section 4.26).
is asserted to PCI2040, it drives this LED output until the serial ROM has completed preload
Table 2−8. General-Purpose Bus Interface
TERMINAL
NO.
PGE GGU
GPD15
GPD14
GPD13
GPD12
GPD11
GPD10
GPD9
GPD8
GPD7
GPD6
GPD5
GPD4
GPD3
GPD2
GPD1
GPD0
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
GP_CS112A11OGP chip select
GP_INT74M13I/OGP interrupt. Interrupt from a device on the GP bus.
GP_RD130B6I/OGP read.
GP_RDY75L12I/O
GP_RST70L11OGP reset. An active low output that will follow the state of GRST.
GP_WR129A6I/OGP write.
100
99
98
97
96
94
93
92
90
89
88
86
85
84
83
82
106
107
108
109
110
111
I/ODESCRIPTION
E10
E11
E12
E13
F10
F12
F13
G10
I/OGP data bus. 16-bit data bus.
G13
G12
H13
H11
H10
J13
J12
J11
C11
B13
B12
I/OGP address lines. 6-bit address bus.
A13
A12
B11
GP ready. Whenever the device on the GP bus is ready to accept a read or write from PCI2040, GP_RDY
is asserted. GP_RDY is deasserted when the device is in recovery from a read or write operation.
2−8
3 PCI2040 Functional Description
This section covers the functional description for PCI2040. The PCI2040 provides a 32-bit PCI host interface and an
interface for 8-bit and 16-bit host port interface (HPI) ports for TI’s C54x and C6x families of DSP processors. The
following conventions are used in this document:
•DSPC54x or C6x
•Word16 bits for PCI, 16 bits for C54x, 32 bits for C6x
•Half-word8 bits for C54x, 16 bits for C6x
•Double-word32 bits for PCI
Figure 3−1 shows a simplified block diagram of the PCI2040.
CPCI Hot-Swap
Miscellaneous
Interface
PCI Host Bus Interface
PCI Power
Management
Serial ROM
GPIO
PCI
Target
SM
HPI
Interface
Registers
&
PCI
Registers
C6x
Host
Port
Extensions
HPI Interface
C54x
Host
Port
SM
GP BUS
Interface
Interrupt
Figure 3−1. PCI2040 System Block Diagram
3.1PCI Interface
PCI2040 provides an integrated 32-bit PCI bus interface compliant with the PCI Local Bus Specification. The PCI2040
incorporates a PCI target interface for configuration cycles, accesses to internal registers, and access to the HPI
interface via memory-mapped space. The PCI2040 does not provide PCI mastering.
As a PCI bus target, PCI2040 incorporates the following features:
•Supports the memory read, memory write, configuration read, and configuration write
•Aliases the memory read multiple, memory read line, and memory write and invalidate to the basic
memory commands (i.e., memory read and memory write)
•Supports PCI_LOCK
3−1
3.2Accessing Internal PCI2040 Registers
PCI configuration space is accessed via PCI configuration read and PCI configuration write cycles. These registers
may be accessed using byte, word, or double-word transfers.
The PCI2040 provides a set of registers specifically for interfacing with the HPI port. These registers are called the
HPI control and status registers (HPI CSRs) (see Section 5), and they may be memory- and I/O-mapped. The HPI
CSR memory base address register (see Section 4.11) provides the mechanism for mapping the HPI CSRs into
memory space. When mapped into memory space, the HPI CSRs may be accessed using bytes, words, or
double-word transfers. Memory mapping the HPI CSR registers is recommended.
The HPI control and status registers may also be mapped into I/O space via the HPI CSR I/O base address register
(see Section 4.32). When this register is programmed to a nonzero value, PCI2040 maps the HPI CSRs into I/O
space, and the index/data access scheme is used to access the registers using byte transfers.
The HPI CSR I/O base address register identifies the I/O address of the index port. I/O address index + 1 is the data
port. To access a HPI CSR register, software writes the offset of the HPI CSR register into the index port. I/O reads
from the data port provide the contents of the indexed register and writes to the data port result in PCI2040 updating
the indexed register.
3.3PCI_LOCK
PCI2040 supports exclusive access via the LOCK protocol defined by PCI and the PCI_LOCK terminal. As a PCI
target, PCI2040 locks all DSP access and internal resources to a particular master when PCI_LOCK
deasserted during the address phase of a PCI cycle that it claims. Once LOCK
locked until both FRAME
(see Section 5.1).
and LOCK are sampled deasserted or bit 30 (HPIError) is set in the interrupt event register
is established, the PCI2040 remains
is sampled
The master that owns the exclusive access lock on PCI2040 drives PCI_LOCK
deasserts PCI_LOCK
addressed to it when PCI_LOCK
addressing a locked PCI2040 and will be retried.
Note that when the PCI2040 is not locked, it can claim and complete data transfers even if PCI_LOCK
asserted in the address phase.
(and asserts FRAME) when addressing the PCI2040. The PCI2040 claims and retries cycles
is asserted. Other masters will not be able to force the PCI_LOCK signal high when
while the lock is established and
is sampled
3.4Serial ROM Interface
The PCI2040 provides a two-wire serial ROM interface that may be used to preload PCI2040 registers following a
power-on reset (GRST
input/output. The SCL signal maps to the GPIO0 terminal and the SDA signal maps to the GPIO1 terminal. The
two-wire serial ROM interface is enabled by pulling up both GPIO0 and GPIO1 terminals to V
PCI2040 will only sense GPIO0 on GRST
the serial ROM interface.
The registers that may be preloaded are given in the following list, and only write accessible bits in these registers
may be preloaded. Figure 3−2 illustrates the PCI2040 serial ROM data format.
Word Address 0
Word Address 1
Word Address 2
Word Address 3
Word Address 4
Word Address 5
Word Address 6
Word Address 7
Word Address 8
Word Address 9
Word Address 10
Word Address 11
Word Address 12
Word Address 13
Word Address 14
Word Address 15
Word Address 16 (10h)
Word Address 17
Word Address 18
Word Address 19
Word Address 20
Word Address 21
Word Address 22
Word Address 23
Word Address 24
Word Address 25
Word Address 26
Word Address 27
Word Address 28
Word Address 29
Word Address 30
Word Address 31
Figure 3−2. PCI2040 Serial ROM Data Format
When PCI2040 accesses an implemented serial ROM, it always addresses the serial ROM at slave address
8’b10100000. The serial ROM data format described above utilizes 32 bytes of address space, some of which are
reserved for future generations of the PCI2040. A byte at address 31 is reserved for diagnostic software purposes
and will not be allocated to future generations of the PCI2040. Serial ROM addresses above word address 31 are
available for use by PCI2040 applications. If the data at word address 0 is FFh, then the PCI2040 will stop reading
from the serial ROM. This feature prevents the uninitialized data from being loaded into the PCI2040’s registers.
3.5PCI2040 Host Port Interface
The PCI2040 HPI interface is used to access TI’s TMS320C54X or TMS320C6X DSP chips. The devices connected
to the HPI interface are memory-mapped in host memory. The host system processor accesses the HPI interface
via slave accesses to PCI2040. The DSP devices can generate interrupts, and the PCI2040 passes these interrupt
requests to the PCI bus via INTA
The HPI port on DSP devices is a parallel port that allows access to the DSP’s memory space and internal registers.
The PCI2040 has to configure the HPI interface on the DSP by accessing the DSP’s HPI control register (HPIC). Other
DSP HPI registers include the HPI data register (HPID) and the HPI address register (HPIA). See Section 6, DSPHPI Overview for more information on DSP registers.
3.5.1Identifying Implemented Ports and DSP Types
The PCI2040 supports up to four DSPs of both the C54x and C6x types. It may be useful for generic software to
discover what number and type of DSPs are connected to the PCI2040. This is accomplished by using the HPI DSP
implementation register (see Section 5.5) and HPI data width register (see Section 5.6) in the HPI control and status
register space. The HPI DSP implementation register identifies how many DSPs are implemented and what HCSn
outputs are connected, and the HPI data width register identifies whether the HPI port per connected DSP is 8 bits
(C54x) or 16 bits (C6x).
. See Section 3.7, Interrupts, for more information on PCI2040 interrupts.
3−3
The HPI DSP implementation register and HPI data width register may be loaded from a serial ROM. Also, these
registers are implemented as read/write so intelligent software can load them with the proper values.
3.5.2DSP Chip Selects
The PCI2040 provides four chip select outputs (HCS3−HCS0) that uniquely select each HPI port DSP (or other HPI
peripheral) per transaction. This section describes how software encodes the chip select in the PCI address to access
a particular DSP interfacing with PCI2040.
The PCI2040’s control space base address register (see Section 4.12) is a standard PCI base address register
requesting 32K bytes of control space nonprefetchable memory to access up to four DSPs. The PCI2040 claims PCI
memory access transactions that fall within the 32-Kbyte memory window by comparing the upper 17 bits of the PCI
address (PCI_AD31−PCI_AD15) to bits 31−15 (A VAIL_ADD field) in the control space base address register. When
a cycle is claimed, the chip select is determined by decoding bits 14 and 13 of the PCI address. PCI_AD14 and
PCI_AD13 determine the chip select according to Table 3−1.
Only when the PCI cycle is claimed (by decoding PCI_AD31−PCI_AD15) is the chip select asserted.
Table 3−1. PCI2040 Chip Select Decoding
PCI_AD(14−13)CHIP SELECT ASSERTED
2’b00HCS0
2’b01HCS1
2’b10HCS2
2’b11HCS3
3.5.3HPI Register Access Control
The HCNTL1 and HCNTL0 terminals are driven by the PCI2040 to select the DSP HPI register and access mode
on a cycle-by-cycle basis. The PCI2040 determines the type of DSP register access from the PCI address, similarly
to the chip select decode as described in Section 3.5.2, DSP Chip Selects.
When a cycle is claimed by decoding PCI_AD31−PCI_AD15, the HCNTL1 and HCNTL0 control signals are
determined by decoding bits 12 and 11 of PCI address. PCI_AD12 maps to HCNTL1 and PCI_AD11 maps to
HCNTL0, and the selected HCNTL1 and HCNTL0 are driven to the HPI interface when the cycle is forwarded.
Table 6−1 and Table 6−3 provides more information on the usage of HCNTL1 and HCNTL0 for both C54x and C6x
DSPs.
3.5.4Mapping HPI DSP Memory to the Host
The PCI address bits PCI_AD10−PCI_AD0 are not forwarded to the HPI interface, and these address bits are not
decoded by PCI2040 for any purpose. This 2-Kbyte of addressable space per DSP (and control) allows the host to
directly map 2K bytes of host memory to the HPI interface for each DSP. This allows for fast memory block copies
rather than an I/O port mechanism.
The PCI2040 does not automatically generate accesses to the HPI address registers based upon
PCI_AD10−PCI_AD0, and it is left to software to synchronize the HPI address register with copies to and from HPI
memory space.
3.5.5Read/Write Procedure
The following procedure illustrates how to read and write HPI space, and covers some of the initialization that must
be done to successfully transfer data to and from DSP memory via the HPI data register.
After a power-on reset (GRST
•PCI2040 preloads several registers if a serial ROM is implemented, and this rewrites the HPI
implementation and HPI data width registers (software can also rewrite these registers).
):
3−4
•HPI CSR memory base address register (see Section 4.11) is programmed to provide a pointer to the HPI
control and status registers (see Section 5). HPI CSR I/O base address register (see Section 4.32) can also
be programmed to give I/O access.
•Control space base address register (see Section 4.12) is programmed and 32K bytes of memory are
allocated.
•The PCI command register (see Section 4.3) is programmed to allow PCI2040 to respond to memory and
I/O cycles.
•Software must clear the HPI reset register (see Section 5.4) to remove the reset assertion to the DSPs.
•When PCI2040 decodes a PCI address within the 32-Kbyte memory control space window, it claims the
cycle and decodes the chip select, HCNTL1 and HCNTL0, to pass to the HPI interface.
•The host initializes the BOB or HWOB bit in the HPI control register (see Section 6.2 or Section 6.3.5,
respectively) to choose the correct byte alignment. This results in an HPI cycle to the DSP’s HPI control
register.
•The host then initializes the HPI address register with the correct HPI memory address. By loading the HPI
address register, an internal DSP HPI memory access is initiated and the data is latched in the HPI data
register.
•If this is a read:
−The host performs a read of the HPI data register. During the read, the contents of the first half-word data
latch appear on the HADn pins when the HWIL signal is low and contents of the second data latch when
the HWIL signal is high.
−If auto-increment is selected, then it occurs between the transfer of the first and second bytes. This
allows back-to-back HPI data register accesses without an intervening HPI address register access.
•If this is a write:
−The first data latch of HPI data register is written from the data coming from the host while HWIL is low
and the second data latch when HWIL is high. If communicating with C6x, then the correct combination
of byte enables must also be used.
−If auto-increment is selected, then it occurs between the transfer of the first and second bytes.
3.5.6HPI Interface Specific Notes
The PCI2040 supports the HPI features from C54x and C6x interfaces given in Table 3−2. See Section 6, DSP HPI
Overview, and the HPI functional specification and timing requirements for more details.
Table 3−2. HPI Interface Features
C54xC6x
Shared access mode (SAM) and host only mode (HOM)Only one mode of operation: host only mode (HOM)
Auto-incrementAuto-increment
Endian byte swap (BOB)Endian byte swap (HWOB)
DSP-to-host interruptDSP-to-host interrupt
Wait states using HRDY5xnWait states using HRDY6xn
Two data strobes: HDS, HR/WTwo data strobes: HDS, HR/W
HPI memory access during resetByte enables
No software handshaking using HRDY and FETCH
Valid byte enablesAll byte enables valid
3−5
3.6General-Purpose I/O Interface
The PCI2040 has six general-purpose input/output (GPIO) terminals for design flexibility, and these terminals reside
in the V
GPIO direction control register (see Section 4.23). When GPIOx is selected as an input, the logical value of the data
input on GPIOx is reported through the GPIO input data register (see Section 4.22). When GPIOx is selected as an
output, the logical value of the data driven by PCI2040 to the GPIOx terminal is programmed via the GPIO output
data register (see Section 4.24). The GPIO input data register , GPIO output data register, and GPIO direction control
register are only meaningful for GPIOx if GPIOx is selected as a general-purpose input/output through the GPIO
select register (see Section 4.21).
Through the GPIO select register, the GPIO5−GPIO0 terminals may be programmed to other signal functions, such
as test outputs and general-purpose interrupt event inputs. See Section 4.21, GPIO select register, for more details
on these options.
If bit 5 in the miscellaneous control register is set to 1 (see Section 4.26), then GPIO5 and GPIO4 provide some
signals from the general-purpose bus interface. Also note that GPIO0 and GPIO1 provide the serial ROM interface
if enabled as described in Section 3.4, Serial ROM Interface.
signaling environment. GPIO5−GPIO0 default to inputs, but may be programmed to be outputs via the
CCP
3.7Interrupts
The PCI2040 reports two classes of interrupts: DSP interrupts and device interrupts. DSP interrupts are generated
when an implemented DSP asserts its HINTn
logic. For example, one such PCI2040 device interrupt indicates that a serious error has occurred on the HPI
interface.
signal, and device interrupts come directly from the remaining PCI2040
3.7.1Interrupt Event and Interrupt Mask Registers
The PCI2040 contains two 32-bit registers to report and control interrupts: interrupt event register (see Section 5.1)
and interrupt mask register (see Section 5.2). These registers exist in the HPI control and status register space. Both
registers have two addresses: a set address and a clear address. For a write to either register, a 1 written to the set
address causes the corresponding bit in the register to be set (excluding bits that are read-only), while a 1 written
to the clear address causes the corresponding bit to be cleared. For both addresses, writing a 0 has no effect on the
corresponding bit in the register.
The interrupt event register contains the actual PCI2040 interrupt request bits, and the response to these sources
can be tested by diagnostic software by setting the corresponding bit in the interrupt event set register. The interrupt
mask register is AND’ed with the interrupt event register to enable selected sources to generate host interrupts
through INTA
event register.
Reading either the set or the clear address for these registers returns the value of the register with one exception.
Reading the interrupt event clear register returns the value of the interrupt event register AND’ed with the interrupt
mask register to report the unmasked bits that are set in the interrupt event register that caused the interrupt event.
Software can then write this value to the interrupt event clear register , which clears the events causing the interrupt,
and the PCI2040 deasserts INTA
PCI2040 also implements a global interrupt enable in the interrupt mask register at bit 31 (masterIntEnable). Only
when bit 31 is set will the PCI2040 generate an INTA
. Software writes to the interrupt event clear register to clear interrupt conditions reported in the interrupt
if no more unmasked interrupt events are pending.
.
3.7.2DSP-to-Host Interrupts
These interrupts are the most common interrupts generated by the PCI2040. The four interrupt events,
IntDSP3−IntDSP0 (bits 3−0 in Section 5.2), occur when the corresponding HINT3
When enabled via the corresponding bits in the interrupt mask register (see Section 5.1), these DSP interrupts are
passed directly to the PCI host.
−HINT0 is asserted by the DSP.
3−6
As a side note, HINT is generated when the HINT bit is set in the HPI control register. See Section 6, DSP HPIOverview, for a description of the DSPs HPI control register.
3.7.3HPI Error Interrupts and HPI Error Reporting
Bit 30 (HPIError) in the interrupt event register (see Section 5.1), set upon serious error conditions on the HPI
interface, allows software to gracefully terminate communication with an HPI device. Bit 30 is set when any of the
bits in the HPI error report register (see Section 5.3) are set (an OR combination).
Bits 3−0 (HPIErr[3:0] field) in the HPI error report register (see Section 5.3) are set for an HPI interface when a cycle
destined for a particular interface experienced as serious error, which may be a result of a DSP losing power. Such
error conditions are as follows:
1. HRDY5xn (or HRDY6xn
of HCSn
Section 4.27).
2. The discard timeout expires for a read transaction from HPI(x)
3. A PCI byte enable combination other than 4’b1100, 4’b0011, or 4’b0000 was received for a transaction
destined for a C54x DSP on HPI(x)
To avoid potential system level catastrophe when the PCI target abort is signaled, PCI2040 implements a feature to
disable target aborts and returns zero data on such error conditions. This mode of operation is enabled via bit 30
(HPIError) in the interrupt mask register (see Section 5.2). When bit 31 is set and bit 30 (HPIError) in the interrupt
event register is also set, on all HPI error conditions, an INTA
Also when bit 30 (HPIError) in the interrupt mask register is set, error on posted writes will not cause the SERR
assertion by bit 8 (SERR_EN) in the PCI command register (see Section 4.3). When bit 30 (HPIError) is 0, target
aborts may occur and SERR
to SERR
Future generations of PCI2040 may support connections to different numbers of DSPs (more or less than 4). A
recommended procedure for software to determine the maximum number of DSP HPI connections is to write all 1s
to the HPI error report register and read back the number of set bits. Similarly, software can perform the same
procedure on the lower 16 bits of the interrupt mask or interrupt event register.
signaling on PCI address parity errors per the PCI Local Bus Specification.
. This timer can be disabled by setting bit 1 (ErrorTimer) in the diagnostic register (see
may be signaled as a result of a posted write error. This mode of operation is not related
) driven by DSP is not asserted within 256 PCI clock cycles following assertion
interrupt is signaled.
signal
3.7.4General-Purpose Interrupts
The GPIO3 and GPIO2 terminals may be configured via the GPIO select register (see Section 4.21) as general
interrupt event inputs. The general interrupt event type may be either input low signal or input state change, and is
programmable via the GPIO interrupt event type register (see Section 4.25). When these general interrupt events
occur, the corresponding bits 28 (IntGPIO3) and 27 (IntGPIO2) are set in the interrupt event register (see Section 5.1)
and may be enabled to generate an interrupt (INTA
) via interrupt mask register (see Section 5.2).
3.7.5Interrupts Versus PME
When an unmasked interrupt event occurs and PCI2040 is in the D0 power state, PCI2040 asserts INTA to signal
the interrupt event. When PCI2040 is in D1, D2, or D3, INTA
(masterIntEnable) in the interrupt mask register (see Section 5.2).
Whenever an unmasked interrupt event occurs and bit 15 (PME_STS) in the power management control/status
register is set (see Section 4.31), a PME
management control/status register is set.
power management event is generated if bit 8 (PME_EN) in the power
generation is disabled regardless of the value of bit 31
3.8PCI2040 Power Management
This section covers the power management aspects of PCI2040, including descriptions of power savings features.
3−7
3.8.1PCI Power Management Register Interface
PCI2040 is PCI Bus Power Interface Management Specification Revision 1.0 and 1.1 compliant. By default, PCI2040
provides the PCI power management PM 1.0 register set which is documented in Section 4.30. PCI2040 may be
programmed to provide a PCI PM 1.1 register set by setting bit 4 (PM11_EN) of the miscellaneous control register
to 1 (see Section 4.26).
The PCI power management register changes required to provide PCI PM 1.1 compliance to the power management
capabilities register (see Section 4.30) are summarized in Table 3−3.
Table 3−3. PMC Changes for PCI PM 1.1 Register Model
BITFIELD NAMETYPEDESCRIPTION
15−9PM 1.0 CompliantSame as PM 1.0 Implementation. No change.
Aux_Current. This field reports the Vaux requirements for PCI2040. If bit 15
(D3cold_PMESupport) in the power management capabilities register is set (see Section 4.30),
8−6Aux_CurrentR
5PM 1.0 CompliantRSame as PM 1.0 Implementation. No change.
4RSVDR
3PM 1.0 CompliantRSame as PM 1.0 Implementation. No change.
2−0VersionR
then this field returns 3’b001 indicating that PCI2040 draws a maximum of 55 mA while
programmed to D3. If bit 15 (D3cold_PMESupport) is 0, then this field returns 3’b000 since no
wake from D3
Bit 6 is aliased to bit 15 and is read-only.
This reserved field returns 0 when read in the PCI PM 1.1 register model and returns 1 when
read in the PCI PM 1.0 model.
These three bits return 010b when read, indicating that there are 4 bytes of general-purpose
power management (PM) registers as described in the draft revision 1.1 PCI Bus PowerManagement Interface Specification.
is supported.
cold
3.8.2PCI Power Management Device States and Transitions
PCI2040 supports all D0−D3 device power states, and can assert PME from any power state including D3
Vaux is supplied. The PCI2040’s power state implementation is simply disabling the HPI state machine when in the
D1, D2, or D3 power states. D0 is the fully operational power state.
If an HPI cycle initiated by PCI2040 is in progress when bits 1 and 0 (PWRSTATE field) in the power management
control/status register are programmed to D1, D2, or D3 (see Section 4.31), then the PCI2040 will complete the cycle
in progress before transitioning to the lower power state.
On a transition to the D0 power state from the D3 power state, PCI2040 asserts an internal signal equivalent to a
PCI_RST which does not reset all internal states. There are several register bits that are reset by GRST versus the
PCI_RST
The PME
, and these are referred to as the PME context (or sometimes sticky) bits.
context bits for PCI2040 are listed below and Figure 3−3 illustrates the relationship between the PME
context bits: GRST, and PCI_RST. The addition of GRST allows for retaining device state from a D3 to D0 transition
when the PCI interface may transition from B3 to B0 and issue a PCI reset.
•0x18 – HPI data width register (all implemented bits)
PCI_RST
GRST
RESET
RESET
Non-PME Context
PME Context
Figure 3−3. PCI2040 Reset Illustration
3.9Compact PCI Hot-Swap
PCI2040 is hot-swap friendly silicon that will support all the hot-swap capable features, contain support for software
control, and integrate circuitry required by the Compact PCI Hot Swap Specification PICMG 2.1. To be hot-swap
capable, PCI2040 supports the following:
•PCI Local Bus Specification, Revision 2.1 compliance
•V
from early power tolerant
CC
•Asynchronous reset
•Precharge voltage tolerant
•I/O buffers must meet modified V/I requirements
•Limited I/O pin voltage at precharge voltage
•Hot swap control and status programming via extended PCI capabilities linked list
•Hot swap terminals: HSENUM
, HSSWITCH, and HSLED
CPCI hot-swap defines a process for installing and removing PCI boards without adversely affecting a running
system. The PCI2040 provides this functionality such that it can be implemented on a board that can be removed
and inserted in a hot-swap system.
The PCI2040 provides three terminals to support hot-swap: HSENUM
(output). The HSENUM
output indicates to the system that an insertion event occurred or that a removal event is about
(output), HSSWITCH (input), and HSLED
to occur. The HSSWITCH input indicates that state of a board ejector handle, and the HSLED output lights a blue
LED to signal insertion and removal ready status.
The PCI2040 hot-swap functionality is controlled via the CPCI hot swap control and status register (see Section 4.35)
in extended PCI configuration space. This register provides four bits for control: bit 7 (INS), bit 6 (EXT), bit 3 (LOO),
3−9
and bit 1 (EIM). Since no HSSWITCH status is provided in the CPCI hot swap control and status register, PCI2040
provides bit 8 (HSSWITCH_STS) in the miscellaneous control register (see Section 4.26).
HSENUM
(EIM, the HSENUM
is an active low open drain output that is asserted when either bit 7 (INS) or bit 6 (EXT) are set and bit 1
mask bit) is cleared. For the insertion event, PCI2040 will drive HSLED after PCI_RST until the
serial ROM preload is complete and the ejector handle is closed (HSSWITCH_STS is 0). When these conditions are
met, the HSLED is under software control via bit 3 (LOO). Bit 7 (INS) is set when the conditions described above are
met and bit 6 (EXT) is 0. Thus, bit 7 (INS) is set following an insertion when the board implementing PCI2040 is ready
for configuration and cannot be set by software.
For the removal event, bit 6 (EXT) is set when the ejector handle is opened (HSSWITCH_STS is 1) and bit 7 (INS)
is 0. This will cause HSENUM
to be asserted if bit 1 (EIM) is 0, and software will halt connection with PCI2040 and
light the LED via bit 3 (LOO). The board may then be safely removed.
See the Compact PCI Hot Swap Specification PICMG 2.1 for more details.
3.10 General-Purpose Bus
This section discusses the general-purpose interface of PCI2040. This is a 16-bit data and a 6-bit address bus. The
6-bit address bus is mapped directly to PCI address bits 7−2. This means that each address on the GP bus
corresponds to a 32-bit (1 DW) address on the PCI bus for a total of 256 bytes of addressable space. Because the
GP bus is only a 16-bit data bus, only the lower 16 bits (15−0) of the PCI data bus is used. In other words, the only
valid byte enable combination is 1100b.
The general-purpose bus read/write strobes must default to the JTAG TBC (8990) timing requirements. However,
GP_RDY
Most of the GP bus signals are multiplexed onto the HPI bus as described in the table below. In addition to the
multiplexed signals, there are three dedicated GP bus signals which are GPINT
signal can be used to extend the use of the bus for slower devices.
, GPRDY, and GPRST.
Table 3−4. General-Purpose Bus Signals
HPI SIGNALSGP BUS SIGNALSTYPENOTES
HAD15−HAD0GP_DATA15−GP_DATA0I/OGP data bus. A 16-bit data bus
HBE0GPA0OOne of the six address lines
HBE1GPA1OOne of the six address lines
HWILGPA2OOne of the six address lines
HCNTL0GPA3OOne of the six address lines
HCNTL1GPA4OOne of the six address lines
HR/WGPA5One of the six address lines
HDSGP_CSOGP chip select. This signal is asserted during an access on the GP bus.
GPIO5GP_RDO
GPIO4GP_WRO
Terminal 74GP_INTIGP interrupt. Interrupt from a device on the GP bus.
Terminal 75GP_RDYI
Terminal 70GP_RSTOGP reset. An active low output that follows the state of GRST.
GP read strobe. This active low signal indicates a read from a device on the bus. The
data on the bus is valid on the rising edge of GP_RD
GP write strobe. This active low signal indicates a write to a device on the bus. The
data on the bus is valid on the rising edge of GP_WR
GP ready. Whenever the device on the GP bus is ready to accept a read or write from
PCI2040, GP_RDY
from a read or write operation.
is asserted. RDY is deasserted when the device is in recovery
.
.
3−10
3.11 Example Transactions on the General-Purpose Bus
This section describes some example transactions on the GP bus.
3.11.1 General-Purpose Bus Word Write
The first diagram, Figure 3−4, depicts a word (16−bits) write to a device residing on the GP bus. The event flow is
as follows:
1. All signals are in a deasserted state except for GP_RDY
. The PCI2040 is driving the address and data bus
to a stable but unknown value.
2. The GP_CS
is driven low. The data bus (GPD15−GPD0) is driven with the data the PCI2040 obtained from
the PCI bus. In this case, the data is BBAAh. The address bus (GPA5−GPA0) is driven with the address
the PCI2040 obtained from the PCI bus. For example, if the address on the PCI bus is FF0B0h, then this
address would translate to a GP bus address of 2Ch.
3. The GP_WR
4. The GP_WR
of the GP_WR
of the write strobe. The PCI2040 samples the GP_RDY
this case, the GP_RDY
5. The transaction completes by deasserting the GP_CS
PCI_CLK
GP_RST
GP_CS
GPD[15:0]
GPA[5:0]
GP_WR
strobe is driven low indicating a write to the device on the GP bus.
strobe is driven high. Typically, a device on the GP bus latches the data on the rising edge
strobe. But as the figure shows, the data is valid on both the falling edge and the rising edge
signal before it deasserts the GP_WR strobe. In
signal is low indicating to the PCI2040 that the device is ready for data.
.
1 2345
BBAA
2C
GP_RD
GP_RDY
Figure 3−4. General-Purpose Bus Word Write
3.11.2 General-Purpose Bus Word Read
The second diagram, Figure 3−5, shows a word read from a device on the GP bus. The event flow is as follows:
1. All signals are in a deasserted state except for GP_RDY
to a stable but unknown value.
2. The GP_CS
is driven low. The data bus (GPD15−GPD0) is placed in a high impedance state. The address
bus is driven with the address the PCI2040 obtained from the PCI bus.
3. The GP_RD strobe is driven low indicating a read to the device on the GP bus. Sometime later during
clock 3, the device on the GP bus drives valid data on the data bus.
4. The GP_RD strobe is driven high. The PCI2040 samples the GP_RDY before it deasserts GP_RD. If
GP_RDY
bus. If GP_RDY
GP_RDY
is sampled asserted, then the PCI2040 deasserts GP_RD strobe and latches the data on the GP
is sampled deasserted, then the PCI2040 keeps GP_RD asserted and waits for the
strobe to be asserted before it deasserts the GP_RD strobe.
. The PCI2040 is driving the address and data bus
3−11
5. The transaction completes by deasserting the GP_CS. The PCI2040 starts driving the GP address and data
bus with stable values.
12345
PCI_CLK
GP_RST
GP_CS
GPD[15:0]
GPA[5:0]
GP_WR
GP_RD
GP_RDY
ZZZZBBAAZZZZ
2C
Figure 3−5. General-Purpose Bus Word Read
3−12
4 PCI2040 Programming Model
This section describes the PCI2040 PCI configuration registers that make up the 256-byte PCI configuration header.
A brief description is provided for each register, followed by the register offset and a default state for each register.
The bit table also has reserved fields that contain read-only reserved bits. These bits return 0s when read.
4.1PCI Configuration Registers
The PCI2040 is a device that interfaces the PCI bus to the 8-bit or 16-bit HPI port of Texas Instruments C54x or C6x
family of DSP processors. The configuration header is compliant with the PCI Local Bus Specification.
The configuration header is compliant with the PCI Local Bus Specification as a type 0 bridge header, and is PC98/99
compliant as well. Table 4−1 shows the PCI configuration header , which includes both the predefined portion of the
configuration space and the user-definable registers.
Table 4−1. PCI Configuration Registers
REGISTER NAMEOFFSET
Device IDVendor ID00h
StatusCommand04h
Class codeRevision ID08h
BISTHeader typeLatency timerCache line size0Ch
HPI CSR memory base address10h
Control space base address14h
GPBus base address18h
Reserved1Ch
Reserved20h
Reserved24h
Reserved28h
Subsystem IDSubsystem vendor ID2Ch
Reserved30h
ReservedReservedReservedCapability pointer34h
Reserved38h
Max_LatMin_GNTInterrupt pinInterrupt line3Ch
ReservedReserved40h
GPIO output dataGPIO direction controlGPIO input dataGPIO select44h
ReservedReservedReservedGPIO interrupt type48h
DiagnosticReservedMiscellaneous control4Ch
Power management capabilitiesPM next-item pointerPM capability ID50h
NOTE: Optional registers not implemented for PCI2040 return 0s when read.
4−1
A bit description table is typically included that indicates bit field names, a detailed field description, and field access
tags. Table 4−2 describes the field access tags.
Table 4−2. Bit Field Access Tag Descriptions
ACCESS
TAG
RReadField may be read by software.
WWriteField may be written by software to any value.
SSetField may be set by a write of 1. Writes of 0 have no effect.
CClearField may be cleared by a write of one. Writes of 0 have no effect.
UUpdate Field may be autonomously updated by PCI2040.
NAMEMEANING
4.2Vendor and Device ID Register
The vendor and device ID register returns AC60104Ch when read which consists of a unique device ID assigned by
TI (AC60h) and a value assigned by the PCI SIG to Texas Instruments (104Ch).
Bit31302928272625242322212019181716
NameDevice ID
TypeRRRRRRRRRRRRRRRR
Default1010110001100000
Bit1514131211109876543210
NameVendor ID
TypeRRRRRRRRRRRRRRRR
Default0001000001001100
Register:Vendor and device ID
Type:Read-only
Offset:00h
Default:AC60104Ch
4−2
4.3PCI Command Register
The system software accesses the status and command registers for error recovery, diagnostic, and control. This
register is provided to enable coarse control over a device’s ability to generate and respond to PCI cycles.
15−10RSVDRReserved. Bits 15−10 return 0s when read.
Fast back-to-back (FBB) enable. This bit controls whether or not the device is allowed to perform
9FBB−ENR
8SERR_ENRW
7STEP_ENR
6PERR_ENRW
5VGA_ENRVGA palette snoop. This bit is not applicable for PCI2040 and is hardwired to a 0.
4MWI_ENR
3SpecialR
2MAST_ENR
1MEM_ENRW
0IO_ENRW
back-to-back capability for bus master transaction. This bit is hardwired to 0 and indicates that FBB
transfers are not supported by PCI2040.
System error (SERR) enable. This bit is an enable for the output driver on the SERR pin. If this bit is
cleared and a system error condition is set inside PCI2040, then the error signal will not appear on the
external SERR pin.
Address/data stepping control. This bit indicates whether or not the device performs address stepping.
Since the PCI2040 does not require address stepping, this bit is hardwired to 0.
Parity error response enable. This bit controls whether or not the device responds to detected parity
errors. If this bit is set, then the PCI2040 responds normally to parity errors. If this bit is cleared, then
the PCI2040 ignores detected parity errors.
Memory write and invalidate enable. This bit enables the device to use the memory write and invalidate
command. Since the PCI2040 does not support MWI but uses MW instead, this bit is hardwired to 0.
Special cycle. This bit controls the device’s response to special cycle commands. Since PCI2040 does
not monitor any special commands, this bit is set to 0.
Bus master control. This bit allows a PCI device to function as a bus master. This bit is always 0 indicating
PCI2040 does not support PCI mastering.
Memory space enable. This bit enables the device to respond to memory accesses to any of the defined
base address memory regions. If this bit is cleared, then the PCI2040 will not respond to
memory-mapped accesses.
I/O space control. This bit enables the device to respond to I/O accesses within its defined base address
register I/O regions.
4−3
4.4PCI Status Register
The PCI status register provides the host information to the host system. A bit in this register is reset when 1 is written
to it. A 0 written to a bit has no effect.
Bit1514131211109876543210
NamePCI status
TypeRCRCRRRCRRRRRRRRRRR
Default0000001000010000
Register:PCI status
Type:Read-only, Read/Write to Clear
Offset:06h
Default:0210h
Table 4−4. PCI Status Register
BITFIELD NAMETYPEDESCRIPTION
15PAR_ERRRCDetected parity error. This bit is set by the PCI2040 to indicate that it detected a parity error.
14SYS_ERRRC
13MABORTRReceive master abort. This bit is set to indicate a transaction has been terminated due to a master abort.
12TABT_RECRReceive target abort. This bit is set when a transaction is terminated by a target abort.
11TABT_SIGRC
10−9PCI_SPEEDR
8DATAPARR
7FBB_CAPR
6UDFRUser definable feature support. Bit 6 is hardwired to 0 indicating that the PCI2040 does not support UDF.
566MHZR66-MHz capable. Bit 5 is hardwired to 0 indicating that the PCI2040 does not support 66 MHz operations.
4CAPLISTR
3−0RSVDRReserved. Bits 3−0 return 0s when read.
Signaled system error. This bit is set by the PCI2040 to indicate that it signaled a system error on the
SERR
pin. This bit can be reset by writing a 1.
Signaled target abort. This bit is set by the PCI slave unit in the PCI2040 to indicate that it has initiated
a target abort.
DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b indicating that
the PCI2040 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.
Data parity error detected. This bit is implemented by the bus mastering devices to indicate that a parity
error has been detected.
Fast back-to-back capable. This bit indicates that the device is capable of performing fast back-to-back
transactions. Since the PCI2040 does not support fast back-to-back transactions, this bit is hardwired
to 0.
Capabilities list. Bit 4 returns 1 when read indicating that capabilities in addition to standard capabilities
are implemented.
4.5Revision ID
This register indicates the silicon revision of the PCI2040.
Bit76543210
NameRevision ID
TypeRRRRRRRR
Default00000000
Register:Revision ID
Type:Read-only
Offset:08h
Default:00h
4−4
4.6Class Code
The class code register categorizes the function as a bridge device (06h), and another bridge device (80h) with a
standard programming interface (00h). Subclass and base class are loaded via serial ROM.
The header type register returns 00h when read, indicating that the PCI2040 configuration space adheres to the
standard PCI header and it is a single function device.
Bit76543210
NameHeader type
TypeRRRRRRRR
Default00000000
Register:Header type
Type:Read-only
Offset:0Eh
Default:00h
4.10 BIST Register
The PCI2040 does not support built-in-self-test (BIST); therefore, this register returns 00h when read.
The HPI CSR memory base address register provides a method of allowing the host to map the PCI2040’s HPI CSR
registers into host memory space.
Bit31302928272625242322212019181716
NameHPI CSR memory base address
TypeRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRW
Default0000000000000000
Bit1514131211109876543210
NameHPI CSR memory base address
TypeRWRWRWRWRRRRRRRRRRRR
Default0000000000000000
Register:HPI CSR memory base address
Type:Read-only, Read/Write
Offset:10h
Default:0000 0000h
Table 4−5. HPI CSR Memory Base Address Register
BITFIELD NAMETYPEDESCRIPTION
31−12AVAIL_ADDRW
11−4UNAVAIL_ADDRUnavailable address bit. Bits 11−4 return 00h when read.
3PREFETCHABLERPrefetchable. This bit is hardwired to 0 in the PCI2040.
2−1TYPER
0MEM_INDR
Available address bits. These bits can be written by the host in order to allow initialization of the base
address at startup. The PCI memory address space is on the 4-Kbyte boundary.
Type. Bits 2 and 1 indicate the size of the base address and how it can be mapped into the host memory.
These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used
which can be located anywhere in memory.
Memory space indicator. This bit indicates whether the base address maps into the host’s memory or
I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that this base address is valid only for
memory accesses.
4−7
4.12 Control Space Base Address Register
The control space base address register allows the host to map the PCI2040’s 32K bytes of control space into host
memory.
Bit31302928272625242322212019181716
NameControl space base address
TypeRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRW
Default0000000000000000
Bit1514131211109876543210
NameControl space base address
TypeRWRRRRRRRRRRRRRRR
Default0000000000000000
Register:Control space base address
Type:Read-only , Read/Write
Offset:14h
Default:0000 0000h
Table 4−6. Control Space Base Address Register
BITFIELD NAMETYPEDESCRIPTION
Available address bits. Bits 31−15 allow the host to map the PCI2040’s 32K bytes of control space into
31−15AVAIL_ADDRW
14−4RSVDRReserved. Bits 14−4 return 0s when read.
3PREFETCHABLERPrefetchable. This bit is hardwired to 0 in the PCI2040. The control space is not prefetchable.
2−1TYPER
0MEM_INDR
memory. See Sections 3.5.2, DSP Chip Selects, and 3.5.3, HPI Register Access Control, for details
on addressing the control space.
Type. Bits 2 and 1 indicate the size of the base address and how it can be mapped into the host memory.
These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used
which can be located anywhere in memory.
Memory space indicator. This bit indicates whether the base address maps into the host’s memory or
I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that the control space is
memory-mapped.
4−8
4.13 GP Bus Base Address Register
The GP bus base address register is used by the PCI2040 to communicate with a device on the GP bus. This 32−bit
register allows software to assign a memory window for the GP bus anywhere in the 4-Gbyte address space. This
window has a 256-byte granularity which means the lower 8 bits of this register default to 0 and are read-only . This
register is controlled via bit 5 (GP_EN) in the miscellaneous control register (see Section 4.26) and if it is set to 0,
then this register will be read-only and always return 0000 0000h when read.
Bit31302928272625242322212019181716
NameGP bus base address
TypeRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRW
Default0000000000000000
Bit1514131211109876543210
NameGP bus base address
TypeRWRWRWRWRWRWRWRWRRRRRRRR
Default0000000000000000
Register:GP bus base address
Type:Read-only , Read/Write
Offset:18h
Default:0000 0000h
Table 4−7. General-Purpose Bus Base Address Register
BITFIELD NAMETYPEDESCRIPTION
31−8AVAIL_ADDRW
7−4RSVDRReserved. Bits 7−4 return 0s when read.
3PREFETCHABLERPrefetchable. This bit is hardwired to 0 in the PCI2040. The control space is not prefetchable.
2−1TYPER
0MEM_INDR
Available address bits. Bits 31−8 allow the host to map the PCI2040’s 128 bytes of control space into
memory.
Type. Bits 2−1 indicate the size of the base address and how it can be mapped into the host memory.
These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used
which can be located anywhere in memory.
Memory space indicator. This bit indicates whether the base address maps into the host’s memory or
I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that this register is memory-mapped.
4.14 Subsystem Vendor ID Register
The subsystem vendor ID register is used for system identification purposes and may be required for certain operating
systems. This register is read-only or read/write depending on the value of bit 0 (SUBSYSRW) in the miscellaneous
control register (see Section 4.26). When bit 0 (SUBSYSRW) is 0, this register is read/write and when bit 0 is 1, this
register is read-only. This register may be loaded from the serial ROM.
Bit1514131211109876543210
NameSubsystem vendor ID
TypeRRRRRRRRRRRRRRRR
Default0000000000000000
Register:Subsystem vendor ID
Type:Read-only
Offset:2Ch
Default:0000h
4−9
4.15 Subsystem ID Register
The subsystem ID register is used for system identification purposes and may be required for certain operating
systems. This register is read-only or read/write depending on the value of bit 0 (SUBSYSRW) in the miscellaneous
control register (see Section 4.26). When bit 0 (SUBSYSRW) is 0, this register is read/write and when bit 0 is 1, this
register is read-only. This register may be loaded from the serial ROM.
Bit1514131211109876543210
NameSubsystem ID
TypeRRRRRRRRRRRRRRRR
Default0000000000000000
Register:Subsystem ID
Type:Read-only
Offset:2Eh
Default:0000h
4.16 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management
block resides.
The interrupt line register is written by the host and indicates to which input of the system interrupt controller the
PCI2040’s interrupt pin is connected.
Bit76543210
NameInterrupt line
TypeRWRWRWRWRWRWRWRW
Default11111111
Register:Interrupt line
Type:Read/Write
Offset:3Ch
Default:FFh
4−10
4.18 Interrupt Pin Register
The interrupt pin register tells which interrupt the device uses. This register is hardwired to 01h in the PCI2040 to
indicate that INTA
This register specifies the length of the burst period for the device needs in 0.25 µsec units. The default value for this
register is 00h as the PCI2040 is a target-only device.
This register specifies how often the device needs to gain access to the PCI bus in 0.25 µsec units. The default value
for this register is 00h as the PCI2040 is a target-only device.
7−6RSVDRReserved. Bits 7 and 6 return 0s when read.
GPIO5 pin. The value of this pin determines the function of GPIO5.
0 = Normal GPIO data (default)
5GPIO5PinRU
4GPIO4PinRU
3GPIO3PinRW
2GPIO2PinRW
1GPIO1PinR
0GPIO0PinR
1 = GP_RD. Read strobe (RD) for the GP bus. The PCI2040 will set this bit when bit 5 (GP_EN) in the
miscellaneous control register is set (see Section 4.26). Clearing bit 5 (GP_EN) will automatically
clear this bit.
GPIO4 pin. The value of this pin determines the function of GPIO4.
0 = Normal GPIO data (default)
1 = GPWR. Write strobe (WR) for the GP bus. The PCI2040 will set this bit when bit 5 (GP_EN) in the
miscellaneous control register is set (see Section 4.26). Clearing bit 5 (GP_EN) will automatically
clear this bit.
GPIO3 pin. The value of this pin determines the function of GPIO3. When programmed as an interrupt
event input, the event is selected in the GPIO interrupt event type register (see Section 4.25). When
programmed as a normal GPIO, the IntGPIO3 interrupt event will never occur.
0 = Normal GPIO data (default)
1 = GPIO3 is an interrupt event input
GPIO2 pin. The value of this pin determines the function of GPIO2. When programmed as an interrupt
event input, the event is selected in the GPIO interrupt event type register (see Section 4.25). When
programmed as a normal GPIO, the IntGPIO2 interrupt event will never occur.
0 = Normal GPIO data (default)
1 = GPIO2 is an interrupt event input
GPIO1 pin. The value of this pin determines the function of GPIO1.
0 = Normal GPIO data (default)
1 = Reserved.
GPIO0 pin. The value of this pin determines the function of GPIO0.
0 = Normal GPIO data (default)
1 = Reserved.
4−12
4.22 GPIO Input Data Register
The GPIO input data register reflects the state of the GPIO pins, and defaults to an unknown value.
Bit76543210
NameGPIO input data
TypeRRRRRRRR
Default00XXXXXX
Register:GPIO input data
Type:Read-only
Offset:45h
Default:XXh
Table 4−9. GPIO Input Data Register
BITFIELD NAMETYPEDESCRIPTION
7−6RSVDRReserved. Bits 7 and 6 return 0s when read.
5−0GPIO[5:0] Pin StateRGPIO5−GPIO0 pin state. Returns the logical value of the data input to the GPIO5−GPIO0 terminals.
4.23 GPIO Direction Control Register
The GPIO direction control register controls the direction of GPIO pins.
Bit76543210
NameGPIO direction control
TypeRRRWRWRWRWRWRW
Default00000000
Register:GPIO direction control
Type:Read-only , Read/Write
Offset:46h
Default:00h
Table 4−10. GPIO Direction Control Register
BITFIELD NAMETYPEDESCRIPTION
7−6RSVDRReserved. Bits 7 and 6 return 0s when read.
5−0
GPIO[5:0] Direction
Control
GPIO5−GPIO0 direction control. When the GPIOn direction control bit is set, then the GPIOn signal
RW
is an output. When the GPIOn direction control bit is 0, the GPIOn signal is an input.
4−13
4.24 GPIO Output Data Register
The GPIO output data register contains the output data for any selected output pin.
Bit76543210
NameGPIO output data
TypeRRRWRWRWRWRWRW
Default00000000
Register:GPIO output data
Type:Read-only, Read/Write
Offset:47h
Default:00h
Table 4−11. GPIO Output Data Register
BITFIELD NAMETYPEDESCRIPTION
7−6RSVDRReserved. Bits 7 and 6 return 0s when read.
GPIO5−GPIO0 output data.
RW
0 = Data out value, if selected, is 0 (default)
1 = Data out value, if selected, is 1.
5−0
GPIO[5:0] Output
data
4.25 GPIO Interrupt Event Type Register
The GPIO interrupt event type register gives the status of GPIO routed through INTA.
Bit76543210
NameGPIO interrupt event type
TypeRRRRRWRWRR
Default00000000
Register:GPIO interrupt event type
Type:Read-only , Read/Write
Offset:48h
Default:00h
Table 4−12. GPIO Interrupt Event Type Register
BITFIELD NAMETYPEDESCRIPTION
7−4RSVDRReserved. Bits 7−4 return 0s when read.
GPIO3 interrupt type.
0 = Bit 28 (IntGPIO3) in the interrupt event register (see Section 5.1) is set when GPIO3 input is
3GPIO3INTYPERW
2GPIO2INTYPERW
1−0RSVDRReserved. Bits 1−0 return 0s when read.
low (default)
1 = Bit 28 (IntGPIO3) in the interrupt event register (see Section 5.1) is set when GPIO3 input
changes state
GPIO2 interrupt type.
0 = Bit 27 (IntGPIO2) in the interrupt event register (see Section 5.1) is set when GPIO2 input is
low (default)
1 = Bit 27 (IntGPIO2) in the interrupt event register (see Section 5.1) is set when GPIO2 input
changes state
4−14
4.26 Miscellaneous Control Register
The miscellaneous control register controls various miscellaneous functions.
Bit1514131211109876543210
Name Miscellaneous control
TypeRURCURRRRRRRRRWRWRWRWRWRW
Default0000000000001111
Register:Miscellaneous control
Type:Read/Clear/Update/Write
Offset:4Ch
Default:000Fh
Table 4−13. Miscellaneous Control Register
BITFIELD NAMETYPEDESCRIPTION
15SEEDSRU
14SEEBESRCU
13SEEBSRSerial EEPROM busy status. When set, the serial ROM interface is busy.
12−9RSVDRReserved. Bits 12−9 return 0s when read.
8HSSWITCH_STSR
7−6RSVDRReserved. Bits 7−6 return 0s when read.
5GP_ENR
4PM11_ENR
3HSENR
2D3COLD_LOCKR
1PWDISR
0SUBSYSRWR
Serial EEPROM detect status. When this bit is set, it indicates that serial EEPROM block has detected
an EEPROM.
Serial EEPROM error status. When set, an error has occurred on the serial ROM interface. Writing a
1 to this bit clears the error status.
Hot swap switch status. Returns logical value of HSSWITCH input.
0 = Handle closed
1 = Handle open
GP bus enable.
0 = GP bus disabled. (default)
1 = GP bus enabled.
PCI PM Specification 1.1 enable.
0 = Use PCI PM 1.0 register implementation (Default)
1 = Use PCI PM 1.1 register implementation
Hot swap enable.
0 = Hot swap disabled
1 = Hot swap enabled (default)
Lock bit for PME support from D3
0 = Bit 15 (D3cold_PMESupport) in the power management capabilities register is read/write
(see Section 4.30)
1 = Bit 15 (D3cold_PMESupport) in the power management capabilities register is read-only
(default) (see Section 4.30)
Posted write disable bit.
0 = Posted writes are disabled
1 = Posted writes are enabled (default)
Subsystem read write enable.
0 = Subsystem ID and subsystem vendor ID registers are read/write
1 = Subsystem ID and subsystem vendor ID registers are read-only (default)
cold
.
4−15
4.27 Diagnostic Register
The diagnostic register is provided for test purposes and should not be accessed during normal operation.
7TRUE_VALRWTrue value. When set, all 1s are returned in the PCI vendor and device ID registers.
6−5RSVDRReserved. Bits 6−5 return 0s when read.
4DIAG4RW
3DIAG3RW
2RSVDRReserved. Bit 2 returns 0 when read.
1ErrorTimerRW
0TI_TESTRW
Diagnostic RETRY_DIS. Delayed transaction disable. When bit 4 is set, delayed transactions are
disabled. When bit 4 is 0 (default), they are enabled.
Diagnostic RETRY_EXT. When set, the PCI2040 extends the target latency from 16 to 64 PCI clocks a nd
is not PCI Local Bus Specification, Revision 2.2 compliant.
Error timer. Bit 1 is used to enable/disable the error timer. By default, the timer is enabled but can be
disabled by writing a 1 to this bit.
TI_TEST_BIT. This is internal TI test bit used by the design.
0 = Disable state vectors to GPIOs (default)
1 = Enable state vectors to GPIOs
4.28 PM Capability ID Register
The PM capability ID register identifies the linked list item as the register for PCI power management. This register
returns 01h when read, which is the unique ID located by the PCI SIG for the PCI location of the capabilities pointer
and the value.
Bit76543210
NamePM capability ID
TypeRRRRRRRR
Default00000001
Register:PM capability ID
Type:Read-only
Offset:50h
Default:01h
4−16
4.29 PM Next-Item Pointer Register
The PM next-item pointer register provides a pointer into the PCI configuration header where the CPCI hot swap
control and status register (HS_CSR) resides. The PCI header at 5Ch provides the hot swap register . If bit 3 (HSEN)
in the miscellaneous control register (see Section 4.26) is 0, then the PM next-item pointer register returns 00h when
read indicating the end of the extended capability list.
The power management capabilities (PMC) register contains information on the capabilities of the PCI2040 related
to power management. The PCI2040 supports all D0−D3 power states.
Table 4−15. Power Management Capabilities Register
BITFIELD NAMETYPEDESCRIPTION
D3
PME support. This bit defaults to read-only and becomes read/write when bit 2
cold
(D3COLD_LOCK) in the miscellaneous control register is set (see Section 4.26). This bit defaults
to 1 indicating the PME signal can be asserted from the D3
15D3cold_PMESupportR(W)
14−11PME SupportR
10D2_SupportRThis bit returns a 1 when read indicating that the PCI2040 supports D2.
9D1_SupportRThis bit returns a 1 when read indicating that the PCI2040 supports D1.
8−6RSVDRReserved. Bits 8−6 return 0s when read.
5DSIR
4AUX_PWRR
3PMECLKR
2−0VersionR
because wake-up support from D3
source to the Vcc terminals. If auxiliary power is not provided to Vcc terminals for D3
then this bit should be cleared. This bit is not reset by the assertion of PCI_RST
GRST
.
This field has a value of 4’b1111 indicating that the PCI2040 can signal PME from the D3
D1 and D0 states.
Device specific initialization. This bit returns 0 when read indicating no special initialization is
required before a standard driver can use the PCI2040.
Auxiliary power source. Bit 4 returns 1 when read indicating PME support in D3
auxiliary power source.
This bit returns 0 when read indicating that no PCI clock is required for the function to generate
PME
.
These three bits return 001b when read indicating compliance to PCI Bus Power ManagementInterface Specification.
is contingent on the system providing an auxiliary power
cold
cold
state. This bit is read/write
wake-up,
cold
, but is reset by
, D2,
hot
requires an
cold
4−17
4.31 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI2040. The
contents of this register are not affected by the internally generated reset caused by the transition from the D3
D0 state. All PCI registers will be reset as a result of a D3
-to-D0 state transition. TI specific registers, PCI power
hot
management registers, and the legacy base address register are not reset.
Table 4−16. Power Management Control/Status Register
BITFIELD NAMETYPEDESCRIPTION
PME status. This bit is set when the PME signal is asserted, independent of the state of bit 8 (PME_EN).
15PME_STSRCU
14−13DATASCALERData scale. This two-bit field returns 0s when read.
12−9DATASELRData select. This four-bit field returns 0s when read.
8PME_ENRW
7−2RSVDRReserved. Bits 7−2 return 0s when read.
1−0PWRSTATERW
This bit is cleared by a write back of 1, and this also clears the PME
a 0 to this bit has no effect. This bit will NOT be cleared by the assertion of PCI_RST
by the assertion of GRST
PME enable. This bit enables the function to assert PME. If bit 8 is cleared, then assertion of PME is
disabled. Bit 8 is NOT cleared by the assertion of PCI_RST
Power state. This two-bit field is used both to determine the current power state of a function, and to set
the function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
11 = D3
hot
.
signal if PME was asserted. Writing
. It will only be cleared
. It is only cleared by the assertion of GRST.
hot
to
4−18
4.32 HPI CSR I/O Base Address Register
The PCI2040 supports the index/data scheme of accessing the HPI CSR registers. An address written to this register
is the address for the index register and the address + 1 is the data address. The base address can be mapped
anywhere in 32-bit I/O space on a word boundary except at address 0x0000; hence, bit 0 is read-only, returning 0
when read.
The HPI CSR I/O base address is only meaningful when a nonzero value is written into this register.
Bit31302928272625242322212019181716
NameHPI CSR I/O base address
TypeRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWRW
Default0000000000000000
Bit1514131211109876543210
NameHPI CSR I/O base address
TypeRWRWRWRWRWRWRWRWRWRWRWRWRWRWRWR
Default0000000000000000
0RSVDRReserved. Bit 0 returns 0 when read for word alignment.
Available address bits. These bits can be written by the host in order to allow initialization of the base
address at startup.
4.33 HS Capability ID Register
The HS capability ID register identifies the linked list item as the register for CompactPCI hot swap. This register
returns 06h when read which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer
and the value.
Bit76543210
NameHS capability ID
TypeRRRRRRRR
Default00000110
Register:HS capability ID
Type:Read-only
Offset:5Ch
Default:06h
4−19
4.34 HS Next-Item Pointer Register
The HS next-item pointer register is used to indicate the next item in the linked list of the PCI extended capabilities.
This register returns 00h indicating no additional capabilities are supported.
The CPCI hot swap control and status register (HS_CSR) provides the control and status information about the
compact PCI hot swap resources.
Bit76543210
NameCPCI hot swap control and status
TypeRCURCURRRWRRWR
Default00000000
Register:CPCI hot swap control and status
Type:Read/Clear/Update/Write
Offset:5Eh
Default:00h
Table 4−18. CPCI Hot Swap Control and Status Register
BITFIELD NAME TYPEDESCRIPTION
ENUM insertion status. When set, the HSENUM output is driven by the PCI2040. This bit defaults to 0, and
will be set after a PCI_RST
7INSRCU
6EXTRCU
5−4RSVDRReserved. Bits 5 and 4 return 0s when read.
3LOORW
2RSVDRReserved. Bit 2 returns 0 when read.
1EIMRW
0RSVDRReserved. Bit 0 returns 0 when read.
bit 13 [SEEBS] is 0), the ejector handle is closed (miscellaneous control register, bit 8 [HSSWITCH_STS] is
0), and bit 6 (EXT) is 0. Thus, this bit is set following an insertion when the board implementing the PCI2040
is ready for configuration. This bit cannot be set under software control.
ENUM extraction status. When set, the HSENUM output is driven by the PCI2040. This bit defaults to 0, and
is set when the ejector handle is opened (miscellaneous control register, bit 8 [HSSWITCH_STS] is 1) and bit 7
(INS) is 0. Thus, this bit is set when the board implementing the PCI2040 is about to be removed. This bit cannot
be set under software control.
LED on/off. This bit defaults to 0, and controls the external LED indicator (HSLED) under normal conditions.
However, for a duration following a PCI_RST
bit will be ignored. When this bit is interpreted, a 1 will cause HSLED high and a 0 will cause HSLED low.
Following PCI_RST
(miscellaneous control register, bit 13 [SEEBS] is 0), and the ejector handle is closed (miscellaneous control
register, bit 8 [HSSWITCH_STS] is 0). When these conditions are met, the HSLED is under software control
via bit 3 (LOO).
ENUM interrupt mask. This bit allows the HSENUM output to be masked by software. Bits 7 (INS) and 6 (EXT)
are set independently from bit 1.
0 = Enable HSENUM output
1 = Mask HSENUM
occurs, the preload of serial ROM is complete (miscellaneous control register,
, the HSLED output is driven high by the PCI2040 control and this
, the HSLED output is driven high by the PCI2040 until both the pre-load of serial ROM
output
4−20
5 HPI Control and Status Registers
This section covers the PCI2040 HPI control and status register (HPI CSR) space. The PCI2040 allows software to
access the HPI configuration through either memory or I/O address space. The memory base address is
programmable via the HPI CSR base address register (PCI offset 10h). The I/O base address is programmable via
the HPI CSR I/O base address register (PCI offset 58h).
Table 5−1. HPI Configuration Register Map
REGISTER NAMEOFFSET
Interrupt event set00h
Interrupt event clear04h
Interrupt mask set08h
Interrupt mask clear0Ch
ReservedHPI error report10h
HPI DSP implementationHPI reset14h
ReservedHPI data width18h
5−1
5.1Interrupt Event Register
The interrupt event register reflects the state of the various PCI2040 interrupt sources. The interrupt bits are set by
an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register.
The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. Note
that the interrupt event register itself is returned on reads from the interrupt event set register (offset 00h), but the
bit-wise AND of the interrupt event and interrupt mask registers is returned on reads from the interrupt event clear
register (offset 04h).
04hClear Register [Returns IntEvent & IntMask when read]
Default:0000 0000h
Table 5−2. Interrupt Event Register
BITFIELD NAMETYPEDESCRIPTION
31RSVDRReserved. Bit 31 returns 0 when read.
Bit 30 is set upon serious error conditions on the HPI interface, and allows software to gracefully terminate
30HPIErrorRU
29GPErrorRSCU
28IntGPIO3RSCU
27IntGPIO2RSCU
26GPINTRSCU
25−4RSVDRReserved. Bits 25−4 return 0s when read.
3IntDSP3RSCU
2IntDSP2RSCU
1IntDSP1RSCU
0IntDSP0RSCU
communication with an HPI device. This bit is the OR combination of the HPI errors in the HPI error report
register (see Section 5.3).
Bit 29 is set upon serious error conditions on the GP interface, and allows software to gracefully terminate
communication with a GP device.
Set when GPIO3Pin (see Section 4.21, bit 3) selects GPIO3 as an interrupt event input, and the event type
selected by the GPIO interrupt event type register occurs (see Section 4.25).
Set when GPIO2Pin (see Section 4.21, bit 2) selects GPIO2 as an interrupt event input, and the event type
selected by the GPIO interrupt event type register occurs (see Section 4.25).
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the GPINT interface.
Software can set this bit for diagnostics.
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[3] interface.
Software can set this bit for diagnostics.
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[2] interface.
Software can set this bit for diagnostics.
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[1] interface.
Software can set this bit for diagnostics.
The PCI2040 sets this bit if an interrupt has been generated by a device connected to the HPI[0] interface.
Software can set this bit for diagnostics.
5−2
5.2Interrupt Mask Register
The interrupt mask register is used to enable the various PCI2040 interrupt sources. Reads from either the set register
or the clear register always return interrupt mask. In all cases, except masterIntEnable (bit 31), the enables for each
interrupt event align with the event register bits detailed in Table 5−2.
When bit 31 is set, external interrupts are generated in accordance with this register. If bit 31 is 0, then
no external interrupts are generated.
When bit 30 is set and the interrupt event register, HPIError bit (see Table 5−2, bit 30) is also set, an
interrupt is generated. When set, the HPI state machine will never cause target aborts on PCI and will
return the PCI slave 0s on such errors.
When set, errors on posted writes will not cause SERR
in the PCI command register (see Section 4.3). When bit 30 is 0, target aborts may occur and SERR
may be signaled as a result of a posted write error.
When bit 29 is set and the interrupt event register, GPError bit (see Table 5−2, bit 29) is also set, an
interrupt is generated. When set, the GP state machine will never cause target aborts on PCI and will
return the PCI slave 0s on such errors. When bits 29 and 30 are set, errors on posted writes will not cause
SERR
signal assertions enabled by bit 8 (SERR_EN) in the PCI command register (see Section 4.3).
Both bits 29 and 30 need to be set to prevent target aborts.
When bit 28 is set and the corresponding interrupt event register bit (see Table 5−2, bit 28) is also set,
an interrupt is generated. When bit 28 is 0, the interrupt is masked.
When bit 27 is set and the corresponding interrupt event register bit (see Table 5−2, bit 27) is also set,
an interrupt is generated. When bit 27 is 0, the interrupt is masked.
When bit 26 is set and the corresponding interrupt event register bit (see Table 5−2, bit 26) is also set,
an interrupt is generated. When bit 26 is 0, the interrupt is masked.
When bit 3 is set and the corresponding interrupt event register bit (see Table 5−2, bit 3) is also set, an
interrupt is generated. When bit 3 is 0, the interrupt is masked.
When bit 2 is set and the corresponding interrupt event register bit (see Table 5−2, bit 2) is also set, an
interrupt is generated. When bit 2 is 0, the interrupt is masked.
When bit 1 is set and the corresponding interrupt event register bit (see Table 5−2, bit 1) is also set, an
interrupt is generated. When bit 1 is 0, the interrupt is masked.
When bit 0 is set and the corresponding interrupt event register bit (see Table 5−2, bit 0) is also set, an
interrupt is generated. When bit 0 is 0, the interrupt is masked.
signal assertions enabled by bit 8 (SERR_EN)
5−3
5.3HPI Error Report Register
The HPI error report register reflects the state of errors on the HPI interfaces. If any bits in this register are set, then
the PCI2040 sets bit 30 (HPIError) in the interrupt event register (see Section 5.1). Software can set the bits in this
register for diagnostics.
PCI2040 sets this bit if a serious error occurs on the HPI[x] interface. The error conditions that cause this
bit to be set are as follows:
1. HRDY5xn (or HRDY6xn) driven by DSPn not sampled asserted within 256 PCI clocks following
3−0HPIErr[3:0]RWU
the assertion of HCSn
2. When the discard timeout expires for a read transaction from HPI[x]
3. A PCI byte enable combination other than 4’b1100, 4’b0011, or 4’b0000 was received for a
transaction destined for a C54x DSP on HPI[x]
by PCI2040
5.4HPI Reset Register
The HPI reset register is used to cause resets to the DSP interfaces. The implemented bits in this register are in the
PME context for PCI2040 and default to set. Thus, a GRST
responsible for removing the HRSTn
3HPI3_RSTRWHPI reset 3. When bit 3 is set, HRST3 is asserted.
2HPI2_RSTRWHPI reset 2. When bit 2 is set, HRST2 is asserted.
1HPI1_RSTRWHPI reset 1. When bit 1 is set, HRST1 is asserted.
0HPI0_RSTRWHPI reset 0. When bit 0 is set, HRST0 is asserted.
causes all DSP interfaces to be reset, and software is
5−4
5.5HPI DSP Implementation Register
The HPI DSP implementation register is used to indicate the presence of implemented DSPs on the HPI interface
and is loaded from the serial ROM.
3DSP_PRSNT3RWUDSP3 present. Bit 3 indicates if the DSP3 is present on the HPI interface.
2DSP_PRSNT2RWUDSP2 present. Bit 2 indicates if the DSP2 is present on the HPI interface.
1DSP_PRSNT1RWUDSP1 present. Bit 1 indicates if the DSP1 is present on the HPI interface.
0DSP_PRSNT0RWUDSP0 present. Bit 0 indicates if the DSP0 is present on the HPI interface.
5.6HPI Data Width Register
The HPI data width register is used to determine if the implemented DSPs are C54x or C6x, and is loaded from the
serial ROM. Each bit in this register is meaningful only if the corresponding bit in the HPI DSP implementation register
is set (see Section 5.5).
Bit1514131211109876543210
NameHPI data width
TypeRRRRRRRRRRRRRWU RWU RWU RWU
Default0000000000000000
Register:HPI data width
Type:Read/Write/Update
Offset:18h
Default:0000h
Table 5−7. HPI Data Width Register
BITFIELD NAMETYPEDESCRIPTION
15−4RSVDRReserved. Bits 15−4 return 0s when read.
3DWIDTH3RWUWhen bit 3 is set, the HPI[3] data bus is 16 bits (C6x). When bit 3 is 0, it is 8 bits (C54x).
2DWIDTH2RWUWhen bit 2 is set, the HPI[2] data bus is 16 bits (C6x). When bit 2 is 0, it is 8 bits (C54x).
1DWIDTH1RWUWhen bit 1 is set, the HPI[1] data bus is 16 bits (C6x). When bit 1 is 0, it is 8 bits (C54x).
0DWIDTH0RWUWhen bit 0 is set, the HPI[0] data bus is 16 bits (C6x). When bit 0 is 0, it is 8 bits (C54x).
5−5
5−6
6 DSP HPI Overview
This section gives an overview of the DSP host port interface (HPI). Refer to the C54x/C6x data sheets for complete
HPI details.
6.1C54X Host Port Interface
The HPI is an 8-bit parallel port used to interface a host device or host processor to a C54x DSP. Information is
exchanged between the DSP and the host device through on-chip C54x memory that is accessible by both the host
and the DSP.
The HPI is designed to interface to the host device as a peripheral, with the host device as the master of the interface,
and so facilitating the ease of access by the host. The host device communicates with the HPI through dedicated
address and data registers, to which the DSP does not have direct access, and the HPI control register using the
external data and interface control signals. Both host devices and the HPI have access to the HPI control register.
In C54x, the HPI provides 16-bit data to the DSP while maintaining an external interface of 8-bit by automatically
combining the successive bytes into 16-bit words. When the host performs a data transfer with the HPI registers, the
HPI control logic automatically performs an access to DSP’s memory to complete the transaction. The DSP can then
access the data within its memory space.
6.1.1Modes of Operation
In C54x, the HPI has two modes of operation as follows:
•Shared access mode (SAM): This is the normal mode of operation and in this mode both the DSP and
host can access the HPI memory. In this case, the asynchronous host accesses are resynchronized
internally. In the case of a conflict between the DSP and host, host has access priority and DSP waits
1 cycle. In SAM, the HPI can transfer 1 byte every 5 CLKOUT1 (40 MHz), i.e., 64 Mbps. The HPI is
designed such that the host can take advantage of its high bandwidth and can run up to 32 MHz without
requiring wait states.
•Host only mode (HOM): In this mode, only the host can access the HPI memory while the DSP is in reset
state or IDLE2 with all internal or external clocks stopped. This mode allows host to access the HPI
memory while the DSP is in minimum power consumption configuration. In HOM, the HPI supports
higher speed back-to-back accesses on the order of 1 byte/50 ns (160 Mbps) independent of the DSP’s
clock rate.
6.1.2HPI Functional Description
In C54x, information is exchanged between the host and the DSP via 8-bit external data bus but, because of the 16-bit
word structure of the C54, all transfers consist of two consecutive bytes. The dedicated HWIL pin indicates whether
the first or second byte is being transferred. Bits 0 and 8 (BOB) in the HPI control register determines whether the
first byte is MSB or LSB. The host must not break the first/second byte sequence, otherwise the data may be lost or
some unpredictable results may happen.
6.1.3HPI Registers
The HPI utilizes three registers for communication between the host device and the CPU. These registers are:
•HPI address register (HPIA). It is directly accessible only by the host and contains the address in HPI
memory at which the current address access occurs.
•HPI control register (HPIC). It is directly accessed by the host or by C54x and contains the control and
status bits for HPI operation.
6−1
•HPI data register (HPID). This register is directly accessible by the host and contains the data that was
read from the HPI memory if the current access is a read, or the data that will be written to the HPI
memory if the current access is a write.
The two control inputs, HCNTL1 and HCNTL0, indicate which internal register is being accessed as shown below.
Table 6−1. C54X HPI Registers Access Control
HCNTL1HCNTL0DESCRIPTION
00PCI2040 read/write to HPI control register.
01
10PCI2040 read/write to HPI address register.
11
PCI2040 read/write to HPI data register. Address auto-increment is
selected.
PCI2040 read/write to HPI data register. Address auto-increment is
not selected.
HPI control register is a 16-bit register but only 4 bits control the HPI operation. Because the transfer consists of two
consecutive half-words, the HPI control register is organized such that it has the same high and low half-word
contents. The control and status bits are located on the least significant 4 bits. When the host writes to the HPI control
register, both bytes must be the same.
6−2
6.2C54X HPI Control Register
Bit1514131211109876543210
NameC54X HPI control
Host TypeRRRRR/WWRR/WRRRRR/WWRR/W
DSP TypeRRRRR/W−R/W−RRRRR/W−R/W−
Default0000000000000000
Table 6−2. C54X HPI Control Register Description
BITFIELD NAME HOST TYPE DSP TYPEFUNCTION
15−12
11HINTR/WR/W
10DSPINTW−
9SMODRR/W
8BOBR/W−
7−4RSVDRRReserved. These bits return 0s when read.
3HINTR/WR/W
2DSPINTW−
1SMODRR/W
0BOBR/W−
RSVD
R
R
Reserved. These bits return 0s when read.
This bit determines the state of the DSP HINT output which is used to generate an interrupt
to the host. HINT= 0 after reset. The HINT can be set only by the DSP by writing a 1 to
this bit and can be cleared only by the host writing a 1 to this bit.
Host to DSP interrupt. This bit can only be written by the host and is not readable by the
host or the DSP. When the host writes a 1 to this bit, an interrupt is generated to the DSP.
Writing a 0 has no effect.
This bit determines the mode of operation.
0 = HOM is selected (Always during reset)
1 = SAM is selected
BOB affects both data and address transfers. Only the host can modify this bit and it is
not visible to the DSP. BOB must be initialized before the first data or address register
access.
0 = First byte is the MS
1 = First byte is the LS
This bit determines the state of the DSP HINT output which is used to generate an interrupt
to the host. HINT= 0 after reset. The HINT can be set only by the DSP by writing a 1 to
this bit and can be cleared only by the host writing a 1 to this bit.
Host to DSP interrupt. This bit can only be written by the host and is not readable by the
host or the DSP. When the host writes a 1 to this bit, an interrupt is generated to the DSP.
Writing a 0 has no effect.
This bit determines the mode of operation.
0 = HOM is selected (always during reset)
1 = SAM is selected
BOB affects both data and address transfers. Only the host can modify this bit and it is
not visible to the DSP. BOB must be initialized before the first data or address register
access.
0 = First byte is MS
1 = First byte is the LS
6.2.1Auto Increment Feature
The HPI data register can be accessed with optional auto-address increment. It provides a convenient way of reading
or writing to subsequent word locations. In the auto-increment mode, the data read causes a postincrement of the
HPI address register and a data write causes a preincrement of the HPI address register. Because the HPI has
2Kx16-bit memory , it uses only the 11 LSBs of the HPI address register but, during the auto-increment operation, all
16 bits will be incremented or decremented.
6.2.2Interrupts
DSP can interrupt the host by writing to bit 3 (HINT) of the HPI control register. By writing a 1 by the DSP to the HINT
bit of the HPI control register, the HPI can assert its HINT
can acknowledge and clear this bit by writing a 1 to this bit. Writing a 0 to the HINT bit has no effect.
pin that is connected to the HINT pin of PCI2040. The host
6−3
A C54x interrupt is generated when the host writes a 1 to the DSPINT bit (bit 2) of the HPI control register. This
interrupt can be used to wake up DSP from IDLE. The host and C54x always read this bit as 0. Once a 1 is written
to DSPINT by the host, a 0 need not be written before generating another interrupt. A DSP write or writing a 0 to this
bit has no effect.
The host should not write a 1 to the DSPINT bit while writing to BOB or HINT and the DSP should not write a 1 to the
HINT bit while writing to SMOD bit or an unwanted interrupt will be generated.
6.2.3Four Strobes (HDS1, HDS2, HR/W, HAS)
HPI has four strobes and they are:
The HCS
•Two data strobes (HDS1
•Read/write strobe (HR/W
•Address strobe (HAS
input serves primarily as the enable input for the HPI and HDS1 and HDS2 control the HPI data transfer.
and HDS2)
)
)
The equivalent circuit of these three inputs is shown in the figure below. This figure shows that the internal strobe
signal that samples the HCNTL1, HCNTL0, HWIL, and HR/W
signals. So the latest of the HCS
, HDS1, and HDS2 control the sampling of these inputs.
HDS1
HDS2
HCS
(when HAS is not used) is derived from all three input
Internal Strobe
Figure 6−1. C54X Select Input Logic
6.2.4Wait States
The HPI ready pin (HRDY) allows insertion of wait states to allow deferred completion of access cycles for hosts that
have faster cycle times that the HPI can accept due to C54x operating clock rates. The PCI2040 has four HRDY
signals, one for each DSP. The HRDY signal will automatically adjust the host access rate to a faster DSP clock rate
or switch the HPI mode (to HOM) for faster access.
6.2.5Host Read/Write Access to HPI
The host begins accessing the HPI interface first by initializing the HPI control register, then by initializing the HPI
address register, and then by reading data from or writing data to the HPI data register. Writing to the HPI address
or HPI data register initiates an internal cycle that transfers the desired data between the HPI data register and the
internal HPI memory . This process may take several cycles. Each time an access is made, data written to HPI data
register is not written to HPI memory until after the host access cycle and the data read from HPI data register is the
data from the previous cycle. Therefore, when reading, the data is obtained from the location specified in the previous
access and the current access serves as an initiation of the next cycle. A similar operation occurs for the write
operation. The data written to the HPI data register is not written to HPI memory until after the external cycle is
completed. If the HPI data register read operation immediately follows an HPI data register write operation, then the
same data (the data written) is read.
During random transfers or sequential transfers selected with auto-increment with a significant amount of time
between them, the HPI address register must be either rewritten, or two reads from the same location must be done,
or an address write prior to read must be made to ensure that the most recent data is read because the DSP may
have changed the contents of the location being accessed.
In SAM, the HRDY signal is used to insert wait states if necessary. However, this signal is inactive in HOM. Unless
back-to-back transfers are being performed, HRDY signal is normally high when the first byte of the cycle is
transferred. HRDY is always high when HCS
is high and it is not used and stays high in SAM when reading the HPI
control or HPI address register or writing to the HPI control register (except writing a 1 to either DSPINT or HINT).
6−4
6.2.6HPI Memory Access During Reset
The DSP is not operational during reset, but the host can access the HPI hereby allowing the program or data to be
downloaded to the HPI memory. However to use this capability, it is convenient for the host to control the DSP’s reset.
Initially, the host stops accessing the HPI at least six DSP periods before driving the DSP reset line low. The HPI mode
is set to HOM during the reset and the host can start accessing the HPI after four DSP periods.
Once the host has finished downloading into the HPI memory, the host stops accessing the HPI and drives the C5x
reset line. At least 20 clock periods after the reset line rising high, the host can again start accessing the HPI. HPI
mode is automatically set to SAM upon exiting reset.
6.2.7Examples of Transactions Targeting the C54X
In order to describe how the PCI2040 translates PCI cycles into 8-bit host port transactions the following examples
are provided. In each example, the following information is common:
1. The control space base address (PCI offset 14h) contains FFEF0000h.
2. There are four TMS320C5410s behind the PCI2040.
6.2.7.1 PCI Word Write
In the first example depicted in Figure 6−2, a PCI write transaction with address FFEF1800, byte enables of 1100b,
and a single data phase of the PCI bus occurs. The data is DDCCBBAAh. The PCI2040 takes this PCI transaction
and translates it to an 8-bit host port transaction. The event flow is as follows:
1. The host port is idle.
2. HCNTL0 and HCNTL1 are driven high indicating to the C5410 that this transaction is going to target the
HPID without auto-increment enabled. The HR/W
is a write.
3. HCS0
4. The PCI2040 samples the state of HRDY5X0. If the C5410 indicates it is not ready, then the PCI2040 waits
5. Because the state of the HRDY5X0 signal indicates the C5410 is ready, the PCI2040 deasserts HDS
6. During clock 6, the PCI2040 starts driving the second byte or half word onto the HAD bus. Please note that
7. Same as Step 4.
8. Same as Step 5 except the data latched is BBh and the HCS0
is asserted indicating that this transaction is targeting DSP0. The first byte or half-word is driven onto
the HAD bus. Notice the upper eight data lines (HAD15−HAD8) are not used. Only the lower eight data lines
are used when communicating with the C5410. Also, during clock 3, the HDS
the C5410 latches the values of HCNTL1, HCNTL0, HWIL, and HR/W
until the C5410 indicates it is ready before it deasserts HDS
C5410 latches the data, AAh, on the rising edge of HDS
the PCI bus uses little endian notation. For this reason, the PCI2040 transfers the least significant byte first
followed by the next least significant byte.
transaction.
is driven low indicating to the C5410 that this transaction
is asserted. During this time,
.
and HWIL.
. The
. The HWIL is driven high.
is deasserted indicating the end of the
6−5
12345678
PCI_CLK
HRST0
HCS0
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HRDY5X0
XXAAXXBB
Figure 6−2. Word Write To HPID Without Auto-Increment Enabled
6.2.7.2 PCI Word Read
The second example outlined in Figure 6−3 shows how the PCI2040 translates a word read on the PCI bus with a
PCI address of FFEF5800h. The event flow is as follows:
1. The host port is idle.
2. HCNTL0 and HCNTL1 are driven high indicating to the C5410 that this transaction is going to target the
HPID without auto-increment enabled. The HR/W
is a read.
is driven high indicating to the C5410 that this transaction
3. HCS2
is asserted indicating that this transaction is targeting DSP0. The first byte or half-word is driven onto
the HAD bus. Also during clock 3 the HDS
HCNTL1, HCNTL0, HWIL, and HR/W
is asserted. During this time, the C5410 latches the values of
.
4. The PCI2040 samples the state of HRDY5X0. If the C5410 indicates it is not ready, then the PCI2040 waits
until the C5410 indicates it is ready before it deasserts HDS
and HWIL. In this case, the C5410 is not ready .
5. Same as Step 4 but in this case the C5410 is ready.
6. The PCI2040 drives both HDS
and HWIL high. The PCI2040 also latches the data on the lower eight data
lines (HAD7−HAD0).
7. Same as Step 3.
8. Same as Step 5.
9. Same as Step 6 except the data latched is BBh and HCS2
is deasserted indicating the end of the
transaction. The PCI2040 then places XXXXBBAAh on the PCI bus.
6−6
12 3 4 567 8 9
PCI_CLK
HRST2
HCS2
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HRDY5X2
ZZZZZZAAZZBB
Figure 6−3. Word Write From HPID Without Auto-Increment Enabled
6.2.7.3 PCI Double Word Write
In the third example depicted in Figure 6−4, a PCI write transaction with address FFEF3800, byte enables of 0000b,
and a single data phase occurs of the PCI bus. The data is DDCCBBAAh. The PCI2040 takes this PCI transaction
and translates it to an 8-bit host port transaction. This example is a little different than a normal write due to the fact
that this PCI transaction is specifying a write to HPID without auto-increment selected. Typically, when performing
a doubleword read or write to the HPID, the PCI address should specify HPID with auto-increment selected. Because
auto-increment was not selected, the PCI2040 attempts to place the data in two different locations in the DSP’s
memory. The event flow is as follows:
1. The host port is idle.
2. HCNTL0 and HCNTL1 are driven high indicating to the C5410 that this transaction is going to target the
HPID without auto-increment enabled. The HR/W
is driven low indicating to the C5410 that this transaction
is a write.
3. HCS1
is asserted indicating that this transaction is targeting DSP1. The first byte or half-word is driven onto
the HAD bus. Also during clock 3 the HDS
HCNTL1, HCNTL0, HWIL, and HR/W
is asserted. During this time, the C5410 latches the values of
.
4. The PCI2040 samples the state of HRDY5X0. If the C5410 indicates it is not ready, then the PCI2040 waits
until the C5410 indicates it is ready before it deasserts HDS
5. Because the state of the HRDY5X0 signal indicates the C5410 is ready, the PCI2040 deasserts HDS
C5410 latches the data, AAh, on the rising edge of HDS
and HWIL.
. The
. The HWIL is driven high.
6. Same as Step 3.
7. Same as Step 4 except the HCNTL1 is driven low. Because a write to the HPID with auto-increment select
will pre-increment the HPIA, the HCNTL1 is driven low to increment the HPIA. This places the most
significant word of the PCI data to a different location in the DSP’s memory than the least significant word
was placed.
8. Same as Step 5 except the data latched by the C5410 is BBh.
9. Same as Step 3.
10. Same as Step 4.
11. Same as Step 5 except the data latched by the C5410 is CCh.
6−7
12. Same as Step 3.
13. Same as Step 4.
14. Same as Step 5 except the data latched is DDh and the HCS1
transaction.
12 345 67891011121314
PCI_CLK
HRST1
HCS1
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HRDY5X1
XXAAXXBBXXCCXXDD
Figure 6−4. Doubleword Write To HPID Without Auto-Increment Enabled
6.2.7.4 PCI Double Word Read
is deasserted indicating the end of the
The fourth example is very similar to the third example. In this case the transaction is a PCI doubleword read. The
steps involved in performing this translation are very similar to the doubleword write example. The important thing
to note is a read from the HPID with auto-increment selected causes the HPIA to be post-incremented.
1 234 567891011121314
PCI_CLK
HRST
HCS
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HRDY5X
ZZZZZZAAZZBBZZCCZZDD
Figure 6−5. Doubleword Read From HPID Without Auto-Increment Enabled
6.3C6X HPI Interface
The HPI interface for C6x is similar to C54x HPI port except for the following:
6.3.1No SAM or HOM Modes
The C6x HPI interface has only one mode of operation which does not support C54x SAM or HOM.
6−8
6.3.2Address/Data Bus
The HPI provides 32-bit data to the CPU with a 16-bit wide parallel external interface (C54x has 8-bit wide external
interface). All transfers with the host consist of two consecutive half-words. On the HPI data register data write access,
HBE1
and HBE0 (byte enables) select the bytes in 32-bit word to be written. For the HPI address register, HPI control
register, and HPI data register read, byte enables are not used. The HWIL pin determines whether the first or second
byte is being transferred and HWOB bit in the HPI control register (see Section 6.3.5) determines whether the first
half-word is most significant or least significant. The host must not break the first half-word/second half-word
sequence or data may be lost, in the case of full word access.
6.3.3Byte Enables (HBE0 and HBE1)
On the HPI data register writes, the value of HBE0 and HBE1 indicate which bytes of the 32-bit word are written. The
value of byte enables, as mentioned earlier, is not important on HPI address or HPI control register accesses and
HPI data register reads. On HPI data register writes, the HBE0
HBE1
determines the most significant byte in the half-word. Following combinations for the HBE0/HBE1 are allowed:
enables the least significant byte in the half-word while
•For byte writes, one HBEn
•For half-word writes, both HBE0
half-words).
•For complete word writes, both HBE0
•No other combinations are valid.
in either of the half-word accesses can be enabled.
and HBE1 must be active low in either half-word access (but not both
and HBE1 must be held active low in both half-word accesses
6.3.4Wait States
In C6x based systems, wait states can be inserted either using HRDY signal as in the case of C54X, or using the
HRDY bit in the HPI control register (see Section 6.3.5).
6−9
6.3.5C6X HPI Registers
C6x contains HPI address, HPI control, and HPI data registers, and these registers have a 32-bit structure as opposed
to the 16-bit structure in the C54x HPI interface.
The HCNTL0/1 control access to the HPI registers as described below. Note that it is different from C54x.
Table 6−3. HCNTL0 and HCNTL1 in C6X
HCNTL1HCNTL0DESCRIPTION
00PCI2040 read/write to HPI control register
01PCI2040 read/write to HPI address register
10
11
Bit31302928272625242322212019181716
NameC6X HPI control
Host TypeRRRRRRRRRRRR/WRR/WR/WR/W
DSP TypeRRRRRRRRRRRRRR/WRR
Default0000000000000111
Bit1514131211109876543210
NameC6X HPI control
Host TypeRRRRRRRRRRRR/WRR/WR/WR/W
DSP TypeRRRRRRRRRRRRRR/WRR
Default0000000000000000
PCI2040 read/write to HPI data register. Address auto-increment is
selected.
PCI2040 read/write to HPI data register. Address auto-increment is
not selected.
6−10
Table 6−4. C6X HPI Control Register
BITFIELD NAME HOST TYPE DSP TYPEFUNCTION
31−21RSVDRRReserved. Bits 31−21 return 0s when read.
Host fetch request. The value read by the host or the CPU is always 0. Only host can write
20FETCH
19HRDY
18HINT
17DSPINTHost-to-DSP interrupt.
16HWOB
15−5RSVDRRReserved. Bits 15−5 return 0s when read.
4FETCH
3HRDY
2HINT
1DSPINTHost-to-DSP interrupt.
0HWOB
to this register. When host writes 1 to this bit, it requests a fetch into HPI data register of
the word at the word pointed to by HPI address register. Note that the value of 1 is never
actually written to this bit.
Ready signal to host. It is not masked by the HCS as the HRDY pin is.
0 = Host is busy; the internal bus is waiting for an HPI data request to finish.
1 = Host is ready to transfer data
DSP-to-host interrupt. The inverted value of this bit determines the state of the HINT
output.
HWOB affects both data and address transfers. Only the host can modify this bit and it is
read-only to the DSP. HWOB must be initialized before the first data or address register
access.
0 = First byte is the MS
1 = First byte is the LS
Host fetch request. The value read by the host or the CPU is always is 0. Only host can
write to this register . When host writes 1 to this bit, it requests a fetch into HPI data register
of the word at the word pointed to by HPI address register. Note that the value of 1 is never
actually written to this bit.
Ready signal to host. It is not masked by the HCS as the HRDY pin is.
0 = Host is busy; the internal bus is waiting for an HPI data request to finish.
1 = Host is ready to transfer data
DSP-to-host interrupt. The inverted value of this bit determines the state of the HINT
output.
HWOB affects both data and address transfers. Only the host can modify this bit and it is
read-only to the DSP. HWOB must be initialized before the first data or address register
access.
0 = First byte is the MS
1 = First byte is the LS
6.3.6Software Handshaking Using HRDY and FETCH
Software handshaking using HRDY and FETCH bits in the HPI control register is a C6x feature not supported in
PCI2040 because it will support HRDY
pin from DSP to host for insertion of wait states.
6−11
6.3.7Host Access Sequence
The host access sequence in C6x is similar to C54x except for the HPI data register write. The host begins accessing
HPI by initializing the HPI control register, then by initializing the HPI address register, and then by writing data to or
reading data from the HPI data register. Reading or writing to the HPI data register initiates an internal cycle that
transfers the desired data between the HPI data register and DMA auxiliary channel. Typically, host does not break
the first half-word/second half-word sequence. If this sequence is broken, then the data is lost. During the HPI data
register write however, HBE0
Enables (HBE0
and HBE1), for more details.
/HBE1 enable the individual bytes in the half-word. Please see Section 6.3.3, Byte
6.3.8Single Half-Word Cycles
In the normal operation, every transfer must consist of two half-word accesses. However, to speed the operation, the
C6x allows single half-word accesses. The PCI2040 does not support the half-word cycles.
6.3.9Memory Access Through HPI During Reset
During the reset, when HCS is active low and HRDY is inactive high, and vice versa, the HPI can not be used but
certain boot modes can allow the host to write to the CPU’s memory space including configuring the EMIF
configuration registers to define external memory before accessing it. Note that the device is not in reset during these
boot modes but the CPU itself is in reset until the boot completes.
6.3.10 Examples of Transactions Targeting the C6X
The following two figures depict typical transactions on the HPI bus which are targeting a C6X. Both of these figures
are very similar with one being a write transaction and the other being a read transaction. Because both transactions
are similar, the following event flow can be used to describe both transactions.
1. The host port is idle.
2. HCNTL0 and HCNTL1 are driven high indicating to the C6X that this transaction is going to target the HPID
w/o auto-increment enabled. The HR/W
3. HCS0
4. The PCI2040 will sample the state of HRDY6X0
5. Because the state of the HRDY6X0
6. Same as Step 3.
7. Same as Step 4.
8. Same as Step 5 except HCS0
is asserted indicating that this transaction is targeting DSP0. The first two bytes or half−word is driven
onto the HAD bus. Both HBE1
this time, the C6X will latch the values of HCNTL1, HCNTL0, HWIL, and HR/W
wait until the C6X indicates it is ready before it deasserts HDS
C6X latches the data, BBAAh, on the rising edge of HDS
the value of HBE1
bytes of the half-word are valid.
and HBE0. In this example, both these signals are low indicating to the C6X that both
and HBE0 are driven low. Also during clock 3 the HDS is asserted. During
is deasserted indicating the transaction has completed.
is driven low indicating to the C6X that this transaction is a write.
.
. If the C6X indicates it is not ready, then the PCI2040 will
and HWIL.
signal indicates the C6X is ready, the PCI2040 deasserts HDS. The
. The HWIL is driven high. The C6X also latches
6−12
12345678
PCI_CLK
HRST0
HCS0
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HBE0
HBE1
HRDY6X0
BBAADDCC
Figure 6−6. Double Word Write To HPID Without Auto-Increment Selected
12 34 567 8
PCI_CLK
HRST0
HCS0
HAD[15:0]
HCNTL0
HCNTL1
HWIL
HDS
HR/W
HBE0
HBE1
HRDY6X0
BBAADDCC
Figure 6−7. Double Word Read From HPID Without Auto-Increment Selected
6−13
6−14
7 Electrical Characteristics
7.1Absolute Maximum Ratings Over Operating Temperature Ranges
Output clamp current, I
Storage temperature range, T
Virtual junction temperature, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies to external input and bidirectional buffers. For 5V tolerant, use VI > V
2. Applies to external output and bidirectional buffers. For 5V tolerant, use VI > V
The PCI2040 is packaged in either a 144-ball GGU BGA or a 144-pin PGE package. The following shows the
mechanical dimensions for the GGU and PGE packages.
GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY
0,95
0,85
12,10
11,90
SQ
1,40 MAX
N
M
L
K
J
H
G
F
E
D
C
B
A
1
Seating Plane
0,80
42 3
9,60 TYP
5
0,80
12 1310 118967
0,12
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Micro Star BGA configuration
Micro Star is a trademark of Texas Instruments Incorporated.
0,55
0,45
0,08
M
0,45
0,35
0,10
4073221/A 11/96
8−1
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK
109
144
1,45
1,35
108
73
72
0,27
0,17
0,50
37
1
17,50 TYP
20,20
SQ
19,80
22,20
SQ
21,80
36
0,05 MIN
0,08
0,25
0,75
0,45
M
0,13 NOM
Gage Plane
0°−ā 7°
1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
8−2
Seating Plane
0,08
4040147/C 11/96
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