TEXAS INSTRUMENTS PCI1510 Technical data
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查询PCI1510供应商
Data Manua
December 2004 Connectivity Solutions
SCPS071E
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Contents
Section Title Page
1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Trademarks 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Document Conventions 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Ordering Information 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 PCI1510 Data Manual Document History 1−3. . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 PCI1510 Terminal Assignments 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Terminal Descriptions 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Power Supply Sequencing 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 I/O Characteristics 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Clamping Voltages 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Component Interconnect (PCI) Interface 3−2. . . . . . . . . . . . . .
3.4.1 PCI GRST
3.4.2 PCI Bus Lock (LOCK
3.4.3 Loading Subsystem Identification 3−3. . . . . . . . . . . . . . . . . . . . .
3.5 PC Card Applications 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 PC Card Insertion/Removal and Recognition 3−4. . . . . . . . . . .
3.5.2 Parallel Power-Switch Interface (TPS2211A) 3−4. . . . . . . . . . .
3.5.3 Zoomed Video Support 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Standardized Zoomed-Video Register Model 3−6. . . . . . . . . . .
3.5.4.1 Zoomed-Video Card Insertion and Configuration
3.5.5 Internal Ring Oscillator 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Integrated Pullup Resistors 3−7. . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 SPKROUT and CAUDPWM Usage 3−8. . . . . . . . . . . . . . . . . . .
3.5.8 LED Socket Activity Indicators 3−8. . . . . . . . . . . . . . . . . . . . . . . .
3.5.9 CardBus Socket Registers 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Serial-Bus Interface 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Serial-Bus Interface Implementation 3−9. . . . . . . . . . . . . . . . . . .
3.6.2 Serial-Bus Interface Protocol 3−10. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Serial-Bus EEPROM Application 3−12. . . . . . . . . . . . . . . . . . . . . .
3.6.4 Accessing Serial-Bus Devices Through Software 3−13. . . . . . .
Signal 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
) 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Procedure 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Title Page
3.7 Programmable Interrupt Subsystem 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 PC Card Functional and Card Status Change Interrupts 3−13.
3.7.2 Interrupt Masks and Flags 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Using Parallel IRQ Interrupts 3−15. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Using Parallel PCI Interrupts 3−16. . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Using Serialized IRQSER Interrupts 3−16. . . . . . . . . . . . . . . . . . .
3.7.6 SMI Support in the PCI1510 Controller 3−16. . . . . . . . . . . . . . . .
3.8 Power Management Overview 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) 3−17. . . .
3.8.2 Clock Run Protocol 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 CardBus PC Card Power Management 3−17. . . . . . . . . . . . . . . .
3.8.4 16-Bit PC Card Power Management 3−17. . . . . . . . . . . . . . . . . . .
3.8.5 Suspend Mode 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.6 Requirements for Suspend Mode 3−18. . . . . . . . . . . . . . . . . . . . .
3.8.7 Ring Indicate 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8 PCI Power Management 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.9 CardBus Bridge Power Management 3−20. . . . . . . . . . . . . . . . . .
3.8.10 ACPI Support 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.11 Master List of PME Context Bits and Global Reset-Only
Bits 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 PC Card Controller Programming Model 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Configuration Registers 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Vendor ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Device ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Command Register 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Status Register 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Revision ID Register 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 PCI Class Code Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Cache Line Size Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Latency Timer Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket/ExCA Base-Address Register 4−6. . . . . . . . . . . . . . . . . .
4.13 Capability Pointer Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Base Registers 0, 1 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Limit Registers 0, 1 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 I/O Base Registers 0, 1 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Title Page
4.22 I/O Limit Registers 0, 1 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base Address Register 4−13. . . . . . . . .
4.29 System Control Register 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 Multifunction Routing Register 4−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Retry Status Register 4−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Card Control Register 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 Device Control Register 4−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 Diagnostic Register 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 Capability ID Register 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.36 Next-Item Pointer Register 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 Power-Management Capabilities Register 4−21. . . . . . . . . . . . . . . . . . . . . .
4.38 Power-Management Control/Status Register 4−22. . . . . . . . . . . . . . . . . . . .
4.39 Power-Management Control/Status Register Bridge Support
Extensions 4−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 Power-Management Data Register 4−23. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 General-Purpose Event Status Register 4−24. . . . . . . . . . . . . . . . . . . . . . . .
4.42 General-Purpose Event Enable Register 4−25. . . . . . . . . . . . . . . . . . . . . . .
4.43 General-Purpose Input Register 4−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.44 General-Purpose Output Register 4−26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.45 Serial-Bus Data Register 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 Serial-Bus Index Register 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Serial-Bus Slave Address Register 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Serial-Bus Control and Status Register 4−29. . . . . . . . . . . . . . . . . . . . . . . . .
5 ExCA Compatibility Registers 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 ExCA Identification and Revision Register 5−4. . . . . . . . . . . . . . . . . . . . . .
5.2 ExCA Interface Status Register 5−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 ExCA Power Control Register 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ExCA Interrupt and General Control Register 5−8. . . . . . . . . . . . . . . . . . .
5.5 ExCA Card Status-Change Register 5−9. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ExCA Card Status-Change Interrupt Configuration Register 5−10. . . . . . .
5.7 ExCA Address Window Enable Register 5−11. . . . . . . . . . . . . . . . . . . . . . . .
5.8 ExCA I/O Window Control Register 5−12. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5−13. . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5−13. . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5−13. . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5−13. . . .
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers 5−14. . .
v
Section Title Page
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers 5−14. . .
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers 5−15. . . .
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers 5−15. . .
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers 5−16. .
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers 5−16.
5.19 ExCA Card Detect and General Control Register 5−17. . . . . . . . . . . . . . . .
5.20 ExCA Global Control Register 5−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5−19. . .
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5−19. . .
5.23 ExCA Memory Windows 0−4 Page Registers 5−19. . . . . . . . . . . . . . . . . . .
6 CardBus Socket Registers 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Socket Event Register 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Socket Mask Register 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Socket Present-State Register 6−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Socket Force Event Register 6−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Socket Control Register 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Socket Power-Management Register 6−8. . . . . . . . . . . . . . . . . . . . . . . . . .
7 Electrical Characteristics 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges 7−1.
7.2 Recommended Operating Conditions 7−2. . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Electrical Characteristics Over Recommended Operating
Conditions 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature 7−3. . . . . . . . . . . . .
7.5 PCI Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature 7−4. . . . . . . . . . . . . . . . . . . .
8 Mechanical Information 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Illustrations
Figure Title Page
2−1 PCI1510 GGU-Package Terminal Diagram 2−1. . . . . . . . . . . . . . . . . . . . . . . . .
2−2 PCI1510 GVF-Package Terminal Diagram 2−2. . . . . . . . . . . . . . . . . . . . . . . . .
2−3 PCI1510 PGE-Package Terminal Diagram 2−3. . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PCI1510 Simplified Block Diagram 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 3-State Bidirectional Buffer 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 TPS2211A Typical Application 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Zoomed Video Implementation Using the PCI1510 Controller 3−5. . . . . . . . .
3−5 Zoomed Video Switching Application 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Sample Application of SPKROUT and CAUDPWM 3−8. . . . . . . . . . . . . . . . . .
3−7 Two Sample LED Circuits 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 Serial EEPROM Application 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Serial-Bus Start/Stop Conditions and Bit Transfers 3−10. . . . . . . . . . . . . . . . . .
3−10 Serial-Bus Protocol Acknowledge 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Serial-Bus Protocol − Byte Write 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Serial-Bus Protocol − Byte Read 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 EEPROM Interface Doubleword Data Collection 3−12. . . . . . . . . . . . . . . . . . . .
3−14 IRQ Implementation 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Signal Diagram of Suspend Function 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 RI_OUT
3−17 Block Diagram of a Status/Enable Cell 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Register Access Through I/O 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Register Access Through Memory 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Accessing CardBus Socket Registers Through PCI Memory 6−1. . . . . . . . . .
Functional Diagram 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
List of Tables
Table Title Page
2−1 Signal Names Sorted by PGE Terminal Number 2−4. . . . . . . . . . . . . . . . . . . .
2−2 Signal Names Sorted by GGU Terminal Number 2−6. . . . . . . . . . . . . . . . . . . .
2−3 Signal Names Sorted by GVF Terminal Number 2−8. . . . . . . . . . . . . . . . . . . .
2−4 CardBus PC Card Signal Names Sorted Alphabetically to Device
Terminals 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 16-Bit PC Card Signal Names Sorted Alphabetically to Device
Terminals 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Power Supply Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 PC Card Power Switch Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 PCI System Terminals 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 PCI Address and Data Terminals 2−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 PCI Interface Control Terminals 2−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Multifunction and Miscellaneous Terminals 2−19. . . . . . . . . . . . . . . . . . . . . . . . .
2−12 16-Bit PC Card Address and Data Terminals 2−20. . . . . . . . . . . . . . . . . . . . . . .
2−13 16-Bit PC Card Interface Control Terminals 2−21. . . . . . . . . . . . . . . . . . . . . . . . .
2−14 CardBus PC Card Interface System Terminals 2−22. . . . . . . . . . . . . . . . . . . . . .
2−15 CardBus PC Card Address and Data Terminals 2−23. . . . . . . . . . . . . . . . . . . . .
2−16 CardBus PC Card Interface Control Terminals 2−24. . . . . . . . . . . . . . . . . . . . . .
3−1 PC Card Card-Detect and Voltage-Sense Connections 3−4. . . . . . . . . . . . . .
3−2 Zoomed-Video Card Interrogation 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Integrated Pullup Resistors 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 CardBus Socket Registers 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Register- and Bit-Loading Map 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 PCI1510 Registers Used to Program Serial-Bus Devices 3−13. . . . . . . . . . . . .
3−7 Interrupt Mask and Flag Registers 3−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 PC Card Interrupt Events and Description 3−14. . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 SMI Control 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Requirements for Internal/External 2.5-V Core Power Supply 3−17. . . . . . . . .
3−11 Power-Management Registers 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 PCI Configuration Registers 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Bit Field Access Tag Descriptions 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Command Register Description 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Status Register Description 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Secondary Status Register Description 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Bridge Control Register Description 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 System Control Register Description 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Multifunction Routing Register Description 4−16. . . . . . . . . . . . . . . . . . . . . . . . .
4−9 Retry Status Register Description 4−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
Table Title Page
4−10 Card Control Register Description 4−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Device Control Register Description 4−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 Diagnostic Register Description 4−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 Power-Management Capabilities Register Description 4−21. . . . . . . . . . . . . . .
4−14 Power-Management Control/Status Register Description 4−22. . . . . . . . . . . . .
4−15 Power-Management Control/Status Register Bridge Support Extensions
Description 4−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 General-Purpose Event Status Register Description 4−24. . . . . . . . . . . . . . . . .
4−17 General-Purpose Event Enable Register Description 4−25. . . . . . . . . . . . . . . .
4−18 General-Purpose Input Register Description 4−26. . . . . . . . . . . . . . . . . . . . . . . .
4−19 General-Purpose Output Register Description 4−26. . . . . . . . . . . . . . . . . . . . . .
4−20 Serial-Bus Data Register Description 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 Serial-Bus Index Register Description 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 Serial-Bus Slave Address Register Description 4−28. . . . . . . . . . . . . . . . . . . . .
4−23 Serial-Bus Control and Status Register Description 4−29. . . . . . . . . . . . . . . . . .
5−1 ExCA Registers and Offsets 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Identification and Revision Register Description 5−4. . . . . . . . . . . . . . .
5−3 ExCA Interface Status Register Description 5−5. . . . . . . . . . . . . . . . . . . . . . . .
5−4 ExCA Power Control Register Description—82365SL Support 5−6. . . . . . . .
5−5 ExCA Power Control Register Description—82365SL-DF Support 5−7. . . . .
5−6 ExCA Interrupt and General Control Register Description 5−8. . . . . . . . . . . .
5−7 ExCA Card Status-Change Register Description 5−9. . . . . . . . . . . . . . . . . . . .
5−8 ExCA Card Status-Change Interrupt Configuration Register
Description 5−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 ExCA Address Window Enable Register Description 5−11. . . . . . . . . . . . . . . .
5−10 ExCA I/O Window Control Register Description 5−12. . . . . . . . . . . . . . . . . . . . .
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
Description 5−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers
Description 5−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers
Description 5−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 ExCA Card Detect and General Control Register Description 5−17. . . . . . . . .
5−15 ExCA Global Control Register Description 5−18. . . . . . . . . . . . . . . . . . . . . . . . .
6−1 CardBus Socket Registers 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Socket Event Register Description 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Socket Mask Register Description 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Socket Present-State Register Description 6−4. . . . . . . . . . . . . . . . . . . . . . . . .
6−5 Socket Force Event Register Description 6−6. . . . . . . . . . . . . . . . . . . . . . . . . .
6−6 Socket Control Register Description 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7 Socket Power-Management Register Description 6−8. . . . . . . . . . . . . . . . . . .
ix
x
1 Introduction
1.1 Description
The Texas Instruments PCI1510 device, a 144-terminal or a 209-terminal single-slot CardBus controller designed
to meet the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges, is an ultralow-power
high-performance PCI-to-CardBus controller that supports a single PC card socket compliant with the PC Card
Standard (rev. 7.2). The controller provides features that make it the best choice for bridging between PCI and PC
Cards in both notebook and desktop computers. The PC Card Standard retains the 16-bit PC Card specification
defined in the PCI Local Bus Specification and defines the 32-bit PC Card, CardBus, capable of full 32-bit data
transfers at 3 3MHz. The controller supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required.
The controller is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master
device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The
controller is also compliant with PCI Bus Power Management Interface Specification (rev. 1.1).
All card signals are internally buffered to allow hot insertion and removal without external buffering. The controller
is register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The controller internal data path
logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance.
Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting.
The controller can also be programmed to accept fast posted writes to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1510 controller , such as a socket activity light-emitting
diode (LED) outputs, are discussed in detail throughout this document.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management
system to further reduce power consumption.
1.2 Features
The controller supports the following features:
• A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball-grid array (GGU/ZGU) package,
or a 209-terminal PBGA (GVF/ZVF) package
• 2.5-V core logic and 3.3-V I/O with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling
environments
• Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5-V power supply
• Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
• A single PC Card or CardBus slot with hot insertion and removal
• Parallel interface to TI TPS2211A single-slot PC Card power switch
• Burst transfers to maximize data throughput with CardBus Cards
• Interrupt configurations: parallel PCI, serialized PCI, parallel ISA, and serialized ISA
• Serial EEPROM interface for loading subsystem ID, subsystem vendor ID, and other configuration registers
• Pipelined architecture for greater than 130-Mbps throughput from CardBus-to-PCI and from PCI-to-
CardBus
1−1
• Up to five general-purpose I/Os
• Programmable output select for CLKRUN
• Five PCI memory windows and two I/O windows available for the 16-bit interface
• Two I/O windows and two memory windows available to the CardBus socket
• Exchangeable-card-architecture- (ExCA-) compatible registers are mapped in memory and I/O space
• Intel 82365SL-DF and 82365SL register compatible
• Ring indicate, SUSPEND
• Socket activity LED terminal
• PCI bus lock (LOCK
• Internal ring oscillator
, PCI CLKRUN, and CardBus CCLKRUN
)
1.3 Related Documents
• Advanced Configuration and Power Interface (ACPI) Specification (revision 1.1)
• PCI Bus Power Management Interface Specification (revision 1.1)
• PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (revision 0.6)
• PCI to PCMCIA CardBus Bridge Register Description (Yenta) (revision 2.1)
• PCI Local Bus Specification (revision 2.2)
• PCI Mobile Design Guide (revision 1.0)
• PC Card Standard (revision 7.2)
• Serialized IRQ Support for PCI Systems (revision 6)
1.4 Trademarks
Intel is a trademark of Intel Corporation.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
1.5 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are listed
below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary
field.
2. T o identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit
hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number are
assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, GRST
NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. RSVD indicates that the referenced item is reserved.
6. In Sections 4 through 6, the configuration space for the controller is defined. For each register bit, the
software access method is identified in an access column. The legend for this access column includes the
following entries:
r – read-only access
1−2
), then this indicates the logical
ru – read-only access with updates by the controller internal hardware
rw – read and write access
rcu – read access with the option to clear an asserted bit with a write-back of 1b including updates by
the controller internal hardware.
1.6 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI1510 PC Card controller 3.3 V, 5-V tolerant I/Os 144-terminal LQFP
144-ball PBGA (GGU or ZGU)
209-ball PBGA (GVF or ZVF)
1.7 PCI1510 Data Manual Document History
DATE PAGE NUMBER REVISION
01/2003 2−23 Modified terminal number of CAD30 from 143 to 142 for PGE package
01/2003 3−2 Added new subsection 3.4.1 to describe GRST during power up
01/2003 3−11 Modified byte-read diagram (Figure 3−12) to better reflect a read transaction to the EEPROM
01/2003 3−20 Modified the description of the power management capabilities register. This register is not a static
08/2003 1−3 Added lead-free (Pb, atomic number 82) MicroStar BGA package (ZGU) to ordering information
08/2003 2−1 Added description for ZGU package
08/2003 8−4 Added ZGU mechanical drawing
10/2003 1−1 Added GVF package to features
10/2003 1−3 Added GVF package to ordering information
10/2003 2−8 Added GVF terminal descriptions, Table 2−3
10/2003 8−2 Added GVF mechanical drawing.
07/2004 Chapters 1, 2, 8 Added RGVF, RZVF, and ZVF packages and pinout.
12/2004 Chapters 1, 2, 8 Removed RGVF and RZVF packages and pinout.
read-only register.
Added Section 1.5, Document Conventions
1−3
1−4
2 Terminal Descriptions
Î
The PCI1510 controller is available in five packages, a 144-terminal quad flatpack (PGE), two 144-terminal MicroStar
BGA packages (GGU/ZGU), and two 209-terminal PBGA packages (GVF/ZVF). The GGU and ZGU packages are
mechanically and electrically identical, but the ZGU is a lead-free (Pb, atomic number 82) design. Throughout the
remainder of this manual, only the GGU package designator is used for either the GGU or ZGU package. The terminal
layout for the GGU package is shown in Figure 2−1. The GVF and ZVF packages are mechanically and electrically
identical, but the ZVF is a lead-free (Pb, atomic number 82) design. Throughout the remainder of this manual, only
the GVF package designator is used for either the GVF or ZVF package. The terminal layout for the GVF package
is shown in Figure 2−2. The terminal layout with signal names for the PGE package is shown in Figure 2−3.
GGU PACKAGE
(TOP VIEW)
13
12
10
CC CC CCCCC T
CC CC CCCCT MCCC
11
9
8
7
6
5
4
3
2
1
C CC CCCCCTC
CC CC C CMMCMC
CC C TM MC
CC C PC
CC MPPC
CC C PP PPC
CC PP PPC
CC PPPPPPPPC
CC PP PPPPP PPPP
C PP PPPPPPPP
PP PPPPP PPP
A
P
PCI Interface
C
PC Card Interface
T
TPS Power Switch
M
MFUNC Pins
DB C
E
HJFG
VCC
Ground (GND)
Miscellaneous
MNKL
Figure 2−1. PCI1510 GGU-Package Terminal Diagram
2−1
GVF PACKAGE
(TOP VIEW)
19
18
17
16
15
14
13
12
11
10
N
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
9
8
C
C
C
7
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
NNNN
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
P
P
NN
N
N
N
N
N
N
N
N
N
N
N
P
P
P
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
P
P
P
P
P
P
P
P
6
5
4
T
NNN
TT
3
2
1
N
N
T
N
N
M
M
M
P
PCI Interface
C
PC Card Interface
T
TPS Power Switch
M
MFUNC Pins
M
M
MM
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
MNKLHJFGDBCAE
P
P
P
P
P
P
P
P
P
PR WTUV
P
P
P
P
P
P
VCC
Ground (GND)
Miscellaneous
N
No Connection
Figure 2−2. PCI1510 GVF-Package Terminal Diagram
2−2
2.1 PCI1510 Terminal Assignments
PGE PACKAGE
Figure 2−3 and Table 2−1 show the terminal assignments for the PGE package. Table 2−2 and Table 2−3 list the
terminal assignments for the GGU and GVF packages, respectively. The signal names for the PC Card slot are given
in a CardBus // 16-bit signal format. All tables are arranged in order by increasing terminal designator, which is
numeric for the PGE package and alphanumeric for the other packages. Table 2−4 and Table 2−5 list the CardBus
and 16-bit signal names, respectively, in alphanumerical order with the corresponding terminal numbers for each
package.
(TOP VIEW)
VCCCB
CIRDY
CFRAME
CC/BE2//A12
CAD17//A24
CAD18//A7
CAD19//A25
CVS2//VS2
CAD20//A6
//RESET
CRST
CAD21//A5
CAD22//A4
CREQ
//INPACK
CAD23//A3
CC/BE3
VR_EN
CAD24//A2
CAD25//A1
CAD26//A0
CVS1//VS1
CINT//READY(IREQ)
CSERR//WAIT
CAUDIO//BVD2(SPKR)
CSTSCHG//BVD1(STSCHG
CCLKRUN
//WP(IOIS16)
CCD2
CAD27//D0
CAD28//D8
CAD29//D1
CAD30//D9
CRSVD//D2
CAD31//D10
//A15
//A23
GND
//REG
VCC
GND
/RI)
VCC
//CD2
//A21
//A22
//WE
CCLK//A16
CDEVSEL
CTRDY
CGNT
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
1234567891011121314151617181920212223242526272829303132333435
//A19
//A14
//A20
VCC
CSTOP
CBLOCK
CPERR
101
102
103
104
CPAR//A13
CRSVD//A18
99
100
//A8
CAD16//A17
CC/BE1
97
98
CAD14//A9
CAD15//IOWR
CAD13//IORD
94
95
96
GND
93
CAD12//A11
92
CAD11//OE
CAD10//CE2
90
91
//CE1
CAD9//A10
CC/BE0
CAD8//D15
87
88
89
CAD7//D7
CLK_48_RSVD
CRSVD//D14
84
85
86
CAD5//D6
CAD6//D13
CAD3//D5
81
82
83
GND
CAD4//D12
79
80
CAD1//D4
78
CAD2//D11
CAD0//D3
76
77
//CD1
CCD1
75
VCCD1
VCCD0
73
74
36
72
VPPD1
71
VPPD0
70
VCC
69
MFUNC6
68
MFUNC5
67
MFUNC4
66
GRST
65
SUSPEND
64
MFUNC3
63
MFUNC2
62
VR_PORT
61
SPKROUT
60
GND
59
MFUNC1
58
MFUNC0
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
RI_OUT
AD0
AD1
VCC
AD2
AD3
AD4
AD5
AD6
AD7
C/BE0
AD8
AD9
AD10
AD11
AD12
AD13
GND
AD14
AD15
C/BE1
/PME
REQ
GNT
AD31
AD30
AD29
AD28
AD27
GND
AD26
AD25
AD24
VCC
C/BE3
IDSEL
AD23
AD22
AD21
AD20
PRST
PCLK
GND
AD19
AD18
AD17
AD16
C/BE2
FRAME
IRDY
Figure 2−3. PCI1510 PGE-Package Terminal Diagram
TRDY
STOP
DEVSEL
VCC
SERR
PERR
PAR
VCCP
2−3
Table 2−1. Signal Names Sorted by PGE Terminal Number
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
1 REQ REQ 43 AD11 AD11
2 GNT GNT 44 AD10 AD10
3 AD31 AD31 45 AD9 AD9
4 AD30 AD30 46 AD8 AD8
5 AD29 AD29 47 C/BE0 C/BE0
6 AD28 AD28 48 AD7 AD7
7 AD27 AD27 49 AD6 AD6
8 GND GND 50 AD5 AD5
9 AD26 AD26 51 AD4 AD4
10 AD25 AD25 52 AD3 AD3
11 AD24 AD24 53 AD2 AD2
12 V
13 C/BE3 C/BE3 55 AD1 AD1
14 IDSEL IDSEL 56 AD0 AD0
15 AD23 AD23 57 RI_OUT/PME RI_OUT/PME
16 AD22 AD22 58 MFUNC0 MFUNC0
17 AD21 AD21 59 MFUNC1 MFUNC1
18 AD20 AD20 60 GND GND
19 PRST PRST 61 SPKROUT SPKROUT
20 PCLK PCLK 62 VR_PORT VR_PORT
21 GND GND 63 MFUNC2 MFUNC2
22 AD19 AD19 64 MFUNC3 MFUNC3
23 AD18 AD18 65 SUSPEND SUSPEND
24 AD17 AD17 66 GRST GRST
25 AD16 AD16 67 MFUNC4 MFUNC4
26 C/BE2 C/BE2 68 MFUNC5 MFUNC5
27 FRAME FRAME 69 MFUNC6 MFUNC6
28 IRDY IRDY 70 V
29 TRDY TRDY 71 VPPD0 VPPD0
30 DEVSEL DEVSEL 72 VPPD1 VPPD1
31 STOP STOP 73 VCCD0 VCCD0
32 V
33 PERR PERR 75 CCD1 CD1
34 SERR SERR 76 CAD0 D3
35 PAR PAR 77 CAD2 D11
36 V
37 C/BE1 C/BE1 79 CAD4 D12
38 AD15 AD15 80 GND GND
39 AD14 AD14 81 CAD3 D5
40 GND GND 82 CAD6 D13
41 AD13 AD13 83 CAD5 D6
42 AD12 AD12 84 CRSVD D14
CC
CC
CCP
V
V
V
CC
CC
CCP
54 V
74 VCCD1 VCCD1
78 CAD1 D4
CARDBUS 16-BIT
CC
CC
SIGNAL NAME
V
CC
V
CC
2−4
Table 2−1. Signal Names Sorted by PGE Terminal Number (Continued)
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
85† CLK_48_RSVD CLK_48_RSVD 115 CAD18 A7
86 CAD7 D7 116 CAD19 A25
87 CAD8 D15 117 CVS2 VS2
88 CC/BE0 CE1 118 CAD20 A6
89 CAD9 A10 119 CRST RESET
90 CAD10 CE2 120 CAD21 A5
91 CAD11 OE 121 CAD22 A4
92 CAD12 A11 122 CREQ INPACK
93 GND GND 123 CAD23 A3
94 CAD13 IORD 124 CC/BE3 REG
95 CAD15 IOWR 125 VR_EN VR_EN
96 CAD14 A9 126 V
97 CAD16 A17 127 CAD24 A2
98 CC/BE1 A8 128 CAD25 A1
99 CRSVD A18 129 CAD26 A0
100 CPAR A13 130 CVS1 VS1
101 CBLOCK A19 131 CINT READY(IREQ)
102 CPERR A14 132 GND GND
103 CSTOP A20 133 CSERR WAIT
104 V
105 CGNT WE 135 CSTSCHG BVD1(STSCHG/RI)
106 CDEVSEL A21 136 CCLKRUN WP(IOIS16)
107 CCLK A16 137 V
108 CTRDY A22 138 CCD2 CD2
109 V
110 CIRDY A15 140 CAD28 D8
111 CFRAME A23 141 CAD29 D1
112 GND GND 142 CAD30 D9
113 CC/BE2 A12 143 CRSVD D2
114 CAD17 A24 144 CAD31 D10
†
Terminal 85 is an NC on the PCI1510 to allow for terminal compatibility with the next generation of devices.
CC
CCCB
V
CC
V
CCCB
134 CAUDIO BVD2(SPKR)
139 CAD27 D0
CARDBUS 16-BIT
CC
CC
SIGNAL NAME
V
CC
V
CC
2−5
Table 2−2. Signal Names Sorted by GGU Terminal Number
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
A01 C/BE3 C/BE3 D05 V
A02 GND GND D06 CAUDIO BVD2(SPKR)
A03 CRSVD D2 D07 CAD25 A1
A04 CAD27 D0 D08 CRST RESET
A05 CCLKRUN WP(IOIS16) D09 CC/BE2 A12
A06 CINT READY(IREQ) D10 CAD23 A3
A07 V
A08 CC/BE3 REG D12 CPERR A14
A09 CVS2 VS2 D13 CGNT WE
A10 CFRAME A23 E01 V
A11 GND GND E02 AD25 AD25
A12 CAD18 A7 E03 AD31 AD31
A13 CBLOCK A19 E04 AD29 AD29
B01 AD27 AD27 E10 CSTOP A20
B02 CVS1 VS1 E11 CC/BE1 A8
B03 CAD31 D10 E12 CPAR A13
B04 CAD30 D9 E13 CRSVD A18
B05 CCD2 CD2 F01 AD22 AD22
B06 CSERR WAIT F02 IDSEL IDSEL
B07 CAD24 A2 F03 AD24 AD24
B08 CREQ INPACK F04 AD26 AD26
B09 CAD19 A25 F10 CAD16 A17
B10 CAD17 A24 F11 CAD14 A9
B11 V
B12 CAD22 A4 F13 GND GND
B13 CCLK A16 G01 PCLK PCLK
C01 GNT GNT G02 AD20 AD20
C02 REQ REQ G03 PRST PRST
C03 AD23 AD23 G04 AD21 AD21
C04 CAD29 D1 G10 CAD11 OE
C05 CAD28 D8 G11 CAD9 A10
C06 CSTSCHG BVD1(STSCHG/RI) G12 CAD12 A11
C07 CAD26 A0 G13 CAD10 CE2
C08 CAD21 A5 H01 AD17 AD17
C09 CAD20 A6 H02 AD19 AD19
C10 CIRDY A15 H03 AD18 AD18
C11 CAD15 IOWR H04 GND GND
C12 CTRDY A22 H10† CLK_48_RSVD CLK_48_RSVD
C13 V
D01 GND GND H12 CAD7 D7
D02 AD28 AD28 H13 CC/BE0 CE1
D03 AD30 AD30 J01 FRAME FRAME
D04 VR_EN VR_EN J02 C/BE2 C/BE2
†
Terminal H10 is not bonded out in the packaged parts in order to have pin compatibility with future devices.
CC
CCCB
CC
V
CC
V
CCCB
V
CC
D11 CDEVSEL A21
F12 CAD13 IORD
H11 CAD8 D15
CARDBUS 16-BIT
CC
CC
SIGNAL NAME
V
CC
V
CC
2−6
Table 2−2. Signal Names Sorted by GGU Terminal Number (Continued)
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
J03 TRDY TRDY L11 GRST GRST
J04 AD16 AD16 L12 VCCD1 VCCD1
J10 CAD5 D6 L13 CCD1 CD1
J11 CAD4 D12 M01 V
J12 CRSVD D14 M02 AD9 AD9
J13 CAD3 D5 M03 C/BE1 C/BE1
K01 IRDY IRDY M04 AD15 AD15
K02 DEVSEL DEVSEL M05 AD10 AD10
K03 PERR PERR M06 AD5 AD5
K04 AD4 AD4 M07 AD1 AD1
K05 AD13 AD13 M08 RI_OUT/PME RI_OUT/PME
K06 C/BE0 C/BE0 M09 SPKROUT SPKROUT
K07 MFUNC0 MFUNC0 M10 MFUNC4 MFUNC4
K08 GND GND M11 VPPD1 VPPD1
K09 VPPD0 VPPD0 M12 CAD2 D11
K10 MFUNC3 MFUNC3 M13 GND GND
K11 CAD0 D3 N01 PAR PAR
K12 CAD1 D4 N02 GND GND
K13 CAD6 D13 N03 AD12 AD12
L01 STOP STOP N04 AD8 AD8
L02 SERR SERR N05 AD7 AD7
L03 V
L04 AD11 AD11 N07 V
L05 AD14 AD14 N08 AD0 AD0
L06 AD6 AD6 N09 MFUNC1 MFUNC1
L07 AD2 AD2 N10 SUSPEND SUSPEND
L08 VR_PORT VR_PORT N11 V
L09 MFUNC2 MFUNC2 N12 MFUNC5 MFUNC5
L10 MFUNC6 MFUNC6 N13 VCCD0 VCCD0
CCP
V
CCP
N06 AD3 AD3
CARDBUS 16-BIT
CC
CC
CC
SIGNAL NAME
V
CC
V
CC
V
CC
2−7
Table 2−3. Signal Names Sorted by GVF Terminal Number
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
A04 VPPD0 VPPD0 E07 NC NC
A05 V
A06 NC NC E09 CAD28 D8
A07 GND GND E10 CSERR WAIT
A08 V
A09 CSTSCHG BVD1(STSCHG/RI) E12 CAD21 A5
A10 GND GND E13 CAD18 A7
A11 V
A12 CAD23 A3 E17 CSTOP A20
A13 V
A14 CAD19 A25 E19 V
A15 GND GND F01 MFUNC5 MFUNC5
A16 CDEVSEL A21 F02 MFUNC3 MFUNC3
B05 VCCD1 VCCD1 F03 MFUNC2 MFUNC2
B06 NC NC F05 MFUNC0 MFUNC0
B07 NC NC F06 NC NC
B08 CAD29 D1 F07 NC NC
B09 CCLKRUN WP(IOIS16) F08 CRSVD D2
B10 CVS1 VS1 F09 CAD27 D0
B11 CC/BE3 REG F10 CAUDIO BVD2(SPKR)
B12 CREQ INPACK F11 CAD26 A0
B13 CRST RESET F12 CVS2 VS2
B14 CAD17 A24 F13 CIRDY A15
B15 CFRAME A23 F14 CPAR A13
C05 VPPD1 VPPD1 F15 CPERR A14
C06 NC NC F17 CRSVD A18
C07 NC NC F18 CAD16 A17
C08 CAD30 D9 F19 CAD14 A9
C09 CCD2 CD2 G01 V
C10 CINT READY(IREQ) G02 VR_PORT VR_PORT
C11 CAD24 A2 G03 SUSPEND SUSPEND
C12 CAD22 A4 G05 MFUNC4 MFUNC4
C13 CAD20 A6 G06 MFUNC1 MFUNC1
C14 CC/BE2 A12 G14 V
C15 CCLK A16 G15 CC/BE1 A8
D01 NC NC G17 CAD15 IOWR
D19 CGNT WE G18 CAD13 IORD
E01 GND GND G19 GND GND
E02 SPKROUT SPKROUT H01 PCLK PCLK
E03 NC NC H02 GRST GRST
E05 NC NC H03 PRST PRST
E06 VCCD0 VCCD0 H05 VR_EN VR_EN
†
Terminal F06 is not bonded out in the packaged parts in order to have pin compatibility with future devices.
CC
CC
CCCB
CC
V
CC
V
CC
V
CCCB
V
CC
E08 CAD31 D10
E11 CAD25 A1
E14 CTRDY A22
E18 CBLOCK A19
CARDBUS 16-BIT
CC
CC
CCCB
SIGNAL NAME
V
CC
V
CC
V
CCCB
2−8
Table 2−3. Signal Names Sorted by GVF Terminal Number (Continued)
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
H06 MFUNC6 MFUNC6 M17 NC NC
H14 CAD11 OE M18 NC NC
H15 CAD12 A11 M19 NC NC
H17 CAD10 CE2 N01 GND GND
H18 CAD9 A10 N02 AD19 AD19
H19 V
J01 GNT GNT N05 FRAME FRAME
J02 REQ REQ N06 AD17 AD17
J03 RI_OUT/PME RI_OUT/PME N14 NC NC
J05 AD31 AD31 N15 NC NC
J06 AD30 AD30 N17 NC NC
J14 CAD8 D15 N18 NC NC
J15 CC/BE0 CE1 N19 NC NC
J17 CAD7 D7 P01 AD16 AD16
J18 CRSVD D14 P02 C/BE2 C/BE2
J19 CAD5 D6 P03 IRDY IRDY
K01 GND GND P05 STOP STOP
K02 AD29 AD29 P06 TRDY TRDY
K03 AD28 AD28 P07 AD14 AD14
K05 AD27 AD27 P08 AD9 AD9
K06 AD26 AD26 P09 NC NC
K14 CAD6 D13 P10 NC NC
K15 CAD3 D5 P11 NC NC
K17 CAD4 D12 P12 NC NC
K18 CAD1 D4 P13 NC NC
K19 GND GND P14 NC NC
L01 V
L02 AD25 AD25 P17 NC NC
L03 AD24 AD24 P18 NC NC
L05 IDSEL IDSEL P19 GND GND
L06 C/BE3 C/BE3 R01 V
L14 CAD2 D11 R02 DEVSEL DEVSEL
L15 CAD0 D3 R03 PERR PERR
L17 CCD1 CD1 R06 AD15 AD15
L18 VR_PORT VR_PORT R07 AD10 AD10
L19 V
M01 V
M02 AD23 AD23 R10 NC NC
M03 AD22 AD22 R11 NC NC
M05 AD20 AD20 R12 NC NC
M06 AD21 AD21 R13 NC NC
M14 NC NC R14 NC NC
M15 NC NC R17 NC NC
CC
CCP
CC
CC
V
V
V
V
CC
CCP
CC
CC
N03 AD18 AD18
P15 NC NC
R08 AD6 AD6
R09 AD0 AD0
CARDBUS 16-BIT
CC
SIGNAL NAME
V
CC
2−9
Table 2−3. Signal Names Sorted by GVF Terminal Number (Continued)
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
R18 NC NC V10 NC NC
R19 NC NC V11 NC NC
T01 SERR SERR V12 NC NC
T19 NC NC V13 NC NC
U05 C/BE1 C/BE1 V14 NC NC
U06 AD12 AD12 V15 NC NC
U07 AD8 AD8 W04 PAR PAR
U08 AD5 AD5 W05 V
U09 AD1 AD1 W06 GND GND
U10 NC NC W07 AD7 AD7
U11 NC NC W08 V
U12 NC NC W09 AD3 AD3
U13 NC NC W10 NC NC
U14 NC NC W11 NC NC
U15 NC NC W12 NC NC
V05 AD13 AD13 W13 NC NC
V06 AD11 AD11 W14 NC NC
V07 C/BE0 C/BE0 W15 NC NC
V08 AD4 AD4 W16 NC NC
V09 AD2 AD2
CARDBUS 16-BIT
CCP
CC
SIGNAL NAME
V
CCP
V
CC
2−10
Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically to Device Terminals
SIGNAL NAME
SIGNAL NAME
TERMINAL
PGE GGU GVF
AD0 56 N08 R09 CAD11 91 G10 H14
AD1 55 M07 U09 CAD12 92 G12 H15
AD2 53 L07 V09 CAD13 94 F12 G18
AD3 52 N06 W09 CAD14 96 F11 F19
AD4 51 K04 V08 CAD15 95 C11 G17
AD5 50 M06 U08 CAD16 97 F10 F18
AD6 49 L06 R08 CAD17 114 B10 B14
AD7 48 N05 W07 CAD18 115 A12 E13
AD8 46 N04 U07 CAD19 116 B09 A14
AD9 45 M02 P08 CAD20 118 C09 C13
AD10 44 M05 R07 CAD21 120 C08 E12
AD11 43 L04 V06 CAD22 121 B12 C12
AD12 42 N03 U06 CAD23 123 D10 A12
AD13 41 K05 V05 CAD24 127 B07 C11
AD14 39 L05 P07 CAD25 128 D07 E11
AD15 38 M04 R06 CAD26 129 C07 F11
AD16 25 J04 P01 CAD27 139 A04 F09
AD17 24 H01 N06 CAD28 140 C05 E09
AD18 23 H03 N03 CAD29 141 C04 B08
AD19 22 H02 N02 CAD30 142 B04 C08
AD20 18 G02 M05 CAD31 144 B03 E08
AD21 17 G04 M06 CAUDIO 134 D06 F10
AD22 16 F01 M03 C/BE0 47 K06 V07
AD23 15 C03 M02 C/BE1 37 M03 U05
AD24 11 F03 L03 C/BE2 26 J02 P02
AD25 10 E02 L02 C/BE3 13 A01 L06
AD26 9 F04 K06 CBLOCK 101 A13 E18
AD27 7 B01 K05 CC/BE0 88 H13 J15
AD28 6 D02 K03 CC/BE1 98 E11 G15
AD29 5 E04 K02 CC/BE2 113 D09 C14
AD30 4 D03 J06 CC/BE3 124 A08 B11
AD31 3 E03 J05 CCD1 75 L13 L17
CAD0 76 K11 L15 CCD2 138 B05 C09
CAD1 78 K12 K18 CCLK 107 B13 C15
CAD2 77 M12 L14 CCLKRUN 136 A05 B09
CAD3 81 J13 K15 CDEVSEL 106 D11 A16
CAD4 79 J11 K17 CFRAME 111 A10 B15
CAD5 83 J10 J19 CGNT 105 D13 D19
CAD6 82 K13 K14 CINT 131 A06 C10
CAD7 86 H12 J17 CIRDY 110 C10 F13
CAD8 87 H11 J14 CLK_48_RSVD 85 H10 —
CAD9 89 G11 H18 CPAR 100 E12 F14
CAD10 90 G13 H17 CPERR 102 D12 F15
PGE GGU GVF
TERMINAL
2−11
Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically to Device Terminals (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
PGE GGU GVF
CREQ 122 B08 B12 MFUNC4 67 M10 G05
CRST 119 D08 B13 MFUNC5 68 N12 F01
CRSVD 84 A03 F08 MFUNC6 69 L10 H06
CRSVD 99 E13 F17 PAR 35 N01 W04
CRSVD 143 J12 J18 PCLK 20 G01 H01
CSERR 133 B06 E10 PERR 33 K03 R03
CSTOP 103 E10 E17 PRST 19 G03 H03
CSTSCHG 135 C06 A09 REQ 1 C02 J02
CTRDY 108 C12 E14 RI_OUT/PME 57 M08 J03
CVS1 130 B02 B10 SERR 34 L02 T01
CVS2 117 A09 F12 SPKROUT 61 M09 E02
DEVSEL 30 K02 R02 STOP 31 L01 P05
FRAME 27 J01 N05 SUSPEND 65 N10 G03
GNT 2 C01 J01 TRDY 29 J03 P06
GRST 66 L11 H02 VCCD0 73 N13 E06
IDSEL 14 F02 L05 VCCD1 74 L12 B05
IRDY 28 K01 P03 VPPD0 71 K09 A04
MFUNC0 58 K07 F05 VPPD1 72 M11 C05
MFUNC1 59 N09 G06 VR_EN 125 D04 H05
MFUNC2 63 L09 F03 VR_PORT 62 L08 G02, L18
MFUNC3 64 K10 F02
PGE GGU GVF
TERMINAL
2−12
Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically to Device Terminals
SIGNAL NAME
SIGNAL NAME
TERMINAL
PGE GGU GVF
AD0 56 N08 R09 A11 92 G12 H15
AD1 55 M07 U09 A12 113 D09 C14
AD2 53 L07 V09 A13 100 E12 F14
AD3 52 N06 W09 A14 102 D12 F15
AD4 51 K04 V08 A15 110 C10 F13
AD5 50 M06 U08 A16 107 B13 C15
AD6 49 L06 R08 A17 97 F10 F18
AD7 48 N05 W07 A18 99 E13 F17
AD8 46 N04 U07 A19 101 A13 E18
AD9 45 M02 P08 A20 103 E10 E17
AD10 44 M05 R07 A21 106 D11 A16
AD11 43 L04 V06 A22 108 C12 E14
AD12 42 N03 U06 A23 111 A10 B15
AD13 41 K05 V05 A24 114 B10 B14
AD14 39 L05 P07 A25 116 B09 A14
AD15 38 M04 R06 BVD1(STSCHG/RI) 135 C06 A09
AD16 25 J04 P01 BVD2(SPKR) 134 D06 F10
AD17 24 H01 N06 C/BE0 47 K06 V07
AD18 23 H03 N03 C/BE1 37 M03 U05
AD19 22 H02 N02 C/BE2 26 J02 P02
AD20 18 G02 M05 C/BE3 13 A01 L06
AD21 17 G04 M06 CD1 75 L13 L17
AD22 16 F01 M03 CD2 138 B05 C09
AD23 15 C03 M02 CE1 88 H13 J15
AD24 11 F03 L03 CE2 90 G13 H17
AD25 10 E02 L02 CLK_48_RSVD 85 H10 —
AD26 9 F04 K06 DEVSEL 30 K02 R02
AD27 7 B01 K05 D0 139 A04 F09
AD28 6 D02 K03 D1 141 C04 B08
AD29 5 E04 K02 D2 143 A03 F08
AD30 4 D03 J06 D3 76 K11 L15
AD31 3 E03 J05 D4 78 K12 K18
A0 129 C07 F11 D5 81 J13 K15
A1 128 D07 E11 D6 83 J10 J19
A2 127 B07 C11 D7 86 H12 J17
A3 123 D10 A12 D8 140 C05 E09
A4 121 B12 C12 D9 142 B04 C08
A5 120 C08 E12 D10 144 B03 E08
A6 118 C09 C13 D11 77 M12 L14
A7 115 A12 E13 D12 79 J11 K17
A8 98 E11 G15 D13 82 K13 K14
A9 96 F11 F19 D14 84 J12 J18
A10 89 G11 H18 D15 87 H11 J14
PGE GGU GVF
TERMINAL
2−13
Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically to Device Terminals (Continued)
SIGNAL NAME
SIGNAL NAME
TERMINAL
PGE GGU GVF
FRAME 27 J01 N05 REG 124 A08 B11
GNT 2 C01 J01 REQ 1 C02 J02
GRST 66 L11 H02 RESET 119 D08 B13
IDSEL 14 F02 L05 RI_OUT/PME 57 M08 J03
INPACK 122 B08 B12 SERR 34 L02 T01
IORD 94 F12 G18 SPKROUT 61 M09 E02
IOWR 95 C11 G17 STOP 31 L01 P05
IRDY 28 K01 P03 SUSPEND 65 N10 G03
MFUNC0 58 K07 F05 TRDY 29 J03 P06
MFUNC1 59 N09 G06 VCCD0 73 N13 E06
MFUNC2 63 L09 F03 VCCD1 74 L12 B05
MFUNC3 64 K10 F02 VPPD0 71 K09 A04
MFUNC4 67 M10 G05 VPPD1 72 M11 C05
MFUNC5 68 N12 F01 VR_EN 125 D04 H05
MFUNC6 69 L10 H06 VR_PORT 62 L08 G02, L18
OE 91 G10 H14 VS1 130 B02 B10
PAR 35 N01 W04 VS2 117 A09 F12
PCLK 20 G01 H01 WAIT 133 B06 E10
PERR 33 K03 R03 WE 105 D13 D19
PRST 19 G03 H03 WP(IOIS16) 136 A05 B09
READY(IREQ) 131 A06 C10
PGE GGU GVF
TERMINAL
2−14
2.2 Terminal Descriptions
NAME
I/O
DESCRIPTION
NAME
I/O
DESCRIPTION
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
Table 2−6. Power Supply Terminals
TERMINAL
NUMBER
PGE GGU GVF
8, 21, 40,
GND
V
CC
V
CCCB
V
CCP
VR_EN 125 D04 H05 I Internal voltage regulator enable. Active-low
VR_PORT 62 L08 G02, L18
60, 80, 93,
112, 132
12, 32, 54,
70, 104,
126, 137
109 B11 A11, G14
36 L03 L01, W05 Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
A02, A11, D01,
F13, H04, K08,
M13, N02
A07, C13, D05,
E01, M01, N07,
N11
A07, A10, A15,
E01, G19, K01,
K19, N01, P19,
W06
A05, A08, A13,
E19, G01, H19,
L19, M01, R01,
W08
I/O DESCRIPTION
Device ground terminals
Power supply terminals for I/O and internal voltage regulator
Clamp voltage for PC Card interface. Matches card signaling
environment, 5 V or 3.3 V
Internal voltage regulator input/output. When VR_EN is low, the
regulator is enabled and this terminal is an output. An external
bypass capacitor is required on this terminal. When VR_EN is high,
the regulator is disabled and this terminal is an input for an external
2.5-V core power source.
VCCD0
VCCD1
VPPD0
VPPD1
TERMINAL
NUMBER
PGE GGU GVF
73
74
71
72
N13
L12
K09
M11
E06
B05
A04
C05
Table 2−7. PC Card Power Switch Terminals
I/O DESCRIPTION
O Logic controls to the TPS2211A PC Card power interface switch to control AVCC
O Logic controls to the TPS2211A PC Card power interface switch to control AVPP
2−15
TERMINAL
NAME
I/O
DESCRIPTION
NUMBER
PGE GGU GVF
GRST 66 L11 H02 I
PCLK 20 G01 H01 I
PRST 19 G03 H03 I
Table 2−8. PCI System Terminals
I/O DESCRIPTION
Global reset. When the global reset is asserted, the GRST signal causes the controller to
place all output buffers in a high-impedance state and reset all internal registers. When GRST
is asserted, the device is completely in its default state. For systems that require wake-up
from D3, GRST
initial boot so that PME context is retained during the transition from D3 to D0.
When the SUSPEND
registers are preserved. All outputs are placed in a high-impedance state.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are
sampled at the rising edge of PCLK.
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all
output buffers in a high-impedance state and reset internal registers. When PRST
the device can generate the PME
controller is in a default state.
When the SUSPEND
registers are preserved. All outputs are placed in a high-impedance state.
normally is asserted only during initial boot. PRST must be asserted following
mode is enabled, the device is protected from GRST, and the internal
signal only if it is enabled. After PRST is deasserted, the
mode is enabled, the device is protected from PRST, and the internal
is asserted,
2−16
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