TEXAS INSTRUMENTS PCI1450 Technical data

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1997 PC Standard Compliant

PCI Bus Power Management Interface Specification 1.0

ACPI 1.0 Compliant

PCI Local Bus Specification Revision

2.1/2.2 Compliant

PC 98/99 Compliant

Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges

Fully Compliant with the PCI Bus Power Management Specification for PCI to CardBus Bridges Specification

Ultra Zoomed Video

Zoomed Video Auto-Detect

Advanced filtering on Card Detect Lines Provide 90 Microseconds of Noise Immunity.

Programmable D3 Status Pin

Internal Ring Oscillator

3.3-V Core Logic with Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards

Supports Two PC Card or CardBus Slots With Hot Insertion and Removal

Uses Serial Interface to TI TPS2206 Dual Power Switch

Supports 132 Mbyte/sec. Burst Transfers to Maximize Data Throughput on Both the PCI Bus and the CardBus Bus

Supports Serialized IRQ with PCI Interrupts

8-Way Legacy IRQ Multiplexing

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Interrupt Modes Supported: Serial ISA/Serial PCI, Serial ISA/Parallel PCI, Parallel ISA/Parallel PCI, Parallel PCI Only.

EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID

Supports Zoomed Video with Internal Buffering

Dedicated Pin for PCI CLKRUN

Four General Purpose I/O’s

Multifunction PCI Device with Separate Configuration Space for each Socket

Five PCI Memory Windows and Two I/O Windows Available to each PC Card16 Socket

Two I/O Windows and Two Memory Windows Available to each CardBus Socket

ExCA-Compatible Registers are Mapped in Memory or I/O Space

Supports Distributed DMA and PC/PCI DMA

Intel 82365SL-DF Register Compatible

Supports 16-bit DMA on Both PC Card Sockets

Supports Ring Indicate, SUSPEND, and PCI CLKRUN

Advanced Submicron, Low-Power CMOS Technology

Provides VGA / Palette Memory and I/O, and Subtractive Decoding Options

LED Activity Pins

Supports PCI Bus Lock (LOCK)

Packaged in a 256-pin BGA or 257-pin Micro-Star BGA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PCI1450 GFN/GJG PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Description 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Names and Terminal Assignments 5. . . . . . . . . . . . . . . . . .

PCI1450 System Block Diagram 9. . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Rail Voltages 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Applications Overview 26. . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 34. . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 38. . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Controller Programming Model 44. . . . . . . . . . . . . . . . . .

PCI Configuration Registers (Functions 0 and 1) 44. . . . . . . . . . .

ExCA Compatibility Registers (Functions 0 and 1) 82. . . . . . . . .

Table of Contents

CardBus Socket Registers (Functions 0 and 1) 106. . . . . . . . . . . . . .

Distributed DMA (DDMA) Registers 114. . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 121. . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 123. . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 124. . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 125. . . . . . . . . . . . . . .

PC Card Cycle Timing 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements, (Memory Cycles) 127. . . . . . . . . . . . . . . . . . . .

Timing Requirements, (I/O Cycles) 127. . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics (Miscellaneous) 128. . . . . . . . . . . . . . . . . .

PC Card Parameter Mesasurement Information 128. . . . . . . . . . . . . .

Mechanical Data 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

description

The Texas Instruments PCI1450 is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two independent PC Card sockets compliant with the 1997 PC Card Standard and the

Interface Specification for PCI-to-CardBus Bridges

the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 and 1997 PC Card Standards retain the 16-bit PC Card specification defined in PCMCIA Release 2.1, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1450 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 Vdc or 3.3 Vdc as required.

. The PCI1450 provides a rich feature set which makes it

PCI Bus

The PCI1450 is compliant with the latest the

PCI Local Bus Specification Revision 2.1

a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers, or CardBus PC Card bridging transactions.

All card signals are internally buffered to allow hot insertion and removal. The PCI1450 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1450 internal data-path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1450 can also be programmed to accept fast posted writes to improve system bus utilization.

The PCI1450 provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC board manufacturers to add a ZV compatible solution and guarantees compliance with the CardBus loading specifications. Multiple system interrupt signaling options are provided: Serial ISA/Serial PCI, Serial ISA/Parallel PCI, Parallel ISA/Parallel PCI, and PCI Only interrupts. Furthermore, general-purpose inputs and outputs (GPIOs) are provided for the board designer to implement sideband functions. Many other features are designed into the PCI1450 such as socket activity LED outputs, and are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes allow the host power management system to further reduce power consumption.

Unused PCI1450 inputs must be pulled up using a 43 kW resistor.

use of symbols in this document

Throughout this data sheet the overbar symbol denotes an active-low signal. For example: FRAME that this is an active-low signal.

PCI Bus Power Management Specification

, and its PCI interface can act as either a PCI master device or

. It is also compliant with

denotes

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PCI1450 GFN/GJG

ÒÒ

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal assignments

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

CCCCCCCCCCCC

CCC CCCC CCC CCCC

CCC PPPP PPPP

PPP

PPPP

PPP

PPPP

PPP

PPPP

PPP

Bottom View

CC C

ZZZZZ

ZZ ZZ ZZ

ZZZZZZZ

ZZZ

ZZZ Z

CCC

CCCC

CCC

CCCC

CCC

CCCC

CCC

A B C D

E F

G H

J K

L M N P R T

U PPPPPPP PPPPPPP

PPPPPPP

GND

Power Switch

Interrupt and miscellaneous

CCCCCCCC CCCCCCCC

PCI Signals

CardBus Signals

Zoom Video Signals

Figure 1. PCI1450 Pin Diagram

CCC

CCCC

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PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments

Signal names and their terminal assignments are shown in Tables 1 and 2 and are sorted alphanumerically by the assigned terminal.

Table 1. GFN Terminals Sorted Alphanumerically for CardBus and 16-bit Signals

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8

GND ZV_UV3 ZV_Y7 V

CCZ

ZV_Y1 ZV_HREF B_RSVD//B_D2 B_CAD28//B_D8 B_CSTSCHG//B_BVD1(STSCHG B_CINT

//B_READY(IREQ) B_CVS1//B_VS1 B_CAD24//B_A2 B_CAD22//B_A4 B_CAD20//B_A6 B_CAD18//B_A7 B_CIRDY B_CCLK//B_A16 B_CDEVSEL B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV5 ZV_UV4 ZV_UV1 ZV_Y6 ZV_Y4 ZV_Y0 B_CAD31//B_D10 B_CAD29//B_D1 B_CCLKRUN B_CSERR B_CAD25//B_A1 B_CC/BE3 B_CAD21//B_A5 B_CVS2//B_VS2 B_CAD17//B_A24 V B_CPERR B_CBLOCK B_CC/BE1 B_CAD14//B_A9 ZV_RSVD1 ZV_SCLK ZV_UV6 ZV_UV2 ZV_Y5 ZV_Y3 ZV_VSYNC B_CAD30//B_D9

//B_A15

//B_A21

//B_WP(IOIS16)

//B_WAIT

//B_REG

CCB

//B_A14

//B_A19

//B_A8

/RI)

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F4 F17 F18 F19 F20 G1 G2

B_CCD2//B_CD2 V

CCB

B_CAD26//B_A0 B_CAD23//B_A3 B_CRST B_CAD19//B_A25 B_CFRAME B_CTRDY B_CSTOP B_CAD16//B_A17 B_CAD15//B_IOWR B_CAD11//B_OE V ZV_UV7 ZV_MCLK GND ZV_UV0 V ZV_Y2 GND B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR V B_CREQ GND B_CC/BE2 V B_CGNT GND B_CAD12//B_A11 B_CAD10//B_CE2 B_CC/BE0//B_CE1 ZV_PCLK ZV_SDATA ZV_LRCLK ZV_RSVD0 B_CAD13//B_IORD B_CAD9//B_A10 B_CAD8//B_D15 B_RSVD//B_D14 G_RST V V V B_CAD5//B_D6 B_CAD3//B_D5 A_CAD2//A_D11 A_CAD0//A_D3

//B_RESET

//B_A23 //B_A22 //B_A20

CCZ

//B_INPACK

//B_A12

//B_WE

CC CC CCB

G3 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1

)

K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3

A_CCD1//A_CD1 B_CAD7//B_D7 B_CAD6//B_D13 B_CAD4//B_D12 B_CAD1//B_D4 A_CAD3//A_D5 A_CAD4//A_D12 A_CAD1//A_D4 GND GND B_CAD2//B_D11 B_CAD0//B_D3 B_CCD1 A_CAD7//A_D7 A_RSVD//A_D14 A_CAD5//A_D6 A_CAD6//A_D13 PCLK CLKRUN PRST GNT A_CC/BE0//A_CE1 V A_CAD8//A_D15 V REQ AD31 AD30 V A_CAD9//A_A10 A_CAD10//A_CE2 A_CAD11//A_OE A_CAD13//A_IORD V AD28 AD27 AD29 A_CAD12//A_A11 A_CAD15//A_IOWR A_CAD14//A_A9 A_CAD16//A_A17 C/BE3 AD24 AD25 AD26 A_CC/BE1 A_RSVD//A_A18 A_CPAR//A_A13

//B_CD1

CCA

CCP

//A_A8

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PCI1450 GFN/GJG PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments (continued)

Table 1. GFN Terminals Sorted Alphanumerically for CardBus and 16-bit Signals (Continued)

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8

GND GND AD22 AD23 IDSEL A_CBLOCK A_CPERR A_CGNT A_CTRDY//A_A22 AD17 V

CCP

AD20 AD21 A_CSTOP A_CDEVSEL V

CCA

AD16 AD18 AD19 A_CCLK//A_A16 A_CIRDY A_CC/BE2 A_CAD19//A_A25 STOP IRDY FRAME C/BE2 A_CFRAME//A_23 A_CAD17//A_A24 A_CVS2//A_VS2 GND A_CAD26//A_A0 V

A_CCLKRUN GND

//A_A19

//A_A14

//A_WE

//A_A20

//A_A21

//A_A15

//A_A12

//A_WP(IOIS16)

IRQMUX1

U10

PCGNT/IRQMUX6

U11

CLOCK

U12

GND

U13

AD6

U14

U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5

AD11 GND PERR SERR TRDY A_CAD18//A_A7 A_CAD20//A_A6 A_CAD21//A_A5 A_CAD25//A_A1 A_CSERR A_CSTSCHG//A_BVD1(STSCHG/RI) A_CAD28//A_D8 A_RSVD//A_D2 IRQMUX2 V

CCI

GPIO0/LEDA1 DATA GPIO3/INTA AD3 V

CCP

AD8 AD12 AD15 GPIO2/LOCK DEVSEL A_CRST//A_RESET A_CAD22//A_A4 A_CAD23//A_A3 A_CAD24//A_A2 V

CCA

//A_WAIT

A_CCD2//A_CD2 A_CAD29//A_D1

A_CAD31//A_D10

IRQMUX3

IRQMUX5

W10

GPIO1/LEDA2

W11

LATCH

W12

IRQSER/INTB

W13

AD1

W14

AD4

W15

AD7

W16

AD9

W17

AD13

W18

C/BE1

W19

W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20

CCP

A_CREQ A_CC/BE3//A_REG A_CVS1//A_VS1 A_CINT//A_READY(IREQ) A_CAUDIO//A_BVD2(SPKR A_CAD27//A_D0 A_CAD30//A_D9 IRQMUX0 IRQMUX4 SPKROUT SUSPEND PCREQ/IRQMUX7

/PME

RI_OUT AD0 AD2 AD5 C/BE0 AD10 AD14 PAR

//A_INPACK

)

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PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments (continued)

Table 2. GJG Terminals Sorted Alphanumerically for CardBus and 16-bit Signals

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11

ZV_UV6 ZV_UV4 ZV_UV2 ZV_Y6 ZV_Y3 ZV_VSYNC V

B_CCLKRUN B_CSERR B_CAD24//B_A2 B_CAD21//B_A5 B_CAD20//B_A6 B_CAD17//B_A24 V

CCB

B_CGNT B_CPERR//B_A14 B_CBLOCK ZV_SCLK ZV_UV5 ZV_UV3 ZV_UV1 ZV_Y7 ZV_Y4 ZV_Y0 B_CAD30//B_D9 B_CCD2 V

CCB

B_CAD25//B_A1 B_CAD22//B_A4 B_CVS2//B_VS2 GND B_CIRDY B_CDEVSEL B_CSTOP B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV7 ZV_MCLK B_CC/BE1 B_CAD14//B_A9 ZV_RSVD0 ZV_RSVD1 GND ZV_UV0 V

CCZ

GND B_RSVD//B_D2 B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR B_CC/BE3

//B_WP(IOIS16)

//B_WAIT

//B_WE

//B_A19

//B_CD2

//B_A15

//B_A21

//B_A20

//B_A8

//B_REG

D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E18 E19 F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F18 F19 G1 G2 G4 G5 G6 G7 G13

)

G14 G15

B_CREQ//B_INPACK B_CRST//B_RESET B_CC/BE2 B_CCLK//B_A16 B_CAD16//B_A17 B_CAD15//B_IOWR B_CAD12//B_A11 ZV_SDATA ZV_PCLK V

CCZ

ZV_LRCLK ZV_Y5 ZV_Y1 B_CAD31//B_D10 B_CAD28//B_D8 B_CSTSCHG//B_BVD1(STSCHG/RI B_CAD26//B_A0 B_CAD23//B_A3 B_CAD19//B_A25 B_CFRAME B_CTRDY B_CAD13//B_IORD B_CAD11//B_OE B_CAD10//B_CE2 A_CCD1//A_CD1 A_CAD0//A_D3 G_RST GND V

ZV_Y2 B_CAD29//B_D1 GND B_CINT B_CVS1//B_VS1 V

B_CAD18//B_A7 VCC B_CAD9//B_A10 B_CC/BE0 B_CAD8//B_D15 V

CCB

A_CAD4//A_D12 V

A_CAD3//A_D5 A_CAD1//A_D4 A_CAD2//A_D11 ZV_HREF B_CAD3//B_D5 B_CAD7//B_D7 B_RSVD//B_D14

//B_A12

//B_A23 //B_A22

//B_READY(IREQ)

//B_CE1

G16

GND

G18

B_CAD5//B_D6

G19

B_CAD6//B_D13

A_CAD5//A_D6

A_RSVD//A_D14

A_CAD7//A_D7

GND

A_CAD6//A_D13

H14

B_CCD1

H15

B_CAD4//B_D12

H16

B_CAD1//B_D4

H18

B_CAD2//B_D11

H19

B_CAD0//B_D3

A_CAD8//A_D15

A_CC/BE0

A_CAD9//A_A10

J14

GNT

J15

PCLK

J16

CLKRUN

J18

PRST

J19

GND

A_CAD11//A_OE

A_CAD13//A_IORD

A_CAD12//A_A11

GND

A_CAD10//A_CE2

K14

K15

REQ

K16

AD31

K18

AD30

K19

A_CAD14//A_A9

A_CAD16//A_A17

A_CC/BE1

A_RSVD//A_A18

A_CAD15//A_IOWR

L14

AD29

L15

AD28

L16

AD25

L18

AD27

L19

AD26

A_CPAR//A_A13

A_CBLOCK

A_CPERR

A_CSTOP

M14

AD22

M15

AD24

//B_CD1

//A_CE1

CCA

CCP

//A_A8

//A_A19 //A_A14 //A_A20

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PCI1450 GFN/GJG PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments (continued)

Table 2. GJG Terminals Sorted Alphanumerically for CardBus and 16-bit Signals. (Continued)

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

M16 M18 M19 N1 N2 N4 N5 N6 N7 N13 N14 N15 N16 N18 N19 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P18 P19 R1 R2 R4 R5

CBE3 IDSEL AD23 A_CDEVSEL GND A_CCLK//A_A16 A_CTRDY V

CCA

A_CGNT//A_WE AD1 GND AD19 AD21 V

CCP

AD20 A_CIRDY A_CFRAME A_CC/BE2 V

A_CAD17//A_A24 A_CAD27//A_D0 V

CCI

SPKROUT PCREQ RI_OUT AD5 AD8 C/BE2 AD16 AD18 AD17 A_CAD18//A_A7 A_CAD19//A_A25 A_CVS2//A_VS2 A_CSERR//A_WAIT

//A_A21

//A_A22

//A_A15

//A_23

//A_A12

/IRQMUX7

/PME

A_CSTSCHG//A_BVD1(STSCHG/RI)

A_CAD28//A_D8

IRQMUX2

IRQMUX5 R10 R11 R12 R13 R14 R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U18 U19 V1 V2

/IRQMUX6

PCGNT

CLOCK

AD0

GND

C/BE0

TRDY

FRAME

IRDY

A_CAD20//A_A6

A_CRST

A_CAD21//A_A5

A_CINT

A_CCLKRUN

A_RSVD//A_D2

IRQMUX1

IRQMUX3

GPIO0/LEDA1

DATA

GPI03/INTA

AD4

AD7

AD11

AD15

DEVSEL

STOP

GND

A_CAD22//A_A4

PERR

SERR

A_CREQ//A_INPACK

A_CAD23//A_A3

//A_RESET

//A_READY(IREQ)

//A_WP(IOIS16)

A_CAD25//A_A1

A_CVS1//A_VS1

A_CAUDIO//A_BVD2(SPKR)

GND

A_CAD29//A_D1

IRQMUX0

GND

V10

GPI01/LEDA2

V11

LATCH

V12

AD3

V13

V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18

CCP

AD10 AD13 C/BE1 V

CCP

GPI02/LOCK A_CC/BE3//A_REG A_CAD24//A_A2 A_CAD26//A_A0 V

CCA

A_CCD2 A_CAD30//A_D9 A_CAD31//A_D10 IRQMUX4 SUSPEND GND IRQSER/INTB AD2 AD6 AD9 AD12 AD14 PAR

//A_CD2

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PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

PCI1450 System Block Diagram

Figure 2 shows a simplified system implementation example using the PCI1450. The PCI interface includes all address/data and control signals for PCI protocol. Highlighted in this diagram is the functionality supported by the PCI1450. The PCI1450 supports PC/PCI DMA, PCI Way DMA (distributed DMA), PME D3

through D0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 IRQMUX,

cold

and 4 GPIO pins) that can be programmed for a wide variety of functions.

PCI Bus

Real Time Clock

Activity LED’s

CLKRUN

South Bridge

wake-up from

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23

pins are used for routing the zoomed video signals to the VGA controller.

Clock

23 for ZV

(See Note)

23 for ZV

PCI1450

Enable

IRQSER

DMA PME

Zoomed Video

19 Video

4 Audio

Interrupt Routing Options:

1) Serial ISA/Serial PCI

2) Serial ISA/Parallel PCI

3) Parallel PCI/Parallel ISA

4) Parallel PCI Only

Embedded

Controller

VGA

Controller

Audio Codec

Figure 2. PCI1450 System Block Diagram

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PCI1450 GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions

This section describes the PCI1450 terminal functions. The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc., for quick reference. The terminal numbers are also listed for convenient reference.

Table 3. Power Supply

TERMINAL

NAME GFN NO. GJG NO.

B14, D4, D7, F5, F9, G16, H5,

J19, K5, N2, N14, R13, U1, V6,

V9, W11

A8, F6, F12, F14, G2, J6, K19,

M6, P5, P8, R15, V12

Device ground terminals

Power supply terminal for core logic (3.3 Vdc) Clamp voltage for PC Card A interface. Indicates Card A

signaling environment. Clamp voltage for PC Card B interface. Indicates Card B

signaling environment. Clamp voltage for interrupt subsystem interface and

miscellaneous I/O. Indicates signaling level of the following inputs and shared outputs: IRQSER, PCGNT SUSPEND INTA

Clamp voltage for zoom video interface (3.3 Vdc or 5 Vdc) and G_RST

, SPKROUT, GPIO1:0, IRQMUX7–IRQMUX0,

, INTB, CLOCK, DATA, LATCH, and RI_OUT.

GND

CCA

CCB

CCP

CCZ

A1, D4, D8, D13, D17, H4, H17,

N4, N17, U4, U8, U13, U17

D6, D11, D15, F4, F17, K4, L17,

CCI

R4, R17, U6, U10, U15

K2, R3, W5 J4, N6, W5

B16, C10, F18, A15, B10, F19

V10 P9

K20, P18, V15, W20 K14, N18, V14, V18 Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc)

A4, D1 D6, E4

, PCREQ,

TERMINAL

NAME GFN NO. GJG NO.

CLOCK U12 R11 I/O

DATA V12 T11 O

LATCH W12 V11 O

I/O

TYPE

Table 4. PC Card Power Switch

3-line power switch clock. Information on the DA TA line is sampled at the rising edge of CLOCK. This terminal defaults as an input which means an external clock source must be used. If the internal ring oscillator is used, then an external CLOCK source is not required. The internal oscillator may be enabled by setting bit 27 of the

(PCI offset 80h) to a 1b.

A 43

pulldown resistor should be tied to this terminal.

3-line power switch data. DA TA is used to serially communicate socket power-control information to the power switch.

3-line power switch latch. LA TCH is asserted by the PCI1450 to indicate to the PC Card power switch that the data on the DATA line is valid.

system control

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FUNCTION

terminal functions (continued)

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

T able 5. PCI System

TERMINAL

NAME GFN NO. GJG NO.

CLKRUN

PCLK J17 J15 I

PRST

G_RST F1 F4 I

J18 J16 I/O

J19 J18 I

I/O

TYPE

PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI1450 responds accordingly. If CLKRUN implemented, then this pin should be tied low. CLKRUN (KEEPCLK) in the

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1450 to place all output buffers in a high-impedance state and reset all internal registers. When PRST the device is completely nonfunctional. After PRST default state. When the SUSPEND and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

Global reset. When the global reset is asserted, the G_RST signal causes the PCI1450 to 3-state all output buffers and reset all internal registers. When G_RST is completely in its default state. For systems that require wake-up from D3, G_RST normally be asserted only during initial boot. PRST so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, G_RST

system control register

mode is enabled, the device is protected from the PRST ,

should be tied to PRST.

is enabled by default by bit 1

is deasserted, the PCI1450 is in its

is asserted, the device

should be asserted following initial boot

is not

is asserted,

will

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FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 6. PCI Address and Data

TERMINAL

NAME GFN NO. GJG NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR Y20 W18 I/O

K18 K19 L20 L18

L19 M20 M19 M18 N19 N18 P20 P19 R20 R19 P17 R18 V18 Y19 W18 V17 U16 Y18 W17 V16 W16 U14 Y16 W15 V14 Y15 W14 Y14

M17

T20 W19 Y17

K16 K18 L14 L15 L18 L19 L16 M15 M19 M14 N16 N19 N15 P18 P19 P16 T16

W17

V16

W16

T15 V15

W15

P14 T14

W14

P13 T13 V13

W13

N13 R12

M16 P15 V17 R14

TYPE

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit

I/O

address or other destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte

I/O

paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PCI bus parity. In all PCI bus read and write cycles, the PCI1450 calculates even parity across the AD31–AD0 and C/BE3 parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

–C/BE0 buses. As an initiator during PCI cycles, the PCI1450 outputs this

–C/BE0 define the bus command.

applies to byte 0 (AD7–AD0), C/BE1

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FUNCTION

terminal functions (continued)

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Table 7. PCI Interface Control

TERMINAL

NAME GFN NO. GJG NO.

DEVSEL

FRAME

GNT

GPIO2/LOCK

IDSEL N20 M18 I

IRDY

PERR

REQ

SERR

STOP

TRDY

V20 T18 I/O

T19 R18 I/O

J20 J14 I

V19 V19 I/O

T18 R19 I/O

U18 U18 I/O

K17 K15 O

U19 U19 O

T17 T19 I/O

U20 R16 I/O

I/O

TYPE

PCI device select. The PCI1450 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1450 monitors DEVSEL target responds before timeout occurs, then the PCI1450 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1450 access to the PCI bus after the current data transaction has completed. GNT request, depending on the PCI bus parking algorithm.

PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI

and used to gain exclusive access downstream. Since this functionality is not typically

LOCK used, a general-purpose I/O may be accessed through this terminal. GPIO2/LOCK to a general-purpose input and can be configured through the

Initialization device select. IDSEL selects the PCI1450 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both

and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states

IRDY are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR

PCI bus request. REQ is asserted by the PCI1450 to request access to the PCI bus as an initiator.

PCI system error. SERR is an output that is pulsed from the PCI1450 when enabled through

command register

the target of the PCI cycle to assert this signal. When SERR

, this signal also pulses, indicating that an address parity error has occurred on a

CardBus interface. PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current

PCI bus transaction. STOP devices that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

is deasserted, the PCI bus transaction is in the final data phase.

is enabled through bit 6 of the

, indicating a system error has occurred. The PCI1450 need not be the

is used for target disconnects and is commonly asserted by target

until a target responds. If no

may or may not follow a PCI bus

GPIO2 control register

command register

is enabled in the

defaults

bridge control

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FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 8. System Interrupt

TERMINAL

NAME GFN NO. GJG NO.

GPIO3/INTA

IRQSER/INTB W13 W12 I/O

IRQMUX7 IRQMUX6 IRQMUX5 IRQMUX4 IRQMUX3 IRQMUX2 IRQMUX1 IRQMUX0

RI_OUT/PME Y13 P12 O

NAME GFN NO. GJG NO.

PCGNT/

IRQMUX6

PCREQ/

IRQMUX7

V13 T12 I/O

Y12 U11

W10

V9 U9 Y8

TERMINAL

U11 R10 I/O

Y12 P11 O

P11 R10

T9 R8 T8 V8

I/O

TYPE

I/O

TYPE

Parallel PCI interrupt. INT A can be optionally mapped to GPI03 when parallel PCI interrupts are used.

programmable interrupt subsystem

See defaults to a general-purpose input.

Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream. See

subsystem

when one of the parallel interrupt modes is selected in the Interrupt request/secondary functions multiplexed. The primary function of these terminals is

to provide the ISA-type IRQ signaling supported by the PCI1450. These interrupt multiplexer outputs can be mapped to any of 15 IRQs. The for the ISA IRQ interrupt mode and the programmed before these terminals are enabled.

All of these terminals have secondary functions, such as PCI INTB request/grant, ring indicate output, and zoom video status, that can be selected with the appropriate programming of this register. When the secondary functions are enabled, the respective terminals are not available for IRQ routing.

See the Ring indicate out and power management event output. Terminal provides an output for

ring-indicate or PME

for details on interrupt signaling. This terminal can be used to signal PCI INTB

IRQMUX routing register

signals.

for details on interrupt signaling. GPIO3/INTA

programmable interrupt

device control register

IRQMUX routing register

for programming options.

must be programmed

must have the IRQ routing

, PC/PCI DMA

T able 9. PC/PCI DMA

PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI DMA scheme.

Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX6 takes precedence over PCGNT PC/PCI DMA.

This terminal is also used for the serial EEPROM interface. PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system

supporting the PC/PCI DMA scheme. Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7

interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX7 takes precedence over PCREQ PC/PCI DMA.

This terminal is also used for the serial EEPROM interface.

, and should not be enabled in a system using

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I/O

terminal functions (continued)

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Table 10. Zoom Video

TERMINAL

NAME

ZV_HREF

ZV_VSYNC

ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0

ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 ZV_UV2 ZV_UV1 ZV_UV0

ZV_SCLK C2 B1 A7 O Audio SCLK PCM

ZV_MCLK D3 C2 A6 O Audio MCLK PCM

ZV_PCLK E1 E2 IOIS16 O Pixel clock to the zoom video port ZV_LRCLK E3 E5 INPACK O Audio LRCLK PCM ZV_SDATA E2 E1 SPKR O Audio SDATA PCM

ZV_RSVD1 ZV_RSVD0

GFN

GJG NO.

NO.

A6 G7 A10 O C7 A7 A11 O A3

B4 C5 B5 C6 D7 A5 B6

D2 C3 B1 B2 A2 C4 B3 D5

C1 E4

I/O AND MEMORY

B5 A5 E6 B6 A6 F7 E7 B7

C1 A2 B2 A3 B3 A4 B4 D5

D2 D1

INTERFACE

SIGNAL

A20 A14 A19 A13 A18

A17

A25 A12 A24 A15 A23 A16 A22 A21

A5 A4

TYPE

Horizontal sync to the zoom video port Vertical sync to the zoom video port

O Video data to the zoom video port in YV:4:2:2 format

Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0

are put into the high-impedance state by host adapter.

FUNCTION

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I/O

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

TERMINAL

NAME GFN NO.

GPIO0/LEDA1 V11 T10 I/O

GPIO1/LEDA2 W1 1 V10 I/O

SPKROUT

SUSPEND

Y10 P10 O

Y11 W10 I

GJG

NO.

TYPE

Table 11. Miscellaneous

FUNCTION

GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it provides an output indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be configured as a general-purpose input and output, GPIO0. The zoom video enable signal (ZV_STAT) can also be routed to this signal through the GPIO0/LEDA1 defaults to a general-purpose input.

GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it provides an output indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be configured as a general-purpose input and output, GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be used for power switch overcurrent (OC) sensing. See general-purpose input.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1450 from the PC Card interface. SPKROUT is driven as the XOR combination of card SPKR

Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See

GPIO1 control register

//CAUDIO inputs.

suspend mode

for details.

for programming details. GPIO1/LEDA2 defaults to a

GPIO0 control register

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FUNCTION

terminal functions (continued)

Table 12. 16-bit PC Card Address and Data (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal T4 is A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal C14 is B_A25.

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SLOT

†

T4 U2 U1 P4 R2 R1 P1 N2 M4 T1 T2 P2 N3 T3 M1

L1 M3 N1 V1 V2 V3

W2 W3 W4

V4 U5

J4 H2 G1

Y7 V7

J3 H1 H3 G2 V8

SLOT

‡

C14 B15 C15 C16 A18 C17 B18 A20 C18 A17 A16 B17 A19 D14 D18 E18 B20 B19 A15 A14 B13 A13 C12 A12 B11 C11

E19

E20 G18 G19

H18

B7 C8 A8

G17

F19

F20 G20

H19

A7 B8 D9

SLOT

†

R2 P6 P2 N5

N1 M5 M2

L2 N4 P1 M4 M1 P4 K4

L4 R1

T4 U2 V2 W3 V3 W4

J1 H2 H6 G1 G6 W8 W7 R7 H4 H1 G4 G5

T7 V7 P7

SLOT

E13 A14 E14 E15 B16 B17 A18 B19 D16 D15 B15 A17 B18 D14 D19 F15 C19 C18 F13 A13 A12 B12 E12 A11 B11 E11

F18 G15 G19 H15 H18

E8 B8

E9 G14 G18 G13 H16 H19

I/O

TYPE

‡

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

PCI1450 GFN/GJG

PC CARD CONTROLLER

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PCI1450 GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 13. 16-bit PC Card Interface Control (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

BVD1

(STSCHG

BVD2

(SPKR

CD1 CD2

CE1 CE2

INPACK Y1 D12 V1 D12 I

IORD

IOWR

SLOT

/RI)

)

SLOT

†

V6 A9 R6 E10 I

Y5 D10 V5 D10 I

G3W6H20C9F1W6H14

K1L2D20

L4 E17 K2 E16 O

M2 C19 L6 D18 O

SLOT

‡

D19J2K6

SLOT

†

F16 E19

I/O

TYPE

‡

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 and BVD2 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See the enable bits. See

status register

Status change. STSCHG write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that

include batteries. BVD2 and BVD1 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See enable bits. See

for the status bits for this signal.

Speaker. SPKR socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1450 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1

are pulled low. For signal status, see Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1 enables even-numbered address bytes, and CE2 enables

odd-numbered address bytes. Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an

I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA

operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1450 to enable 16-bit I/O PC Card data output during host I/O read cycles.

DMA write. IORD 16-bit PC Card that supports DMA. The PCI1450 asserts IORD transfers from the PC Card to host memory.

I/O write. IOWR is driven low by the PCI1450 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

DMA read. IOWR 16-bit PC Card that supports DMA. The PCI1450 asserts IOWR during transfers from host memory to the PC Card.

ExCA card status-change interrupt configuration register

ExCA card status-change register

for the status bits for this signal.

is used to alert the system to a change in the READY,

is used by 16-bit modem cards to indicate a ring detection.

ExCA card status-change interrupt configuration register

ExCA card status-change register

is an optional binary audio signal available only when the card and

ExCA interface status register

is used as the DMA write strobe during DMA operations from a

and the

ExCA interface status

ExCA interface

and CD2

during DMA

for

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FUNCTION

PC CARD CONTROLLER

terminal functions (continued)

Table 13. 16-bit PC Card Interface Control (slots A and B) (continued)

TERMINAL

GFN NO. GJG NO.

NAME

OE L3 C20 K1 E18 O

READY

(IREQ

REG

RESET W1 C13 T2 D13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE P3 D16 N7 A16 O

(IOIS16

VS1 VS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal P3 is A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal D16 is B_WE

SLOT

†

Y4 A10 T5 F10 I

)

Y2 B12 W2 D11 O

V5 B10 R5 A10 I

U7 B9 T6 A9 I

)

Y3U3A11

SLOT

‡

B14V4R4

SLOT

†

F11

B13

I/O

TYPE

‡

Output enable. OE is driven low by the PCI1450 to enable 16-bit memory PC Card data output during host memory read cycles.

DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1450 asserts OE to indicate TC for a DMA write operation.

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ that a device on the 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG and to the I/O space (IORD accessed section of card memory and is generally used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG operations to a 16-bit PC Card that supports DMA. The PCI1450 asserts REG indicate a DMA operation. REG or DMA write (IORD

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE that supports DMA. The PCI1450 asserts WE to indicate TC for a DMA read operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.

I/O is 16 bits. IOIS16 PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with

I/O

each other, determine the operating voltage of the 16-bit PC Card.

is asserted, access is limited to attribute memory (OE or WE active)

is asserted by a 16-bit I/O PC Card to indicate to the host

or IOWR active). Attribute memory is a separately

is used as a DMA acknowledge (DACK) during DMA

is used in conjunction with the DMA read (IOWR)

) strobes to transfer data.

is used as TC during DMA operations to a 16-bit PC Card

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit

PCI1450 GFN/GJG

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PCI1450 GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 14. CardBus PC Card Interface System (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CCLK T1 A17 N4 D15 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal T1 is A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal A17 is B_CCLK.

SLOT

†

U7 B9 T6 A9 O

W1 C13 T2 D13 I/O

SLOT

‡

SLOT

†

I/O

TYPE

‡

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST CAUDIO, CCD2:1 all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1450 to indicate that the CCLK frequency is decreased. CardBus clock run (CCLKRUN (CLKRUN

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST Card signals must be 3-stated, and the PCI1450 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

, and CVS2–CVS1 are sampled on the rising edge of CCLK, and

, CCLKRUN, CINT, CSTSCHG,

) follows the PCI clock run

is asserted, all CardBus PC

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FUNCTION

terminal functions (continued)

Table 15. CardBus PC Card Address and Data (slots A and B)

TERMINAL

E8 B8

F8 E9 D9

I/O

TYPE

‡

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle,

–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is

CC/BE3 used as byte enables. The byte enables determine which byte paths of the full 32-bit data

I/O

bus carry meaningful data. CC/BE0 to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1450 calculates even parity across the CAD and CC/BE outputs CPAR with a one-CCLK delay . As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

applies to byte 0 (CAD7–CAD0), CC/BE1 applies

applies to byte 2 (CAD23–CAD8), and CC/BE3

buses. As an initiator during CardBus cycles, the PCI1450

GFN NO. GJG NO.

NAME

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR N3 A19 M1 B18 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal N3 is A_CPAR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_CPAR.

SLOT

†

V7 Y6 U5

V4 W4 W3 W2

U2 M4 M2 M3

L3 L2 L1

J1 J4

J3 H2 H1 G1 H3 G2

Y2 T3 N1 K1

SLOT

‡

B7 C8 B8 A8

D9 C11 B11 A12 C12 A13 B13 A14 C14 A15 B15 C18 C19 B20 E17 D18 C20 D19 E18 E19 G17 G18 F19 G19 F20 H18 G20 H19

B12 D14 B19 D20

SLOT

†

W8 W7

V7 R7 P7

V2 U2 T4 T1 R2 R1 P6

L2 L6

L1 K2 K4 K1 K6

J1 H4 H6 H1 G1 G4 G6 G5 F2

SLOT

E11 B11 A11 E12 B12 A12 A13 E13 F13

A14 D16 D18 C19

E16 D19

E18

E19

F15

F18 G14 G19 G18 H15 G13 H18 H16 H19

D11 D14 C18

F16

PCI1450 GFN/GJG

PC CARD CONTROLLER

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PCI1450 GFN/GJG

FUNCTION

ith CVS1

CVS2 to identif

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 16. CardBus PC Card Interface Control (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CAUDIO Y5 D10 V5 D10 I

CBLOCK

CCD1 CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 CVS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal Y5 is A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal D10 is B_CAUDIO.

SLOT

†

P1 B18 M2 A18 I/O

G3 H20 F1 H14

W6 C9 W6 B9

R2 A18 N1 B16 I/O

U1 C15 P2 E14 I/O

P3 D16 N7 A16 I

Y4 A10 T5 F10 I

T2 A16 P1 B15 I/O

P2 B17 M4 A17 I/O

Y1 D12 V1 D12 I

V5 B10 R5 A10 I

R1 C17 M5 B17 I/O

V6 A9 R6 E10 I

P4 C16 N5 E15 I/O

Y3U3A11

SLOT

‡

B14V4R4

SLOT

†

F11

B13

I/O

TYPE

‡

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1450 supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

w operating voltage and card type.

CardBus device select. The PCI1450 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1450 monitors CDEVSEL the PCI1450 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME transfers continue while this signal is asserted. When CFRAME CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI1450 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY both sampled asserted, wait states are inserted.

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1450 can report CSERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’ s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

I/O

in conjunction with CCD1 to determine the operating voltage and card type.

and

until a target responds. If no target responds before timeout occurs, then

is asserted to indicate that a bus transaction is beginning, and data

y card insertion and interrogate cards to determine the

and CTRDY are asserted. Until CIRDY and CTRDY are

to the system by assertion of SERR on the PCI interface.

and CTRDY are asserted; until this time, wait states are

and CCD2 to identify card insertion and interrogate cards

is deasserted, the

is driven by the card synchronous to

is used for target disconnects, and is

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I/O characteristics

PCI1450 GFN/GJG

PC CARD CONTROLLER

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Figure 3 shows a 3-state bidirectional buffer illustration for reference. The table,

conditions

provides the electrical characteristics of the inputs and outputs. The PCI1450 meets the ac

recommended operating

specifications of the PC Card 95 Standard and the PCI Bus 2.1 specifications.

Tied for Open Drain

CCP

Pad

Figure 3. 3-State Bidirectional Buffer

clamping rail splits

The I/O sites can be pulled through a clamping diode to a power rail for protection. The core power supply is independent of the clamping rails. The clamping (protection) diodes are required if the signaling environment on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and the PCI1450 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with tolerance (protection) at V

5.0-V power supply. A standard die has only one clamping rail for the sites as shown in Figure 3. After the terminal assignments

are fixed, the fabrication facility will support a design by splitting the clamping rail for customization. The PCI1450 requires five separate clamping rails since it supports a wide range of features. The five rails are listed and defined in the table,

. If a system design requires a 5.0-V PCI bus, then the V

CCP

recommended operating conditions

would be connected to the

CCP

PCI interface

This section describes the PCI interface of the PCI1450, and how the device responds and participates in PCI bus cycles. The PCI1450 provides all required signals for PCI master/slave devices, and may operate in either 5-V or 3.3-V PCI signaling environments by connecting the V

PCI bus lock (LOCK)

The bus locking protocol defined in the PCI Specification is not highly recommended, but is provided on the PCI1450 as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the terminal function defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions may proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with the PCI bus clock, the CardBus signal for this protocol is CBLOCK

An agent may need to do an exclusive operation because a critical memory access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive, real-time data transfer, such as video.

terminals to the desired signaling level.

CCP

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The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress.

The PCI1450 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions, and blocks access as the target until it completes a delayed read. This target characteristic is prohibited by the 2.1 PCI Specification, and the issue is resolved by the PCI master using LOCK

loading the subsystem identification (EEPROM interface)

The

subsystem vendor ID register

space located at offset 40h for functions 0 and 1. This doubleword register, used for system and option card (mobile dock) identification purposes, is required by some operating systems. Implementation of this unique identifier register is a PC ‘97 requirement.

The PCI1450 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but the access mode may be made read/write by clearing the SUBSYSRW bit in the the BIOS may write a subsystem identification value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the access. This approach saves the added cost of implementing the serial EEPROM.

system control register

and

subsystem ID register

(bit 5 of the

system control register

subsystem vendor ID register

make up a double-word of PCI configuration

, offset 80h). Once this bit is cleared (0),

and

subsystem ID register

are limited to read-only

In some conditions, such as in a docking environment, the

double-word of data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the PRST and G_RST from the entire PCI1450 core, including the serial EEPROM state machine. Refer to

mode

EEPROM. The system designer must implement a pulldown resistor on the PCI1450 LA TCH terminal to indicate the serial

EEPROM mode. Only when this pulldown resistor is present will the PCI1450 attempt to load data through the serial EERPOM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and one clock signal (SCL). The SDA signal is mapped to the PCI1450 IRQMUX6 terminal and the SCL signal is mapped to the PCI1450 IRQMUX7 terminal. Figure 4 illustrates a typical PCI1450 application using the serial EEPROM interface.

must be loaded with a unique identifier through a serial EEPROM interface. The PCI1450 loads the

for details on using SUSPEND. The PCI1450 provides a two-line serial bus interface to the serial

subsystem vendor ID register

and

subsystem ID

suspend

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Serial EEPROM

A0 A1A2SCL

SDA

IRQMUX7 IRQMUX6

PCI1450

Latch

Figure 4. Serial EEPROM Application

As stated above, when the PCI1450 is reset by G_RST, the subsystem data is read automatically from the EEPROM. The PCI1450 masters the serial EEPROM bus and reads four bytes as described in Figure 5.

Slave Address

b6 b5 b4 b3 b2 b1 b0 0 A b7 b6 b5 b4 b3 b2 b1 b0 A S b6 b5 b4 b3 b2 b1 b0 1 A

R/W# Restart

Data Byte 0 M PData Byte 1 M Data Byte 2 M Data Byte 3 M

S/P – Start/Stop Condition A – Slave Acknowledgment M – Master Acknowledgment

Word Address Slave Address

R/W#

Figure 5. EEPROM Interface Subsystem Data Collection

The EEPROM is addressed at word address 00h, as indicated in Figure 5, and the address auto-increments after each byte transfers according to the protocol. Thus, to provide the subsystem register with data AABBCCDDh the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.

The serial EEPROM is addressed at slave address 1010000b by the PCI1450. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit, Figure 4, assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional transfers. Both the SCL and SDA signals are 3-stated and pulled high when the bus is not active. When the SDA line transitions to a logic low, this signals a start condition (S). A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. Data is valid and stable during the clock high period. Figure 6 illustrates this protocol.

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SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 6. Serial EEPROM Start/Stop Conditions and BIt Transfers

Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 5. When the PCI1450 transmits the addresses, it returns the SDA signal to the high state and 3-states the line. The PCI1450 then generates an SCL clock cycle and expects the EEPROM to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI1450 transmitter and the EEPROM receiver. Figure 7 illustrates general acknowledges.

During the data byte transfers from the serial EEPROM to the PCI1450, the EEPROM clocks the SCL signal. After the EEPROM transmits the data to the PCI1450, it returns the SDA signal to the high state and 3-states the line. The EEPROM then generates an SCL clock cycle and expects the PCI1450 to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM transmitter and the PCI1450 receiver. Figure 7 illustrates general acknowledges.

SCL From

Master

SDA Output

By Transmitter

123 789

SDA Output

By Receiver

Figure 7. Serial EEPROM Protocol – Acknowledge

EEPROM interface status information is communicated through the

general status register

located at PCI offset 85h. The EEDETECT bit in this register indicates whether or not the PCI1450 serial EEPROM circuitry detects the pulldown resistor on LA TCH. An error condition, such as a missing acknowledge, results in the DATAERR bit being set. The EEBUSY bit is set while the

subsystem ID register

is loading (serial EEPROM interface is

busy).

PC Card applications overview

This section describes the PC Card interfaces of the PCI1450. A discussion is provided on PC Card recognition, which details the card interrogation procedure. The card powering procedure is discussed in this section including the protocol of the P2C power switch interface. The internal ZV buffering provided by the PCI1450 and programming model is detailed in this section. Also, standard PC Card register models are described, as well as a brief discussion of the PC Card software protocol layers.

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PC Card insertion/removal and recognition

The 1995 PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16-bit vs. CardBus) are determined.

The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four pins in a certain configuration depending on the type of card and the supply voltage. The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 17.

Table 17. PC Card – Card Detect and Voltage Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface Voltage

Ground Ground Open Open 5 V 16-bit PC Card 5 V Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V

Ground Ground Ground Ground 5 V 16-bit PC Card Ground Ground Open Ground LV 16-bit PC Card 3.3 V

Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V

Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card

Ground Ground Ground Open LV 16-bit PC Card Y.Y V

Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V

Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved

5 V, 3.3 V, and

X.X V

3.3 V, X.X V, and Y.Y V

P2C power switch interface (TPS2202A/2206)

A power switch with a PCMCIA-to-peripheral control (P2C) interface is required for the PC Card powering interface. The TI TPS2206 (or TPS2202A) Dual-Slot PC Card Power-Interface Switch provides the P2C interface to the CLOCK, DA T A, and LA TCH terminals of the PCI1450. Figure 8 shows the terminal assignments of the TPS2206. Figure 9 illustrates a typical application where the PCI1450 represents the PCMCIA controller.

There are two ways to provide a clock source to the power switch interface. The first method is to provide an external clock source such as a 32 kHz real time clock to the CLOCK terminal. The second method is to use the internal ring oscillator. If the internal ring oscillator is used, then the PCI1450 provides its own clock source for the PC Card interrogation logic and the power switch interface. The mode of operation is determined by the setting of bit 27 of the

system control register

(PCI offset 80h). This bit is encoded as follows: 0 = CLOCK terminal (terminal U12) is an input (default). 1 = CLOCK terminal is an output that utilizes the internal oscillator.

A 43 kW pulldown resistor should be tied to the CLOCK pin.

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Power Supply

12V

3.3V

Supervisor

5V 5V

DATA

CLOCK

LATCH

RESET

12V

AVPP AVCC AVCC AVCC

GND

RESET

3.3V

NC – No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

5V NC NC NC NC NC 12V BVPP BVCC BVCC BVCC NC OC

3.3V

Figure 8. TPS2206 Terminal Assignments

TPS2206

12V 5V

3.3V

RESET RESET

AVPP

AVCC AVCC AVCC

V V V

PP1 PP2 CC

PC Card A

V V V

PP1 PP2 CC

PC Card B

PCI1450

PC Card Interface (68 pins/socket)

Serial I/F

BVCC BVCC BVCC

BVPP

Figure 9. TPS2206 Typical Application

zoomed video support

The zoomed video (ZV) port on the PCI1450 provides an internally buffered 16-bit ZV PC Card data path. This internal routing is programmed through the subsystem implemented in the PCI1450, and details the bit functions found in the

An output port (PORTSEL) is always selected. The PCI1450 defaults to socket 0 (see the

). When ZVOUTEN is enabled, the zoom video output terminals are enabled and allow the PCI1450

multimedia control register

. Figure 9 summarizes the zoomed video

multimedia control register

multimedia control

to route the zoom video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled in the

multimedia control register

. If the PORTSEL maps to a card port that is disabled (ZVEN =0 or ZVEN1 = 0), then

the zoom video port is driven low (i.e., no data is transmitted).

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Card Output

Enable Logic

PC Card Socket 0

PC Card Socket 1

Zoomed Video Subsystem

ZVEN0

PC Card

I/F

PC Card

I/F

ZVOUTEN

PORTSEL

Note: ZVSTAT must be enabled through the GPIO Control Register

ZVSTAT

19 Video Signals

VGA

Audio

Codec

4 Audio Signals

ZVEN1

NOTES: A. ZVSTA T must be enabled through the GPIO control register.

Figure 10. Zoomed Video Subsystem

zoomed video auto detect

Zoomed video auto detect, when enabled, allows the PCI1450 to automatically detect zoomed video data by sensing the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. The PCI1450 automatically switches the internal zoomed video MUX to route the zoomed video stream to the PCI1450’s zoomed video output port. This eliminates the need for software to switch the internal MUX using the

multimedia control register

(PCI offset 84h, bits 6 and 7).

The PCI1450 can be programmed to switch a third zoomed video source by programming IRQMUX2 as a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed video source. ZVST AT may then be programmed onto IRQMUX4 and this signal may switch the zoomed video buffers from the third zoomed video source. To account for the possibility of several zoomed video sources being enabled at the same time, a programmable priority scheme may be enabled.

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The PCI1450 defaults with zoomed video auto-detect disabled so that it will function exactly like the PCI1250A. To enable zoomed video auto-detect and the programmable priority scheme, the following bits must be set:

Multimedia control register

000 = Slot A, Slot B, External Source 001 = Slot A, External Source, Slot B 010 = Slot B, Slot A, External Source 011 = Slot B, External Source, Slot A 100 = External Source, Slot A, Slot B 101 = External Source, Slot B, Slot A 110 = External Source, Slot B, Slot A 111 = Reserved

If it is desired to switch a third zoomed video source, then the following bits must also be set:

IRQMUX routing register

input pin.

IRQMUX routing register

Card Output

Enable Logic

(PCI offset 84h) bit 5: Writing a 1b enables zoomed video auto-detect (PCI offset 84h) bits 4–2: Set the programmable priority scheme

(PCI offset 8Ch), bits 11–8: Write 0010b to program IRQMUX2 as a pixel clock

(PCI ofset 8Ch), bits 19–16: Write 0001b to program IRQMUX4 as a ZVST A T pin.

Zoomed Video Subsystem

3rd Zoomed Video Source

ZVEN0

PC Card Socket 0

PC Card Socket 1

PC Card

I/F

Pixel Clock Sense

Auto Z/V

Arbiter

Pixel Clock Sense

PC Card

I/F

ZVEN1

Pixel Clock Sense

Programmed on IRQMUX2

ZVSTAT

ZV Data

IRQMUX2

Buffers

Enable

VGA

19 Video Signals

Audio

Codec

4 Audio Signals

Figure 11. Zoomed Video with Auto Detect Enabled

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TEXAS INSTRUMENTS PCI1450 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual