TEXAS INSTRUMENTS PCI1450 Technical data

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1997 PC Standard Compliant

PCI Bus Power Management Interface Specification 1.0

ACPI 1.0 Compliant

PCI Local Bus Specification Revision

2.1/2.2 Compliant

PC 98/99 Compliant

Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges

Fully Compliant with the PCI Bus Power Management Specification for PCI to CardBus Bridges Specification

Ultra Zoomed Video

Zoomed Video Auto-Detect

Advanced filtering on Card Detect Lines Provide 90 Microseconds of Noise Immunity.

Programmable D3 Status Pin

Internal Ring Oscillator

3.3-V Core Logic with Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments

Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards

Supports Two PC Card or CardBus Slots With Hot Insertion and Removal

Uses Serial Interface to TI TPS2206 Dual Power Switch

Supports 132 Mbyte/sec. Burst Transfers to Maximize Data Throughput on Both the PCI Bus and the CardBus Bus

Supports Serialized IRQ with PCI Interrupts

8-Way Legacy IRQ Multiplexing

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Interrupt Modes Supported: Serial ISA/Serial PCI, Serial ISA/Parallel PCI, Parallel ISA/Parallel PCI, Parallel PCI Only.

EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID

Supports Zoomed Video with Internal Buffering

Dedicated Pin for PCI CLKRUN

Four General Purpose I/O’s

Multifunction PCI Device with Separate Configuration Space for each Socket

Five PCI Memory Windows and Two I/O Windows Available to each PC Card16 Socket

Two I/O Windows and Two Memory Windows Available to each CardBus Socket

ExCA-Compatible Registers are Mapped in Memory or I/O Space

Supports Distributed DMA and PC/PCI DMA

Intel 82365SL-DF Register Compatible

Supports 16-bit DMA on Both PC Card Sockets

Supports Ring Indicate, SUSPEND, and PCI CLKRUN

Advanced Submicron, Low-Power CMOS Technology

Provides VGA / Palette Memory and I/O, and Subtractive Decoding Options

LED Activity Pins

Supports PCI Bus Lock (LOCK)

Packaged in a 256-pin BGA or 257-pin Micro-Star BGA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1450 GFN/GJG PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Description 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Names and Terminal Assignments 5. . . . . . . . . . . . . . . . . .

PCI1450 System Block Diagram 9. . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clamping Rail Voltages 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Applications Overview 26. . . . . . . . . . . . . . . . . . . . . . . . .

Programmable Interrupt Subsystem 34. . . . . . . . . . . . . . . . . . . . . .

Power Management Overview 38. . . . . . . . . . . . . . . . . . . . . . . . . .

PC Card Controller Programming Model 44. . . . . . . . . . . . . . . . . .

PCI Configuration Registers (Functions 0 and 1) 44. . . . . . . . . . .

ExCA Compatibility Registers (Functions 0 and 1) 82. . . . . . . . .

Table of Contents

CardBus Socket Registers (Functions 0 and 1) 106. . . . . . . . . . . . . .

Distributed DMA (DDMA) Registers 114. . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 121. . . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCI Clock/Reset Timing Requirements 123. . . . . . . . . . . . . . . . . . . . .

PCI Timing Requirements 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 124. . . . . . . . . . . . . . . . . . . . . . .

PCI Bus Parameter Measurement Information 125. . . . . . . . . . . . . . .

PC Card Cycle Timing 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements, (Memory Cycles) 127. . . . . . . . . . . . . . . . . . . .

Timing Requirements, (I/O Cycles) 127. . . . . . . . . . . . . . . . . . . . . . . . .

Switching Characteristics (Miscellaneous) 128. . . . . . . . . . . . . . . . . .

PC Card Parameter Mesasurement Information 128. . . . . . . . . . . . . .

Mechanical Data 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

description

The Texas Instruments PCI1450 is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two independent PC Card sockets compliant with the 1997 PC Card Standard and the

Interface Specification for PCI-to-CardBus Bridges

the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 and 1997 PC Card Standards retain the 16-bit PC Card specification defined in PCMCIA Release 2.1, and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1450 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 Vdc or 3.3 Vdc as required.

. The PCI1450 provides a rich feature set which makes it

PCI Bus

The PCI1450 is compliant with the latest the

PCI Local Bus Specification Revision 2.1

a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers, or CardBus PC Card bridging transactions.

All card signals are internally buffered to allow hot insertion and removal. The PCI1450 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1450 internal data-path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1450 can also be programmed to accept fast posted writes to improve system bus utilization.

The PCI1450 provides an internally buffered zoom video (ZV) path. This reduces the design effort of PC board manufacturers to add a ZV compatible solution and guarantees compliance with the CardBus loading specifications. Multiple system interrupt signaling options are provided: Serial ISA/Serial PCI, Serial ISA/Parallel PCI, Parallel ISA/Parallel PCI, and PCI Only interrupts. Furthermore, general-purpose inputs and outputs (GPIOs) are provided for the board designer to implement sideband functions. Many other features are designed into the PCI1450 such as socket activity LED outputs, and are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes allow the host power management system to further reduce power consumption.

Unused PCI1450 inputs must be pulled up using a 43 kW resistor.

use of symbols in this document

Throughout this data sheet the overbar symbol denotes an active-low signal. For example: FRAME that this is an active-low signal.

PCI Bus Power Management Specification

, and its PCI interface can act as either a PCI master device or

. It is also compliant with

denotes

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1450 GFN/GJG

ÒÒ

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal assignments

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

CCCCCCCCCCCC

CCC CCCC CCC CCCC

CCC PPPP PPPP

PPP

PPPP

PPP

PPPP

PPP

PPPP

PPP

Bottom View

CC C

ZZZZZ

ZZ ZZ ZZ

ZZZZZZZ

ZZZ

ZZZ Z

CCC

CCCC

CCC

CCCC

CCC

CCCC

CCC

A B C D

E F

G H

J K

L M N P R T

U PPPPPPP PPPPPPP

PPPPPPP

GND

Power Switch

Interrupt and miscellaneous

CCCCCCCC CCCCCCCC

PCI Signals

CardBus Signals

Zoom Video Signals

Figure 1. PCI1450 Pin Diagram

CCC

CCCC

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments

Signal names and their terminal assignments are shown in Tables 1 and 2 and are sorted alphanumerically by the assigned terminal.

Table 1. GFN Terminals Sorted Alphanumerically for CardBus and 16-bit Signals

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8

GND ZV_UV3 ZV_Y7 V

CCZ

ZV_Y1 ZV_HREF B_RSVD//B_D2 B_CAD28//B_D8 B_CSTSCHG//B_BVD1(STSCHG B_CINT

//B_READY(IREQ) B_CVS1//B_VS1 B_CAD24//B_A2 B_CAD22//B_A4 B_CAD20//B_A6 B_CAD18//B_A7 B_CIRDY B_CCLK//B_A16 B_CDEVSEL B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV5 ZV_UV4 ZV_UV1 ZV_Y6 ZV_Y4 ZV_Y0 B_CAD31//B_D10 B_CAD29//B_D1 B_CCLKRUN B_CSERR B_CAD25//B_A1 B_CC/BE3 B_CAD21//B_A5 B_CVS2//B_VS2 B_CAD17//B_A24 V B_CPERR B_CBLOCK B_CC/BE1 B_CAD14//B_A9 ZV_RSVD1 ZV_SCLK ZV_UV6 ZV_UV2 ZV_Y5 ZV_Y3 ZV_VSYNC B_CAD30//B_D9

//B_A15

//B_A21

//B_WP(IOIS16)

//B_WAIT

//B_REG

CCB

//B_A14

//B_A19

//B_A8

/RI)

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F4 F17 F18 F19 F20 G1 G2

B_CCD2//B_CD2 V

CCB

B_CAD26//B_A0 B_CAD23//B_A3 B_CRST B_CAD19//B_A25 B_CFRAME B_CTRDY B_CSTOP B_CAD16//B_A17 B_CAD15//B_IOWR B_CAD11//B_OE V ZV_UV7 ZV_MCLK GND ZV_UV0 V ZV_Y2 GND B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR V B_CREQ GND B_CC/BE2 V B_CGNT GND B_CAD12//B_A11 B_CAD10//B_CE2 B_CC/BE0//B_CE1 ZV_PCLK ZV_SDATA ZV_LRCLK ZV_RSVD0 B_CAD13//B_IORD B_CAD9//B_A10 B_CAD8//B_D15 B_RSVD//B_D14 G_RST V V V B_CAD5//B_D6 B_CAD3//B_D5 A_CAD2//A_D11 A_CAD0//A_D3

//B_RESET

//B_A23 //B_A22 //B_A20

CCZ

//B_INPACK

//B_A12

//B_WE

CC CC CCB

G3 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1

)

K2 K3 K4 K17 K18 K19 K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3

A_CCD1//A_CD1 B_CAD7//B_D7 B_CAD6//B_D13 B_CAD4//B_D12 B_CAD1//B_D4 A_CAD3//A_D5 A_CAD4//A_D12 A_CAD1//A_D4 GND GND B_CAD2//B_D11 B_CAD0//B_D3 B_CCD1 A_CAD7//A_D7 A_RSVD//A_D14 A_CAD5//A_D6 A_CAD6//A_D13 PCLK CLKRUN PRST GNT A_CC/BE0//A_CE1 V A_CAD8//A_D15 V REQ AD31 AD30 V A_CAD9//A_A10 A_CAD10//A_CE2 A_CAD11//A_OE A_CAD13//A_IORD V AD28 AD27 AD29 A_CAD12//A_A11 A_CAD15//A_IOWR A_CAD14//A_A9 A_CAD16//A_A17 C/BE3 AD24 AD25 AD26 A_CC/BE1 A_RSVD//A_A18 A_CPAR//A_A13

//B_CD1

CCA

CCP

//A_A8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1450 GFN/GJG PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments (continued)

Table 1. GFN Terminals Sorted Alphanumerically for CardBus and 16-bit Signals (Continued)

GFN SIGNAL NAME GFN SIGNAL NAME GFN SIGNAL NAME

N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8

GND GND AD22 AD23 IDSEL A_CBLOCK A_CPERR A_CGNT A_CTRDY//A_A22 AD17 V

CCP

AD20 AD21 A_CSTOP A_CDEVSEL V

CCA

AD16 AD18 AD19 A_CCLK//A_A16 A_CIRDY A_CC/BE2 A_CAD19//A_A25 STOP IRDY FRAME C/BE2 A_CFRAME//A_23 A_CAD17//A_A24 A_CVS2//A_VS2 GND A_CAD26//A_A0 V

A_CCLKRUN GND

//A_A19

//A_A14

//A_WE

//A_A20

//A_A21

//A_A15

//A_A12

//A_WP(IOIS16)

IRQMUX1

U10

PCGNT/IRQMUX6

U11

CLOCK

U12

GND

U13

AD6

U14

U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5

AD11 GND PERR SERR TRDY A_CAD18//A_A7 A_CAD20//A_A6 A_CAD21//A_A5 A_CAD25//A_A1 A_CSERR A_CSTSCHG//A_BVD1(STSCHG/RI) A_CAD28//A_D8 A_RSVD//A_D2 IRQMUX2 V

CCI

GPIO0/LEDA1 DATA GPIO3/INTA AD3 V

CCP

AD8 AD12 AD15 GPIO2/LOCK DEVSEL A_CRST//A_RESET A_CAD22//A_A4 A_CAD23//A_A3 A_CAD24//A_A2 V

CCA

//A_WAIT

A_CCD2//A_CD2 A_CAD29//A_D1

A_CAD31//A_D10

IRQMUX3

IRQMUX5

W10

GPIO1/LEDA2

W11

LATCH

W12

IRQSER/INTB

W13

AD1

W14

AD4

W15

AD7

W16

AD9

W17

AD13

W18

C/BE1

W19

W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20

CCP

A_CREQ A_CC/BE3//A_REG A_CVS1//A_VS1 A_CINT//A_READY(IREQ) A_CAUDIO//A_BVD2(SPKR A_CAD27//A_D0 A_CAD30//A_D9 IRQMUX0 IRQMUX4 SPKROUT SUSPEND PCREQ/IRQMUX7

/PME

RI_OUT AD0 AD2 AD5 C/BE0 AD10 AD14 PAR

//A_INPACK

)

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PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments (continued)

Table 2. GJG Terminals Sorted Alphanumerically for CardBus and 16-bit Signals

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11

ZV_UV6 ZV_UV4 ZV_UV2 ZV_Y6 ZV_Y3 ZV_VSYNC V

B_CCLKRUN B_CSERR B_CAD24//B_A2 B_CAD21//B_A5 B_CAD20//B_A6 B_CAD17//B_A24 V

CCB

B_CGNT B_CPERR//B_A14 B_CBLOCK ZV_SCLK ZV_UV5 ZV_UV3 ZV_UV1 ZV_Y7 ZV_Y4 ZV_Y0 B_CAD30//B_D9 B_CCD2 V

CCB

B_CAD25//B_A1 B_CAD22//B_A4 B_CVS2//B_VS2 GND B_CIRDY B_CDEVSEL B_CSTOP B_CPAR//B_A13 B_RSVD//B_A18 ZV_UV7 ZV_MCLK B_CC/BE1 B_CAD14//B_A9 ZV_RSVD0 ZV_RSVD1 GND ZV_UV0 V

CCZ

GND B_RSVD//B_D2 B_CAD27//B_D0 B_CAUDIO//B_BVD2(SPKR B_CC/BE3

//B_WP(IOIS16)

//B_WAIT

//B_WE

//B_A19

//B_CD2

//B_A15

//B_A21

//B_A20

//B_A8

//B_REG

D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E18 E19 F1 F2 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F18 F19 G1 G2 G4 G5 G6 G7 G13

)

G14 G15

B_CREQ//B_INPACK B_CRST//B_RESET B_CC/BE2 B_CCLK//B_A16 B_CAD16//B_A17 B_CAD15//B_IOWR B_CAD12//B_A11 ZV_SDATA ZV_PCLK V

CCZ

ZV_LRCLK ZV_Y5 ZV_Y1 B_CAD31//B_D10 B_CAD28//B_D8 B_CSTSCHG//B_BVD1(STSCHG/RI B_CAD26//B_A0 B_CAD23//B_A3 B_CAD19//B_A25 B_CFRAME B_CTRDY B_CAD13//B_IORD B_CAD11//B_OE B_CAD10//B_CE2 A_CCD1//A_CD1 A_CAD0//A_D3 G_RST GND V

ZV_Y2 B_CAD29//B_D1 GND B_CINT B_CVS1//B_VS1 V

B_CAD18//B_A7 VCC B_CAD9//B_A10 B_CC/BE0 B_CAD8//B_D15 V

CCB

A_CAD4//A_D12 V

A_CAD3//A_D5 A_CAD1//A_D4 A_CAD2//A_D11 ZV_HREF B_CAD3//B_D5 B_CAD7//B_D7 B_RSVD//B_D14

//B_A12

//B_A23 //B_A22

//B_READY(IREQ)

//B_CE1

G16

GND

G18

B_CAD5//B_D6

G19

B_CAD6//B_D13

A_CAD5//A_D6

A_RSVD//A_D14

A_CAD7//A_D7

GND

A_CAD6//A_D13

H14

B_CCD1

H15

B_CAD4//B_D12

H16

B_CAD1//B_D4

H18

B_CAD2//B_D11

H19

B_CAD0//B_D3

A_CAD8//A_D15

A_CC/BE0

A_CAD9//A_A10

J14

GNT

J15

PCLK

J16

CLKRUN

J18

PRST

J19

GND

A_CAD11//A_OE

A_CAD13//A_IORD

A_CAD12//A_A11

GND

A_CAD10//A_CE2

K14

K15

REQ

K16

AD31

K18

AD30

K19

A_CAD14//A_A9

A_CAD16//A_A17

A_CC/BE1

A_RSVD//A_A18

A_CAD15//A_IOWR

L14

AD29

L15

AD28

L16

AD25

L18

AD27

L19

AD26

A_CPAR//A_A13

A_CBLOCK

A_CPERR

A_CSTOP

M14

AD22

M15

AD24

//B_CD1

//A_CE1

CCA

CCP

//A_A8

//A_A19 //A_A14 //A_A20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1450 GFN/GJG PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

signal names and terminal assignments (continued)

Table 2. GJG Terminals Sorted Alphanumerically for CardBus and 16-bit Signals. (Continued)

NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME

M16 M18 M19 N1 N2 N4 N5 N6 N7 N13 N14 N15 N16 N18 N19 P1 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P18 P19 R1 R2 R4 R5

CBE3 IDSEL AD23 A_CDEVSEL GND A_CCLK//A_A16 A_CTRDY V

CCA

A_CGNT//A_WE AD1 GND AD19 AD21 V

CCP

AD20 A_CIRDY A_CFRAME A_CC/BE2 V

A_CAD17//A_A24 A_CAD27//A_D0 V

CCI

SPKROUT PCREQ RI_OUT AD5 AD8 C/BE2 AD16 AD18 AD17 A_CAD18//A_A7 A_CAD19//A_A25 A_CVS2//A_VS2 A_CSERR//A_WAIT

//A_A21

//A_A22

//A_A15

//A_23

//A_A12

/IRQMUX7

/PME

A_CSTSCHG//A_BVD1(STSCHG/RI)

A_CAD28//A_D8

IRQMUX2

IRQMUX5 R10 R11 R12 R13 R14 R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U18 U19 V1 V2

/IRQMUX6

PCGNT

CLOCK

AD0

GND

C/BE0

TRDY

FRAME

IRDY

A_CAD20//A_A6

A_CRST

A_CAD21//A_A5

A_CINT

A_CCLKRUN

A_RSVD//A_D2

IRQMUX1

IRQMUX3

GPIO0/LEDA1

DATA

GPI03/INTA

AD4

AD7

AD11

AD15

DEVSEL

STOP

GND

A_CAD22//A_A4

PERR

SERR

A_CREQ//A_INPACK

A_CAD23//A_A3

//A_RESET

//A_READY(IREQ)

//A_WP(IOIS16)

A_CAD25//A_A1

A_CVS1//A_VS1

A_CAUDIO//A_BVD2(SPKR)

GND

A_CAD29//A_D1

IRQMUX0

GND

V10

GPI01/LEDA2

V11

LATCH

V12

AD3

V13

V14 V15 V16 V17 V18 V19 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18

CCP

AD10 AD13 C/BE1 V

CCP

GPI02/LOCK A_CC/BE3//A_REG A_CAD24//A_A2 A_CAD26//A_A0 V

CCA

A_CCD2 A_CAD30//A_D9 A_CAD31//A_D10 IRQMUX4 SUSPEND GND IRQSER/INTB AD2 AD6 AD9 AD12 AD14 PAR

//A_CD2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

PCI1450 System Block Diagram

Figure 2 shows a simplified system implementation example using the PCI1450. The PCI interface includes all address/data and control signals for PCI protocol. Highlighted in this diagram is the functionality supported by the PCI1450. The PCI1450 supports PC/PCI DMA, PCI Way DMA (distributed DMA), PME D3

through D0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 IRQMUX,

cold

and 4 GPIO pins) that can be programmed for a wide variety of functions.

PCI Bus

Real Time Clock

Activity LED’s

CLKRUN

South Bridge

wake-up from

TPS2206

Power

Switch

PC Card

Socket A

PC Card

Socket B

NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23

pins are used for routing the zoomed video signals to the VGA controller.

Clock

23 for ZV

(See Note)

23 for ZV

PCI1450

Enable

IRQSER

DMA PME

Zoomed Video

19 Video

4 Audio

Interrupt Routing Options:

1) Serial ISA/Serial PCI

2) Serial ISA/Parallel PCI

3) Parallel PCI/Parallel ISA

4) Parallel PCI Only

Embedded

Controller

VGA

Controller

Audio Codec

Figure 2. PCI1450 System Block Diagram

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PCI1450 GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions

This section describes the PCI1450 terminal functions. The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc., for quick reference. The terminal numbers are also listed for convenient reference.

Table 3. Power Supply

TERMINAL

NAME GFN NO. GJG NO.

B14, D4, D7, F5, F9, G16, H5,

J19, K5, N2, N14, R13, U1, V6,

V9, W11

A8, F6, F12, F14, G2, J6, K19,

M6, P5, P8, R15, V12

Device ground terminals

Power supply terminal for core logic (3.3 Vdc) Clamp voltage for PC Card A interface. Indicates Card A

signaling environment. Clamp voltage for PC Card B interface. Indicates Card B

signaling environment. Clamp voltage for interrupt subsystem interface and

miscellaneous I/O. Indicates signaling level of the following inputs and shared outputs: IRQSER, PCGNT SUSPEND INTA

Clamp voltage for zoom video interface (3.3 Vdc or 5 Vdc) and G_RST

, SPKROUT, GPIO1:0, IRQMUX7–IRQMUX0,

, INTB, CLOCK, DATA, LATCH, and RI_OUT.

GND

CCA

CCB

CCP

CCZ

A1, D4, D8, D13, D17, H4, H17,

N4, N17, U4, U8, U13, U17

D6, D11, D15, F4, F17, K4, L17,

CCI

R4, R17, U6, U10, U15

K2, R3, W5 J4, N6, W5

B16, C10, F18, A15, B10, F19

V10 P9

K20, P18, V15, W20 K14, N18, V14, V18 Clamp voltage for PCI signaling (3.3 Vdc or 5 Vdc)

A4, D1 D6, E4

, PCREQ,

TERMINAL

NAME GFN NO. GJG NO.

CLOCK U12 R11 I/O

DATA V12 T11 O

LATCH W12 V11 O

I/O

TYPE

Table 4. PC Card Power Switch

3-line power switch clock. Information on the DA TA line is sampled at the rising edge of CLOCK. This terminal defaults as an input which means an external clock source must be used. If the internal ring oscillator is used, then an external CLOCK source is not required. The internal oscillator may be enabled by setting bit 27 of the

(PCI offset 80h) to a 1b.

A 43

pulldown resistor should be tied to this terminal.

3-line power switch data. DA TA is used to serially communicate socket power-control information to the power switch.

3-line power switch latch. LA TCH is asserted by the PCI1450 to indicate to the PC Card power switch that the data on the DATA line is valid.

system control

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FUNCTION

terminal functions (continued)

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

T able 5. PCI System

TERMINAL

NAME GFN NO. GJG NO.

CLKRUN

PCLK J17 J15 I

PRST

G_RST F1 F4 I

J18 J16 I/O

J19 J18 I

I/O

TYPE

PCI clock run. CLKRUN is used by the central resource to request permission to stop the PCI clock or to slow it down, and the PCI1450 responds accordingly. If CLKRUN implemented, then this pin should be tied low. CLKRUN (KEEPCLK) in the

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1450 to place all output buffers in a high-impedance state and reset all internal registers. When PRST the device is completely nonfunctional. After PRST default state. When the SUSPEND and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

Global reset. When the global reset is asserted, the G_RST signal causes the PCI1450 to 3-state all output buffers and reset all internal registers. When G_RST is completely in its default state. For systems that require wake-up from D3, G_RST normally be asserted only during initial boot. PRST so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, G_RST

system control register

mode is enabled, the device is protected from the PRST ,

should be tied to PRST.

is enabled by default by bit 1

is deasserted, the PCI1450 is in its

is asserted, the device

should be asserted following initial boot

is not

is asserted,

will

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FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 6. PCI Address and Data

TERMINAL

NAME GFN NO. GJG NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

C/BE3 C/BE2 C/BE1 C/BE0

PAR Y20 W18 I/O

K18 K19 L20 L18

L19 M20 M19 M18 N19 N18 P20 P19 R20 R19 P17 R18 V18 Y19 W18 V17 U16 Y18 W17 V16 W16 U14 Y16 W15 V14 Y15 W14 Y14

M17

T20 W19 Y17

K16 K18 L14 L15 L18 L19 L16 M15 M19 M14 N16 N19 N15 P18 P19 P16 T16

W17

V16

W16

T15 V15

W15

P14 T14

W14

P13 T13 V13

W13

N13 R12

M16 P15 V17 R14

TYPE

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit

I/O

address or other destination information. During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte

I/O

paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PCI bus parity. In all PCI bus read and write cycles, the PCI1450 calculates even parity across the AD31–AD0 and C/BE3 parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR

–C/BE0 buses. As an initiator during PCI cycles, the PCI1450 outputs this

–C/BE0 define the bus command.

applies to byte 0 (AD7–AD0), C/BE1

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FUNCTION

terminal functions (continued)

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Table 7. PCI Interface Control

TERMINAL

NAME GFN NO. GJG NO.

DEVSEL

FRAME

GNT

GPIO2/LOCK

IDSEL N20 M18 I

IRDY

PERR

REQ

SERR

STOP

TRDY

V20 T18 I/O

T19 R18 I/O

J20 J14 I

V19 V19 I/O

T18 R19 I/O

U18 U18 I/O

K17 K15 O

U19 U19 O

T17 T19 I/O

U20 R16 I/O

I/O

TYPE

PCI device select. The PCI1450 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1450 monitors DEVSEL target responds before timeout occurs, then the PCI1450 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1450 access to the PCI bus after the current data transaction has completed. GNT request, depending on the PCI bus parking algorithm.

PCI bus general-purpose I/O pins or PCI bus lock. GPIO2/LOCK can be configured as PCI

and used to gain exclusive access downstream. Since this functionality is not typically

LOCK used, a general-purpose I/O may be accessed through this terminal. GPIO2/LOCK to a general-purpose input and can be configured through the

Initialization device select. IDSEL selects the PCI1450 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both

and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states

IRDY are inserted.

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR

PCI bus request. REQ is asserted by the PCI1450 to request access to the PCI bus as an initiator.

PCI system error. SERR is an output that is pulsed from the PCI1450 when enabled through

command register

the target of the PCI cycle to assert this signal. When SERR

, this signal also pulses, indicating that an address parity error has occurred on a

CardBus interface. PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current

PCI bus transaction. STOP devices that do not support burst data transfers.

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

is deasserted, the PCI bus transaction is in the final data phase.

is enabled through bit 6 of the

, indicating a system error has occurred. The PCI1450 need not be the

is used for target disconnects and is commonly asserted by target

until a target responds. If no

may or may not follow a PCI bus

GPIO2 control register

command register

is enabled in the

defaults

bridge control

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PCI1450 GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 8. System Interrupt

TERMINAL

NAME GFN NO. GJG NO.

GPIO3/INTA

IRQSER/INTB W13 W12 I/O

IRQMUX7 IRQMUX6 IRQMUX5 IRQMUX4 IRQMUX3 IRQMUX2 IRQMUX1 IRQMUX0

RI_OUT/PME Y13 P12 O

NAME GFN NO. GJG NO.

PCGNT/

IRQMUX6

PCREQ/

IRQMUX7

V13 T12 I/O

Y12 U11

W10

V9 U9 Y8

TERMINAL

U11 R10 I/O

Y12 P11 O

P11 R10

T9 R8 T8 V8

I/O

TYPE

I/O

TYPE

Parallel PCI interrupt. INT A can be optionally mapped to GPI03 when parallel PCI interrupts are used.

programmable interrupt subsystem

See defaults to a general-purpose input.

Serial interrupt signal. IRQSER provides the IRQSER-style serial interrupting scheme. Serialized PCI interrupts can also be sent in the IRQSER stream. See

subsystem

when one of the parallel interrupt modes is selected in the Interrupt request/secondary functions multiplexed. The primary function of these terminals is

to provide the ISA-type IRQ signaling supported by the PCI1450. These interrupt multiplexer outputs can be mapped to any of 15 IRQs. The for the ISA IRQ interrupt mode and the programmed before these terminals are enabled.

All of these terminals have secondary functions, such as PCI INTB request/grant, ring indicate output, and zoom video status, that can be selected with the appropriate programming of this register. When the secondary functions are enabled, the respective terminals are not available for IRQ routing.

See the Ring indicate out and power management event output. Terminal provides an output for

ring-indicate or PME

for details on interrupt signaling. This terminal can be used to signal PCI INTB

IRQMUX routing register

signals.

for details on interrupt signaling. GPIO3/INTA

programmable interrupt

device control register

IRQMUX routing register

for programming options.

must be programmed

must have the IRQ routing

, PC/PCI DMA

T able 9. PC/PCI DMA

PC/PCI DMA grant. PCGNT is used to grant the DMA channel to a requester in a system supporting the PC/PCI DMA scheme.

Interrupt request MUX 6. When configured for IRQMUX6, this terminal provides the IRQMUX6 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX6 takes precedence over PCGNT PC/PCI DMA.

This terminal is also used for the serial EEPROM interface. PC/PCI DMA request. PCREQ is used to request DMA transfers as DREQ in a system

supporting the PC/PCI DMA scheme. Interrupt request MUX 7. When configured for IRQMUX7, this terminal provides the IRQMUX7

interrupt output of the interrupt multiplexer, and can be mapped to any of 15 ISA-type IRQs. IRQMUX7 takes precedence over PCREQ PC/PCI DMA.

This terminal is also used for the serial EEPROM interface.

, and should not be enabled in a system using

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I/O

terminal functions (continued)

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Table 10. Zoom Video

TERMINAL

NAME

ZV_HREF

ZV_VSYNC

ZV_Y7 ZV_Y6 ZV_Y5 ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0

ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 ZV_UV2 ZV_UV1 ZV_UV0

ZV_SCLK C2 B1 A7 O Audio SCLK PCM

ZV_MCLK D3 C2 A6 O Audio MCLK PCM

ZV_PCLK E1 E2 IOIS16 O Pixel clock to the zoom video port ZV_LRCLK E3 E5 INPACK O Audio LRCLK PCM ZV_SDATA E2 E1 SPKR O Audio SDATA PCM

ZV_RSVD1 ZV_RSVD0

GFN

GJG NO.

NO.

A6 G7 A10 O C7 A7 A11 O A3

B4 C5 B5 C6 D7 A5 B6

D2 C3 B1 B2 A2 C4 B3 D5

C1 E4

I/O AND MEMORY

B5 A5 E6 B6 A6 F7 E7 B7

C1 A2 B2 A3 B3 A4 B4 D5

D2 D1

INTERFACE

SIGNAL

A20 A14 A19 A13 A18

A17

A25 A12 A24 A15 A23 A16 A22 A21

A5 A4

TYPE

Horizontal sync to the zoom video port Vertical sync to the zoom video port

O Video data to the zoom video port in YV:4:2:2 format

Reserved. No connection in the PC Card. ZV_RSVD1 and ZV_RSVD0

are put into the high-impedance state by host adapter.

FUNCTION

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PCI1450 GFN/GJG

I/O

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

TERMINAL

NAME GFN NO.

GPIO0/LEDA1 V11 T10 I/O

GPIO1/LEDA2 W1 1 V10 I/O

SPKROUT

SUSPEND

Y10 P10 O

Y11 W10 I

GJG

NO.

TYPE

Table 11. Miscellaneous

FUNCTION

GPIO0/socket activity LED indicator 1. When GPIO0/LEDA1 is configured as LEDA1, it provides an output indicating PC Card socket 0 activity. Otherwise, GPIO0/LEDA1 can be configured as a general-purpose input and output, GPIO0. The zoom video enable signal (ZV_STAT) can also be routed to this signal through the GPIO0/LEDA1 defaults to a general-purpose input.

GPIO1/socket activity LED indicator 2. When GPIO1/LEDA2 is configured as LEDA2, it provides an output indicating PC Card socket 1 activity. Otherwise, GPIO1/LEDA2 can be configured as a general-purpose input and output, GPIO1. A CSC interrupt can be generated on a GPDATA change, and this input can be used for power switch overcurrent (OC) sensing. See general-purpose input.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1450 from the PC Card interface. SPKROUT is driven as the XOR combination of card SPKR

Suspend. SUSPEND is used to protect the internal registers from clearing when PRST is asserted. See

GPIO1 control register

//CAUDIO inputs.

suspend mode

for details.

for programming details. GPIO1/LEDA2 defaults to a

GPIO0 control register

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FUNCTION

terminal functions (continued)

Table 12. 16-bit PC Card Address and Data (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal T4 is A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal C14 is B_A25.

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SLOT

†

T4 U2 U1 P4 R2 R1 P1 N2 M4 T1 T2 P2 N3 T3 M1

L1 M3 N1 V1 V2 V3

W2 W3 W4

V4 U5

J4 H2 G1

Y7 V7

J3 H1 H3 G2 V8

SLOT

‡

C14 B15 C15 C16 A18 C17 B18 A20 C18 A17 A16 B17 A19 D14 D18 E18 B20 B19 A15 A14 B13 A13 C12 A12 B11 C11

E19

E20 G18 G19

H18

B7 C8 A8

G17

F19

F20 G20

H19

A7 B8 D9

SLOT

†

R2 P6 P2 N5

N1 M5 M2

L2 N4 P1 M4 M1 P4 K4

L4 R1

T4 U2 V2 W3 V3 W4

J1 H2 H6 G1 G6 W8 W7 R7 H4 H1 G4 G5

T7 V7 P7

SLOT

E13 A14 E14 E15 B16 B17 A18 B19 D16 D15 B15 A17 B18 D14 D19 F15 C19 C18 F13 A13 A12 B12 E12 A11 B11 E11

F18 G15 G19 H15 H18

E8 B8

E9 G14 G18 G13 H16 H19

I/O

TYPE

‡

O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

PCI1450 GFN/GJG

PC CARD CONTROLLER

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PCI1450 GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 13. 16-bit PC Card Interface Control (slots A and B)

TERMINAL

GFN NO. GJG NO.

NAME

BVD1

(STSCHG

BVD2

(SPKR

CD1 CD2

CE1 CE2

INPACK Y1 D12 V1 D12 I

IORD

IOWR

SLOT

/RI)

)

SLOT

†

V6 A9 R6 E10 I

Y5 D10 V5 D10 I

G3W6H20C9F1W6H14

K1L2D20

L4 E17 K2 E16 O

M2 C19 L6 D18 O

SLOT

‡

D19J2K6

SLOT

†

F16 E19

I/O

TYPE

‡

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 and BVD2 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See the enable bits. See

status register

Status change. STSCHG write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that

include batteries. BVD2 and BVD1 indicate the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See enable bits. See

for the status bits for this signal.

Speaker. SPKR socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1450 and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1

are pulled low. For signal status, see Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1 enables even-numbered address bytes, and CE2 enables

odd-numbered address bytes. Input acknowledge. INP ACK is asserted by the PC Card when it can respond to an

I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA

operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the PCI1450 to enable 16-bit I/O PC Card data output during host I/O read cycles.

DMA write. IORD 16-bit PC Card that supports DMA. The PCI1450 asserts IORD transfers from the PC Card to host memory.

I/O write. IOWR is driven low by the PCI1450 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

DMA read. IOWR 16-bit PC Card that supports DMA. The PCI1450 asserts IOWR during transfers from host memory to the PC Card.

ExCA card status-change interrupt configuration register

ExCA card status-change register

for the status bits for this signal.

is used to alert the system to a change in the READY,

is used by 16-bit modem cards to indicate a ring detection.

ExCA card status-change interrupt configuration register

ExCA card status-change register

is an optional binary audio signal available only when the card and

ExCA interface status register

is used as the DMA write strobe during DMA operations from a

and the

ExCA interface status

ExCA interface

and CD2

during DMA

for

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FUNCTION

PC CARD CONTROLLER

terminal functions (continued)

Table 13. 16-bit PC Card Interface Control (slots A and B) (continued)

TERMINAL

GFN NO. GJG NO.

NAME

OE L3 C20 K1 E18 O

READY

(IREQ

REG

RESET W1 C13 T2 D13 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card.

WAIT

WE P3 D16 N7 A16 O

(IOIS16

VS1 VS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal P3 is A_WE.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal D16 is B_WE

SLOT

†

Y4 A10 T5 F10 I

)

Y2 B12 W2 D11 O

V5 B10 R5 A10 I

U7 B9 T6 A9 I

)

Y3U3A11

SLOT

‡

B14V4R4

SLOT

†

F11

B13

I/O

TYPE

‡

Output enable. OE is driven low by the PCI1450 to enable 16-bit memory PC Card data output during host memory read cycles.

DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1450 asserts OE to indicate TC for a DMA write operation.

Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.

Interrupt request. IREQ that a device on the 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested.

Attribute memory select. REG remains high for all common memory accesses. When REG and to the I/O space (IORD accessed section of card memory and is generally used to record card capacity and other configuration and attribute information.

DMA acknowledge. REG operations to a 16-bit PC Card that supports DMA. The PCI1450 asserts REG indicate a DMA operation. REG or DMA write (IORD

Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress.

Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies.

DMA terminal count. WE that supports DMA. The PCI1450 asserts WE to indicate TC for a DMA read operation.

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.

I/O is 16 bits. IOIS16 PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation.

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with

I/O

each other, determine the operating voltage of the 16-bit PC Card.

is asserted, access is limited to attribute memory (OE or WE active)

is asserted by a 16-bit I/O PC Card to indicate to the host

or IOWR active). Attribute memory is a separately

is used as a DMA acknowledge (DACK) during DMA

is used in conjunction with the DMA read (IOWR)

) strobes to transfer data.

is used as TC during DMA operations to a 16-bit PC Card

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit

PCI1450 GFN/GJG

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PCI1450 GFN/GJG

FUNCTION

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 14. CardBus PC Card Interface System (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CCLK T1 A17 N4 D15 O

CCLKRUN

CRST

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal T1 is A_CCLK.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal A17 is B_CCLK.

SLOT

†

U7 B9 T6 A9 O

W1 C13 T2 D13 I/O

SLOT

‡

SLOT

†

I/O

TYPE

‡

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST CAUDIO, CCD2:1 all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1450 to indicate that the CCLK frequency is decreased. CardBus clock run (CCLKRUN (CLKRUN

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST Card signals must be 3-stated, and the PCI1450 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

, and CVS2–CVS1 are sampled on the rising edge of CCLK, and

, CCLKRUN, CINT, CSTSCHG,

) follows the PCI clock run

is asserted, all CardBus PC

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FUNCTION

terminal functions (continued)

Table 15. CardBus PC Card Address and Data (slots A and B)

TERMINAL

E8 B8

F8 E9 D9

I/O

TYPE

‡

PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle,

I/O

CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit.

CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle,

–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is

CC/BE3 used as byte enables. The byte enables determine which byte paths of the full 32-bit data

I/O

bus carry meaningful data. CC/BE0 to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 3 (CAD31–CAD24).

CardBus parity. In all CardBus read and write cycles, the PCI1450 calculates even parity across the CAD and CC/BE outputs CPAR with a one-CCLK delay . As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

applies to byte 0 (CAD7–CAD0), CC/BE1 applies

applies to byte 2 (CAD23–CAD8), and CC/BE3

buses. As an initiator during CardBus cycles, the PCI1450

GFN NO. GJG NO.

NAME

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR N3 A19 M1 B18 I/O

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal N3 is A_CPAR.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal A19 is B_CPAR.

SLOT

†

V7 Y6 U5

V4 W4 W3 W2

U2 M4 M2 M3

L3 L2 L1

J1 J4

J3 H2 H1 G1 H3 G2

Y2 T3 N1 K1

SLOT

‡

B7 C8 B8 A8

D9 C11 B11 A12 C12 A13 B13 A14 C14 A15 B15 C18 C19 B20 E17 D18 C20 D19 E18 E19 G17 G18 F19 G19 F20 H18 G20 H19

B12 D14 B19 D20

SLOT

†

W8 W7

V7 R7 P7

V2 U2 T4 T1 R2 R1 P6

L2 L6

L1 K2 K4 K1 K6

J1 H4 H6 H1 G1 G4 G6 G5 F2

SLOT

E11 B11 A11 E12 B12 A12 A13 E13 F13

A14 D16 D18 C19

E16 D19

E18

E19

F15

F18 G14 G19 G18 H15 G13 H18 H16 H19

D11 D14 C18

F16

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

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PCI1450 GFN/GJG

FUNCTION

ith CVS1

CVS2 to identif

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

terminal functions (continued)

Table 16. CardBus PC Card Interface Control (slots A and B)

TERMINAL GFN NO. GJG NO.

NAME

CAUDIO Y5 D10 V5 D10 I

CBLOCK

CCD1 CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 CVS2

†

Terminal name for slot A is preceded with A_. For example, the full name for terminal Y5 is A_CAUDIO.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminal D10 is B_CAUDIO.

SLOT

†

P1 B18 M2 A18 I/O

G3 H20 F1 H14

W6 C9 W6 B9

R2 A18 N1 B16 I/O

U1 C15 P2 E14 I/O

P3 D16 N7 A16 I

Y4 A10 T5 F10 I

T2 A16 P1 B15 I/O

P2 B17 M4 A17 I/O

Y1 D12 V1 D12 I

V5 B10 R5 A10 I

R1 C17 M5 B17 I/O

V6 A9 R6 E10 I

P4 C16 N5 E15 I/O

Y3U3A11

SLOT

‡

B14V4R4

SLOT

†

F11

B13

I/O

TYPE

‡

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1450 supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction

w operating voltage and card type.

CardBus device select. The PCI1450 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1450 monitors CDEVSEL the PCI1450 terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME transfers continue while this signal is asserted. When CFRAME CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the PCI1450 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY both sampled asserted, wait states are inserted.

CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1450 can report CSERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the CardBus target’ s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used

I/O

in conjunction with CCD1 to determine the operating voltage and card type.

and

until a target responds. If no target responds before timeout occurs, then

is asserted to indicate that a bus transaction is beginning, and data

y card insertion and interrogate cards to determine the

and CTRDY are asserted. Until CIRDY and CTRDY are

to the system by assertion of SERR on the PCI interface.

and CTRDY are asserted; until this time, wait states are

and CCD2 to identify card insertion and interrogate cards

is deasserted, the

is driven by the card synchronous to

is used for target disconnects, and is

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I/O characteristics

PCI1450 GFN/GJG

PC CARD CONTROLLER

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Figure 3 shows a 3-state bidirectional buffer illustration for reference. The table,

conditions

provides the electrical characteristics of the inputs and outputs. The PCI1450 meets the ac

recommended operating

specifications of the PC Card 95 Standard and the PCI Bus 2.1 specifications.

Tied for Open Drain

CCP

Pad

Figure 3. 3-State Bidirectional Buffer

clamping rail splits

The I/O sites can be pulled through a clamping diode to a power rail for protection. The core power supply is independent of the clamping rails. The clamping (protection) diodes are required if the signaling environment on an I/O is system dependent. For example, PCI signaling can be either 3.3 Vdc or 5.0 Vdc, and the PCI1450 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V buffer with tolerance (protection) at V

5.0-V power supply. A standard die has only one clamping rail for the sites as shown in Figure 3. After the terminal assignments

are fixed, the fabrication facility will support a design by splitting the clamping rail for customization. The PCI1450 requires five separate clamping rails since it supports a wide range of features. The five rails are listed and defined in the table,

. If a system design requires a 5.0-V PCI bus, then the V

CCP

recommended operating conditions

would be connected to the

CCP

PCI interface

This section describes the PCI interface of the PCI1450, and how the device responds and participates in PCI bus cycles. The PCI1450 provides all required signals for PCI master/slave devices, and may operate in either 5-V or 3.3-V PCI signaling environments by connecting the V

PCI bus lock (LOCK)

The bus locking protocol defined in the PCI Specification is not highly recommended, but is provided on the PCI1450 as an additional compatibility feature. The PCI LOCK terminal is multiplexed with GPIO2, and the terminal function defaults to a general-purpose input (GPI). The use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions may proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. To avoid confusion with the PCI bus clock, the CardBus signal for this protocol is CBLOCK

An agent may need to do an exclusive operation because a critical memory access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive, real-time data transfer, such as video.

terminals to the desired signaling level.

CCP

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The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress.

The PCI1450 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions, and blocks access as the target until it completes a delayed read. This target characteristic is prohibited by the 2.1 PCI Specification, and the issue is resolved by the PCI master using LOCK

loading the subsystem identification (EEPROM interface)

The

subsystem vendor ID register

space located at offset 40h for functions 0 and 1. This doubleword register, used for system and option card (mobile dock) identification purposes, is required by some operating systems. Implementation of this unique identifier register is a PC ‘97 requirement.

The PCI1450 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but the access mode may be made read/write by clearing the SUBSYSRW bit in the the BIOS may write a subsystem identification value into the registers at offset 40h. The BIOS must set the SUBSYSRW bit such that the access. This approach saves the added cost of implementing the serial EEPROM.

system control register

and

subsystem ID register

(bit 5 of the

system control register

subsystem vendor ID register

make up a double-word of PCI configuration

, offset 80h). Once this bit is cleared (0),

and

subsystem ID register

are limited to read-only

In some conditions, such as in a docking environment, the

double-word of data from the serial EEPROM after a reset of the primary bus. The SUSPEND input gates the PRST and G_RST from the entire PCI1450 core, including the serial EEPROM state machine. Refer to

mode

EEPROM. The system designer must implement a pulldown resistor on the PCI1450 LA TCH terminal to indicate the serial

EEPROM mode. Only when this pulldown resistor is present will the PCI1450 attempt to load data through the serial EERPOM interface. The serial EEPROM interface is a two-pin interface with one data signal (SDA) and one clock signal (SCL). The SDA signal is mapped to the PCI1450 IRQMUX6 terminal and the SCL signal is mapped to the PCI1450 IRQMUX7 terminal. Figure 4 illustrates a typical PCI1450 application using the serial EEPROM interface.

must be loaded with a unique identifier through a serial EEPROM interface. The PCI1450 loads the

for details on using SUSPEND. The PCI1450 provides a two-line serial bus interface to the serial

subsystem vendor ID register

and

subsystem ID

suspend

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Serial EEPROM

A0 A1A2SCL

SDA

IRQMUX7 IRQMUX6

PCI1450

Latch

Figure 4. Serial EEPROM Application

As stated above, when the PCI1450 is reset by G_RST, the subsystem data is read automatically from the EEPROM. The PCI1450 masters the serial EEPROM bus and reads four bytes as described in Figure 5.

Slave Address

b6 b5 b4 b3 b2 b1 b0 0 A b7 b6 b5 b4 b3 b2 b1 b0 A S b6 b5 b4 b3 b2 b1 b0 1 A

R/W# Restart

Data Byte 0 M PData Byte 1 M Data Byte 2 M Data Byte 3 M

S/P – Start/Stop Condition A – Slave Acknowledgment M – Master Acknowledgment

Word Address Slave Address

R/W#

Figure 5. EEPROM Interface Subsystem Data Collection

The EEPROM is addressed at word address 00h, as indicated in Figure 5, and the address auto-increments after each byte transfers according to the protocol. Thus, to provide the subsystem register with data AABBCCDDh the EEPROM should be programmed with address 0 = AAh, 1 = BBh, 2 = CCh, and 3 = DDh.

The serial EEPROM is addressed at slave address 1010000b by the PCI1450. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit, Figure 4, assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

The serial EEPROM interface signals require pullup resistors. The serial EEPROM protocol allows bidirectional transfers. Both the SCL and SDA signals are 3-stated and pulled high when the bus is not active. When the SDA line transitions to a logic low, this signals a start condition (S). A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). One bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. Data is valid and stable during the clock high period. Figure 6 illustrates this protocol.

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SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 6. Serial EEPROM Start/Stop Conditions and BIt Transfers

Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 5. When the PCI1450 transmits the addresses, it returns the SDA signal to the high state and 3-states the line. The PCI1450 then generates an SCL clock cycle and expects the EEPROM to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a slave acknowledge with the PCI1450 transmitter and the EEPROM receiver. Figure 7 illustrates general acknowledges.

During the data byte transfers from the serial EEPROM to the PCI1450, the EEPROM clocks the SCL signal. After the EEPROM transmits the data to the PCI1450, it returns the SDA signal to the high state and 3-states the line. The EEPROM then generates an SCL clock cycle and expects the PCI1450 to pull down the SDA line during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM transmitter and the PCI1450 receiver. Figure 7 illustrates general acknowledges.

SCL From

Master

SDA Output

By Transmitter

123 789

SDA Output

By Receiver

Figure 7. Serial EEPROM Protocol – Acknowledge

EEPROM interface status information is communicated through the

general status register

located at PCI offset 85h. The EEDETECT bit in this register indicates whether or not the PCI1450 serial EEPROM circuitry detects the pulldown resistor on LA TCH. An error condition, such as a missing acknowledge, results in the DATAERR bit being set. The EEBUSY bit is set while the

subsystem ID register

is loading (serial EEPROM interface is

busy).

PC Card applications overview

This section describes the PC Card interfaces of the PCI1450. A discussion is provided on PC Card recognition, which details the card interrogation procedure. The card powering procedure is discussed in this section including the protocol of the P2C power switch interface. The internal ZV buffering provided by the PCI1450 and programming model is detailed in this section. Also, standard PC Card register models are described, as well as a brief discussion of the PC Card software protocol layers.

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PC Card insertion/removal and recognition

The 1995 PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface (16-bit vs. CardBus) are determined.

The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four pins in a certain configuration depending on the type of card and the supply voltage. The encoding scheme for this, defined in the 1997 PC Card Standard, is shown in Table 17.

Table 17. PC Card – Card Detect and Voltage Sense Connections

CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 Key Interface Voltage

Ground Ground Open Open 5 V 16-bit PC Card 5 V Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V

Ground Ground Ground Ground 5 V 16-bit PC Card Ground Ground Open Ground LV 16-bit PC Card 3.3 V

Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V

Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card

Ground Ground Ground Open LV 16-bit PC Card Y.Y V

Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card Y.Y V

Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V

Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V

Ground Connect to CVS1 Ground Connect to CCD1 Reserved Ground Connect to CVS2 Connect to CCD1 Ground Reserved

5 V, 3.3 V, and

X.X V

3.3 V, X.X V, and Y.Y V

P2C power switch interface (TPS2202A/2206)

A power switch with a PCMCIA-to-peripheral control (P2C) interface is required for the PC Card powering interface. The TI TPS2206 (or TPS2202A) Dual-Slot PC Card Power-Interface Switch provides the P2C interface to the CLOCK, DA T A, and LA TCH terminals of the PCI1450. Figure 8 shows the terminal assignments of the TPS2206. Figure 9 illustrates a typical application where the PCI1450 represents the PCMCIA controller.

There are two ways to provide a clock source to the power switch interface. The first method is to provide an external clock source such as a 32 kHz real time clock to the CLOCK terminal. The second method is to use the internal ring oscillator. If the internal ring oscillator is used, then the PCI1450 provides its own clock source for the PC Card interrogation logic and the power switch interface. The mode of operation is determined by the setting of bit 27 of the

system control register

(PCI offset 80h). This bit is encoded as follows: 0 = CLOCK terminal (terminal U12) is an input (default). 1 = CLOCK terminal is an output that utilizes the internal oscillator.

A 43 kW pulldown resistor should be tied to the CLOCK pin.

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Power Supply

12V

3.3V

Supervisor

5V 5V

DATA

CLOCK

LATCH

RESET

12V

AVPP AVCC AVCC AVCC

GND

RESET

3.3V

NC – No internal connection

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

5V NC NC NC NC NC 12V BVPP BVCC BVCC BVCC NC OC

3.3V

Figure 8. TPS2206 Terminal Assignments

TPS2206

12V 5V

3.3V

RESET RESET

AVPP

AVCC AVCC AVCC

V V V

PP1 PP2 CC

PC Card A

V V V

PP1 PP2 CC

PC Card B

PCI1450

PC Card Interface (68 pins/socket)

Serial I/F

BVCC BVCC BVCC

BVPP

Figure 9. TPS2206 Typical Application

zoomed video support

The zoomed video (ZV) port on the PCI1450 provides an internally buffered 16-bit ZV PC Card data path. This internal routing is programmed through the subsystem implemented in the PCI1450, and details the bit functions found in the

An output port (PORTSEL) is always selected. The PCI1450 defaults to socket 0 (see the

). When ZVOUTEN is enabled, the zoom video output terminals are enabled and allow the PCI1450

multimedia control register

. Figure 9 summarizes the zoomed video

multimedia control register

multimedia control

to route the zoom video data. However, no data is transmitted unless either ZVEN0 or ZVEN1 is enabled in the

multimedia control register

. If the PORTSEL maps to a card port that is disabled (ZVEN =0 or ZVEN1 = 0), then

the zoom video port is driven low (i.e., no data is transmitted).

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Card Output

Enable Logic

PC Card Socket 0

PC Card Socket 1

Zoomed Video Subsystem

ZVEN0

PC Card

I/F

PC Card

I/F

ZVOUTEN

PORTSEL

Note: ZVSTAT must be enabled through the GPIO Control Register

ZVSTAT

19 Video Signals

VGA

Audio

Codec

4 Audio Signals

ZVEN1

NOTES: A. ZVSTA T must be enabled through the GPIO control register.

Figure 10. Zoomed Video Subsystem

zoomed video auto detect

Zoomed video auto detect, when enabled, allows the PCI1450 to automatically detect zoomed video data by sensing the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. The PCI1450 automatically switches the internal zoomed video MUX to route the zoomed video stream to the PCI1450’s zoomed video output port. This eliminates the need for software to switch the internal MUX using the

multimedia control register

(PCI offset 84h, bits 6 and 7).

The PCI1450 can be programmed to switch a third zoomed video source by programming IRQMUX2 as a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed video source. ZVST AT may then be programmed onto IRQMUX4 and this signal may switch the zoomed video buffers from the third zoomed video source. To account for the possibility of several zoomed video sources being enabled at the same time, a programmable priority scheme may be enabled.

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The PCI1450 defaults with zoomed video auto-detect disabled so that it will function exactly like the PCI1250A. To enable zoomed video auto-detect and the programmable priority scheme, the following bits must be set:

Multimedia control register

000 = Slot A, Slot B, External Source 001 = Slot A, External Source, Slot B 010 = Slot B, Slot A, External Source 011 = Slot B, External Source, Slot A 100 = External Source, Slot A, Slot B 101 = External Source, Slot B, Slot A 110 = External Source, Slot B, Slot A 111 = Reserved

If it is desired to switch a third zoomed video source, then the following bits must also be set:

IRQMUX routing register

input pin.

IRQMUX routing register

Card Output

Enable Logic

(PCI offset 84h) bit 5: Writing a 1b enables zoomed video auto-detect (PCI offset 84h) bits 4–2: Set the programmable priority scheme

(PCI offset 8Ch), bits 11–8: Write 0010b to program IRQMUX2 as a pixel clock

(PCI ofset 8Ch), bits 19–16: Write 0001b to program IRQMUX4 as a ZVST A T pin.

Zoomed Video Subsystem

3rd Zoomed Video Source

ZVEN0

PC Card Socket 0

PC Card Socket 1

PC Card

I/F

Pixel Clock Sense

Auto Z/V

Arbiter

Pixel Clock Sense

PC Card

I/F

ZVEN1

Pixel Clock Sense

Programmed on IRQMUX2

ZVSTAT

ZV Data

IRQMUX2

Buffers

Enable

VGA

19 Video Signals

Audio

Codec

4 Audio Signals

Figure 11. Zoomed Video with Auto Detect Enabled

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ultra zoomed video

Ultra zoomed video is an enhancement to the PCI1450’s DMA engine and is intended to improve the 16-bit bandwidth for MPEG I and MPEG II decoder PC Cards. This enhancement allows the 1450 to fetch 32 bits of data from memory versus the 1 1XX/12XX 16-bit fetch capability. This enhancement allows a higher sustained throughput to the 16-bit PC Card because the 1450 prefetches an extra 16 bits (32 bits total) during each PCI read transaction. If the PCI Bus becomes busy, then the 1450 has an extra 16 bits of data to perform back-to-back 16-bit transactions to the PC Card before having to fetch more data. This feature is built into the DMA engine and software is not required to enable this enhancement.

NOTE:The 11XX and 12XX series CardBus controllers have enough 16-bit bandwidth to support MPEG II PC Card decoders. But it was decided to improve the bandwidth even more in the 14XX series CardBus controllers.

D3_STAT pin

Additional functionality added for the 1450 versus the 1250A/1251 series is the D3_ST A T pin is asserted under the following two conditions (both conditions must be true before D3_ST AT

Function 0 and Function 1 are placed in D3

PME is enabled

The intent of including this feature in the PCI1450 is to use this pin to switch an external VCC/V feature can be programmed on GPIO1 pin (terminal W1 1) by writing 01b to bits 7–6 of the

(D3 status) pin. This

is asserted):

AUX

GPIO1 control register

(PCI offset 89h).

internal ring oscillator

The internal ring oscillator provides an internal clock source for the PCI1450 so that neither the PCI clock nor an external clock is required in order for the PCI1450 to power down a socket or interrogate a PC Card. This internal oscillator operates nominally at 16 kHz and can be enabled by setting bit 27 of the

(PCI offset 80h) to a 1b. This function is disabled by default.

system control

SPKROUT usage

The SPKROUT signal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 pin becomes SPKR is referred to as CAUDIO. SPKR

passes a TTL level digital audio signal to the PCI1450. The CardBus CAUDIO

. This terminal, also used in CardBus applications,

signal also can pass a single amplitude, binary waveform. The binary audio signals from the two PC Card sockets are XOR’ed in the PCI1450 to produce SPKROUT. Figure 12 illustrates the SPKROUT connection.

Bit 1, Card Control Register (offset 91h)

Card A SPKROUT Enable

Card A SPKR

Bit 1, Card Control Register (offset 91h)

Card B SPKROUT Enable

Card B SPKR

SPKROUT

switch. This

Speaker

Driver

Card A SPKROUT Enable Card B SPKROUT Enable

Figure 12. SPKROUT Connection to Speaker Driver

The SPKROUT signal is typically driven only by PC modem cards. To verify the SPKROUT on the PCI1450, a sample circuit was constructed, and this simplified schematic is provided below. The PCI1130/1131 required a pullup resistor on the SUSPEND/SPKROUT terminal. Since the PCI1450 does not multiplex any other function on SPKROUT, this terminal does not require a pullup resistor.

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SPKROUT

Figure 13. Simplified Test Schematic

LED socket activity indicators

The socket activity LEDs indicate when an access is occurring to a PC Card. The LED signals are multiplexed with general-purpose inputs and outputs (GPIOs); the default for these terminals is GPI. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. LEDA1 indicates socket 0 (card A) activity, and LEDA2 indicates socket 1 (card B) activity.

3 7 2

+ –

LM386

Speaker

The active-high LED signal is driven for 64 ms durations. When the LED is not being driven high, then it is driven to a low state. Either of the two circuits illustrated in Figure 14 can be implemented to provide the LED signaling, and it is left for the board designer to implement the circuit to best fit the application.

Current Limiting

R ≈ 500 Ω

PCI1450

Application-

Specific Delay

Current Limiting

R ≈ 500 Ω

LED

Figure 14. T wo Sample LED Circuits

As indicated, the LED signals are driven for 64 ms, and this is accomplished by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when either the SUSPEND signal is asserted or when the PCI clock is to be stopped per the CLKRUN protocol.

Furthermore, if any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals will remain driven.

PC Card 16 DMA support

The PCI1450 supports both PC/PCI (centralized) DMA and a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. Table 18 provides the DDMA register configuration.

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Reserved

Page

Reserved

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Table 18. Distributed DMA Registers

TYPE REGISTER NAME

R N/A

W Mode

R Multichannel

W Mask

N/A Status 08h

Request Command

N/A

Master Clear

Current address 00h

Base address Current count 04h

Base count

DMA BASE

ADDRESS OFFSET

CardBus socket register

The PCI1450 contains all registers for compatibility with the latest PCI to PCMCIA CardBus Bridge Specification. These registers exist as the CardBus socket registers, and are listed in Table 19.

Table 19. CardBus Socket Registers

Socket event 00h Socket mask 04h

Socket present state 08h

Socket force event 0Ch

Socket control 10h

Reserved 14h Reserved 18h Reserved 1Ch

Socket power management 20h

0Ch

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programmable interrupt subsystem

Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1450. The PCI1450 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based upon various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1450 is therefore backward compatible with existing interrupt control register definitions, and new registers have been defined where required.

The PCI1450 detects PC Card interrupts and events at the PC Card interface and notifies the host controller via one of several interrupt signaling protocols. T o simplify the discussion of interrupts in the PCI1450, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts.

The method by which any type of PCI1450 interrupt is communicated to the host interrupt controller varies from system to system. The PCI1450 offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. Traditional ISA IRQ signaling is provided through eight IRQMUX terminals. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow.

PC Card functional and card status change interrupts

PC Card functional interrupts are defined as requests from a PC Card application for interrupt service. They are indicated by asserting specially defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards.

Card status change (CSC) type interrupts are defined as events at the PC Card interface which are detected by the PCI1450 and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.

Table 20 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent upon the type of card inserted in the PC Card socket. The three types of cards that may be inserted into any PC Card socket are: 16-bit memory card, 16-bit I/O card, and CardBus cards. Functional interrupt events are valid only for 16-bit I/O and CardBus cards, that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal type CSC interrupts are independent of the card type.

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CSC

()

16-bit I/O

PC CARD CONTROLLER

Table 20. PC Card Interrupt Events and Description

Card Type Event Type Signal Description

BVD1 (STSCHG) // A transition on the BVD1 signal indicates a change

16-bit Memory

CardBus

All PC Cards

Battery conditions

(BVD1, BVD2)

Wait states

(READY)

Change in card status

(STSCHG)

Interrupt request

(IREQ)

Change in card status

(CSTSCHG)

Interrupt request

Power cycle complete CSC N/A

Card insertion or

Power cycle complete CSC N/A

(CINT

removal

)

CSC BVD2 (SPKR) // CAUDIO

CSC READY (IREQ) // CINT

CSC

Functional READY (IREQ) // CINT

CSC

Functional READY (IREQ) // CINT

CSC

CSTSCHG

BVD1 (STSCHG) //

CSTSCHG

BVD1 (STSCHG) //

CSTSCHG

CD1 // CCD1,

CD2 // CCD2

in the PC Card battery conditions. A transition on the BVD2 signal indicates a change

in the PC Card battery conditions. A transition on the READY signal indicates a change

in the ability of the memory PC Card to accept or provide data.

The assertion of the STSCHG signal indicates a status change on the PC Card.

The assertion of the IREQ signal indicates an interrupt request from the PC Card.

The assertion of the CSTSCHG signal indicates a status change on the PC Card.

The assertion of the CINT signal indicates an interrupt request from the PC Card.

An interrupt is generated when a PC Card power-up cycle has completed.

A transition on either the CD1//CCD1 signal or the

//CCD2 signal indicates an insertion or removal

CD2 of a 16-bit // CardBus PC Card.

An interrupt is generated when a PC Card power-up cycle has completed.

PCI1450 GFN/GJG

SCPS044 – SEPTEMBER 1998

The signal naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well as CardBus. For example, the READY(IREQ)//CINT signal includes the READY signal for 16-bit memory cards, the IREQ signal for 16-bit I/O cards, and the CINT signal for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second enclosed in parentheses. The CardBus signal name follows after a forward double slash (//).

The PC Card Standard describes the power-up sequence that must be followed by the PCI1450 when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1450 interrupt scheme may be used to notify the host system, as in indicated in Table 20, denoted by the power cycle complete event. This interrupt source is considered a PCI1450 internal event because it does not depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket.

interrupt masks and flags

Host software may individually mask, or disable, most of the potential interrupt sources listed in Table 21 by setting the appropriate bits in the PCI1450. By individually masking the interrupt sources listed in these tables, software can control which events will cause a PCI1450 interrupt. Host software has some control over which system interrupt the PCI1450 will assert by programming the appropriate routing registers. The PCI1450 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. A discussion of interrupt routing is somewhat specific to the interrupt signaling method used, and will be discussed in more detail in the next few sections.

When an interrupt is signaled by the PCI1450, the interrupt service routine must be able to discern which of the events in Table 21 caused the interrupt. Internal registers in the PCI1450 provide flags which report which of the interrupt sources was the cause of an interrupt. By reading these status bits, the interrupt service routine can determine which action is to be taken.

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Battery conditions

ExCA Offset 05h/45h/805h

ExCA Offset 04h/44h/804h

(BVD1, BVD2)

Bits 1 & 0

16-bit Memory

16-bit I/O

CardBus

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

T able 21 details the registers and bits associated with masking and reporting potential interrupts. All interrupts may be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Table 21. PCI1450 Interrupt Masks and Flags Registers

Card Type Event Mask Flag

Wait states

(READY)

Change in card status

(STSCHG

Interrupt request

All 16-bit PC Cards Power cycle complete

Change in card status

(CSTSCHG)

Interrupt request

Power cycle complete

Card insertion or removal

(IREQ

(CINT

)

ExCA Offset 05h/45h/805h

Bit 2

ExCA Offset 05h/45h/805h

Bit 0

Always enabled

ExCA Offset 05h/45h/805h

Bit 3

Socket mask register

Bit 0

Always enabled

Socket mask register

Bit 3

Socket mask register

Bits 2 & 1

ExCA Offset 04h/44h/804h

Bit 2

ExCA Offset 04h/44h/804h

Bit 0

PCI Configuration Offset 91h

Bit 0

ExCA Offset 04h/44h/804h

Bit 3

Socket event register

Bit 0

PCI Configuration Offset 91h

Bit 0

Socket event register

Bit 3

Socket event register

Bits 2 & 1

Notice that there is not a mask bit to stop the PCI1450 from passing PC Card functional interrupts through to the appropriate interrupt scheme. Functional interrupts should not be fired until the PC Card is initialized and powered.

There are various methods of clearing the interrupt flag bits listed in T able 21. The flag bits in the ExCA registers (16-bit PC Card related interrupt flags) may be cleared by two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is a reading of the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the flag cleared on read method.

The CardBus related interrupt flags can only be cleared by an explicit write of 1 to the interrupt flag in the

event register

registers, software should not program the chip through both register sets when a CardBus card is functioning.

legacy interrupt multiplexer

The IRQ multiplexer implemented in the PCI1450 provides a mechanism to route the IRQMUX signals to any of the 15 legacy IRQ signals. The IRQMUX7–6 signals share the PC/PCI DMA terminals, and take precedence when routed. The other 6 IRQMUX signals (IRQMUX5–IRQMUX0) are available in all platforms. To use the IRQMUX interrupt signaling, software must program the select the legacy IRQ signaling scheme.

Figure 15 illustrates the IRQMUX functionality. This illustration describes only the PCREQ/IRQMUX7/SCL signal.

socket

. Although some of the functionality is shared between the CardBus registers and the ExCA

device control register

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, located at PCI offset 92h, to

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

System Control Register (Bit 3):

When bit 3 = 0 EEPROM SCL is routed on IRQMUX7 When bit 3 = 1 PCREQ is routed on IRQMUX7

EEPROM SCL

PCREQ

0000

0001

  

0010

  

1111

IRQMUX Routing Register

PCREQ/IRQMUX7/SCL

Figure 15. Interrupt Mux Functionality – Example of IRQMUX7 Routing

If parallel ISA IRQs are selected in the

device control register

, then the

IRQMUX routing register

, located at PCI offset 8Ch, must be programmed with the associated ISA IRQ connections. The PCI1450 supports up to eight parallel ISA IRQ signal connections, IRQMUX7–IRQMUX0. Figure 16 is an example PCI1450 IRQ implementation that provides eight ISA interrupts. The system in this example cannot support PC/PCI DMA since all eight ISA IRQs are used. In this example, the IRQMUX7 and IRQMUX6 terminals are used to signal ISA IRQs, and are not available for PC/PCI DMA. For systems not using all eight IRQs, PC/PCI DMA can be implemented and coexist with ISA IRQs by using IRQMUX6 and IRQMUX7 for PC/PCI DMA, i.e., legacy IRQs and PC/PCI DMA implementation are not mutually exclusive. However, if the IRQMUX registers are programmed to use IRQMUX7–IRQMUX6, then they will override PC/PCI DMA.

PCI1450 PCI

IRQMUX0 IRQMUX1 IRQMUX2 IRQMUX3 IRQMUX4 IRQMUX5 IRQMUX6 IRQMUX7

IRQ3 IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15

Figure 16. Example PCI1450 IRQ Implementation

Software is responsible for programming the

IRQMUX routing register

to reflect the IRQ configuration shown in Figure 16. In this example, this programming is accomplished by writing a double-word of data FCBA9543h to the PCI1450

IRQMUX routing register

, PCI offset 8Ch. In this example (FCBA9543h), F corresponds to

IRQ15, C to IRQ12, B to IRQ11, A to IRQ10, 9 to IRQ9, 5 to IRQ5, 4 to IRQ4, and 3 to IRQ3.

IRQMUX routing register

The

is shared between the two PCI1450 functions, and only one write to function 0

or function 1 is necessary to configure the IRQMUX signals.

using parallel PCI interrupts

Parallel PCI interrupts are available when in pure parallel PCI interrupt mode, IRQMUX signaling mode, and when only IRQs are serialized with the IRQSER protocol. The PCI interrupt signaling is dependent upon the interrupt mode and is summarized in Table 22. The interrupt mode is selected in the

device control register

(92h). The IRQSER/INTB signals INTB when one of the parallel interrupt modes is selected via bits 2–1 in the

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device control register

to 0001b in the bits 7–6 in the

IRQMUX routing register

GPIO3 control register

(92h). PCI INTB is also available on the IRQMUX0 terminal by programming bits 3–0

(8Ch). PCI INT A is available on the GPIO3 terminal by programming

Table 22. Interrupt Pin Register Cross Reference

Interrupt Signaling Mode

Parallel PCI Interrupts Only 0x01 (INTA) 0x02 (INTB) Parallel IRQ & Parallel PCI Interrupts 0x01 (INTA) 0x02 (INTB) IRQ Serialized (IRQSER) & Parallel PCI Interrupts 0x01 (INTA) 0x01 (INTA) IRQ & PCI Serialized (IRQSER) Interrupts (default) 0x01 (INTA) 0x02 (INTB)

INTPIN

Function 0

INTPIN

Function 1

power management overview

In addition to the low-power CMOS technology process used for the PCI1450, various features are designed into the device to allow implementation of popular power saving techniques. These features and techniques are discussed in this section.

CLKRUN protocol

CLKRUN chipsets do not implement CLKRUN, this is not always available to the system designer, and alternate power savings features are provided.

If CLKRUN is not implemented, then the CLKRUN pin should be tied low. CLKRUN is enabled by default via bit 1 (KEEPCLK) in the

is the primary method of power management on the PCI bus side of the PCI1450. Since some

system control register

(80h).

CardBus PC Card power management

The PCI1450 implements its own card power management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The CCLK can also be configured as divide by 16 instead of stopped. The CLKRUN protocol is followed on the CardBus interface to control this clock management.

PCI bus power management

The PCI Bus Power Management Interface Specification (PCIPM) establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible power management states, which result in varying levels of power savings.

The four power management states of PCI functions are: D0 - Fully On state, D1 and D2 - intermediate states, and D3 - Off state. Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power state of the upstream bridge device.

For the operating system to manage the device power states on the PCI bus, the PCI function should support four power management operations. The four operations are: capabilities reporting; power status reporting; setting the power state; and system wake-up. The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by a 1b in bit 4 of the PCI seeing that bit 4 of the PCI

status register

(PCI offset 06h). When software determines that the device has a capabilities list by

status register

is set, it will read the

capability pointer register

at PCI offset 14h. This

value in the register points the location in PCI configuration space of the capabilities linked list.

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The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer should be set to 0. The registers following the next item pointer are specific to the function’s capability. The PCIPM capability implements the following register block:

Power Management Register Block

Power Management Capabilities (PMC) Next Item Pointer Capability ID Offset = 0

Data

The

power management capabilities (PMC) register

the capabilities of the function, related to power management. The PMCSR register enables control of power management states and enables/monitors power management events. The data register is an optional register that provides a mechanism for state-dependent power measurements such as power consumed or heat dissipation.

CardBus device class power management

The

PCI Bus Interface Specification for PCI-to-CardBus Bridges

1997. This specification follows the device and bus state definitions provided in the

Management Interface Specification

addressed in the without losing wake-up context (also called PME context).

PCI Bus Interface Specification for PCI-to-CardBus Bridges

PMCSR Bridge

Support Extensions

published by the PCI Special Interest Group (SIG). The main issue

Power Management Control Status (CSR) Offset = 4

is a static read-only register that provides information on

was approved by PCMCIA in December of

PCI Bus Power

is wake-up from D3

hot

or D3

cold

The specific issues addressed by the up are as follows:

Preservation of device context: The must be asserted when transitioning from D3 be implemented so that PRST

Power source in D3

The Texas Instruments PCI1450 addresses these D3 wake-up issues in the following manner:

Preservation of device context: When PRST is asserted, bits required to preserve PME context are not cleared. To clear all bits in the PCI1450, another reset pin is defined: G_RST normally only asserted during the initial power-on sequence. After the initial boot, PRST should be asserted so that PME context is retained for D3-to-D0 transitions. Bits cleared by G_RST, but not cleared by PRST (if the PME enable bit is set), are referred to as PME context bits. Please refer to the master list of PME context bits in the next section.

Power source in D3 auxiliary power source must be switched to the PCI1450 VCC pins. This switch should be a

break

type of switch, so that VCC to the PCI1450 is not interrupted.

if wake-up support is required from this state.

cold

if wake-up support is required from this state. Since VCC is removed in D3

cold

PCI Bus Interface Specification for PCI-to-CardBus Bridges

PCI Power Management Specification

to D0. Some method to preserve wake-up context must

does not clear the PME context registers.

cold

version 1.0 states that PRST

(global reset). G_RST is

master list of PME context bits and global reset only bits

PME context bit means that the bit is cleared only by the assertion of G_RST when the PME enable bit is set (PCI offset A4h, bit 8). If PME is not enabled, then these bits are cleared when either PRST or G_RST is asserted.

Global reset only bits, as the name implies, are only cleared by G_RST . These bits are never cleared by PRST regardless of the setting of the PME enable bit. (PCI offset A4h, bit 8). The G_RST signal is gated only by the SUSPEND all register contents.

signal. This means that assertion of SUSPEND blocks the G_RST signal internally, thus preserving

for D3 wake

, an

cold

make before

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Global reset only bits:

Subsystem ID/subsystem vendor ID (PCI offset 40h): bits 31–0

PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1

System control register (PCI offset 80h): bits 31–29, 27–24, 22–14, 6, 5, 4, 3, 1, 0

Multimedia control register (PCI offset 84h): bits 7–0

General status register (PCI offset 85h): bits 2–0

GPIO0 control register (PCI offset 88h): bits 7, 6, 4, 3, 1, 0

GPIO1 control register (PCI offset 89h): bits 7, 6, 3, 1, 0

GPIO2 control register (PCI offset 8Ah): bits 7, 6, 4, 3, 1, 0

GPIO3 control register (PCI offset 8Bh): bits 7, 6, 3, 1, 0

IRQMUX routing register (PCI offset 8Ch): bits 31–0

Retry status register (PCI offset 90h): bits 7–1

Card control register (PCI offset 91h): bits 7, 6, 2, 1, 0

Device control register (PCI offset 92h): bits 7–0

Diagnostic register (PCI offset 93h): bits 7–0

Socket DMA register 0 (PCI offset 94h): bits 1–0

Socket DMA register 1 (PCI offset 98h): bits 15–0

GPE control/status register (PCI offset A8h): bits 10, 9, 8, 2, 1, 0

PME context bits

Bridge control register (PCI offset 3Eh): bit 6

Power management capabilities register (PCI offset A2h): bit 15

Power management control/status register (PCI offset A4h): bits 15, 8

ExCA power control register (ExCA 802h/842h): bits 4, 3, 1, 0

ExCA interrupt and general control (ExCA 803h/843h): bit 6

ExCA card status change register (ExCA 804h/844h): bits 3, 2, 1, 0

ExCA card status change interrupt register (ExCA 805h/845h): bits 3, 2, 1, 0

CardBus socket event register (CardBus offset 00h): bits 3, 2, 1, 0

CardBus socket mask register (CardBus offset 04h): bits 3, 2, 1, 0

CardBus socket control register (CardBus offset 10h): bits 6, 5, 4, 2, 1, 0

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system diagram implementing CardBus device class power management

PCI Bus

G_RST

PRST

South Bridge

GPIO

CLKRUN

PME

Not required if internal oscillator is used

TPS2206

Power

Switch

Real Time

Clock

PCI1450

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

Embedded

Controller

System Vcc

aux

PC Card

Socket A

PC Card

Socket B

NOTE: The system connection to G_RST

PRST

should be applied for subsequent warm resets.

Vcc

is implementation specific. G_RST should be applied whenever Vcc is applied to the PCI1450.

Status

Make before

break switch

suspend mode

The SUSPEND signal, provided for backward compatibility , gates the PRST (PCI reset) signal and the G_RST (global reset) signal from the PCI1450. Besides gating PRST and G_RST, SUSPEND also gates PCLK inside the PCI1450 in order to minimize power consumption.

Gating PCLK does not create any issues with respect to the power switch interface in the PCI1450. This is because the PCI1450 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock the power switch interface in the PCI1450:

Use an external clock to the PCI1450 CLOCK pin

Use the internal oscillator

It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt stream, then the PCI clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine.

PRST

G_RST

SUSPEND

GNT

PCLK

PCI1450

Core

Figure 17. SUSPEND Functional Illustration

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requirements for SUSPEND

A requirement for implementing suspend mode is that the PCI bus must not be parked on the PCI1450 when SUSPEND is asserted. The PCI1450 responds to SUSPEND being asserted by 3-stating the REQ pin. The PCI1450 will also gate the internal clock and reset.

The GPIOs, IRQMUX signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled in the appropriate PCI1450 registers.

ring indicate

The RI_OUT

output is an important feature used in legacy power management. It is used so that a system can go into a suspended mode and wake up on modem rings and other card events. The RI_OUT signal on the PCI1450 may be asserted under any of the following conditions:

A 16-bit PC Card modem in a powered socket asserts RI to indicate an incoming call to the system.

A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up.

A card status change (CSC) event, such as insertion/removal of cards, battery voltage levels, occurs.

A CSTSCHG signal from a powered CardBus card is indicated as a CSC event, not as a CBWAKE event. These two RI_OUT events are enabled separately. The following figure details various enable bits for the PCI1450 RI_OUT function; however, it does not illustrate the masking of CSC events. See

interrupt masks and flags

for

a detailed description of CSC interrupt masks and flags. RI_OUT is multiplexed on the same pin with PME. The default is for RI_OUT to be signaled on this pin. In PCI

power managed systems, the PME signal should be enabled by setting bit 0 (RI_OUT/PME) in the

control register

(80h) and clearing bit 7 (RIENB) in the

RI_OUT Function

PC Card Socket 0

Card

I/F

16–bit Card

card control register

Bus

CBWAKERICSC

RIENB

(91h).

system

RICSC(A)

RI_OUT

RICSC(B)

CBWAKERICSC

PC Card Socket 1

Card

I/F

16–bIt Card

Bus

Figure 18. RI_OUT Functional Illustration

Routing of CSC events to the RI_OUT signal, enabled on a per socket basis, is programmed by the RICSC bit in the

card control register

. This bit is socket dependent (not shared), as illustrated in Figure 18.

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The RI signal from the 16-bit PC Card interface is masked by the ExCA control bit RINGEN in the

and general control register

card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The

mask bit, CSTSMASK, is programmed through the

. This is programmed on a per socket basis, and is only applicable when a 16-bit

socket mask register

in the CardBus socket registers.

ExCA interrupt

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PC CARD CONTROLLER PROGRAMMING MODEL

This section describes the PCI1450 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1450 function. As noted below, some bits are global in nature and should be accessed only through function 0.

Registers containing one or more global bits are denoted by a “§.” Any bit followed by a “†” is not cleared by the assertion of PRST

management

for more details) if PME is enabled (PCI offset A4h, bit 8). In this case, these bits are only cleared

(refer to

CardBus device class power

by G_RST. If PME is not enabled, then these bits are cleared by G_RST or PRST. These bits are sometimes referred to as PME context bits and are implemented to allow PME context to be preserved when transitioning from D3

hot

or D3

to D0. If the PME context PRST functionality is not desired, then the PRST and G_RST

cold

signals should be tied together. If a bit is followed by a “‡”, then this bit is only cleared by G_RST in all cases (not conditional on PME being

enabled). These bits are intended to maintain device context such as interrupt routing and IRQMUX programming during “warm” resets.

PCI configuration registers (functions 0 and 1)

The PCI1450 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. The configuration header, compliant with the PCI Specification as a CardBus bridge header, is PC97/PC98 compliant as well. Table 23 illustrates the PCI configuration header, which includes both the predefined portion of the configuration space and the user definable registers.

Table 23. Functions 0 and 1 PCI Configuration Register Map

Device ID Vendor ID 00h

Status Command 04h

Class code Revision ID 08h

BIST Header type Latency timer Cache line size 0Ch

CardBus socket registers/ExCA base address 10h

Secondary status Reserved Capability pointer 14h

CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h

CardBus memory base register 0 1Ch

CardBus memory limit register 0 20h

CardBus memory base register 1 24h

CardBus memory limit register 1 28h

CardBus I/O base register 0 2Ch

CardBus I/O limit register 0 30h

CardBus I/O base register 1 34h

CardBus I/O limit register 1 38h

Bridge control † Interrupt pin Interrupt line 3Ch

Subsystem ID ‡ Subsystem vendor ID ‡ 40h

PC Card 16-bit I/F legacy mode base address ‡ 44h

Reserved 48h–7Fh

†

One or more bits in the register are PME context bits and can only be cleared by the assertion of G_RST then these bits are cleared by the assertion of PRST

‡

One or more bits in this register are only cleared by the assertion G_RST

or G_RST.

when PME is enabled. If PME is not enabled,

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Table 23. Functions 0 and 1 PCI Configuration Register Map (continued)

System control ‡ 80h

Reserved Reserved General status † Multimedia control ‡ 84h

GPIO3 control ‡ GPIO2 control ‡ GPIO1 control ‡ GPIO0 control ‡ 88h

IRQMUX routing † 8Ch

Diagnostic ‡ Device control ‡ Card control ‡ Retry status ‡ 90h

Socket DMA register 0 ‡ 94h Socket DMA register 1 ‡ 98h

Reserved 9Ch

Power management capabilities † Next pointer item Capability ID A0h

Data (Reserved)

†

One or more bits in the register are PME context bits and can only be cleared by the assertion of G_RST then these bits are cleared by the assertion of PRST

‡

One or more bits in this register are only cleared by the assertion G_RST

vendor ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

PMCSR bridge support

extensions

Reserved GPE control/status ‡ A8h

or G_RST.

Power management control/status † A4h

when PME is enabled. If PME is not enabled,

Register: V endor ID Type: Read-only Offset: 00h (Functions 0, 1) Default: 104Ch Description: This 16-bit register contains a value allocated by the PCI SIG that identifies the manufacturer

of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.

device ID register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 0 1 1

Register: Device ID Type: Read-only Offset: 02h (Functions 0, 1) Default: AC1Bh Description: This 16-bit register contains a value assigned to the PCI1450 by Texas Instruments. The

device identification for the PCI1450 is AC1B.

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command register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R R R R/W R R/W R/W R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

command register

provides control over the PCI1450 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, see Table 24. None of the bit functions in this register are shared between the two PCI1450 PCI functions. Two command registers exist in the PCI1450, one for each function. Software manipulates the two PCI1450 functions as separate entities when enabling functionality through the

. The SERR_EN and PERR_EN enable bits in this register are internally wired OR

command

between the two functions, and these control bits appear separate per function to software.

Table 24. PCI Command Register Description

BIT TYPE FUNCTION

15–10 R

9 R

8 R/W

7 R

6 R/W

5 R/W

4 R

3 R

2 R/W

1 R/W

0 R/W

Reserved. These bits return 0s when read. Writes have no effect. Fast back-to-back enable. The PCI1450 will not generate fast back-to-back transactions; therefore, this bit is read-only. This

bit returns a 0 when read. System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR can be asserted

after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set for the PCI1450 to report address parity errors.

Address/data stepping control. The PCI1450 does not support address/data stepping, and this bit is hardwired to 0. Writes to this bit have no effect.

Parity error response enable. This bit controls the PCI1450’s response to parity errors through the PERR signal. Data parity errors are indicated by asserting PERR

VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI1450does not respond to palette register writes and snoops the data). When the bit is 0, the PCI1450 will treat all palette accesses like all other accesses.

Memory write and invalidate enable. This bit controls whether a PCI initiator device can generate memory write and invalidate commands. The PCI1450 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns 0 when read. Writes to this bit have no effect.

Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI1450 does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns 0 when read. Writes to this bit have no effect.

Bus master control. This bit controls whether or not the PCI1450 can act as a PCI bus initiator (master). The PCI1450 can take control of the PCI bus only when this bit is set.

Memory space enable. This bit controls whether or not the PCI1450 may claim cycles in PCI memory space.

I/O space control. This bit controls whether or not the PCI1450 may claim cycles in PCI I/O space.

0 = Disables the SERR 1 = Enables the SERR

0 = PCI1450 ignores detected parity error (default). 1 = PCI1450 responds to detected parity errors.

0 = Disables the PCI1450’s ability to generate PCI bus accesses (default). 1 = Enables the PCI1450’s ability to generate PCI bus accesses.

0 = Disables the PCI1450’s response to memory space accesses (default). 1 = Enables the PCI1450’s response to memory space accesses.

0 = Disables the PCI1450 from responding to I/O space accesses (default). 1 = Enables the PCI1450 to respond to I/O space accesses.

output driver (default).

output driver.

, while address parity errors are indicated by asserting SERR.

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status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Status Type R/W R/W R/W R/W R/W R R R/W R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

BIT TYPE FUNCTION

15 R/W

14 R/W

13 R/W

12 R/W

11 R/W

10–9 R

8 R/W

7 R 6 R UDF. UDF supported. The PCI1450 does not support the user definable features; therefore, this bit is hardwired to 0.

5 R 66 MHz capable. The PCI1450 operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to 0. 4 R

3–0 R Reserved. These bits return 0s when read.

PAR_ERR. Detected parity error . This bit is set when a parity error is detected, either address or data parity errors. W rite a 1 to clear this bit.

SYS_ERR. Signaled system error. This bit is set when SERR is enabled and the PCI1450 signaled a system error to the host. Write a 1 to clear this bit.

MABORT . Received master abort. This bit is set when a cycle initiated by the PCI1450 on the PCI bus has been terminated by a master abort. Write a 1 to clear this bit.

TABT_REC. Received target abort. This bit is set when a cycle initiated by the PCI1450 on the PCI bus was terminated by a target abort. Write a 1 to clear this bit.

TABT_SIG. Signaled target abort. This bit is set by the PCI1450 when it terminates a transaction on the PCI bus with a target abort. Write a 1 to clear this bit.

PCI_SPEED. DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b indicating that the PCI1450 asserts this signal at a medium speed on nonconfiguration cycle accesses.

DATAPAR. Data parity error detected. Write a 1 to clear this bit.

FBB_CAP. Fast back-to-back capable. The PCI1450 cannot accept fast back-to-back transactions; thus, this bit is hardwired to 0.

Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power management capabilities is implemented in this function.

status register

read normally. A bit in the

provides device information to the host system. Bits in this register may be

status register

is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown through each function.

Table 25. Status Register Description

0 = The conditions for setting this bit have not been met. 1 = A data parity error occurred and the following conditions were met:

a. PERR b. The PCI1450 was the bus master during the data parity error. c. The parity error response bit is set in the

was asserted by any PCI device including the PCI1450.

command register

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revision ID register

Bit 7 6 5 4 3 2 1 0 Name Revision ID Type R R R R R R R R Default 0 0 0 0 0 0 1 0

Register: Revision ID Type: Read-only Offset: 08h (Functions 0, 1) Default: 02h Description: This register indicates the silicon revision of the PCI1450. This data sheet reflects the

PCI1450 revision 02h silicon.

PCI class code register

Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Base Class Sub Class Programming Interface Name PCI class code Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

Register: PCI class code Type: Read-only Offset: 09h (Functions 0, 1) Default: 060700h Description: This register recognizes the PCI1450 functions 0 and 1 as a bridge device (06h), and CardBus

bridge device (07h), with a 00h programming interface.

cache line size register

Bit 7 6 5 4 3 2 1 0 Name Cache line size Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Cache line size Type: Read/Write Offset: 0Ch (Functions 0, 1) Default: 00h Description: This register is programmed by host software to indicate the system cache line size.

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latency timer register

Bit 7 6 5 4 3 2 1 0 Name Latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Latency timer Type: Read/Write Offset: 0Dh Default: 00h Description: This register specifies the latency timer for the PCI1450, in units of PCI clock cycles. When

the PCI1450 is a PCI bus initiator and asserts FRAME zero. If the latency timer expires before the PCI1450 transaction has terminated, then the PCI1450 terminates the transaction when its GNT

header type register

Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 1 0 0 0 0 0 1 0

, the latency timer begins counting from

is deasserted.

Register: Header type Type: Read-only Offset: 0Eh (Functions 0, 1) Default: 82h Description: This register returns 82h when read, indicating that the PCI1450 functions 0 and 1

configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h–FFh is user definable extension registers.

BIST register

Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: BIST Type: Read-only Offset: 0Fh (Functions 0, 1) Default: 00h Description: Since the PCI1450 does not support a built-in self-test (BIST), this register returns the value of

00h when read. This register returns 0s for the two PCI1450 functions.

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CardBus socket registers / ExCA registers base address register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket registers/ExCA base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket registers/ExCA base address Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: CardBus socket registers/ExCA base address Type: Read-only, Read/Write Offset: 10h Default: 0000 0000h Description: This register is programmed with a base address referencing the

and the memory mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4K-byte boundary . Bits 1 1–0 are read-only, returning 0s when read. When software writes all ones to this register, the value read back will be FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory mapped ExCA registers begin at offset 800h. This register is not shared by functions 0 and 1, mapping each

socket control register

separately.

CardBus socket registers

capability pointer

Bit 7 6 5 4 3 2 1 0 Name Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0

Register: Capability pointer Type: Read-only Offset: 14h Default: A0h Description: This register provides a pointer into the PCI configuration header where the PCI power

management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own

capability pointer register

. This

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secondary status register

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Secondary status Type R/WC R/WC R/WC R/WC R/WC R R R/WC R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Register: Secondary status Type: Read-only, Read/Write to Clear Offset: 16h Default: 0200h Description: This register is compatible with the PCI-PCI bridge secondary status register. It indicates

CardBus related device information to the host system. This register is very similar to the PCI

status register

shared by the two socket functions, but is accessed on a per socket basis.

BIT TYPE FUNCTION

15 R/WC

14 R/WC

13 R/WC

12 R/WC

11 R/WC

10–9 R

8 R/WC

7 R

6 R

5 R

4–0 R Reserved. These bits return 0s when read.

CBPARITY . Detected parity error . This bit is set when a CardBus parity error is detected; either address or data parity errors. Write a 1 to clear this bit.

CBSERR. Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI1450 does not assert the CSERR

CBMABORT. Received master abort. This bit is set when a cycle initiated by the PCI1450 on the CardBus bus has been terminated by a master abort. Write a 1 to clear this bit.

REC_CBTA. Received target abort. This bit is set when a cycle initiated by the PCI1450 on the CardBus bus was terminated by a target abort. Write a 1 to clear this bit.

SIG_CBTA. Signaled target abort. This bit is set by the PCI1450 when it terminates a transaction on the CardBus bus with a target abort. Write a 1 to clear this bit.

CB_SPEED. CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b indicating that the PCI1450 asserts this signal at a medium speed.

CB_DPAR. CardBus data parity error detected. Write a 1 to clear this bit.

CBFBB_CAP. Fast back-to-back capable. The PCI1450 cannot accept fast back-to-back transactions; therefore, this bit is hardwired to 0.

CB_UDF . User definable feature support. The PCI1450 does not support the user definable features; therefore, this bit is hardwired to 0.

CB66MHZ. 66 MHz capable. The PCI1450 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, this bit is hardwired to 0.

signal. Write a 1 to clear this bit.

0 = The conditions for setting this bit have not been met. 1 = A data parity error occurred and the following conditions were met:

(offset 06h), and status bits are cleared by a writing a 1. This register is not

Table 26. Secondary Status Register Description

a. CPERR b. The PCI1450 was the bus master during the data parity error. c. The parity error response bit is set in the

was asserted on the CardBus interface.

bridge control register

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PCI bus number register

Bit 7 6 5 4 3 2 1 0 Name PCI bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: PCI bus number Type: Read/Write Offset: 18h (Functions 0, 1) Default: 00h Description: This register is programmed by the host system to indicate the bus number of the PCI bus to

which the PCI1450 is connected. The PCI1450 uses this register, in conjunction with the

CardBus bus number

PCI configuration cycles to its secondary buses.

CardBus bus number register

Bit 7 6 5 4 3 2 1 0 Name CardBus bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

and

subordinate bus number registers

, to determine when to forward

Register: CardBus bus number Type: Read/Write Offset: 19h Default: 00h Description: This register is programmed by the host system to indicate the bus number of the CardBus

bus to which the PCI1450 is connected. The PCI1450 uses this register, in conjunction with the

PCI bus number

and

subordinate bus number registers

, to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI1450 controller function.

subordinate bus number register

Bit 7 6 5 4 3 2 1 0 Name Subordinate bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Subordinate bus number Type: Read/Write Offset: 1Ah Default: 00h Description: This register is programmed by the host system to indicate the highest numbered bus below

the CardBus bus. The PCI1450 uses this register, in conjunction with the

CardBus bus number registers

, to determine when to forward PCI configuration cycles to its

PCI bus number

secondary buses. This register is separate for each CardBus controller function.

and

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CardBus latency timer register

Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: CardBus latency timer Type: Read/Write Offset: 1Bh (Functions 0, 1) Default: 00h Description: This register is programmed by the host system to specify the latency timer for the PCI1450

CardBus interface, in units of CCLK cycles. When the PCI1450 is a CardBus initiator and asserts CFRAME before the PCI1450 transaction has terminated, then the PCI1450 terminates the transaction at the end of the next data phase. A recommended minimum value for this register of 20h allows most transactions to be completed.

memory base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

, the CardBus latency timer begins counting. If the latency timer expires

Register: Memory base registers 0, 1 Type: Read-only, Read/Write Offset: 1Ch, 24h Default: 0000 0000h Description: These registers indicate the lower address of a PCI memory address range. They are used by

bridge control register

memory base register

specify whether memory windows 0 and 1

or the

memory limit register

must be nonzero in order for the PCI1450 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of memory to CardBus).

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memory limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Memory limit registers 0, 1 Type: Read-only, Read/Write Offset: 20h, 28h Default: 0000 0000h Description: These registers indicate the upper address of a PCI memory address range. They are used by

the PCI1450 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 1 1–0 are read-only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the are prefetchable or nonprefetchable. The must be nonzero in order for the PCI1450 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K bytes of memory to CardBus).

bridge control register

memory base register

specify whether memory windows 0 and 1

or the

memory limit register

I/O base registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O base registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O base registers 0, 1 Type: Read-only, Read/Write Offset: 2Ch, 34h Default: 0000 0000h Description: These registers indicate the lower address of a PCI I/O address range. They are used by the

PCI1450 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K-byte page, and the upper 16 bits (31–16) are all 0s which locate this 64K-byte page in the first page of the 32-bit PCI I/O address space. Bits 31–16 and bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary in the first 64K-byte page of PCI I/O address space. These I/O windows are enabled when either the

I/O base register

or the

I/O limit register

are nonzero.

The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus.

Either the

I/O base

or the

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I/O limit register

must be nonzero to enable any I/O transactions.

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PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

I/O limit registers 0, 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: I/O limit registers 0, 1 Type: Read-only, Read/Write Offset: 30h, 38h Default: 0000 0000h Description: These registers indicate the upper address of a PCI I/O address range. They are used by the

PCI1450 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64K-byte page, and the upper 16 bits are a page register which locates this 64K-byte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64K-byte page (indicated by bits 31–16 of the appropriate

I/O base register

) on doubleword boundaries.

Bits 31–16 are read-only and always return 0s when read. The page is set in the

. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a

I/O base

natural doubleword boundary . Writes to read-only bits have no effect. The PCI1450 assumes that the lower two bits of the limit address are ones.

These I/O windows are enabled when either the

I/O base register

or the

I/O limit register

nonzero. The I/O windows are not enabled by default to pass the first doubleword of I/O to CardBus.

Either the

I/O base

or the

I/O limit register

must be nonzero to enable any I/O transactions.

interrupt line register

Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1

Register: Interrupt line Type: Read/Write Offset: 3Ch Default: FFh Description: This register communicates interrupt line routing information to the host system. This register

is not used by the PCI1450, since there are many programmable interrupt signaling options. This register is considered reserved; however, host software may read and write to this register. Each PCI1450 function has an

interrupt line register

are

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interrupt pin register

PCI function 0

Bit 7 6 5 4 3 2 1 0 Name Interrupt pin – PCI function 0 Type R R R R R R R R Default 0 0 0 0 0 0 0 1

PCI function 1

Bit 7 6 5 4 3 2 1 0 Name Interrupt pin – PCI function 1 Type R R R R R R R R Default 0 0 0 0 0 0 1 0

Register: Interrupt pin Type: Read-only Offset: 3Dh Default: The default depends on the interrupt signaling mode. Description: The value read from this register is function dependent. The value depends on the interrupt

INTRTIE bit in the

device control register

functions. The PCI1450 defaults to signaling PCI & IRQ interrupts through the IRQSER serial interrupt terminal. Refer to Table 27 for a complete description of the register contents.

system control register

and the signaling mode, selected through the

. When the INTRTIE bit is set, this register will read 0x01 (INT A) for both

Table 27. Interrupt Pin Register Cross Reference

Interrupt Signaling Mode

Parallel PCI interrupts only 0 0x01 (INTA) 0x02 (INTB) Parallel IRQ & parallel PCI interrupts 0 0x01 (INTA) 0x02 (INTB) IRQ serialized (IRQSER) & parallel PCI Interrupts 0 0x01 (INTA) 0x02 (INTB) IRQ & PCI serialized (IRQSER) interrupts (default) 0 0x01 (INTA) 0x02 (INTB) Parallel PCI interrupts only 1 0x01 (INTA) 0x01 (INTA) Parallel IRQ & parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ serialized (IRQSER) & parallel PCI interrupts 1 0x01 (INTA) 0x01 (INTA) IRQ & PCI serialized (IRQSER) interrupts (default) 1 0x01 (INTA) 0x01 (INTA)

INTRTIE Bit INTPIN

Function 0

INTPIN

Function 1

bridge control register

Bit 15 14 13 12 11 10 9 8 7 6† 5 4 3 2 1 0 Name Bridge control Type R R R R R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W Default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0

Register: Bridge control Type: Read-only, Read/Write Offset: 3Eh (Function 0, 1) Default: 0340h Description: This register provides control over various PCI1450 bridging functions. Some bits in this

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Table 28. Bridge Control Register Description

BIT TYPE FUNCTION

15–1 1 R Reserved. These bits return 0s when read.

POSTEN. Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables posting of

10 R/W

9 R/W

8 R/W

7 R/W

6† R/W

5§ R/W

4 R Reserved. This bit returns 0 when read. 3 R/W

2 R/W

1 R/W

0 R/W

†

This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST.

These bits are global in nature and should be accessed only through function 0.

write data on burst cycles. Operating with write posting disabled will inhibit performance on burst cycles. Note that bursted write data can be posted, but various write transactions may not. This bit is socket dependent and is not shared between functions 0 and 1.

PREFETCH1. Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. This bit is encoded as:

PREFETCH0. Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is encoded as:

PCI Interrupt – IREQ routing enable. This bit is used to select whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers.

CRST . CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST signal may also be asserted by passing a PRST

This bit will not be cleared by the assertion of PRST MABTMODE. Master abort mode. This bit controls how the PCI1450 responds to a master abort when the PCI1450 is an

initiator on the CardBus interface. This bit is common between each socket.

VGAEN. VGA enable. This bit affects how the PCI1450 responds to VGA addresses. When this bit is set, accesses to VGA addresses will be forwarded.

ISAEN. ISA mode enable. This bit affects how the PCI1450 passes I/O cycles within the 64K-byte ISA range. This bit is not common between sockets. When this bit is set, the PCI1450 will not forward the last 768 bytes of each 1K I/O range to CardBus.

CSERREN. CSERR enable. This bit controls the response of the PCI1450 to CSERR signals on the CardBus bus. This bit is separate for each socket.

CPERREN. CardBus parity error response enable. This bit controls the response of the PCI1450 to CardBus parity errors. This bit is separate for each socket.

0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default).

0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default).

0 = Functional interrupts are routed to PCI interrupts (default). 1 = Functional interrupts are routed by ExCA registers.

0 = CRST 1 = CRST

0 = Master aborts not reported (default). 1 = Signal target abort on PCI and signal SERR

0 = CSERR 1 = CSERR

0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR

is deasserted. is asserted (default).

is not forwarded to PCI SERR. is forwarded to PCI SERR.

assertion to CardBus.

. It will only be cleared by the assertion of G_RST.

, if enabled.

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subsystem vendor ID register

Bit 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ 8‡ 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Name Subsystem vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

‡

This bit is cleared only by the assertion of G_RST

Register: Subsystem vendor ID Type: Read-only, Read/Write (when bit 5 in the Offset: 40h (Functions 0, 1) Default: 0000h Description: This register, used for system and option card identification purposes, may be required for

certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the when bit 5 is 1, this register is read-only. The default mode is read-only.

subsystem ID register

Bit 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ 8‡ 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Name Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

‡

This bit is cleared only by the assertion of G_RST.

system control register

. When bit 5 is 0, this register is read/write;

is 0.)

system control register

is 0.) Offset: 42h (Functions 0, 1) Default: 0000h Description: This register, used for system and option card identification purposes, may be required for

certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the

system control register

. When bit 5 is 0, this register is read/write;

when bit 5 is 1, this register is read-only. The default mode is read-only. If an EEPROM is present, then the subsystem ID and subsystem vendor ID will be loaded

from EEPROM after an reset.

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PC Card 16-bit I/F legacy mode base address register

Bit 31‡ 30‡ 29‡ 28‡ 27‡ 26‡ 25‡ 24‡ 23‡ 22‡ 21‡ 20‡ 19‡ 18‡ 17‡ 16‡ Name PC Card 16-bit I/F legacy mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ 8‡ 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0 Name PC Card 16-bit I/F legacy mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

‡

This bit is cleared only by the assertion of G_RST.

Register: PC Card 16-bit I/F legacy mode base address Type: Read-only, Read/Write Offset: 44h (Functions 0, 1) Default: 0000 0001h Description: The PCI1450 supports the index/data scheme of accessing the ExCA registers, which is

mapped by this register. An address written to this register is the address for the index register and the address+1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only returning 1 when read. As specified in the Yenta specification, this register is shared by functions 0 and 1. Refer to the

ExCA register set

description for register offsets.

system control register

Bit 31‡ 30‡ 29‡ 28 27‡ 26‡ 25‡ 24‡ 23 22‡ 21‡ 20‡ 19‡ 18‡ 17‡ 16‡ Name System control Type R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15‡ 14‡ 13 12 11 10 9 8 7 6‡ 5‡ 4‡ 3‡ 2 1‡ 0‡ Name System control Type R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0

‡

This bit is cleared only by the assertion of G_RST

Register: System control Type: Read-only, Read/Write Offset: 80h (Functions 0, 1) Default: 0044 9060h Description: System level initializations are performed through programming this doubleword register.

Some of the bits are global in nature and should be accessed only through function 0.

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Table 29. System Control Register Description

BIT TYPE FUNCTION

SER_STEP. Serialized PCI interrupt routing step. These bits are used to configure the serialized PCI interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. These bits are global to both PCI1450 functions.

31–30‡§ R/W

INTRTIE. Tie internal PCI interrupts. When this bit is set, the INT A and INTB signals are tied together internally and are

29‡§ R/W

28 R Reserved. This bit returns 0 when read.

27‡§ R/W

26‡§ R/W

25‡ R/W

24‡§ R/W

23 R Reserved

22‡ R/W

21‡ R/W

20‡ R/W

19‡ R/W

18–16‡ R/W

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

signaled as INT A

P2CCLK. P2C power switch CLOCK. This bit determines whether the CLOCK terminal (terminal U12) is an input that requires an external clock source or if this terminal is an output that uses the internal oscillator.

A 43

SMIROUTE. SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket.

SMISTA TUS. SMI interrupt status. This socket dependent bit is set when a write occurs to set the socket power , and the SMIENB bit is set. Writing a 1 to this bit clears the status.

SMIENB. SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).

CBRSVD. CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals will be driven low when a CardBus card is inserted. When this bit is low, as default, these signals are 3-stated.

VCCPROT. VCC protection enable. This bit is socket dependent.

Reduced zoom video enable. When this bit is enabled, A25–22 of the card interface for PC Card 16 cards is placed in the high impedance state. This bit is encoded as:

CDREQEN. PC/PCI DMA card enable. When this bit is set, the PCI1450 allows 16-bit PC Cards to request PC/PCI DMA using the DREQ

CDMACHAN. PC/PCI DMA channel assignment. These bits are encoded as:

00 = INTA 01 = INTA 10 = INTA 11 = INTA

0 = INTA 1 = INTA

0 = CLOCK terminal (terminal U12) is an input (default) (disabled). 1 = CLOCK terminal is an output, the internal oscillator is enabled.

pulldown resistor should be tied to this terminal.

0 = PC Card power change interrupts routed to IRQ2 (default). 1 = A CSC interrupt is generated on PC Card power changes.

0 = SMI interrupt is signaled. 1 = SMI interrupt is not signaled.

0 = SMI interrupt mode is disabled (default). 1 = SMI interrupt mode is enabled.

0 = 3-state the CardBus RSVD terminals 1 = Drive the Cardbus RSVD terminals low (default).

0 = VCC protection is enabled for 16-bit cards (default). 1 = VCC protection is disabled for 16-bit cards.

0 = Reduced zoom video is disabled (default). 1 = Reduced zoom video is enabled.

0 = Ignore DREQ 1 = Signal DMA request on DREQ

0–3 = 8-bit DMA channels 4 = PCI master; not used (default) 5–7 = 16-bit DMA channels

/INTB signal in INTA/INTB IRQSER slots (default) /INTB signal in INTB/INTC IRQSER slots /INTB signal in INTC/INTD IRQSER slots

/INTB signal in INTD/INTA IRQSER slots

. INTA may then be shifted by using the SER_STEP bits. This bit is global to both PCI1450 functions.

and INTB are not tied together internally (default). and INTB are tied together internally.

signaling. DREQ is selected through the

signaling from PC Cards (default).

socket DMA register 0

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Table 29. System Control Register Description (continued)

BIT TYPE FUNCTION

MRBURSTDN. Memory read burst enable downstream. When this bit is set, memory read transactions are allowed to

15‡§ R/W

14‡§ R/W

13 R

12 R Reserved. This bit returns 1 when read. This is the power rail bit in functions 0 and 1.

11 R

10 R

9 R

8 R

7 R Reserved. This bit returns 0 when read.

6‡§ R/W

5‡§ R/W

4‡§ R/W

3‡§ R/W

2 R Reserved. This bit returns 0 when read.

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

burst downstream.

MRBURSTUP . Memory read burst enable upstream. When this bit is set, the PCI1450 allows memory read transactions to burst upstream.

SOCACTIVE. Socket activity status. When set, this bit indicates access has been performed to or from a PC Card, and is cleared upon read of this status bit. This bit is socket dependent.

PWRSTREAM. Power stream in progress status bit. When set, this bit indicates that a power stream to the power switch is in progress and a powering change has been requested. When this bit is clear, it indicates that the power stream is complete.

DELAYUP. Power-up delay in progress status bit. When set, this bit indicates that a power-up stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up delay has expired.

DELAYDOWN. Power-down delay in progress status bit. When set, this bit indicates that a power-down stream has been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-down delay has expired.

INTERROGATE. Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when the interrogation completes. This bit is socket dependent.

PWRSAVINGS. Power savings mode enable. When this bit is set, the PCI1450 will consume less power with no performance loss. This bit is shared between the two PCI1450 functions.

SUBSYSRW. read/write enable. This bit is shared by functions 0 and 1.

CB_DPAR. CardBus data parity SERR signaling enable.

CDMA_EN. PC/PCI DMA enable. Enables PC/PCI DMA when set, and disables the IRQMUX7 and IRQMUX6 signaling.

0 = MRBURSTDN downstream is disabled. 1 = MRBURSTDN downstream is enabled (default).

0 = MRBURSTUP upstream is disabled (default). 1 = MRBURSTUP upstream is enabled.

0 = No socket activity (default) 1 = Socket activity

0 = Power stream is complete, delay has expired. 1 = Power stream is in progress.

0 = Power-up delay has expired. 1 = Power-up stream sent to switch. Power might not be stable.

0 = Power-down delay has expired. 1 = Power-down stream sent to switch. Power might not be stable.

0 = Interrogation not in progress (default) 1 = Interrogation in progress

0 = Power savings mode disabled 1 = Power savings mode enabled (default)

Subsystem ID

0 =

Subsystem ID, subsystem vendor ID

1 =

Subsystem ID, subsystem vendor ID

(default).

0 = CardBus data parity not signaled on PCI SERR 1 = CardBus data parity signaled on PCI SERR

0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled

(SS ID),

subsystem vendor ID

, and the

(SS VID), and the

ExCA identification and revision registers

signal (default)

signal

PCI1450 GFN/GJG

PC CARD CONTROLLER

SCPS044 – SEPTEMBER 1998

ExCA identification and revision registers

are read/write.

are read-only

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Table 29. System Control Register Description (continued)

BIT TYPE FUNCTION

KEEPCLK. Keep clock. When this bit is set, the PCI1450 will always follow CLKRUN protocol to maintain the system PCLK and the CCLK (CardBus clock). This bit is global to the PCI1450 functions.

1‡§ R/W

0‡§ R/W

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

Note that the functionality of this bit has changed versus the PCI12XX series of TI CardBus controllers. In these CardBus controllers, setting this bit would only maintain the PCI clock, not the CCLK. In the PCI1450, setting this bit will maintain both the PCI clock and the CCLK.

PME/RI_OUT select bit. When this bit is 1, the PME signal is routed on to pin Y13 (PME/RI_OUT pin). When this bit is 0 and bit 7 (RIENB) of the of the

NOTE: If this bit (bit 0) is 0 and bit 7 of the

0 = Allow system PCLK and CCLK to stop (default) 1 = Never allow system PCLK or CCLK clock to stop

card control register

0 = RI_OUT 1 = PME

card control register

signal is routed on pin Y13 of the PCI1450 controller.

is 0, then the output (Y13) will be 3-stated. This pin is encoded as:

signal is routed to pin Y13 if bit 7 of the

is 1, the RI_OUT signal is routed on to pin Y13. If this bit is 0 and bit 7 (RIENB)

card control register is 0

card control register

, then the output on pin Y13 is 3-stated.

is 1*. (default)

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multimedia control register

Bit 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Name Multimedia control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Multimedia control Type: Read/Write Offset: 84h (Functions 0, 1) Default: 00h Description: This register provides port mapping for the PCI1450 zoom video/data ports. See

video support

for details on the PCI1450 zoom video support. Access this register only

through function 0.

Table 30. Multimedia Control Register Description

BIT TYPE FUNCTION

ZVOUTEN. ZV output enable. This bit enables the output for the PCI1450 outsourcing ZV terminals. When this bit is reset,

7‡ R/W

6‡ R/W

5‡ R/W

4–2‡ R/W

1‡ R/W

0‡ R/W

‡

This bit is cleared only by the assertion of G_RST

‘0’, these terminals are in a high impedance state.

0 = PCI1450 ZV output terminals disabled (default) 1 = PCI1450 ZV output terminals enabled

PORTSEL. ZV port select. This bit controls the multiplexing control over which PC Card ZV port data will be driven to the outsourcing PCI1450 ZV port.

0 = Output card 0 ZV if enabled (default) 1 = Output card 1 ZV if enabled

Zoomed video auto-detect. This bit enables the zoomed video auto-detect feature. This bit is encoded as:

0 = Zoomed video auto detect disabled (default) 1 = Zoomed video auto detect enabled

Auto-detect priority encoding. These bits have meaning only if zoomed video auto-detect is enabled in bit 5 of this register. If auto-detect is enabled, then bits 4–2 are encoded as follows:

ZVEN1. PC Card 1 ZV mode enable. Enables the zoom video mode for socket 1. When set, the PCI1450 inputs ZV data from the PC Card interface, and disables output drivers on ZV terminals.

0 = PC Card 1 ZV disabled (default) 1 = PC Card 1 ZV enabled

ZVEN0. PC Card 0 ZV mode enable. Enables the zoom video mode for socket 0. When set, the PCI1450 inputs ZV data from the PC Card interface, and disables output drivers on ZV terminals.

0 = PC Card 0 ZV disabled (default) 1 = PC Card 0 ZV enabled

zoomed

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general status register

Bit 7 6 5 4 3 2‡ 1‡ 0‡ Name General status Type R R R R R R R R Default 0 0 0 0 0 X 0 0

Register: General status Type: Read-only Offset: 85h (Functions 0) Default: 00h Description: This register provides the general device status information. The status of the serial

EEPROM interface is provided through this register.

Table 31. General Status Register Description

BIT TYPE FUNCTION

7–3 R Reserved. These bits return 0s when read.

EEDETECT . Serial EEPROM detect. When this bit is cleared, it indicates that the PCI1450 serial EEPROM circuitry has detected an EEPROM. A pull-up resistor must be implemented on the LA TCH terminal for this bit to be set. This status bit

2‡§ R

1‡§ R

0‡§ R

This bit is global in nature and should only be accessed through function 0.

‡

This bit is cleared only by the assertion of G_RST

is encoded as:

0 = EEPROM not detected (default) 1 = EEPROM detected

DAT AERR. Serial EEPROM data error status. This bit indicates when a data error occurs on the serial EEPROM interface. This bit may be set due to a missing acknowledge. This bit is cleared by a writing a 1.

0 = No error detected. (default) 1 = Data error detected.

EEBUSY . Serial EEPROM busy status. This bit indicates the status of the PCI1450 serial EEPROM circuitry . This bit is set during the loading of the subsystem ID value.

0 = Serial EEPROM circuitry is not busy (default). 1 = Serial EEPROM circuitry is busy.

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GPIO0 control register

Bit 7‡ 6‡ 5 4‡ 3‡ 2 1‡ 0‡ Name GPIO0 control Type R/W R/W R R/W R/WC R R/W R/W Default 1 0 0 0 0 0 0 0

Register: GPIO0 control Type: Read-only, Read/Write, Read/Write to Clear Offset: 88h (Functions 0, 1) Default: 80h Description: This register is used for control of the general-purpose I/O, GPIO0. This terminal defaults to a

general-purpose input, but can be reconfigured as the socket 0 activity LED output, a zoom video enabled status output, or general-purpose output. Access this register only through function 0.

Table 32. GPIO0 Control Register Description

BIT TYPE FUNCTION

GP0. General-purpose 0 mode. These bits select the functionality of the LEDA1/GPIO0 signal. These bits are encoded as:

7–6‡ R/W

5 R Reserved. This bit returns 0 when read. A write has no effect.

4‡ R/W

3‡ R/WC

2 R Reserved. This bit returns 0 when read. A write has no effect.

1‡ R/W

0‡ R/W

‡

This bit is cleared only by the assertion of G_RST

GPINTEN0. GP interrupt enable. When this bit is set, a socket A card status change (CSC) interrupt is generated when the DELTA0 bit is set.

DELT A0. DA T AIN0 change status. This bit is set when the DA T AIN0 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without this bit. This bit is cleared by a write back of 1.

DATAOUT0. General-purpose data output. When in general-purpose output mode, this bit represents the data. Data written to this bit in GPO mode is signaled to the output.

DATAIN0. General-purpose data input. When in either general-purpose input or output mode, this bit represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

00 = Signal LEDA1 to indicate PC Card socket 0 activity 01 = Signal ZVSTAT to indicate zoom video output enabled 10 = General-purpose input (GPI) 11 = General-purpose output (GPO)

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GPIO1 control register

Bit 7‡ 6‡ 5 4 3‡ 2 1‡ 0‡ Name GPIO1 control Type R/W R/W R R R/WC R R/W R/W Default 1 0 0 0 0 0 0 0

Register: GPIO1 control Type: Read-only, Read/Write, Read/Write to Clear Offset: 89h (Functions 0, 1) Default: 80h Description: This register is used for control of the general-purpose I/O, GPIO1. This terminal defaults to a

general-purpose input, but can be reconfigured as the socket 1 activity LED output, or general-purpose output. Access this register only through function 0.

Table 33. GPIO1 Control Register Description

BIT TYPE FUNCTION

GP1. General-purpose 1 mode. These bits select the functionality of the LEDA2/GPIO1 signal. These bits are encoded as:

7–6‡ R/W

5 R Reserved. This bit returns 0 when read. A write has no effect. 4 R Reserved. This bit returns 0 when read. A write has no effect.

3‡ R/WC

2 R Reserved. This bit returns 0 when read. A write has no effect.

1‡ R/W

0‡ R/W

‡

This bit is cleared only by the assertion of G_RST.

DELT A1. DA T AIN1 change status. This bit is set when the DA T AIN1 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without this bit. This bit is cleared by a write back of 1.

DATAOUT1. General-purpose data output. When in general-purpose output mode, this bit represents the data. Data written to this bit in GPO mode is signaled to the output.

DATAIN1. General-purpose data input. When in either general-purpose input or output mode, this bit represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

00 = Signal LEDA2 to indicate PC Card socket 1 activity 01 = D3_STAT

function 1 are placed in the D3 state and PME 10 = General-purpose input (GPI) 11 = General-purpose output (GPO)

. This programs GPIO1 as a D3 status pin. D3 status will be asserted if both function 0 and

is enabled via bit 8 of PCI offset A4h.

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GPIO2 control register

Bit 7‡ 6‡ 5 4‡ 3‡ 2 1‡ 0‡ Name GPIO2 control Type R/W R/W R R/W R/WC R R/W R/W Default 1 0 0 0 0 0 0 0

Register: GPIO2 control Type: Read-only, Read/Write, Read/Write to Clear Offset: 8Ah (Functions 0, 1) Default: 80h Description: This register is used for control of the general-purpose I/O, GPIO2. This terminal defaults to a

general-purpose input, but can be reconfigured as the PCI LOCK enabled status output, or general-purpose output. Access this register only through function

Table 34. GPIO2 Control Register Description

BIT TYPE FUNCTION

GP2. General-purpose 2 mode. These bits select the functionality of the LOCK/GPIO2 signal. These bits are encoded as:

7–6‡ R/W

5 R Reserved. This bit returns 0 when read. A write has no effect.

4‡ R/W GPINTEN2. GP interrupt enable. When this bit and the DELTA2 bit are set, a socket B CSC is generated. 3‡ R/WC

2 R Reserved. This bit returns 0 when read. A write has no effect.

1‡ R/W

0‡ R/W

‡

This bit is cleared only by the assertion of G_RST

DELT A2. DA T AIN2 change status. This bit is set when the DA T AIN2 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without this bit. This bit is cleared by a write back of 1.

DATAOUT2. General-purpose data output. When in general-purpose output mode, this bit represents the data. Data written to this bit in GPO mode is signaled to the output.

DATAIN2. General-purpose data input. When in either general-purpose input or output mode, this bit represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

00 = Terminal is configured as the PCI LOCK 01 = Signal ZVSTAT to indicate zoom video output is enabled. 10 = General-purpose input (GPI) 11 = General-purpose output (GPO)

signal.

signal, a zoom video

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GPIO3 control register

Bit 7‡ 6‡ 5 4 3‡ 2 1‡ 0‡ Name GPIO3 control Type R/W R/W R R R/WC R R/W R/W Default 1 0 0 0 0 0 0 0

Register: GPIO3 control Type: Read-only, Read/Write, Read/Write to Clear Offset: 8Bh (Functions 0, 1) Default: 80h Description: This register is used for control of the general-purpose I/O, GPIO3. This terminal defaults to a

general-purpose input, but can be reconfigured as the PCI INT A output. Access this register only through function 0.

Table 35. GPIO3 Control Register Description

BIT TYPE FUNCTION

GP3. General-purpose 3 mode. These bits select the functionality of the INTA/GPIO3 signal. These bits are encoded as:

7–6‡ R/W

5 R Reserved. This bit returns 0 when read. A write has no effect. 4 R Reserved. This bit returns 0 when read. A write has no effect.

3‡ R/WC

2 R Reserved. This bit returns 0 when read. A write has no effect.

1‡ R/W

0‡ R/W

‡

This bit is cleared only by the assertion of G_RST

DELT A3. DA T AIN3 change status. This bit is set when the DA T AIN3 bit changes state when in GPI mode. Glitches on the GPI terminal may not be detected by software without this bit. This bit is cleared by a write back of 1.

DATAOUT3. General-purpose data output. When in general-purpose output mode, this bit represents the data. Data written to this bit in GPO mode is signaled to the output.

DATAIN3. General-purpose data input. When in either general-purpose input or output mode, this bit represents the data on the GPIO terminal. Data signaled on the GPI terminal is identified through this bit.

00 = Terminal is configured as the PCI INTA 01 = Reserved. 10 = General-purpose input (GPI) 11 = General-purpose output (GPO)

signal.

signal, or general-purpose

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IRQMUX routing register

Bit 31‡ 30‡ 29‡ 28‡ 27‡ 26‡ 25‡ 24‡ 23‡ 22‡ 21‡ 20‡ 19‡ 18‡ 17‡ 16‡ Name IRQMUX routing Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ 8‡ 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Name IRQMUX routing Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: IRQMUX routing Type: Read/Write Offset: 8Ch (Functions 0, 1) Default: 0000 0000h Description: This register is used for the legacy interrupt mux routing feature of the PCI1450, which is

described in the is selected, then all PCI1450 interrupts sent to ISA IRQs will be signaled on the corresponding IRQMUX7–IRQMUX0 signals. These signals are routed directly to various IRQ inputs on the system PIC. The routing information is programmed through this register. Each terminal has at least one secondary function that can be selected by programming the bits appropriately . Access this register only through function 0.

programmable interrupt support

section. If the parallel IRQ interrupt scheme

Table 36. IRQMUX Routing Register Description

BIT TYPE FUNCTION

IRQMUX7 routing. These bits select 1 of 15 interrupts that can be routed on the IRQMUX7 pin. When these bits are 0000 and bit 3 in the

NOTE: These bits should not be configured for IRQ signaling if IRQMUX7 is being used for PCREQ signaling.

31–28‡ R/W

IRQMUX6 routing. These bits select 1 of 15 interrupts that can be routed on the IRQMUX6 pin. When these bits are 0000 and bit 3 is the

NOTE: These bits should not be configured for IRQ signaling if IRQMUX6 is being used for PCGNT signaling. An EEPROM cannot be used if IRQMUX7 and IRQMUX 6 are being used for DMA PCREQ

27–24‡ R/W

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

system control register

0000 = EEPROM SCL routed on IRQMUX7 pin (default) 0000 = PCREQ 0001 = PC/PCI DMA request (PCREQ 0010 = IRQ2 routed on IRQMUX7 pin 0011 = IRQ3 routed on IRQMUX7 pin : 1111 = IRQ15 routed on IRQMUX7 pin

system control register

0000 = EEPROM SDA routed on IRQMUX6 pin (default) 0000 = PCGNT 0001 = IRQ1 routed on IRQMUX6 pin 0010 = IRQ2 routed on IRQMUX6 pin : 1111 = IRQ15 routed on IRQMUX6 pin

routed on IRQMUX 7 pin when bit 3 of the

routed on IRQMUX6 pin when bit 3 of the

is set, this pin is used for PCREQ DMA signaling.

) routed on IRQMUX7 pin

is set, this pin is used for PCGNT DMA signaling.

system control register

and PCGNT.

system control register

is 1

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Table 36. IRQMUX Routing Register Description (continued)

BIT TYPE FUNCTION

IRQMUX5 routing. These bits select 1 of 15 interrupts that the IRQMUX5 signal may be routed. When these bits are in the default state of all 0s, then no routing is selected.

23–20‡ R/W

IRQMUX4 routing. These bits select 1 of 15 interrupts that the IRQMUX4 signal may be routed. When these bits are in the default state of all 0s, then no routing is selected.

19–16‡ R/W

IRQMUX3 routing. These bits select 1 of 15 interrupts that the IRQMUX3 signal may be routed. When these bits are in the default state of all 0s, then no routing is selected.

15–12‡ R/W

IRQMUX2 routing. These bits select 1 of 15 interrupts that the IRQMUX2 signal may be routed. When these bits are in the default state of all 0s, then no routing is selected.

11–8 ‡ R/W

IRQMUX1 routing. These bits select 1 of 15 interrupts that the IRQMUX1 signal may be routed. When these bits are in the default state of all 0s, then no routing is selected.

7–4‡ R/W

IRQMUX0 routing. These bits select 1 of 15 interrupts that the IRQMUX0 signal may be routed. When these bits are in the default state of all 0s, then no routing is selected.

3–0‡ R/W

‡

This bit is cleared only by the assertion of G_RST

0000 = No IRQ routing selected (default) 0001 = CardBus audio (CBAUDIO) routed on IRQMUX5 pin 0010 =GPE 0011 = IRQ3 routed on IRQMUX5 pin : 1111 = IRQ15 routed on IRQMUX5 pin

0000 = No IRQ routing selected (default) 0001 = ZVSTAT is routed on IRQMUX4 pin 0010 = RI_OUT 0011 = IRQ3 routed on IRQMUX4 pin 0100 = IRQ4 routed on IRQMUX4 pin : 1111 = IRQ15 routed on IRQMUX4 pin

0000 = No IRQ routing selected (default) 0001 = LEDA or LEDB routed on IRQMUX3 pin 0010 = RI_OUT 0011 = IRQ3 routed on IRQMUX3 pin 0100 = IRQ4 routed on IRQMUX3 pin : 1111 = IRQ15 routed on IRQMUX3

0000 = No IRQ routing selected (default) 0001 = LEDB routed on IRQMUX2 pin 0010 = Zoomed Video Pixel Clock (PCLK) Input 0011 = IRQ3 routed on IRQMUX2 pin : 1111 = IRQ15 routed on IRQMUX2 pin

0000 = No IRQ routing selected (default) 0001 = LEDA routed on IRQMUX1 pin 0010 = IRQ2 routed on IRQMUX1 pin 0011 = IRQ3 routed on IRQMUX1 pin : 1111 = IRQ15 routed on IRQMUX1 pin

0000 = No IRQ routing selected (default) 0001 = INTB 0010 = IRQ2 routed on IRQMUX0 pin 0011 = IRQ3 routed on IRQMUX0 pin : 1111 = IRQ15 routed on IRQMUX0 pin

on IRQMUX5 pin

is routed on IRQMUX4 pin

routed on IRQMUX3 pin

routed on IRQMUX0 pin

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retry status register

Bit 7‡ 6‡ 5‡ 4 3‡ 2 1‡ 0 Name Retry status Type R/W R/W R/WC R R/WC R R/WC R Default 1 1 0 0 0 0 0 0

Register: Retry status Type: Read-only, Read/Write Offset: 90h (Functions 0, 1) Default: C0h Description: The contents of this register enable the retry time-out counters and display the retry expiration

status. The flags are set when the PCI1450 retries a PCI or CardBus master request, and the master does not return within 2 bit. These bits are expected to be incorporated into the PCI

, and

bridge control register

Table 37. Retry Status Register Description

PCI clock cycles. The flags are cleared by writing a 1 to the

command register

, PCI

by the PCI SIG. Access this register only through function

status

BIT TYPE FUNCTION

PCIRETRY. PCI retry time-out counter enable. This bit is encoded as:

7‡ R/W

CBRETRY. CardBus retry time-out counter enable. This bit is encoded as:

6‡§ R/W

TEXP_CBB. CardBus target B retry expired. Write a 1 to clear this bit.

5‡ R/WC

4 R Reserved. This bit returns 0 when read.

TEXP_CBA. CardBus target A retry expired. Write a 1 to clear this bit.

3‡§ R/WC

2 R Reserved. This bit returns 0 when read.

TEXP_PCI. PCI target retry expired. Write a 1 to clear this bit.

1‡ R/WC

0 R Reserved. This bit returns 0 when read.

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

0 = PCI retry counter disabled 1 = PCI retry counter enabled (default)

0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default)

0 = Inactive (default) 1 = Retry has expired.

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card control register

Bit 7‡ 6‡ 5 4 3 2‡ 1‡ 0‡ Name Card control Type R/W R/W R/W R R R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: Card control Type: Read-only, Read/Write Offset: 91h Default: 00h Description: This register is provided for PCI1 130 compatibility . The contents provide the PC Card function

interrupt flag (IFG) and an alias for the ZVEN0 and ZVEN1 bits found in the PCI1450

multimedia control register

alias with ZVENABLE. When this register is accessed by function 1, the ZVEN1 bit will alias with ZVENABLE. Setting ZVENABLE only places the PC Card socket interface ZV terminals in a high impedance state, but does not enable the PCI1450 to drive ZV data onto the ZV terminals.

. When this register is accessed by function 0, the ZVEN0 bit will

The RI_OUT

signal is enabled through this register, and the enable bit is shared between

functions 0 and 1.

Table 38. Card Control Register Description

BIT TYPE FUNCTION

7‡§ R/W

6‡ R/W

5 R/W Reserved.

4–3 R Reserved. These bits default to 0.

2‡ R/W

1‡ R/W

0‡ R/W

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

RIENB. Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit is global in nature and should be accessed only through function 0. This bit defaults to 0.

ZVENABLE. Compatibility ZV mode enable. When this bit is 1, the corresponding PC Card socket interface ZV terminals will enter a high impedance state. This bit defaults to 0.

AUD2MUX. CardBus Audio-to-IRQMUX. When this bit is set, the CAUDIO CardBus signal is routed to the corresponding IRQMUX terminal. Function 0, A_CAUDIO, is routed to IRQMUX0 and function 1, B_CAUDIO, is routed to IRQMUX1. If this bit is set for both functions, then function 0 gets routed.

SPKROUTEN. Speaker output enable. When this bit is 1, it enables SPKR on the PC Card and routes it to SPKROUT on the PCI bus. The SPKR SPKROUT terminal only drives data then either functions SPKROUTEN bit is set. This bit is encoded as:

IFG. Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when a functional interrupt is signaled from a PC Card interface, and is socket dependent (i.e., not global). Write back a ‘1’ to clear this bit.

0 = CAUDIO set to CAUDPWM on IRQMUX pin (default) 1 = CAUDIO is not routed.

signal from socket 0 is XOR’ed with the SPKR signal from socket 1 and sent to SPKROUT . The

0 = SPKR 1 = SPKR

0 = No PC Card functional interrupt detected (default) 1 = PC Card functional interrupt detected

to SPKROUT not enabled (default) to SPKROUT enabled

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device control register

Bit 7‡ 6‡ 5‡ 4 3‡ 2‡ 1‡ 0‡ Name Device control Type R/W R/W R/W R R/W R/W R/W R/W Default 0 1 1 0 0 1 1 0

Register: Device control Type: Read-only, Read/Write Offset: 92h (Functions 0, 1) Default: 66h Description: This register is provided for PCI1 130 compatibility . It contains bits which are shared between

functions 0 and 1. The interrupt mode select is programmed through this register. The socket capable force bits are also programmed through this register.

Table 39. Device Control Register Description

BIT TYPE FUNCTION

Socket power lock bit. When this bit is set to 1, software will not be able to power down the PC Card socket while in D3.

7‡ R/W

6‡§ R/W

5‡ R/W IO16R2. Diagnostic bit. This bit defaults to 1.

4 R Reserved. This bit returns 0 when read. A write has no effect.

3‡§ R/W TEST. TI test bit. Write only 0 to this bit. This bit can be set to shorten the interrogation counter.

2–1‡§ R/W

0‡§ R/W

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

This may be necessary to support Wake on LAN or RING if the operating system is programmed to power down a socket when the CardBus controller is placed in the D3 state.

3VCAPABLE. 3-V socket capable force bit.

INTMODE. Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:

Reserved. NAND tree enable bit. There is a NAND tree diagnostic structure in the PCI1450, and it tests only the pins that are inputs or I/Os. Any output only terminal on the PCI1450 is excluded from the NAND tree test.

0 = Not 3-V capable 1 = 3-V capable (default)

00 = Parallel PCI interrupts only 01 = Parallel IRQ & parallel PCI interrupts 10 = IRQ serialized interrupts & parallel PCI interrupts INTA 11 = IRQ & PCI serialized interrupts (default)

and INTB

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diagnostic register

Bit 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Name Diagnostic Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 0 0 0 0 1

Register: Diagnostic Type: Read/Write Offset: 93h (Functions 0, 1) Default: 61h Description: This register is provided for internal Texas Instruments test purposes.

Table 40. Diagnostic Register Description

BIT TYPE FUNCTION

This bit defaults to 0. This bit is encoded as:

7‡§ R/W

6‡ R/W Reserved.

CSC interrupt routing control

5‡ R/W

4‡§ R/W DIAG. Diagnostic RETRY_DIS. Delayed transaction disable. 3‡§ R/W DIAG. Diagnostic RETRY_EXT. Extends the latency from 16 to 64. 2‡§ R/W DIAG. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, Reset = 2 1‡§ R/W DIAG. Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, Reset = 2

ASYNC_CSC. Asynchronous interrupt generation.

0‡§ R/W

These bits are global in nature and should be accessed only through function 0.

‡

This bit is cleared only by the assertion of G_RST

0 = Reads true values in PCI 1 = Reads all ones in reads to the PCI

0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1. 1 = CSC Interrupts routed to PCI if ExCA 805 bits 7–4 = 0000b. (Default) In this case, the setting of ExCA 803 bit 4 is a “don’t care.”

0 = CSC interrupt not generated asynchronously 1 = CSC interrupt is generated asynchronously (default)

vendor ID

and PCI

vendor ID

device ID registers

and PCI

device ID registers

(default).

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socket DMA register 0

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name socket DMA register 0 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1‡ 0‡ Name socket DMA register 0 Type R R R R R R R R R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: DMA socket register 0 Type: Read-only, Read/Write Offset: 94h (Functions 0, 1) Default: 0000 0000h Description: This register provides control over the PC Card DREQ (DMA request) signaling.

Table 41. Socket DMA Register 0 Description

BIT TYPE FUNCTION

31–2 R Reserved. These bits return 0s when read.

DREQPIN. DMA request (DREQ) pin. These bits indicate which pin on the 16-bit PC Card interface will as the DREQ signal during DMA transfers. This field is encoded as:

1–0‡ R/W

‡

This bit is cleared only by the assertion of G_RST.

00 = Socket not configured for DMA (default) 01 = DREQ 10 = DREQ uses IOIS16 11 = DREQ uses INPACK

uses SPKR

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socket DMA register 1

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name socket DMA register 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15‡ 14‡ 13‡ 12‡ 11‡ 10‡ 9‡ 8‡ 7‡ 6‡ 5‡ 4‡ 3‡ 2‡ 1‡ 0‡ Name socket DMA register 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: DMA socket register 1 Type: Read-only, Read/Write Offset: 98h (Functions 0, 1) Default: 0000 0000h Description: The contents of this register provide control over the

the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI I/O address space. Note that 32-bit transfers to the 16-bit PC Card interface are not supported; the maximum transfer possible to the PC Card interface is 16-bits. However, 32 bits of data are prefetched from the PCI bus, thus allowing back-to-back 16-bit transfers to the PC Card interface.

distributed DMA (DDMA) registers

and

Table 42. Socket DMA Register 1 Description

BIT TYPE FUNCTION

31–16 R Reserved. These bits return 0s when read.

DMABASE. DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI

15–4‡ R/W

3‡ R EXTMODE. Extended addressing. This feature is not supported by the PCI1450, and always returns a 0.

2–1‡ R/W

0‡ R/W

‡

This bit is cleared only by the assertion of G_RST.

I/O address. The upper 16 bits of the address are hard-wired to 0, forcing this window to within the lower 64K bytes of I/O address space. The lower four bits are hard-wired to 0, and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary

XFERSIZE. Transfer size. These bits specify the width of the DMA transfer on the PC Card interface, and are encoded as:

DDMAEN. DDMA registers decode enable. Enables the decoding of the of DMABASE.

00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved

distributed DMA registers

0 = Disabled (default) 1 = Enabled

based upon the value

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capability ID register

Bit 7 6 5 4 3 2 1 0 Name Capability ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1

Register: Capability ID Type: Read-only Offset: A0h Default: 01h Description: This register identifies the linked list item as the register for PCI power management. The

register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value.

next item pointer register

Bit 7 6 5 4 3 2 1 0 Name Next item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Register: Next item pointer Type: Read-only Offset: A1h Default: 00h Description: The contents of this register indicate the next item in the linked list of the PCI power

management capabilities. Since the PCI1450 functions only include one capabilities item, this register returns 0s when read.

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power management capabilities register

Bit 15† 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Power management capabilities Type R/W R R R R R R R R R R R R R R R Default 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1

Register: Power management capabilities Type: Read-only, Read/Write Offset: A2h (Functions 0, 1) Default: FE11h Description: This register contains information on the capabilities of the PC Card function related to power

management. Both PCI1450 CardBus bridge functions support D0, D2, and D3 power states.

Table 43. Power Management Capabilities Register Description

BIT TYPE FUNCTION

PME support. This 5-bit field indicates the power states from which the PCI1450 device functions may assert PME. A 0b (zero) for any bit indicates that the function cannot assert the PME 0Fh when read. Each of these bits is described below:

15†

14–1 1

10 R D2_Support. This bit returns a 1 when read, indicating that the function supports the D2 device power state.

9 R D1_Support. This bit returns a 1 when read, indicating that the function supports the D1 device power state.

8–6 R Reserved. These bits return 000b when read.

5 R DSI. Device specific initialization. This bit returns 0 when read.

4 R

3 R

2–0 R

†

This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST.

R/W

Bit 15 – defaults to the value 1 indicating the PME wake-up support from D3 system designer chooses not to provide an auxiliary power source to the VCC terminals for D3 BIOS should write a 0 to this bit. Bit 14 – contains the value 1 indicating that the PME

Bit 13 – contains the value 1 to indicate that the PME Bit 12 – contains the value 1 to indicate that the PME Bit 11 – contains the value 1 indicating that the PME

AUX_PWR. Auxiliary power source. This bit is meaningful only if bit 15 (D3 it indicates that support for PME vehicle. A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source. If the function does not support PME while in the D3

PMECLK. When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PME operation. When this bit is 0, it indicates that no PCI clock is required for the function to generate PME

Functions that do not support PME generation in any state must return 0 for this field. Version. These 3 bits return 001b when read, indicating that there are 4 bytes of general-purpose power management (PM)

registers as described in the draft revision 1.0 PCI Bus Power Management Interface Specification.

is contingent on the system providing an auxiliary power source to the VCC terminals. If the

cold

in D3

cold

signal can be asserted from the D3

signal can be asserted from the D2 state. signal can be asserted from the D1 state.

signal can be asserted from the D0 state.

requires auxiliary power supplied by the system by way of a proprietary delivery

state (bit 15=0), then this field must always return 0.

cold

signal while in that power state. These five bits return

state. This bit is R/W because

cold

wake-up support, then

cold state.

hot

supporting PME) is set. When this bit is set,

cold

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power management control/status register

Bit 15† 14 13 12 11 10 9 8† 7 6 5 4 3 2 1 0 Name Power management control/status Type R/WC R R R R R R R/W R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Power management control/status Type: Read-only, Read/Write, Read/Write to Clear Offset: A4h (Functions 0, 1) Default: 000000h Description: This register determines and changes the current power state of the PCI1450 CardBus

function. The contents of this register are not affected by the internally generated reset caused by the transition from the D3

All PCI registers, ExCA registers, and CardBus registers are reset as a result of a D3 state transition, with the exception of the PME context bits (if PME is enabled) and the G_RST only bits.

Table 44. Power Management Control/Status Register Description

to D0 state.

hot

-to-D0

BIT TYPE FUNCTION

PMESTAT. PME status. This bit is set when the CardBus function would normally assert the PME signal, independent of

15† R/WC

14–13 R

12–9 R

8† R/W

7–2 R Reserved. These bits return 0s when read.

1–0 R/W

†

This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST.

the state of the PME_EN bit. This bit is cleared by a write back of 1, and this also clears the PME by this function. Writing a 0 to this bit has no effect.

DAT ASCALE. This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data, as indicated by the DYN_DATA bit.

DAT ASEL. Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data, as indicated by the DYN_DATA bit.

PME enable. This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. This bit will not be cleared by the assertion of PRST

PWRSTATE. Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. This field is encoded as:

00 = D0 01 = D1 10 = D2 11 = D3

hot

. It will only be cleared by the assertion of G_RST.

signal if PME was asserted

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power management control/status register bridge support extensions

Bit 7 6 5 4 3 2 1 0 Name Power management control/status register bridge support extensions Type R R R R R R R R Default 1 1 0 0 0 0 0 0

Register: Power management control/status register bridge support extensions Type: Read-only Offset: A6h (Functions 0, 1) Default: C0h Description: This register supports PCI bridge specific functionality. It is required for all PCI-to-PCI

bridges.

T able 45. PMCSR_BSE Bridge Support Extensions

BIT TYPE FUNCTION

BPCC_Enable. Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as:

7 R

6 R

5–0 R Reserved. These bits return 0s when read.

A 0 indicates that the bus power/clock control policies defined in the PCI Power Management specification are disabled. When the bus power/clock control enable mechanism is disabled, the bridge’s PMCSR powerstate field cannot be used by the system software to control the power or the clock of the bridge’s secondary bus. A 1 indicates that the bus power/clock control mechanism is enabled. When bus power/clock control is disabled, the bridge’s PMCSR power state field cannot be used by the system software to control power or the clock of the bridge’s secondary bus.

B2_B3. B2/B3 support for D3 the function to D3

0 = Bus power/clock control is disabled. 1 = Bus power/clock control is enabled (default).

. The state of this bit determines the action that is to occur as a direct result of programming

hot

. This bit is only meaningful if bit 7 (BPCC_Enable) is a 1. This bit is encoded as:

hot

0 = when the bridge is programmed to D3 1 = when the bridge function is programmed to D3

(Default)

, its secondary bus will have its power removed (B3).

hot

, its secondary bus’s PCI clock will be stopped (B2).

hot

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GPE control/status register

Bit 15 14 13 12 11 10‡ 9‡ 8‡ 7 6 5 4 3 2‡ 1‡ 0‡ Name GPE control/status Type R R R R R R/WC R/WC R/WC R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: GPE control/status Type: Read-only, Read/Write, Read/Write to Clear Offset: A8h Default: 0001h Description: If the GPE

0010b to bits 23–20 of the multifunction routing register (PCI offset 8Ch), then this register may be used to program which events will cause GPE to be asserted and report the status.

BIT TYPE FUNCTION

15–1 1 R Reserved. These bits return 0s when read.

10‡ R/WC ZV1_STS. PC Card socket 1 status. This bit is set on a change in status of the ZVENABLE bit in function 1.

9‡ R/WC ZV0_STS. PC Card socket 0 status. This bit is set on a change in status of the ZVENABLE bit in function 0. 8‡ R/WC

7–3 R Reserved. These bits return 0s when read.

2‡ R/W

1‡ R/W

0‡ R/W

‡

This bit is cleared only by the assertion of G_RST.

VPP12_STS. 12 volt VPP request status. This bit is set when software has changed the requested VPP level to or from 12 volts from either socket.

ZV1_EN. PC Card socket 1 zoomed video event enable. When this bit is set, GPE is signaled on a change in status of the ZVENABLE bit in function 1 of the PC Card controller.

ZV0_EN. PC Card socket 0 zoomed video event enable. When this bit is set, GPE is signaled on a change in status of the ZVENABLE bit in function 0 of the PC Card controller.

VPP12_EN. 12 Volt VPP request event enable. When this bit is set, a GPE is signaled when software has changed the requested VPP level to or from 12 Volts for either socket.

(general-purpose event) function is programmed onto the IRQMUX5 pin by writing

Table 46. GPE Control/Status Register Description

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ExCA compatibility registers (functions 0 and 1)

The ExCA (exchangeable card architecture) registers implemented in the PCI1450 are register-compatible with the popular Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value, which is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base), and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the The offsets from this base address run contiguous from 00h to 3Fh for socket A, and from 40h to 7Fh for socket B. Refer to Figure 19 for an ExCA I/O mapping illustration. Table 47 identifies each ExCA register and its respective ExCA offset.

The TI PCI1450 also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the (PCI register 10h) at memory offset 800h. Each socket has a separate base address programmable by function. Refer to Figure 20 for an ExCA memory mapping illustration. Note that memory offsets are 800h–844h for both functions 0 and 1. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K window at memory offset 0h.

The interrupt registers, as defined by the 82365SL Specification, in the ExCA register set control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1450 to ensure that all possible PCI1450 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h.

PC Card 16-bit I/F legacy mode base address register

CardBus socket registers/ExCA registers base address register

, which is shared by both card sockets.

Access to I/O mapped 16-bit PC Cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity .

Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. Memory windows have 4K byte granularity.

A bit location followed by a cleared by the assertion of G_RST. This is necessary to retain device context when transitioning from D3 to D0.

‡ means that this bit is not cleared by the assertion of PRST. This bit will only be

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PCI1450 Configuration Registers

10hCard Bus Socket / ExCA Base Address

16–bit Legacy Mode Base Address

Note: The 16–bit legacy mode base address register is shared by function 0 and 1 as indicated by the shading.

44h

Figure 19. ExCA Register Access Through I/O

PCI1450 Configuration Registers

CardBus Socket/ExCA Base Address

16-bit Legacy-Mode Base Address

Note: The CardBus Socket/ExCA Base Address Mode Register is separate for functions 0 and 1.

Offset

10h

44h

Host I/O Space

PC Card A

ExCA

Index

Data

Offset of desired register is placed in the Index register and the data from that location is returned in the data register.

Host

Memory Space

Offset

CardBus Socket A Registers

ExCA Registers Card A

00h

20h

800h

844h

Registers

PC Card B

ExCA

Registers

Host

Memory Space

CardBus Socket B Registers

ExCA Registers Card B

Offset

00h

3Fh

40h

7Fh

Offset

00h

20h

800h

844h

Offsets are from the CardBus socket/ExCA base

Address register’s base address

Figure 20. ExCA Register Access Through Memory

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Table 47. ExCA Registers and Offsets

PCI

Identification and revision 800 00 40 Interface status 801 01 41 Power control † 802† 02 42 Interrupt and general control † 803† 03 43 Card status change † 804† 04 44 Card status change interrupt configuration † 805† 05 45 Address window enable 806 06 46 I / O window control 807 07 47 I / O window 0 start-address low-byte 808 08 48 I / O window 0 start-address high-byte 809 09 49 I / O window 0 end-address low-byte 80A 0A 4A I / O window 0 end-address high-byte 80B 0B 4B I / O window 1 start-address low-byte 80C 0C 4C I / O window 1 start-address high-byte 80D 0D 4D I / O window 1 end-address low-byte 80E 0E 4E I / O window 1 end-address high-byte 80F 0F 4F Memory window 0 start-address low-byte 810 10 50 Memory window 0 start-address high-byte 811 11 51 Memory window 0 end-address low-byte 812 12 52 Memory window 0 end-address high-byte 813 13 53 Memory window 0 offset-address low-byte 814 14 54 Memory window 0 offset-address high-byte 815 15 55 Card detect and general control 816 16 56 Reserved 817 17 57 Memory window 1 start-address low-byte 818 18 58 Memory window 1 start-address high-byte 819 19 59 Memory window 1 end-address low-byte 81A 1A 5A Memory window 1 end-address high-byte 81B 1B 5B Memory window 1 offset-address low-byte 81C 1C 5C Memory window 1 offset-address high-byte 81D 1D 5D Global control 81E 1E 5E Reserved 81F 1F 5F Memory window 2 start-address low-byte 820 20 60 Memory window 2 start-address high-byte 821 21 61 Memory window 2 end-address low-byte 822 22 62 Memory window 2 end-address high-byte 823 23 63 Memory window 2 offset-address low-byte 824 24 64 Memory window 2 offset-address high-byte 825 25 65 Reserved 826 26 66 Reserved 827 27 67

†

One or more bits in this register are cleared only by the assertion of G_RST when PME is enabled. If PME is NOT enabled, then this bit is cleared by the assertion of PRST

or G_RST.

MEMORY

ADDRESS

OFFSET

ExCA

OFFSET

(CARD A)

ExCA

OFFSET

(CARD B)

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Table 47. ExCA Registers and Offsets (continued)

PCI

Memory window 3 start-address low-byte 828 28 68 Memory window 3 start-address high-byte 829 29 69 Memory window 3 end-address low-byte 82A 2A 6A Memory window 3 end-address high-byte 82B 2B 6B Memory window 3 offset-address low-byte 82C 2C 6C Memory window 3 offset-address high-byte 82D 2D 6D Reserved 82E 2E 6E Reserved 82F 2F 6F Memory window 4 start-address low-byte 830 30 70 Memory window 4 start-address high-byte 831 31 71 Memory window 4 end-address low-byte 832 32 72 Memory window 4 end-address high-byte 833 33 73 Memory window 4 offset-address low-byte 834 34 74 Memory window 4 offset-address high-byte 835 35 75 I/O window 0 offset-address low-byte 836 36 76 I/O window 0 offset-address high-byte 837 37 77 I/O window 1 offset-address low-byte 838 38 78 I/O window 1 offset-address high-byte 839 39 79 Reserved 83A 3A 7A Reserved 83B 3B 7B Reserved 83C 3C 7C Reserved 83D 3D 7D Reserved 83E 3E 7E Reserved 83F 3F 7F Memory window page register 0 840 - Memory window page register 1 841 - Memory window page register 2 842 - Memory window page register 3 843 - Memory window page register 4 844 - -

MEMORY

ADDRESS

OFFSET

ExCA

OFFSET

(CARD A)

ExCA

OFFSET

(CARD B)

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ExCA identification and revision register (Index 00h)

Bit 7 6 5 4 3 2 1 0 Name ExCA identification and revision Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 0 1 0 0

Register: ExCA identification and revision Type: Read/Write Offset: CardBus Socket Address + 800h: Card A ExCA Offset 00h

Card B ExCA Offset 40h Default: 84h Description: This register provides host software with information on 16-bit PC Card support and

82365SL-DF compatibility.

NOTE: If bit 5 (SUBSYRW) in the

system control register

Table 48. ExCA Identification and Revision Register Description

BIT TYPE FUNCTION

7–6 R/W 5–4 R/W Reserved. These bits can be used for 82365SL emulation. 3–0 R/W

IFTYPE. Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI1450. The PCI1450 supports both I/O and memory 16-bit PC Cards.

365REV . 82365SL revision. This field stores the 82365SL revision supported by the PCI1450. Host software may read this field to determine compatibility to the 82365SL register set. This field defaults to 0100b upon reset.

is 1, then this register is read-only.

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ExCA interface status register (Index 01h)

Bit 7 6 5 4 3 2 1 0 Name ExCA interface status Type R R R R R R R R Default 0 0 x x x x x x

Card B ExCA Offset 41h Default: 00XX XXXXb Description: This register provides information on current status of the PC Card interface. An x in the

default bit values indicates that the value of the bit after reset depends on the state of the PC Card interface.

Table 49. ExCA Interface Status Register Description

BIT TYPE FUNCTION

7 R Reserved. This bit returns 0 when read. A write has no effect.

6 R

5 R

4 R

3 R

2 R

1–0 R

CARDPWR. Card power. This bit indicates the current power status of the PC Card socket. This bit reflects how the

power control register

READY. This bit indicates the current status of the READY signal at the PC Card interface.

CARDWP. Card write protect. This bit indicates the current status of the WP signal at the PC Card interface. This signal reports to the PCI1450 whether or not the memory card is write protected. Further, write protection for an entire PCI1450 16-bit memory window is available by setting the appropriate bit in the

CDETECT2. Card detect 2. This bit indicates the status of the CD2 signal at the PC Card interface. Software may use this and CDETECT1 to determine if a PC Card is fully seated in the socket.

CDETECT1. Card detect 1. This bit indicates the status of the CD1 signal at the PC Card interface. Software may use this and CDETECT2 to determine if a PC Card is fully seated in the socket.

BVDSTA T . Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 0 reflects the BVD1 status, and bit 1 reflects BVD2.

When a 16-bit I/O card is inserted, this field indicates the status of the SPKR PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.

has been programmed. The bit is encoded as: 0 = VCC and VPP to the socket is turned off (default). 1 = VCC and VPP to the socket is turned on.

0 = PC Card is not ready for a data transfer. 1 = PC Card is ready for a data transfer.

ExCA memory window offset-address high byte

0 = WP signal is 0. PC Card is R/W. 1 = WP signal is 1. PC Card is read-only.

0 = CD2 signal is 1. No PC Card inserted. 1 = CD2 signal is 0. PC Card at least partially inserted.

0 = CD1 signal is 1. No PC Card inserted. 1 = CD1 signal is 0. PC Card at least partially inserted.

00 = Battery is dead. 01 = Battery is dead. 10 = Battery is low; warning. 11 = Battery is good.

(bit 1) signal and the STSCHG (bit 0) at the

ExCA

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ExCA power control register (Index 02h)

Bit 7 6 5 4† 3† 2 1† 0† Name ExCA power control Type R/W R R R/W R/W R R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 42h Default: 00h Description: This register provides PC Card power control. Bit 7 of this register controls the 16-bit output

enables on the socket interface, and can be used for power management in 16-bit PC Card applications.

Table 50. ExCA Power Control Register Description

BIT TYPE FUNCTION

COE. Card output enable. This bit controls the state of all of the 16-bit outputs on the PCI1450. This bit is encoded as:

7 R/W

6–5 R Reserved. These bits return 0s when read. Writes have no effect.

EXCAVCC. VCC. These bits are used to request changes to card VCC. This field is encoded as:

4–3† R/W

2 R Reserved. This bit returns 0 when read. A write has no effect.

EXCAVPP . VPP. These bits are used to request changes to card VPP. The PCI1450 ignores this field unless VCC to the socket is enabled (i.e., 5 Vdc or 3.3 Vdc). This field is encoded as:

1–0† R/W

†

This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST.

0 = 16-bit PC Card outputs are disabled (default). 1 = 16-bit PC Card outputs are enabled.

00 = 0 V (default) 01 = 0 V Reserved 10 = 5 V 11 = 3 V

00 = 0 V (default) 01 = V

10 = 12 V 11 = 0 V Reserved

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ExCA interrupt and general control register (Index 03h)

Bit 7 6† 5 4 3 2 1 0 Name ExCA interrupt and general control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA interrupt and general control Type: Read/Write Offset: CardBus Socket Address + 803h: Card A ExCA Offset 03h

Card B ExCA Offset 43h Default: 00h Description: This register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card

functions.

Table 51. ExCA Interrupt and General Control Register Description

BIT TYPE FUNCTION

RINGEN. Card ring indicate enable. Enables the ring indicate function of the BVD1/RI pins. This bit is encoded as:

7 R/W

Card reset. This bit controls the 16-bit PC Card RESET signal, and allows host software to force a card reset. This bit affects

6† R/W

5 R/W

4 R/W

3–0 R/W

†

This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST.

16-bit cards only . This bit is encoded as:

CARDTYPE. Card type. This bit indicates the PC Card type. This bit is encoded as:

CSCROUTE. PCI interrupt – CSC routing enable bit. This bit has meaning only if the CSC interrupt routing control bit (PCI offset 93h, bit 5) is 0b. In this case, when this bit is set (high), the card status change interrupts are routed to PCI interrupts. When low the card status change interrupts are routed, using bits 7–4 in the

If the CSC interrupt routing control bit (PCI offset 93h, bit 5) is set to 1b, this bit has no meaning which is the default case. INTSELECT . Card interrupt select for I/O PC Card functional interrupts. These bits select the interrupt routing for I/O PC

Card functional interrupts. This field is encoded as:

0 = Ring indicate disabled (default) 1 = Ring indicate enabled

0 = RESET signal asserted (default) 1 = RESET signal deasserted.

0 = Memory PC Card is installed (default) 1 = I/O PC Card is installed

ExCA card status change interrupt configuration

. This bit is encoded as:

0 = CSC interrupts routed by ExCA registers (default) 1 = CSC interrupts routed to PCI interrupts

0000 = No ISA interrupt routing (default). CSC interrupts routed to PCI Interrupts. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

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ExCA card status-change register (Index 04h)

Bit 7 6 5 4 3† 2† 1† 0† Name ExCA card status-change Type R R R R R R R R Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 44h Default: 00h Description: This register reflects the status of PC Card CSC interrupt sources. The

change interrupt configuration register

enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads as 0. When an interrupt source is enabled and that particular event occurs, the corresponding bit in this register is set to indicate the interrupt source. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register, as well. Resetting a bit is accomplished by one of two methods: a read of this register, or an explicit write back of 1 to the status bit. The choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the

ExCA global control register

ExCA card status

Table 52. ExCA Card Status-Change Register Description

BIT TYPE FUNCTION

7–4 R Reserved. These bits return 0s when read. Writes have no effect.

CDCHANGE. Card detect change. This bit indicates whether a change on the CD1 or CD2 signals occurred at the PC Card

3† R

2† R

1† R

0† R

†

This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST.

interface. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

0 = No change detected on either CD1 or CD2 1 = A change was detected on either CD1 or CD2

READYCHANGE. Ready change. When a 16-bit memory is installed in the socket, this bit includes whether the source of a PCI1450 interrupt was due to a change on the READY signal at the PC Card interface indicating that PC Card is now able ready to accept new data. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

0 = No low-to-high transition detected on READY (default) 1 = Detected a low-to-high transition on READY

When a 16-bit I/O card is installed, this bit is always 0. BATW ARN. Battery warning change. When a 16-bit memory card is installed in the socket, this bit indicates whether the

source of a PCI1450 interrupt was due to a battery low warning condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

0 = No battery warning condition (default) 1 = Detected a battery warning condition

When a 16-bit I/O card is installed, this bit is always 0. BATDEAD. Battery dead or status change. When a 16-bit memory card is installed in the socket, this bit indicates whether

the source of a PCI1450 interrupt was due to a battery dead condition. A read of this bit or writing a 1 to this bit clears it. This bit is encoded as:

0 = STSCHG deasserted (default) 1 = STSCHG asserted

Ring indicate. When the PCI1450 is configured for ring indicate operation this bit indicates the status of the RI pin.

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ExCA card status-change interrupt configuration register (Index 05h)

Bit 7 6 5 4 3† 2† 1† 0† Name ExCA card status-change interrupt configuration Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA card status-change interrupt configuration Type: Read/Write Offset: CardBus Socket Address + 805h: Card A ExCA Offset 05h

Card B ExCA Offset 45h Default: 00h Description: This register controls interrupt routing for CSC interrupts, as well as masks/unmasks CSC

interrupt sources.

Table 53. ExCA Card Status-Change Interrupt Register Description

BIT TYPE FUNCTION

CSCSELECT. Interrupt select for card status change. These bits select the interrupt routing for card status change interrupts. This field is encoded as:

7–4 R/W

CDEN. Card detect enable. Enables interrupts on CD1 or CD2 changes. This bit is encoded as:

3† R/W

READYEN. Ready enable. This bit enables/disables a low-to-high transition on the PC Card READY signal to generate a

2† R/W

1† R/W

0† R/W

†

This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST or G_RST.

host interrupt. This interrupt source is considered a card status change. This bit is encoded as:

BATW ARNEN. Battery warning enable. This bit enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as:

BATDEADEN. Battery dead enable. This bit enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt.

0000 = CSC interrupts routed to PCI interrupts if bit 5 of the

In this case bit 4 of ExCA 803 is a “don’t care.” This is the default setting.

0000 = No ISA interrupt routing if bit 5 of the

CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled

0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enable interrupts on CD1 or CD2 line changes

0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation

diagnostic register

(PCI offset 93h) is set to 0b. In this case,

(PCI offset 93h) is set to 1b.

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ExCA address window enable register (Index 06h)

Bit 7 6 5 4 3 2 1 0 Name ExCA address window enable Type R/W R/W R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Register: ExCA address window enable Type: Read-only, Read/Write Offset: CardBus Socket Address + 806h: Card A ExCA Offset 06h

Card B ExCA Offset 46h Default: 00h Description: This register enables/disables the memory and I/O windows to the 16-bit PC Card. By default,

all windows to the card are disabled. The PCI1450 will not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the

Table 54. ExCA Address Window Enable Register Description

BIT TYPE FUNCTION

IOWIN1EN. I/O window 1 enable. This bit enables/disables I/O window 1 for the card. This bit is encoded as:

7 R/W

IOWIN0EN. I/O window 0 enable. This bit enables/disables I/O window 0 for the card. This bit is encoded as:

6 R/W

5 R Reserved. This bit returns 0 when read. A write has no effect.

MEMWIN4EN. Memory window 4 enable. This bit enables/disables memory window 4 for the card. This bit is encoded as:

4 R/W

MEMWIN3EN. Memory window 3 enable. This bit enables/disables memory window 3 for the card. This bit is encoded as:

3 R/W

MEMWIN2EN. Memory window 2 enable. This bit enables/disables memory window 2 for the card. This bit is encoded as:

2 R/W

MEMWIN1EN. Memory window 1 enable. This bit enables/disables memory window 1 for the PC Card.

1 R/W

0 R/W

This bit is encoded as:

MEMWIN0EN. Memory window 0 enable. This bit enables/disables memory window 0 for the PC Card. This bit is encoded as:

0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled

0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled

0 = memory window 4 disabled (default) 1 = memory window 4 enabled

0 = memory window 3 disabled (default) 1 = memory window 3 enabled

0 = memory window 2 disabled (default) 1 = memory window 2 enable

0 = memory window 1 disabled (default) 1 = memory window 1 enabled

0 = memory window 0 disabled (default) 1 = memory window 0 enabled

ExCA memory and I/O window start/end/offset address registers

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ExCA I/O window control register (Index 07h)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window control Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 47h Default: 00h Description: This register contains parameters related to I/O window sizing and cycle timing.

Table 55. ExCA I/O Window Control Register Description

BIT TYPE FUNCTION

WAITST ATE1. I/O window 1 wait-state. This bit controls the I/O window 1 wait-state for 16-bit I/O accesses. This bit has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.

7 R/W

6 R/W

5 R/W

4 R/W

3 R/W

2 R/W

1 R/W

0 R/W

This bit is encoded as:

ZEROWS1. I/O window 1 zero wait-state. This bit controls the I/O window 1 wait-state for 8-bit I/O accesses. NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.

IOSIS16W1. I/O window 1 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the IOIS16

DAT ASIZE1. I/O window 1 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window 1 IOIS16 source bit (bit 5) is set. This bit is encoded as:

WAITST ATE0. I/O window 0 wait-state. This bit controls the I/O window 0 wait-state for 16-bit I/O accesses. This bit has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF. This bit is encoded as:

ZEROWS0. I/O window 0 zero wait-state. This bit controls the I/O window 0 wait-state for 8-bit I/O accesses. NOTE: This bit has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait-state used by the 82365SL-DF.

IOIS16W0. I/O window 0 IOIS16 source. This bit controls the I/O window automatic data sizing feature which used the IOIS16

DAT ASIZE0. I/O window 0 data size. This bit controls the I/O window 1 data size. This bit is ignored if the I/O window 1 IOIS16 Source bit (bit 1) is set. This bit is encoded as:

0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent ISA wait state

0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three ISA cycles

signal from the PC Card to determine the data width of the I/O data transfer.

0 = Data width determined by DATASIZE1, bit 4 (default) 1 = Window data width determined by IOIS16

0 = Window data width is 8 bits (default) 1 = Window data width is 16 bits

0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent ISA wait state

0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three ISA cycles

signal from the PC Card to determine the data width of the I/O data transfer.

0 = Data width determined by DATASIZE0, bit 0 (default) 1 = Window data width determined by IOIS16

0 = Window data width is 8 bits (default) 1 = Window data width is 16 bits

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ExCA I/O window 0 & 1 start-address low-byte register (Index 08h, 0Ch)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 & 1 start-address low-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 48h Register: ExCA I/O window 1 start-address low-byte Offset: CardBus Socket Address + 80Ch: Card A ExCA Of fset 0Ch

Card B ExCA Offset 4Ch Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit I/O window start address for I/O windows 0

and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.

ExCA I/O window 0 & 1 start-address high-byte register (Index 09h, ODh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 & 1 start-address high-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 49h Register: ExCA I/O window 1 start-address high-byte Offset: CardBus Socket Address + 80Dh: Card A ExCA Of fset 0Dh

Card B ExCA Offset 4Dh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-byte of the 16-bit I/O window start address for I/O windows 0

and 1. The 8 bits of these registers correspond to the upper 8 bits of the start address.

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ExCA I/O window 0 & 1 end-address low-byte register (Index 0Ah, 0Eh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 & 1 end-address low-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 4Ah Register: ExCA I/O window 1 end-address low-byte Offset: CardBus Socket Address + 80Eh: Card A ExCA Offset 0Eh

Card B ExCA Offset 4Eh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit I/O window end address for I/O windows 0

and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.

ExCA I/O window 0 & 1 end-address high-byte register (Index 0Bh, 0Fh)

Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 & 1 end-address high-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 4Bh Register: ExCA I/O window 1 end-address high-byte Offset: CardBus Socket Address + 80Fh: Card A ExCA Offset 0Fh

Card B ExCA Offset 4Fh Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-byte of the 16-bit I/O window end address for I/O windows 0

and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

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ExCA memory window 0–4 start-address low-byte register (Index 10h/18h/20h/28h/30h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address low-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 50h Register: ExCA memory window 1 start-address low-byte Offset: CardBus Socket Address + 818h: Card A ExCA Offset 18h

Card B ExCA Offset 58h Register: ExCA memory window 2 start-address low-byte Offset: CardBus Socket Address + 820h: Card A ExCA Offset 20h

Card B ExCA Offset 60h Register: ExCA memory window 3 start-address low-byte Offset: CardBus Socket Address + 828h: Card A ExCA Offset 28h

Card B ExCA Offset 68h Register: ExCA memory window 4 start-address low-byte Offset: CardBus Socket Address + 830h: Card A ExCA Offset 30h

Card B ExCA Offset 70h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit memory window start address for memory

windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the start address.

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ExCA memory window 0–4 start-address high-byte register (Index 11h/19h/21h/29h/31h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address high-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 51h Register: ExCA memory window 1 start-address high-byte Offset: CardBus Socket Address + 819h: Card A ExCA Offset 19h

Card B ExCA Offset 59h Register: ExCA memory window 2 start-address high-byte Offset: CardBus Socket Address + 821h: Card A ExCA Offset 21h

Card B ExCA Offset 61h Register: ExCA memory window 3 start-address high-byte Offset: CardBus Socket Address + 829h: Card A ExCA Offset 29h

Card B ExCA Offset 69h Register: ExCA memory window 4 start-address high-byte Offset: CardBus Socket Address + 831h: Card A ExCA Offset 31h

Card B ExCA Offset 71h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-nibble of the 16-bit memory window start address for

memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory window data width and wait states are set in this register.

Table 56. ExCA Memory Window 0–4 Start-Address High-Byte Register Description

BIT TYPE FUNCTION

DATASIZE. This bit controls the memory window data width. This bit is encoded as:

7 R/W

ZEROWAIT . Zero wait-state. This bit controls the memory window wait state for 8- and 16-bit accesses. This wait state timing emulates the ISA wait-state used by the 82365SL-DF. This bit is encoded as:

6 R/W

16-bit cycles reduce to the equivalent of two ISA cycles.

5–4 R/W SCRATCH. Scratch pad bits. These bits have no effect on memory window operation. 3–0 R/W

STAHN. Start address high-nibble. These bits represent the upper address bits A23–A20 of the memory window start address.

0 = Window data width is 8 bits (default) 1 = Window data width is 16 bits

0 = 8- and 16-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three ISA cycles

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ExCA memory window 0–4 end-address low-byte register (Index 12h/1Ah/22h/2Ah/32h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address low-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 52h Register: ExCA memory window 1 end-address low-byte Offset: CardBus Socket Address + 81Ah: Card A ExCA Offset 1Ah

Card B ExCA Offset 5Ah Register: ExCA memory window 2 end-address low-byte Offset: CardBus Socket Address + 822h: Card A ExCA Offset 22h

Card B ExCA Offset 62h Register: ExCA memory window 3 end-address low-byte Offset: CardBus Socket Address + 82Ah: Card A ExCA Offset 2Ah

Card B ExCA Offset 68h Register: ExCA memory window 4 end-address low-byte Offset: CardBus Socket Address + 832h: Card A ExCA Offset 32h

Card B ExCA Offset 72h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the end address.

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ExCA memory window 0–4 end-address high-byte register (Index 13h/1Bh/23h/2Bh/33h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address high-byte Type R/W R/W R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 53h Register: ExCA memory window 1 end-address high-byte Offset: CardBus Socket Address + 81Bh: Card A ExCA Offset 1Bh

Card B ExCA Offset 5Bh Register: ExCA memory window 2 end-address high-byte Offset: CardBus Socket Address + 823h: Card A ExCA Offset 23h

Card B ExCA Offset 63h Register: ExCA memory window 3 end-address high-byte Offset: CardBus Socket Address + 82Bh: Card A ExCA Offset 2Bh

Card B ExCA Offset 6Bh Register: ExCA Memory window 4 end-address high-byte Offset: CardBus Socket Address + 833h: Card A ExCA Offset 33h

Card B ExCA Offset 73h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the high-nibble of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory window wait states are set in this register.

Table 57. ExCA Memory Window 0–4 End-Address High-Byte Register Description

BIT TYPE FUNCTION

7–6 R/W 5–4 R Reserved. These bits return 0s when read. Writes have no effect. 3–0 R/W

MEMWS. Wait state. These bits specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits.

ENDHN. End address high-nibble. These bits represent the upper address bits A23–A20 of the memory window and address.

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ExCA memory window 0–4 offset-address low-byte register (Index 14h/1Ch/24h/2Ch/34h)

Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 offset-address low-byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0

Card B ExCA Offset 54h Register: ExCA memory window 1 offset-address low-byte Offset: CardBus Socket Address + 81Ch: Card A ExCA Of fset 1Ch

Card B ExCA Offset 5Ch Register: ExCA memory window 2 offset-address low-byte Offset: CardBus Socket Address + 824h: Card A ExCA Offset 24h

Card B ExCA Offset 64h Register: ExCA memory window 3 offset-address low-byte Offset: CardBus Socket Address + 82Ch: Card A ExCA Of fset 2Ch

Card B ExCA Offset 6Ch Register: ExCA memory window 4 offset-address low-byte Offset: CardBus Socket Address + 834h: Card A ExCA Offset 34h

Card B ExCA Offset 74h Type: Read/Write Default: 00h Size: One byte Description: These registers contain the low-byte of the 16-bit memory window offset address for memory

windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19–A12 of the offset address.

100

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