Texas Instruments MSP430G2955, MSP430G2855, MSP430G2755 User Manual

MSP430G2955 MSP430G2855 MSP430G2755

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MIXED SIGNAL MICROCONTROLLER

Check for Samples: MSP430G2955, MSP430G2855, MSP430G2755

FEATURES

• Low Supply-Voltage Range: 1.8 V to 3.6 V • Universal Serial Communication Interface

• Ultra-Low Power Consumption – Active Mode: 250 µA at 1 MHz, 2.2 V – Standby Mode: 0.7 µA – Off Mode (RAM Retention): 0.1 µA

• Five Power-Saving Modes

• Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs

• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time

• Basic Clock Module Configurations – Internal Frequencies up to 16 MHz With

Four Calibrated Frequency

– Internal Very-Low-Power Low-Frequency

(LF) Oscillator – 32-kHz Crystal – High-Frequency (HF) Crystal up to 16 MHz – External Digital Clock Source – External Resistor

• Two 16-Bit Timer_A With Three Capture/Compare Registers

• One 16-Bit Timer_B With Three Capture/Compare Registers

• Up to 32 Touch-Sense-Enabled I/O Pins

(USCI) – Enhanced UART Supporting Auto Baudrate

Detection (LIN) – IrDA Encoder and Decoder – Synchronous SPI – I2C™

• On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion

• 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sampleand-Hold, and Autoscan

• Brownout Detector

• Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse

• Bootstrap Loader

• On-Chip Emulation Logic

• Family Members are Summarized in Table 1

• Package Options – TSSOP: 38 Pin (DA) – QFN: 40 Pin (RHA)

• For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (SLAU144)

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430G2x55 series are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, up to 32 I/O touch-sense-enabled pins, a versatile analog comparator, and built-in communication capability using the universal serial communication interface. For configuration details, see Table 1.

Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

1TEST/SBWTCK

2DVCC

3P2.5/TA1.0/ROSC

XOUT/P2.7

XIN/P2.6 6

RST/NMI/SBWTDIO

P2.0/TA1CLK/ACLK/A0

P2.1/TA0INCLK/SMCLK/A1 9

P2.2/TA0.0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB 00. /CA0

P4.1/TB 10. /CA1

P4.2/TB 20. /CA2

P4.3/TB 0/A120. /CA3

18 P4.4/TB 1/A130. /CA4

38 P1.7/TA 2/TDO/TDI0.

37 P1.6/TA 1/TDI0.

P1.5/TA 0/TMS0.

35 P1.4/SMCLK/TCK

P1.3/TA 20.

P1.2/TA 10.

32 P1.1/TA 00.

P1.0/TA0CLK/ADC10CLK

P2.4/TA 2/A4/VREF+/VEREF+0.

29 P2.3/TA 1/A3/VREF−/VEREF−0.

28 P3.7/TA1.2/A7

27 P3.6/TA1.1/A6

26 P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TB0CLK/CA7

P4.6/TB0OUTH/A15/CA6

DVSS

P4.5/TB 2/A140. /CA5

MSP430G2955 MSP430G2855 MSP430G2755

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Table 1. Available Options

Device BSL EEM Clock I/O

MSP430G2955IDA38 HF, LF, 32 38-TSSOP MSP430G2955IRHA40 32 40-QFN MSP430G2855IDA38 HF, LF, 32 38-TSSOP MSP430G2855IRHA40 32 40-QFN MSP430G2755IDA38 HF, LF, 32 38-TSSOP MSP430G2755IRHA40 32 40-QFN

1 1 56 4096 8 12 1 DCO,

1 1 48 4096 8 12 1 DCO,

1 1 32 4096 8 12 1 DCO,

Flash RAM Timer_A COMP_A+ ADC10 USCI_A0 Package

(KB) (B) Timer_B Channels Channels USCI_B0 Type

2x TA3 1x TB3

(1)(2)

VLO

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Device Pinout, 38-Pin TSSOP (DA Package)

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Basic Clock

System+

RAM

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15 or 16 Bit

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

56 kB 48 kB 32 kB

ACLK

XIN

MDB

MAB

Spy-Bi-Wire

3 CC

Registers,

Shadow Register

USCI_A0:

UART, LIN,

IrDA,SPI

USCI_B0:

SPI,I2C

ADC

10-Bit

12 Channels, Autoscan,

DTC

Ports P1, P2

2x8 I/O,

Interrupt

capability,

Pullup or pulldown

resistors

P1.x, P2.x

2x8

P3.x, P4.x

2x8

4 kB

Timer0_A3

3 CC

Registers

Timer1_A3

Timer0_B3

COMP_A+

Channels

Ports P3, P4

2x8 I/O, Pullup or pulldown resistors

1DVSS

P1.5/TA0.0/TMS

P1.0/TA0CLK/ADC10CLK

P1.1/TA0.0

P1.2/TA0.1

P1.3/TA0.2

P1.4/SMCLK/TCK

P2.4/TA0.2/A4/VREF+/VEREF+

P2.5/TA1.0/ROSC

DVCC

TEST/SBWTCK

P1.6/TA0.1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/TA1CLK/ACLK/A0

P2.1/TA0INCLK/SMCLK/A1

P2.2/TA0.0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA0.2/TDO/TDI

P2.3/TA0.1/A3/VREF−/VEREF−

P3.7/TA1.2/A7

P3.6/TA1.1/A6

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.3/UCB0CLK/UCA0STE

P4.0/TB0.0/CA0

P4.1/TB0.1/CA1

P4.2/TB0.2/CA2

P4.3/TB0.0/A12/CA3

P4.4/TB0.1/A13/CA4

P4.5/TB0.2/A14/CA5

P4.6/TB0OUTH/A15/CA6

P4.7/TB0CLK/CA7

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Device Pinout, 40-Pin QFN (RHA Package)

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Functional Block Diagram

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Table 2. Terminal Functions

TERMINAL

NAME

P1.0/ General-purpose digital I/O pin TACLK/ 31 29 I/O Timer_A, clock signal TACLK input ADC10CLK ADC10, conversion clock P1.1/ General-purpose digital I/O pin TA0.0 Timer_A, capture: CCI0A input, compare: OUT0 output or BSL transmit P1.2/ General-purpose digital I/O pin TA0.1 Timer_A, capture: CCI1A input, compare: OUT1 output P1.3/ General-purpose digital I/O pin TA0.2 Timer_A, capture: CCI2A input, compare: OUT2 output P1.4/ General-purpose digital I/O pin SMCLK/ 35 33 I/O SMCLK signal output TCK JTAG test clock, input terminal for device programming and test P1.5/ General-purpose digital I/O pin TA0.0/ 36 34 I/O Timer_A, compare: OUT0 output TMS JTAG test mode select, input terminal for device programming and test P1.6/ General-purpose digital I/O pin / TA0.1/ Timer_A, compare: OUT1 output TDI/ JTAG test data input terminal during programming and test TCLK JTAG test clock input terminal during programming and test P1.7/ General-purpose digital I/O pin TA0.2/ Timer_A, compare: OUT2 output TDO/ JTAG test data output terminal during programming and test

(1)

TDI P2.0/ General-purpose digital I/O pin TA1CLK/ Timer1_A3.TACLK ACLK/ ACLK output A0 ADC10, analog input A0 P2.1/ General-purpose digital I/O pin TAINCLK/ Timer_A, clock signal at INCLK SMCLK/ SMCLK signal output A1 ADC10, analog input A1 P2.2/ General-purpose digital I/O pin TA0.0/ 10 8 I/O Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output A2 ADC10, analog input A2 P2.3/ General-purpose digital I/O pin TA0.1/ Timer_A, capture CCI1B input, compare: OUT1 output A3/ 29 27 I/O ADC10, analog input A3 VREF-/ Negative reference voltage output VEREF- Negative reference voltage input P2.4/ General-purpose digital I/O pin TA0.2/ Timer_A, compare: OUT2 output A4/ 30 28 I/O ADC10, analog input A4 VREF+/ Positive reference voltage output VEREF+ Positive reference voltage input

NO. I/O DESCRIPTION

DA RHA

32 30 I/O

33 31 I/O

34 32 I/O

37 35 I/O

38 36 I/O

JTAG test data input terminal during programming and test

8 6 I/O

9 7 I/O

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

P2.5/ General-purpose digital I/O pin TA1.0/ 3 40 I/O Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output ROSC Input for external DCO resistor to define DCO frequency XIN/ Input terminal of crystal oscillator P2.6 General-purpose digital I/O pin XOUT/ Output terminal of crystal oscillator P2.7 General-purpose digital I/O pin P3.0/ General-purpose digital I/O pin UCB0STE/ USCI_B0 slave transmit enable UCA0CLK/ USCI_A0 clock input/output A5 ADC10, analog input A5 P3.1/ General-purpose digital I/O pin UCB0SIMO/ 12 10 I/O USCI_B0 slave in, master out in SPI mode UCB0SDA USCI_B0 SDA I2C data in I2C mode P3.2/ General-purpose digital I/O pin UCB0SOMI/ 13 11 I/O USCI_B0 slave out, master in SPI mode UCB0SCL USCI_B0 SCL I2C clock in I2C mode P3.3/ General-purpose digital I/O pin UCB0CLK/ 14 12 I/O USCI_B0 clock input/output UCA0STE USCI_A0 slave transmit enable P3.4/ General-purpose digital I/O pin UCA0TXD/ 25 23 I/O USCI_A0 transmit data output in UART mode UCA0SIMO USCI_A0 slave in, master out in SPI mode P3.5/ General-purpose digital I/O pin UCA0RXD/ 26 24 I/O USCI_A0 receive data input in UART mode UCA0SOMI USCI_A0 slave out, master in SPI mode P3.6/ General-purpose digital I/O pin TA1.1/ 27 25 I/O Timer_A, capture: CCI1B input or BSL receive, compare: OUT2 output A6 ADC10 analog input A6 P3.7/ General-purpose digital I/O pin TA1.2/ 28 26 I/O Timer_A, capture: CCI2B input or BSL receive, compare: OUT2 output A7 ADC10 analog input A7 P4.0/ General-purpose digital I/O pin TB0.0/ 17 15 I/O Timer_B, capture: CCI0A input, compare: OUT0 output CA0 Comparator_A+, CA0 input P4.1/ General-purpose digital I/O pin TB0.1/ 18 16 I/O Timer_B, capture: CCI1A input, compare: OUT1 output CA1 Comparator_A+, CA1 input P4.2/ General-purpose digital I/O pin TB0.2/ 19 17 I/O Timer_B, capture: CCI2A input, compare: OUT2 output CA2 Comparator_A+, CA2 input

NO. I/O DESCRIPTION

DA RHA

6 3 I/O

5 2 I/O

11 9 I/O

(2)

SLAS800 –MARCH 2013

(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

P4.3/ General-purpose digital I/O pin TB0.0/ Timer_B, capture: CCI0B input, compare: OUT0 output A12/ ADC10 analog input A12 CA3 Comparator_A+, CA3 input P4.4/ General-purpose digital I/O pin TB0.1/ Timer_B, capture: CCI1B input, compare: OUT1 output A13/ ADC10 analog input A13 CA4 Comparator_A+, CA4 input P4.5/ General-purpose digital I/O pin TB0.2/ Timer_B, compare: OUT2 output A14/ ADC10 analog input A14 CA5 Comparator_A+, CA5 input P4.6/ General-purpose digital I/O pin TBOUTH/ Timer_B, switch all TB0 to TB3 outputs to high impedance CAOUT/ 23 21 I/O Comparator_A+ Output A15/ ADC10 analog input A15 CA6 Comparator_A+, CA6 input P4.7/ General-purpose digital I/O pinCB0 TBCLK/ Timer_B, clock signal TBCLK input CAOUT/ Comparator_A+ Output CA7 Comparator_A+, CA7 input RST/ Reset or nonmaskable interrupt input NMI/SBWTDIO Spy-Bi-Wire test data input/output during programming and test TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is

SBWTCK Spy-Bi-Wire test clock input during programming and test DV

QFN Pad NA Pad NA QFN package pad; connection to DVSSrecommended.

NO. I/O DESCRIPTION

DA RHA

20 18 I/O

21 19 I/O

22 20 I/O

24 22 I/O

7 5 I

1 37 I

2 38, 39 Digital supply voltage

16 14 Analog supply voltage

4 1, 4 Digital ground reference

15 13 Analog ground reference

connected to TEST.

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General-PurposeRegister

ProgramCounter

StackPointer

StatusRegister

ConstantGenerator

General-PurposeRegister

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-PurposeRegister

R10

R11

General-PurposeRegister

R14

R15

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SHORT-FORM DESCRIPTION

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

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Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.

Table 3 shows examples of the three types of

instruction formats; Table 4 shows the address modes.

Dual operands, source-destination ADD R4,R5 R4 + R5 ---> R5 Single operands, destination only CALL R8 PC -->(TOS), R8--> PC Relative jump, un/conditional JNE Jump-on-equal bit = 0

Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) -- --> M(TONI)

Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11

(1) S = source, D = destination

INSTRUCTION FORMAT EXAMPLE OPERATION

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- --> M(6+R6)

Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT)

Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6)

Immediate ✓ MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI)

Table 3. Instruction Word Formats

Table 4. Address Mode Descriptions

(1)

M(R10) -- --> R11 R10 + 2-- --> R10

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Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM) – All clocks are active.

• Low-power mode 0 (LPM0) – CPU is disabled. – ACLK and SMCLK remain active. – MCLK is disabled.

• Low-power mode 1 (LPM1) – CPU is disabled – ACLK and SMCLK remain active. – MCLK is disabled. – DCO's dc generator is disabled if DCO not used in active mode.

• Low-power mode 2 (LPM2) – CPU is disabled. – ACLK remains active. – MCLK and SMCLK are disabled. – DCO's dc generator remains enabled.

• Low-power mode 3 (LPM3) – CPU is disabled. – ACLK remains active. – MCLK and SMCLK are disabled. – DCO's dc generator is disabled.

• Low-power mode 4 (LPM4) – CPU is disabled. – ACLK, MCLK, and SMCLK are disabled. – DCO's dc generator is disabled. – Crystal oscillator is stopped.

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the CPU goes into LPM4 immediately after power-up.

Table 5. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

Power-Up PORIFG

External Reset RSTIFG

Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest Flash key violation KEYV PC out-of-range

(1)

(2)

NMI NMIIFG (non)-maskable

Oscillator fault OFIFG (non)-maskable 0FFFCh 30

Flash memory access violation ACCVIFG

Timer0_B3 TB0CCR0 CCIFG Timer0_B3 TB0CCR2 TB0CCR1 CCIFG,

TBIFG

Comparator_A+ CAIFG

(2)(3)

(4)

(2)(4)

(4)

Watchdog Timer+ WDTIFG maskable 0FFF4h 26

Timer0_A3 TA0CCR0 CCIFG Timer0_A3 TA0CCR2 TA0CCR1 CCIFG,

TAIFG

USCI_A0 or USCI_B0 receive UCA0RXIFG, UCB0RXIFG

(4)

(5)(4)

(2)(5)

USCI_B0 I2C status

USCI_A0 or USCI_B0 transmit UCA0TXIFG, UCB0TXIFG

(2)(6)

USCI_B0 I2C receive or transmit

ADC10 ADC10IFG

(4)

Reserved 0FFE8h 20 I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7 I/O Port P1 (up to eight flags) P1IFG.0 to P1IFG.7

Timer1_A3 TA1CCR0 CCIFG Timer1_A3 TA1CCR2 TA1CCR1 CCIFG,

TAIFG

(7)

See

(8)

See

(2)(4) (2)(4) (4)

(2)(4)

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges. (2) Multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. (4) Interrupt flags are located in the module. (5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG. (6) In UART or SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. (7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)

disables the erasure of the flash if an invalid password is supplied. (8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

SYSTEM WORD

INTERRUPT ADDRESS

(non)-maskable

maskable 0FFFAh 29 maskable 0FFF8h 28 maskable 0FFF6h 27

maskable 0FFF2h 25 maskable 0FFF0h 24

maskable 0FFEEh 23

maskable 0FFECh 22 maskable 0FFEAh 21

maskable 0FFE6h 19 maskable 0FFE4h 18 maskable 0FFE2h 17

maskable 0FFE0h 16

0FFDEh 15

0FFDEh to

0FFC0h

SLAS800 –MARCH 2013

14 to 0, lowest

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Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend rw: Bit can be read and written.

rw-0,1: Bit can be read and written. It is reset or set by PUC. rw-(0,1): Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address 7 6 5 4 3 2 1 0

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog timer is configured in

interval timer mode.

OFIE Oscillator fault interrupt enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable

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Address 7 6 5 4 3 2 1 0

01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw-0 rw-0 rw-0 rw-0

UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 receive interrupt enable UCB0TXIE USCI_B0 transmit interrupt enable

Table 7. Interrupt Flag Register 1 and 2

Address 7 6 5 4 3 2 1 0

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

OFIFG Flag set on oscillator fault. PORIFG Power-on reset interrupt flag. Set on VCCpower-up. RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCCpower-up. NMIIFG Set via RST/NMI pin

Address 7 6 5 4 3 2 1 0

03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

UCA0RXIFG USCI_A0 receive interrupt flag UCA0TXIFG USCI_A0 transmit interrupt flag UCB0RXIFG USCI_B0 receive interrupt flag UCB0TXIFG USCI_B0 transmit interrupt flag

Reset on VCCpower-on or a reset condition at the RST/NMI pin in reset mode.

rw-1 rw-0 rw-1 rw-0

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Memory Organization

Table 8. Memory Organization

MSP430G2755 MSP430G2855 MSP430G2955

Memory Size 32kB 48kB 56kB Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 Main: code memory Flash 0xFFFF to 0x8000 0xFFFF to 0x4000 0xFFFF to 0x2100 Information memory Size 256 Byte 256 Byte 256 Byte

Flash 0x10FF to 0x1000 0x10FF to 0x1000 0x10FF to 0x1000

RAM (total) Size 4kB 4kB 4kB

0x20FF to 0x1100 0x20FF to 0x1100 0x20FF to 0x1100

Extended Size 2KB 2KB 2KB

0x20FF to 0x1900 0x20FF to 0x1900 0x20FF to 0x1900

Mirrored Size 2KB 2KB 2KB

0x18FF to 0x1100 0x18FF to 0x1100 0x18FF to 0x1100

RAM (mirrored at 0x18FF to 0x1100)

Peripherals 16-bit 0x01FF to 0x0100 0x01FF to 0x0100 0x01FF to 0x0100

Size 2KB 2KB 2KB

0x09FF to 0x0200 0x09FF to 0x0200 0x09FF to 0x0200

8-bit 0x00FF to 0x0010 0x00FF to 0x0010 0x00FF to 0x0010

8-bit SFR 0x000F to 0x0000 0x000F to 0x0000 0x000F to 0x0000

SLAS800 –MARCH 2013

Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).

Table 9. BSL Function Pins

BSL FUNCTION DA PACKAGE PINS RHA PACKAGE PINS

Data transmit 32 - P1.1 30 - P1.1

Data receive 10 - P2.2 8 - P2.2

Flash Memory

The flash memory can be programmed via the Spy-Bi-Wire or JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also

called information memory.

• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.

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DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

average

DCO(RSEL,DCO) DCO(RSEL,DCO+1)

32 × f × f

f =

MOD × f + (32 – MOD) × f

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals:

• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

• Main clock (MCLK), the system clock used by the CPU.

• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

Main DCO Characteristics

• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

• DCO control bits DCOx have a step size as defined by parameter S

• Modulation control bits MODx select how often f

cycles. The frequency f

DCO(RSEL,DCO)

is used for the remaining cycles. The frequency is an average equal to:

DCO(RSEL,DCO+1)

DCO

is used within the period of 32 DCOCLK

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Calibration Data Stored in Information Memory Segment A

Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value (TLV) structure.

Table 10. Tags Used by the Devices

NAME ADDRESS VALUE DESCRIPTION

TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC= 3 V and TA= 30°C at calibration

TAG_ADC10_1 0x10DA 0x10 ADC10_1 calibration tag

TAG_EMPTY - 0xFE Identifier for empty memory areas

Table 11. Labels Used by the Devices

LABEL SIZE CONDITION AT CALIBRATION AND DESCRIPTION

CAL_ADC_25T85 0x0010 word INCHx = 0x1010, REF2_5 = 1, TA= 85°C CAL_ADC_25T30 0x000E word INCHx = 0x1010, REF2_5 = 1, TA= 30°C

CAL_ADC_25VREF_FACTOR 0x000C word REF2_5 = 1, TA= 30°C, I

CAL_ADC_15T85 0x000A word INCHx = 0x1010, REF2_5 = 0, TA= 85°C CAL_ADC_15T30 0x0008 word INCHx = 0x1010, REF2_5 = 0, TA= 30°C

CAL_ADC_15VREF_FACTOR 0x0006 word REF2_5 = 0, TA= 30°C, I

CAL_ADC_OFFSET 0x0004 word External VREF = 1.5 V, f

CAL_ADC_GAIN_FACTOR 0x0002 word External VREF = 1.5 V, f

CAL_BC1_1MHZ 0x0009 byte -

CAL_DCO_1MHZ 0x0008 byte -

CAL_BC1_8MHZ 0x0007 byte -

CAL_DCO_8MHZ 0x0006 byte -

CAL_BC1_12MHZ 0x0005 byte -

CAL_DCO_12MHZ 0x0004 byte -

CAL_BC1_16MHZ 0x0003 byte -

CAL_DCO_16MHZ 0x0002 byte -

ADDRESS

OFFSET

VREF+

VREF+ ADC10CLK ADC10CLK

= 1 mA

= 0.5 mA

= 5 MHz = 5 MHz

SLAS800 –MARCH 2013

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

Digital I/O

Four 8-bit I/O ports are implemented:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.

• Edge-selectable interrupt input capability for all bits of port P1 and port P2.

• Read and write access to port-control registers is supported by all instructions.

• Each I/O has an individually programmable pullup or pulldown resistor.

• Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing.

Watchdog Timer (WDT+)

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

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Timer_A3 (TA0, TA1)

Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 12. Timer0_A3 Signal Connections

INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER

DA38 RHA40 DA38 RHA40

P1.0 - 31 P1.0-29 TACLK TACLK

P2.1 - 9 P2.1 - 7 TACLK INCLK P1.1 - 32 P1.1 - 30 TA0.0 CCI0A P1.1- 32 P1.1 - 30 P2.2 - 10 P2.2 - 8 ACLK CCI0B P2.2 - 10 P2.2 - 8

P1.2 - 33 P1.2 - 31 TA0.1 CCI1A P1.2 - 33 P1.2 - 31 P2.3 - 29 P2.3 - 27 TA0.1 CCI1B P2.3 - 29 P2.3 - 27

P1.3 - 34 P1.3 - 32 TA0.2 CCI2A P1.3 - 34 P1.3 - 32

DEVICE INPUT MODULE MODULE

SIGNAL INPUT NAME BLOCK

ACLK ACLK

SMCLK SMCLK

GND P1.5 - 36 P1.5 - 34

GND P1.6 - 37 P1.6 - 35

ACLK (internal) CCI2B P2.4 - 30 P2.4 - 28

GND P1.7 - 38 P1.7 - 36

Timer NA

CCR0 TA0

CCR1 TA1

CCR2 TA2

OUTPUT

SIGNAL

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Table 13. Timer1_A3 Signal Connections

INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER

DA38 RHA40 DA38 RHA40

P2.0 - 8 P2.0 - 6 TACLK TACLK

PinOsc PinOsc TACLK INCLK

P2.5 - 3 P2.5 - 40 TA1.0 CCI0A P2.5 - 3 P2.5 - 40

P3.6 - 27 P3.6 - 25 TA1.1 CCI1A P3.6 - 27 P3.6 - 25

P3.7 - 28 P3.7 - 26 TA1.2 CCI2A P3.7 - 28 P3.7 - 26

PinOsc PinOsc TA1.2 CCI2B

DEVICE INPUT MODULE MODULE

SIGNAL INPUT NAME BLOCK

ACLK ACLK

SMCLK SMCLK

TA1.0 CCI0B

GND

CAOUT CCI1B

GND

Timer NA

CCR0 TA0

CCR1 TA1

CCR2 TA2

OUTPUT

SIGNAL

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Timer_B3 (TB0)

Timer0_B3 is a 16-bit timer/counter with three capture/compare registers. Timer0_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 14. Timer0_B3 Signal Connections

INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER

DA38 RHA40 DA38 RHA40

P4.7 - 24 P4.7 - 22 TBCLK TBCLK

P4.7 - 27 P4.7 - 22 TBCLK INCLK P4.0 - 17 P4.0 - 15 TB0.0 CCI0A P4.0 - 17 P4.0 - 15

P4.3 -20 P4.3 - 18 TB0.0 CCI0B P4.3 - 20 P4.3 - 18

P4.1 - 18 P4.1 - 16 TB0.1 CCI1A P4.1 - 18 P4.1 - 16 P4.4 - 21 P4.4 - 19 TB0.1 CCI1B P4.4 - 21 P4.4 - 19

P4.2 - 19 P4.2 - 17 TB0.2 CCI2A P4.2 - 19 P4.2 - 17

DEVICE INPUT MODULE MODULE

SIGNAL INPUT NAME BLOCK

ACLK ACLK

SMCLK SMCLK

ACLK (internal) CCI2B P4.5 - 22 P4.5 - 20

GND

Timer NA

CCR0 TB0

CCR1 TB1

CCR2 TB2

OUTPUT

SIGNAL

SLAS800 –MARCH 2013

Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

Comparator_A+

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

ADC10

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention.

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Peripheral File Map

Table 15. Peripherals With Word Access

MODULE REGISTER DESCRIPTION OFFSET

ADC10 ADC data transfer start address ADC10SA 1BCh

ADC memory ADC10MEM 1B4h ADC control register 1 ADC10CTL1 1B2h ADC control register 0 ADC10CTL0 1B0h

Timer0_B3 Capture/compare register TB0CCR2 0196h

Capture/compare register TB0CCR1 0194h Capture/compare register TB0CCR0 0192h Timer_B register TB0R 0190h Capture/compare control TB0CCTL2 0186h Capture/compare control TB0CCTL1 0184h Capture/compare control TB0CCTL0 0182h Timer_B control TB0CTL 0180h Timer_B interrupt vector TB0IV 011Eh

Timer0_A3 Capture/compare register TA0CCR2 0176h

Capture/compare register TA0CCR1 0174h Capture/compare register TA0CCR0 0172h Timer_A register TA0R 0170h Capture/compare control TA0CCTL2 0166h Capture/compare control TA0CCTL1 0164h Capture/compare control TA0CCTL0 0162h Timer_A control TA0CTL 0160h Timer_A interrupt vector TA0IV 012Eh

Timer1_A3 Capture/compare register TA1CCR2 0156h

Capture/compare register TA1CCR1 0154h Capture/compare register TA1CCR0 0152h Timer_A register TA1R 0150h Capture/compare control TA1CCTL2 0146h Capture/compare control TA1CCTL1 0144h Capture/compare control TA1CCTL0 0142h Timer_A control TA1CTL 0140h Timer_A interrupt vector TA1IV 011Ch

Flash Memory Flash control 3 FCTL3 012Ch

Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h

Watchdog Timer+ Watchdog/timer control WDTCTL 0120h

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Table 16. Peripherals With Byte Access

MODULE REGISTER DESCRIPTION OFFSET

USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh

USCI_B0 receive buffer UCB0RXBUF 06Eh USCI_B0 status UCB0STAT 06Dh USCI B0 I2C Interrupt enable UCB0CIE 06Ch USCI_B0 bit rate control 1 UCB0BR1 06Bh USCI_B0 bit rate control 0 UCB0BR0 06Ah USCI_B0 control 1 UCB0CTL1 069h USCI_B0 control 0 UCB0CTL0 068h USCI_B0 I2C slave address UCB0SA 011Ah USCI_B0 I2C own address UCB0OA 0118h

USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h

USCI_A0 receive buffer UCA0RXBUF 066h USCI_A0 status UCA0STAT 065h USCI_A0 modulation control UCA0MCTL 064h USCI_A0 baud rate control 1 UCA0BR1 063h USCI_A0 baud rate control 0 UCA0BR0 062h USCI_A0 control 1 UCA0CTL1 061h USCI_A0 control 0 UCA0CTL0 060h USCI_A0 IrDA receive control UCA0IRRCTL 05Fh USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh USCI_A0 auto baud rate control UCA0ABCTL 05Dh

ADC10 ADC analog enable 0 ADC10AE0 04Ah

ADC analog enable 1 ADC10AE1 04Bh ADC data transfer control register 1 ADC10DTC1 049h ADC data transfer control register 0 ADC10DTC0 048h

Comparator_A+ Comparator_A+ port disable CAPD 05Bh

Comparator_A+ control 2 CACTL2 05Ah Comparator_A+ control 1 CACTL1 059h

Basic Clock System+ Basic clock system control 3 BCSCTL3 053h

Basic clock system control 2 BCSCTL2 058h Basic clock system control 1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h

Port P4 Port P4 selection 2 P4SEL2 044h

Port P4 resistor enable P4REN 011h Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch

Port P3 Port P3 selection 2 P3SEL2 043h

Port P3 resistor enable P3REN 010h Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h

NAME

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Table 16. Peripherals With Byte Access (continued)

MODULE REGISTER DESCRIPTION OFFSET

Port P2 Port P2 selection 2 P2SEL2 042h

Port P2 resistor enable P2REN 02Fh Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h

Port P1 Port P1 selection 2 P1SEL2 041h

Port P1 resistor enable P1REN 027h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h

Special Function SFR interrupt flag 2 IFG2 003h

SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

NAME

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Supply voltage range, during flash memory programming

Supply voltage range, during program execution

Legend:

16 MHz

System Frequency - MHz

12 MHz

6 MHz

1.8 V Supply Voltage - V

3.3 V

2.7 V

2.2 V

3.6 V

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Absolute Maximum Ratings

Voltage applied at VCCto V Voltage applied to any pin Diode current at any device pin ±2 mA

Storage temperature range, T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

(2)

stg

(1)

(3)

Unprogrammed device –55°C to 150°C Programmed device –55°C to 150°C

Recommended Operating Conditions

Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)

V T

SYSTEM

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the (2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Supply voltage V

Supply voltage 0 V

Operating free-air temperature -40 85 °C

Processor frequency (maximum MCLK frequency VCC= 2.7 V, using the USART module)

specified maximum frequency.

(1)(2)

During program execution 1.8 3.6 During flash programming or erase 2.2 3.6

VCC= 1.8 V, Duty cycle = 50% ± 10%

Duty cycle = 50% ± 10% VCC= 3.3 V,

Duty cycle = 50% ± 10%

SLAS800 –MARCH 2013

–0.3 V to 4.1 V

–0.3 V to VCC+ 0.3 V

MIN NOM MAX UNIT

dc 6

dc 12 MHz

dc 16

Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V

of 2.2 V.

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Figure 1. Safe Operating Area

0.0

1.0

2.0

3.0

4.0

5.0

1.5 2.0 2.5 3.0 3.5 4.0

VCC− Supply Voltage − V

Active Mode Current − mA

DCO

= 1 MHz

DCO

= 8 MHz

DCO

= 12 MHz

DCO

= 16 MHz

0.0

1.0

2.0

3.0

4.0

0.0 4.0 8.0 12.0 16.0

DCO

− DCO Frequency − MHz

Active Mode Current − mA

TA= 25 °C

TA= 85 °C

VCC= 2.2 V

VCC= 3 V

TA= 25 °C

TA= 85 °C

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Electrical Characteristics Active Mode Supply Current Into VCCExcluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS T

= f

MCLK

= 0 Hz,

= f

DCO

ACLK

AM,1MHz

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

Active mode (AM) current at 1 MHz

Program executes in flash, BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

= 1 MHz, 2.2 V 250

SMCLK

3 V 350 450

(1)(2)

MIN TYP MAX UNIT

Typical Characteristics, Active Mode Supply Current (Into VCC)

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Figure 2. Active Mode Current vs VCC, TA= 25°C Figure 3. Active Mode Current vs DCO Frequency

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0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.0

−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0

I − Low−power mode current − µA

LPM3

V = 3.6 V

TA− Temperature − °C

V = 1.8 V

V = 3 V

V = 2.2 V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

−40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0

TA− Temperature − C

V = 3.6 V

TA− Temperature − C

I − Low−power mode current − µA

LPM4

V = 1.8 V

V = 3 V

V = 2.2 V

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Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LPM0,1MHz

PARAMETER TEST CONDITIONS T

= 0 MHz,

MCLK

= f

= 1 MHz,

DCO

= 32768 Hz,

Low-power mode 0 (LPM0) current

(3)

SMCLK

ACLK

BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 56 µA DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

LPM2

Low-power mode 2 (LPM2) current

(4)

= f

MCLK

= 1 MHz,

DCO

= 32768 Hz,

ACLK

BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 22 µA DCOCTL = CALDCO_1MHZ,

SMCLK

= 0 MHz,

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

= f

LPM3,LFXT1

Low-power mode 3 f (LPM3) current

(4)

DCO ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

= f

MCLK

= 32768 Hz,

SMCLK

= 0 MHz,

25°C 2.2 V 1.0 1.5 µA OSCOFF = 0 f

= f

LPM3,VLO

Low-power mode 3 f current, (LPM3)

(4)

DCO ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

= f

MCLK

from internal LF oscillator (VLO),

SMCLK

= 0 MHz,

25°C 2.2 V 0.5 0.7 µA OSCOFF = 0 f

= f

LPM4

Low-power mode 4 f (LPM4) current

(5)

MCLK

= 0 Hz,

= f

DCO ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1

= 0 MHz, 25°C 2.2 V 0.1 0.5

SMCLK

85°C 2.2 V 1.6 2.5

load capacitance is chosen to closely match the required 9 pF. (3) Current for brownout and WDT clocked by SMCLK included. (4) Current for brownout and WDT clocked by ACLK included. (5) Current for brownout included.

MIN TYP MAX UNIT

SLAS800 –MARCH 2013

(1) (2)

µA

Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 4. LPM3 Current vs Temperature Figure 5. LPM4 Current vs Temperature

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Schmitt-Trigger Inputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V R C

Positive-going input threshold voltage V

IT+

Negative-going input threshold voltage V

IT–

Input voltage hysteresis (V

hys

Pullup or pulldown resistor 3 V 20 35 50 kΩ

Pull

Input capacitance VIN= VSSor V

IT+

– V

) 3 V 0.3 1 V

IT–

For pullup: VIN= V For pulldown: VIN= V

3 V 1.35 2.25

3 V 0.75 1.65

MIN TYP MAX UNIT

0.45 V

0.25 V

5 pF

Leakage Current, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

lkg(Px.y)

PARAMETER TEST CONDITIONS V

High-impedance leakage current

(1) (2)

3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

MIN MAX UNIT

0.75 V

0.55 V

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Outputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V V

High-level output voltage I

Low-level output voltage I

(1) The maximum total current, I

specified.

(OHmax)

and I

= –6 mA

(OHmax)

= 6 mA

(OLmax)

, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

(OLmax)

(1)

3 V VCC– 0.3 V 3 V VSS+ 0.3 V

MIN TYP MAX UNIT

Output Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Px.y

Port_CLK

PARAMETER TEST CONDITIONS V

Port output frequency (with load)

Px.y, CL= 20 pF, RL= 1 kΩ

Clock output frequency Px.y, CL= 20 pF

(2)

(1) (2)

3 V 12 MHz 3 V 16 MHz

(1) A resistive divider with two 0.5-kΩ resistors between VCCand VSSis used as load. The output is connected to the center tap of the

divider. (2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

MIN TYP MAX UNIT

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