Texas Instruments LP87702-Q1 Datasheet

SW_B0VIN_B0

VIN_B1

VANA

VIN

FB_B0

VOUT0

LOAD

SDA (EN3)

SCL (EN2)

nINT

CLKIN (GPO2/WD_DIS)

GNDs

EN1

SW_B1

FB_B1

VOUT1

PG0

VMON1

VMON2

PG1 (GPO1)

WDI WD_RESET

SW_BST

VOUT_BST

VOUT2

LOAD

GPO0

NRST

Output Current (mA)

Efficiency (%)

1 10 100 1000 5000

100

Exce

VIN=3.3V, VOUT=1.2V VIN=3.3V, VOUT=1.8V VIN=3.3V, VOUT=2.3V

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Reference Design

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

LP87702-Q1 Dual Buck Converter and 5-V Boost With Diagnostic Functions

1 Features

• AEC-Q100 Qualified for Automotive Applications: – Device Temperature Grade 1: –40°C to

+125°C, T

• FMEDA and Functional Safety Manual available to support your ASIL compliant system designs

• Two High-Efficiency Step-Down DC/DC converters:

– Maximum Output Current 3.5 A – 2-MHz, 3-MHz, or 4-MHz Switching Frequency – Auto PWM/PFM and Forced-PWM Operations – Output Voltage = 0.7 V to 3.36 V

• 5-V Boost Converter With Bypass-Mode Option: – Maximum Output Current 600 mA

• Two Inputs for External Voltage Monitoring

• Two Programmable Power-Good Signals

• Dedicated Reference Voltage for Diagnostics

• Window Watchdog With Reset Output

• External Clock Input to Synchronize Switching

• Spread-Spectrum Modulation

• Programmable Start-up and Shutdown Delays and Sequencing With Enable Signal

• Configurable General Purpose Outputs (GPOs)

• I2C-Compatible Interface Supporting Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes

• Interrupt Function With Programmable Masking

• Output Short-Circuit and Overload Protection

• Overtemperature Warning and Protection

• Overvoltage Protection (OVP) and Undervoltage Lockout (UVLO)

Simplified Schematic

2 Applications

Automotive Radar, Automotive Camera, Automotive Sensor Fusion, Industrial Radar, Building Automation

3 Description

The LP87702-Q1 helps meet the power management requirements of the latest platforms, particularly in automotive radar and camera and industrial radar applications. The device contains two step-down DC/DC converters, and a 5-V boost converter/bypass switch. To support safety critical applications. the device integrates two voltage monitoring inputs for external power supplies, and a window watchdog.

The automatic PWM/PFM (AUTO mode) operation gives high efficiency over a wide output current range for buck converters. The LP87702-Q1 uses remote voltage sensing to compensate IR drop between the converter output and the point-of-load, thus improving the accuracy of the output voltage.

Programmable start-up and shutdown sequences synchronized to the enable signal are supported, including general purpose digital outputs. During start-up and voltage change, the device controls the output slew rate for minimum output voltage overshoot and inrush current. This device contains one-time-programmable (OTP) memory. Each orderable part number has specific OTP settings for a given application. Details of the default OTP configuration for each orderable part number can be found in the technical reference manual.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

LP87702-Q1 VQFN (32) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

Buck Efficiency vs Output Current

(1)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 I2C Serial Bus Timing Parameters.......................... 12

6.7 Typical Characteristics............................................ 15

7 Detailed Description............................................ 16

7.1 Overview................................................................. 16

7.2 Functional Block Diagram....................................... 17

7.3 Feature Descriptions............................................... 17

7.4 Device Functional Modes ....................................... 40

7.5 Programming........................................................... 42

7.6 Register Maps......................................................... 45

8 Application and Implementation ........................ 81

8.1 Application Information............................................ 81

8.2 Typical Application.................................................. 81

9 Power Supply Recommendations...................... 90

10 Layout................................................................... 90

10.1 Layout Guidelines ................................................. 90

10.2 Layout Example .................................................... 91

11 Device and Documentation Support................. 92

11.1 Device Support...................................................... 92

11.2 Receiving Notification of Documentation Updates 92

11.3 Community Resources.......................................... 92

11.4 Trademarks........................................................... 92

11.5 Electrostatic Discharge Caution............................ 92

11.6 Glossary................................................................ 92

12 Mechanical, Packaging, and Orderable

Information........................................................... 92

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (July 2018) to Revision B Page

• Added FMEDA and Functional Safety Manual support availability feature............................................................................ 1

• Changed Description wording ................................................................................................................................................ 1

• Added cross reference to VANA

...................................................................................................................................... 5

OVP

• Added test condition .............................................................................................................................................................. 9

• Changed from typical value to max value ........................................................................................................................... 10

• Added comment on VANA

setting and it's impact on device input voltage range ......................................................... 16

OVP

• Added comment on minimum WDI pulse length .................................................................................................................. 26

• Changed BOOST_SC_INT bit set delay from immediate to 1 ms ...................................................................................... 37

• Changed multiple register bit descriptions............................................................................................................................ 45

Changes from Original (December 2017) to Revision A Page

• First release of production-data data sheet ........................................................................................................................... 1

Product Folder Links: LP87702-Q1

2 3 4 5 61 7

20 19 18 1723 2122

GPO0

NRST

VIN_B1

SW_B1

PGND_B1

SCL (EN2)

SDA (EN3)

CLK(GPO2)

PGND_B0

WD_RESET

VANA

AGND

FB_B1

FB_B0

SW_B0

VIN_B0

THERMAL PAD

SW_B1

26 15

PG0

VMON1

VMON2 PGND_BST

VOUT_BST

SW_BST

EN1

WDI

PG1 (GPO1)

nINT

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5 Pin Configuration and Functions

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

32-Pin VQFN With Thermal Pad

RHB Package

Top View

Product Folder Links: LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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Pin Functions

NUMBER NAME

1 nINT D/O Open-drain interrupt output. Active LOW. 2 FB_B0 A Output voltage feedback for Buck0. 3 FB_B1 A Output voltage feedback for Buck1. 4 AGND G Ground. 5 VANA P Supply voltage for analog and digital blocks. Must be connected to same node with VIN_Bx. 6 WD_RESET D/O Reset output from window watchdog 7 WDI D/I Digital input signal for window watchdog 8 VOUT_BST P/O Boost output. Bypass switch output when this mode is selected. 9 SW_BST P/I Boost input. Bypass switch input when this mode is selected. 10 PGND_BST P/G Power ground for boost. 11 NRST D/I Reset signal for the device. 12 GPO0 D/O General purpose digital output 0.

13, 14 VIN_B1 P/I 15, 16 SW_B1 P/O Buck1 switch node.

17, 18 PGND_B1 P/G Power Ground for Buck1. 19 EN1 D/I Programmable Enable 1 signal.

20 SCL D/I

21 SDA D/I/O

22 CLKIN D/I/O 23, 24 PGND_B0 P/G Power ground for Buck0.

25, 26 SW_B0 P/O Buck0 switch node. 27, 28 VIN_B0 P/I 29 PG0 D/O Programmable power-good indication signal.

30 VMON1 A/I Voltage monitoring input 1. 31 VMON2 A/I Voltage monitoring input 2.

32 PG1 D/O Thermal pad N/A G

A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin

TYPE DESCRIPTION

Input for Buck1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.

Serial interface clock input for I2C access. Connect a pullup resistor. Alternative function is programmable enable 2 signal.

Serial interface data input and output for I2C access. Connect a pullup resistor. Alternative function is programmable enable 3 signal.

External clock input. Alternative function is general purpose digital output 2 (GPO2). Second alternative function is watchdog disable (WD_DIS)

Input for Buck0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.

Programmable power-good indication signal. Alternative function is general purpose digital output 1 (GPO1).

Product Folder Links: LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

VIN_B0, VIN_B1, SW_BST, VANA

SW_B0, SW_B1 Voltage on buck switch nodes –0.3 (VIN_Bx + 0.3 V) with

FB_B0, FB_B1 Voltage on buck voltage sense nodes –0.3 (VANA + 0.3 V) with

VOUT_BST Voltage on boost output –0.3 6 V SCL (EN2), SDA

(EN3), VMON1, VMON2

NRST, EN1, nINT Voltage on logic pins (input or output pins) –0.3 6 V PG0, PG1 (GPO1),

GPO0, CLKIN (GPO2), WDI, WD_RESET

J-MAX

stg

Maximum lead temperature (soldering, 10 sec.) 260 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground.

Voltage on input power connections –0.3 6

Voltage on voltage monitoring pins –0.3 (VANA + 0.3 V) with

Voltage on logic pins (input or output pins) –0.3 (VANA + 0.3 V) with

Junction temperature −40 150 °C Storage temperature –65 150 °C

(1) (2)

MIN MAX UNIT

6-V max

6-V max V

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2

Charged-device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B

(1)

All pins ±500 Corner pins (1, 8, 9, 16,

17, 24, 25, 32)

±2000

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

INPUT VOLTAGE

VIN_B0, VIN_B1, SW_BST, VANA Voltage on input power connections. See also

VANA

OVP

. VMON1, VMON2 Voltage on voltage monitoring pins 0 5.5 NRST, EN1, EN2, EN3, nINT Voltage on logic pins (input or output pins) 0 5.5 PG0, PG1 (GPO1), GPO0, CLKIN

Voltage on logic pins (input or output pins)

(GPO2), WDI, WD_RESET

Voltage on I2C interface, Standard (100 kHz), Fast (400 kHz), Fast+ (1 MHz), and High-Speed (3.4

SCL, SDA

MHz) Modes Voltage on I2C interface, Standard (100 kHz), Fast

(400 kHz), and Fast+ (1 MHz) Modes

TEMPERATURE

Junction temperature –40 140 °C Ambient temperature –40 125 °C

2.8 5.5 V

0 VANA V

0 1.95 V

VANA with 3.6-V

max

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6.4 Thermal Information

(1)

R R R

θJA θJCtop θJB

JT JB

θJCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 31.7 °C/W Junction-to-case (top) thermal resistance 17.1 °C/W Junction-to-board thermal resistance 5.6 °C/W Junction-to-top characterization parameter 0.2 °C/W Junction-to-board characterization parameter 5.6 °C/W Junction-to-case (bottom) thermal resistance 1.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

RHB (VQFN)

32 PINS

UNIT

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EXTERNAL COMPONENTS

IN_BUCK

OUT_BUC

K_POL

Input filtering capacitance for buck converters

Output filtering capacitance for buck converters

Point-of-load (POL) capacitance for buck converters

Effective capacitance, connected from VIN_Bx to PGND_Bx

Effective total capacitance. Maximum includes POL capacitance

Optional POL capacitance 22 µF

Output filtering

OUT_BST

ESR

BUCK

capacitance for boost converter

Input and output

capacitor ESR Inductor for buck

converters

Effective capacitance 10 22 40 µF

[1-10] MHz 2 10 mΩ

Inductance of the inductor

Inductance of the inductor, 2-MHz switching 1

BST

Inductor for boost converters

Inductance of the inductor –30% 30%

DCR

Inductor DCR 25 mΩ

BUCK CONVERTERS

(VIN_Bx)

(VANA)

Input voltage range 2.8 3.3 5.5 V

Programmable voltage range 0.7 1 3.36 V

OUT_Bx

Output voltage

Step size, 0.7 V ≤ V

Step size, 1.4 V ≤ V Output current Output current 3.5 Minimum voltage

difference between V electrical characteristics

(VIN_Bx)

and V

OUT_Bx

for

(VIN_Bx)

– V

OUT,IOUT_Bx

– V

OUT,IOUT_Bx

< 0.73 V 10

OUT

< 1.4 V 5

OUT

≤ 3.36 V 20

OUT

≤ 2 A 0.8 > 2 A 1

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

1.9 10 µF

15 22 100 µF

0.47

–30% 30%

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

(3)

OUT

mVStep size, 0.73 V ≤ V

µH

µHInductance of the inductor, 4-MHz switching 1

(1) All voltage values are with respect to network ground. (2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. (3) The maximum output current can be limited by the forward current limit I

junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction

. The maximum output current is also limited by the

LIM FWD

temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.

Product Folder Links: LP87702-Q1

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Electrical Characteristics (continued)

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DC DC

LNR

LDR

LDSR

LNSR

DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature

Ripple voltage

DC line regulation I DC load regulation in

PWM mode Transient load step

response

Transient line response

Force PWM mode, V

PFM mode, V

voltage level is increased by max. 20 mV

PFM mode, V

voltage level is increased by max. 20 mV

PWM mode, V

OUT

= 22 + 22 µF (GCM31CR71A226KE02)

OUT

PFM mode, L = 0.47 µH, C

(GCM31CR71A226KE02)

= I

OUT

OUT(max)

mode, V

= 22 + 22 µF, L = 0.47 µH, fSW= 4 MHz

µs, I

= 1.0 V, I

OUT_Bx

= 0 A to 3 A, TR= TF= 1 µs, PWM

OUT

(VIN_Bx)

OUT

= 3.3V, V

VIN_Bx

stepping 3 V ↔ 3.5 V, TR= TF= 10

= I

OUT(max)

˂ 1.0 V –20 20 mV

OUT

≥ 1.0 V –2% 2%

OUT

˂ 1.0 V, the average output

≥ 1.0 V, the average output

= 1.2 V, fSW= 4 MHz,

= 22 + 22 µF

OUT

from 0 to I

OUT

= 1.2 V, C

OUT_Bx

Programmable range 1.5 4.5

LIM FWD

LIM NEG

DS(ON) BUCK HS FET

DS(ON) BUCK LS FET

Forward current limit for both bucks (peak for every switching cycle)

Negative current limit 1.6 2 3 A On-resistance, high-side

FET

On-resistance, low-side FET

Switching frequency, PWM mode

OTP programmable

Start-up time (soft start)

Step size 0.5 Accuracy, V Accuracy, 2.8 V ≤ V

(VIN_Bx)

≥ 3 V, I

(VIN_Bx)

= 4 A –5% 7.5% 20%

LIM

< 3 V, I

Each phase, between VIN_Bx and SW_Bx pins (I = 1.0 A)

Each phase, between SW_Bx and PGND_Bx pins (I = 1.0 A)

2-MHz setting or V

4-MHz setting and V From ENx to V

control begins)

OUT_Bx

< 0.8 V 1.8 2 2.2

OUT_Bx

≥ 0.8 V 2.7 3 3.3

OUT_Bx

≥ 1.1 V 3.6 4 4.4

OUT_Bx

= 0.35 V (slew-rate

Overshoot during startup

Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate Output voltage slew-

(4)

rate

SLEW_RATEx[2:0] = 010, V

SLEW_RATEx[2:0] = 011, V

SLEW_RATEx[2:0] = 100, V

SLEW_RATEx[2:0] = 101, V

SLEW_RATEx[2:0] = 110, V

SLEW_RATEx[2:0] = 111, V

VOUT_Bx

= V

VANA

OUT(max)

LIM

VIN_Bx

OUT

= 4 A –20% 7.5% 20%

≥ 0.7 V –15% 10 15% mV/µs

≥ 0.7 V –15% 7.5 15% mV/µs

≥ 0.7 V –15% 3.8 15% mV/µs

≥ 0.7 V –15% 1.9 15% mV/µs

≥ 0.7 V –15% 0.94 15% mV/µs

≥ 0.7 V –15% 0.47 15% mV/µs

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

–20 40 mV

–2% 2% + 20mV

±0.05 %/V

0.3%

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

OUT

±65 mV

±20 mV

60 110 mΩ

55 80 mΩ

MHz3-MHz setting and V

120 µs

50 mV

p-p

(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current. Applies when

internal oscillator is used.

Product Folder Links: LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

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Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

OUT

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PFM-PWM

PWM-PFM

PFM-to-PWM switch current threshold

PWM-to-PFM switch current threshold

(5)

Output pull-down resistance

520 mA

240 mA

Converter disabled 75 125 175 Ω

BOOST CONVERTER

IN_BST

Input voltage range for boost power inputs

Input voltage range when

2.8 3.3 4 V

4.5 5.5 V bypass switch mode selected

BOOST_VSET = 00 4.9

OUT_BST

Output voltage, boost mode

BOOST_VSET = 01 5.0 BOOST_VSET = 10 5.1

BOOST_VSET = 11 5.2

OUT_BST

LIM_BST

Output current Both boost and bypass mode 0.6 A Output current limit BOOST_ILIM = 00, V

BOOST_ILIM = 01, V BOOST_ILIM = 10, V BOOST_ILIM = 11, V

< 3.6 V 0.8 1 1.3 A

IN_BST

< 3.6 V 1.1 1.4 1.9

IN_BST

< 3.6 V 1.5 1.9 2.3

IN_BST

< 3.6 V 2.2 2.8 3.4

IN_BST

DC output voltage accuracy, includes

OUT_BST

_DC

voltage reference, DC load and line regulations, process and

Default output voltage –3% 3%

temperature. Boost mode

DROP

LDSR

SHORT

DS(ON) BST HS FET

DS(ON) BST LS FET

Voltage drop, bypass mode,

Ripple voltage, boost mode

DC load regulation,

LDR

boost mode Transient load step

response, boost mode Short circuit current

limitation

On-resistance, high-side FET

On-resistance, low-side FET

Switching frequency, boost mode

Start-up time, boost mode

Output pull-down resistance

Iout = 250 mA 83 mV

22 µF effective output capacitance 20 mV

= 1 mA to I

OUT

= 1 mA to 250 mA, TR= TF= 1 µs, 22

OUT

µF effective output capacitance, VIN > 3 V

OUT(max)

–220 220 mV

0.3%

During start-up, both boost and bypass mode. Short circuit current limit applies until V

OUT_BST

= V

IN_BST

Pin-to-pin, between SW_BST and VOUT_BST pins (I = 250 mA)

Pin-to-pin, between SW_BST and PGND_BST pins (I = 250 mA)

625 mA

145 220 mΩ

90 175 mΩ

2-MHz setting 1.8 2 2.2 MHz 4-MHz setting 3.6 4 4.4 MHz From enable to boost VOUT within 3% of

target value. C

OUT_BST

= 22 µF

450 µs

Converter disabled 135 Ω

(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and

the inductor current level.

p-p

Product Folder Links: LP87702-Q1

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Electrical Characteristics (continued)

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EXTERNAL CLOCK AND PLL

Nominal frequency 1 24

External input clock

(6)

Nominal frequency step size 1 Required accuracy from nominal frequency –30% 10% Delay for detecting loss of external clock,

External clock detection

nominal internal clock, clock accuracy ±10% Delay for detecting valid external clock,

nominal internal clock, clock accuracy ±10%

Clock change delay (internal to external)

Delay from valid clock detection to use of external clock

PLL output clock jitter Cycle to cycle 300 ps, p-p

MONITORING FUNCTIONS

Voltage threshold, VANA_THRESHOLD = 0 3.3

Voltage threshold, VANA_THRESHOLD = 1 5.0 VANA Voltage Monitoring

Voltage window, VANA_WINDOW = 00 +/-3% +/-4% +/-5%

Voltage window, VANA_WINDOW = 01 +/-4% +/-5% +/-6%

Voltage window, VANA_WINDOW = 10 or 11 +/-9% +/-10% +/-11%

VMONx_THRESHOLD = 000 0.65

VMONx_THRESHOLD = 001 0.8

VMONx_THRESHOLD = 010 1.0 VMON1 and VMON2

Voltage Monitoring Thresholds

VMONx_THRESHOLD = 011 1.1

VMONx_THRESHOLD = 100 1.2

VMONx_THRESHOLD = 101 1.3

VMONx_THRESHOLD = 110 1.8

VMONx_THRESHOLD = 111 1.8

VMONx_WINDOW = 00,

VMONx_THRESHOLD from 000 to 111

VMON1 and VMON2 Voltage Monitoring Windows

VMONx_WINDOW = 01,

VMONx_THRESHOLD from 000 to 111

VMONx_WINDOW = 10,

VMONx_THRESHOLD from 000 to 111

VMONx_WINDOW = 11,

VMONx_THRESHOLD from 000 to 111

BUCKx_WINDOW = 00 +/-20 +/-30 +/-40 Buck0 and Buck1

Voltage Monitoring Windows

BUCKx_WINDOW = 01 +/-37 +/-50 +/-63

BUCKx_WINDOW = 10 +/-57 +/-70 +/-83

BUCKx_WINDOW = 11 +/-77 +/-90 +/-103

BOOST_WINDOW = 00 +/-0.6% +/-2% +/-3.4%

Boost Voltage Monitoring

BOOST_WINDOW = 01 +/-2.6% +/-4% +/-5.4%

BOOST_WINDOW = 10 +/-4.6% +/-6% +/-7.4%

BOOST_WINDOW = 11 +/-6.6% +/-8% +/-9.4%

Deglitch time

VANA, VMONx and BOOST monitoring 12 17

BUCKx monitoring 6 9

PROTECTION FUNCTIONS

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

600 µs

+/-1% +/-2% +/-3%

+/-2% +/-3% +/-4%

+/-3% +/-4% +/-5%

+/-5% +/-6% +/-7%

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

1.8

OUT

MHz

µs

μs

(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.

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Electrical Characteristics (continued)

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Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Temperature rising, TDIE_WARN_LEVEL =

0 Thermal warning

Hysteresis 20

Thermal shutdown

Temperature rising 140 150 160

Hysteresis 20

Voltage rising, VANA_OVP_SEL = 0 5.6 5.8 6.1

Voltage falling, VANA_OVP_SEL = 0 5.45 5.73 5.96

VANA

VANA Overvoltage

OVP

Voltage rising, VANA_OVP_SEL = 1 4.1 4.3 4.6

Voltage falling, VANA_OVP_SEL = 1 3.95 4.23 4.46

Hysteresis 40 200 mV

VANA

VANA Undervoltage

UVL

Lockout BUCKx short circuit

Voltage rising 2.51 2.63 2.75

Voltage falling 2.5 2.6 2.7

Threshold 0.32 0.35 0.45 V detection

Bypass short circuit current limit

LOAD CURRENT MEASUREMENT FOR BUCK CONVERTERS

Current measurement range

Current corresponding to maximum output

code (note: maximum current for LP87702

buck is 3.5A) Resolution LSB 20 mA Measurement accuracy I

> 1A <10%

OUT

Auto mode (automatically changing to PWM Measurement time

mode for the measurement)

PWM mode 25

CURRENT CONSUMPTION

Shutdown current

NRST = 0 1 µA consumption

Standby current consumption, converters

NRST = 1 9 µA disabled

Active current consumption, one buck converter enabled in Auto mode, internal RC

= 0 mA, not switching 55 µA

OUT_Bx

oscillator Active current

consumption, two buck converters enabled in Auto mode, internal RC

= 0 mA, not switching 90 µA

OUT_Bx

oscillator Active current

consumption during PWM operation, one

= 0 mA 15 mA

OUT_Bx

buck converter enabled Active current

consumption during PWM operation, two

= 0 mA 27 mA

OUT_Bx

buck converters enabled

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

115 125 135

130 140 150

VIN_Bx

OUT_BST

, V

VOUT_Bx

, V

VOUT_BST

= 5 V and V

270 420 mA

, and I

= 1 V,

OUT_Bx

10.22 A

OUT

°CTemperature rising, TDIE_WARN_LEVEL =

°C

µs

Product Folder Links: LP87702-Q1

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Electrical Characteristics (continued)

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Active current consumption, Boost converter in PWM

OUT_BST

= 0 mA, fSW= 4 MHz 18 mA operation PLL and clock detector

current consumption

Additional current consumption when enabled, 2 MHz external clock

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

VOUT_Bx

= 5 V and V

, V

VOUT_BST

OUT_Bx

, and I

= 1 V,

OUT

2 mA

Product Folder Links: LP87702-Q1

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Electrical Characteristics (continued)

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Limits apply over the junction temperature range –40°C ≤ TJ≤ 140°C, specified V range, unless otherwise noted. Typical values are at TA= 25°C, V unless otherwise noted.

(1) (2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUT SIGNALS SCL, SDA, NRST, EN1, EN2, EN3, CLKIN, WDI

HYS

Input low level 0.4 Input high level 1.2 Hysteresis of Schmitt

Trigger inputs ENx, CLKIN, WDI pull-

down resistance NRST pull-down

resistance

ENx_PD = 1, CLKIN_PD = 1, WDI_PD = 1 500 kΩ

Always enabled 500 kΩ

DIGITAL OUTPUT SIGNALS nINT, SDA

Output low level

External pull-up resistor for nINT

SDA: I nINT: I

To VIO Supply 10 kΩ

= 20 mA 0.5

SOURCE

= 2 mA 0.4

SOURCE

DIGITAL OUTPUT SIGNALS PGOOD, PG1, GPO0, GPO1, GPO2, WD_RESET

Output low level I Output high level,

configured to push-pull

= 2 mA 0.4

SOURCE

= 2 mA V

SINK

Supply voltage for

external pull-up resistor, configured to open-drain

External pull-up resistor, configured to open-drain

ALL DIGITAL INPUTS

All logic inputs except NRST, over pin

LEAK

Input current

voltage range, when PD not enabled NRST, over pin voltage range. Other logic

inputs when PD enabled.

VANA

= V

VIN_Bx

, V

VANA

= 3.3 V, V

VIN_Bx

OUT_BST

, V

10 80 200 mV

- 0.4 V

VANA

−1 1 µA –1 20 µA

, V

VOUT_Bx

= 5 V and V

VOUT_BST

OUT_Bx

10 kΩ

VANA

, and I

= 1 V,

OUT

6.6 I2C Serial Bus Timing Parameters

(1)

See

. MIN MAX UNIT

Standard mode 100 Fast mode 400

SCL

LOW

(1) Cbrefers to the capacitance of one bus line. Cbis expressed in pF units. 12

Serial clock frequency

Fast mode + 1

High-speed mode, Cb= 400 pF 1.7 Standard mode 4.7

SCL low time

Fast mode + 0.5 High-speed mode, Cb= 100 pF 160 High-speed mode, Cb= 400 pF 320

Product Folder Links: LP87702-Q1

kHz

MHzHigh-speed mode, Cb= 100 pF 3.4

µsFast mode 1.3

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I2C Serial Bus Timing Parameters (continued)

(1)

See

. MIN MAX UNIT

Standard mode 4

HIGH

SU;DAT

HD;DAT

SU;STA

HD;STA

BUF

SU;STO

rDA

fDA

rCL

SCL high time

Data setup time

Data hold time

Setup time for a start or a repeated start condition

Hold time for a start or a repeated start condition

Bus free time between a stop and start condition

Setup time for a stop condition

Rise time of SDA signal

Fall time of SDA signal

Rise time of SCL signal

Fast mode + 0.26 High-speed mode, Cb= 100 pF 60 High-speed mode, Cb= 400 pF 120 Standard mode 250 Fast mode 100 Fast mode + 50 High-speed mode 10 Standard mode 0.01 3.45

Fast mode + 0.01 High-speed mode, Cb= 100 pF 10 70 High-speed mode, Cb= 400 pF 10 150 Standard mode 4.7

Fast mode + 0.26 High-speed mode 160 ns Standard mode 4

Fast mode + 0.26 High-speed mode 160 ns Standard Mode 4.7

Fast mode + 0.5 Standard Mode 4

Fast mode + 0.26 High-speed mode 160 ns Standard mode 1000 Fast mode 20+0.1 C Fast mode + 120 High-speed mode, Cb= 100 pF 10 80 High-speed mode, Cb= 400 pF 20 160 Standard mode 250 Fast mode 20+0.1 C Fast mode + 20+0.1 C High-speed mode, Cb= 100 pF 10 80 High-speed mode, Cb= 400 pF 20 160 Standard mode 1000 Fast mode 20+0.1 C Fast mode + 120 High-speed mode, Cb= 100 pF 10 40 High-speed mode, Cb= 400 pF 20 80

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

µsFast mode 0.6

µsFast mode 0.01 0.9

µsFast mode 0.6

µsFast Mode 1.3

µsFast Mode 0.6

b b

300

250 120

300

Product Folder Links: LP87702-Q1

SCL

SDA

LOW

rCL

HD;DAT

HIGH

fCL

SU;DAT

SU;STA

SU;STO

START

REPEATED

START

STOP

HD;STA

START

rDA

BUF

fDA

HD;STA

RS P

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

I2C Serial Bus Timing Parameters (continued)

(1)

See

. MIN MAX UNIT

Standard mode 1000 Fast mode 20+0.1 C Fast mode + 120 High-speed mode, Cb= 100 pF 10 80 High-speed mode, Cb= 400 pF 20 160 Standard mode 300 Fast mode 20+0.1 C Fast mode + 20+0.1 C High-speed mode, Cb= 100 pF 10 40 High-speed mode, Cb= 400 pF 20 80

Fast mode, Fast mode + 50

High-speed mode 10

rCL1

fCL

Rise time of SCL signal after a repeated start condition and after an acknowledge bit

Fall time of a SCL signal

Capacitive load for each bus line (SCL and SDA)

Pulse width of spike suppressed (Spikes shorter than indicated width are suppressed)

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300

b b

300 120

400 pF

Figure 1. I2C Timing

Product Folder Links: LP87702-Q1

Input Voltage (V)

Input Current (mA)

2.8 3 3.2 3.4 3.6 3.8 4

D014

OUT

= 5.0 V Load = 0 mA

Input Voltage (V)

Input Current (µA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

D013

OUT

= 1.2 V Load = 0 mA

Input Voltage (V)

Input Current (mA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

D012

OUT

= 1.2 V Load = 0 mA

Input Voltage (V)

Input Current (µA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

0.5

1.5

2.5

3.5

D016

(NRST)

= 0 V

Input Voltage (V)

Input Current (µA)

2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5

D015

(NRST)

= 1.8 V Regulators disabled

LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

6.7 Typical Characteristics

Unless otherwise specified: VIN= 3.3 V, TA= 25°C, ƒSW-setting 4 MHz, L0 = L1 = 0.47 µH (TOKO DFE252012PD-R47M), L2 = 1 µH (TFM252012ALMA1R0), C

OUT_BUCK

using connections in the Figure 81.

Figure 2. Shutdown Current Consumption vs Input Voltage Figure 3. Standby Current Consumption vs Input Voltage

= 22 µF, and C

POL_BUCK

= 22 µF, C

OUT_BOOST

= 22 µF. Measurements are done

Figure 4. Active State Current Consumption vs Input

Voltage, One Buck Converter Enabled in PFM Mode

Figure 6. Active State Current Consumption vs Input Voltage, Boost Converter Enabled in PWM Mode

Figure 5. Active State Current Consumption vs Input Voltage, One Buck Converter Enabled in PWM Mode

Product Folder Links: LP87702-Q1

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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7 Detailed Description

7.1 Overview

The LP87702-Q1 is a high-efficiency, high-performance power supply IC with two step-down DC/DC converters (Buck0 and Buck1) and boost converter for automotive and industrial applications. Input voltage range is from 2.8 V to 5.5 V. Typical application input voltage levels are 3.3 V and 5 V. With 3.3V input and boost enabled, VANA to 5.8 V (typ). VANA output characteristics of the various converters. Boost has an alternate bypass switch mode. Selection between boost and bypass modes is defined in OTP and is fixed.

is set to 4.3V (typ). When input voltage is 5 V, boost can be used as a load switch and VANA

OVP

is selected in OTP by VANA_OVP_SEL and is a fixed factory setting. Table 1 lists the

OVP

Table 1. Supply Specification

SUPPLY

Boost 4.9 to 5.2 100 600

Buck0 0.7 to 3.36

Buck1 0.7 to 3.36

RANGE (V) RESOLUTION (mV) I

OUT

10 (0.7 V to 0.73 V)

5 (0.73 V to 1.4 V)

20 (1.4 V to 3.36 V) 10 (0.7 V to 0.73 V)

5 (0.73 V to 1.4 V)

20 (1.4 V to 3.36 V)

OUTPUT

MAXIMUM OUTPUT CURRENT (mA)

MAX

3500

OVP

is set

The LP87702-Q1 converters support switching clock synchronization to an external clock connected to CLKIN input. The external clock can be from 1 MHz to 24 MHz with 1-MHz steps. Alternatively, optional spread spectrum mode can be enabled to reduce EMI.

LP87702-Q1 features include diagnostics, monitoring and protections for both device internal and system level operation:

• Soft start

• Input undervoltage lockout

• Programmable undervoltage or window (over- and undervoltage) monitoring for the input (from VANA pin)

• Programmable undervoltage or window (over- and undervoltage) monitoring for the buck and boost converter outputs

• Two inputs (VMONx) with programmable undervoltage or window (over- and undervoltage) thresholds, for monitoring external rails in the system

• One dedicated power-good output (PG0) to which selected monitoring signals can be combined

• Second programmable power-good output (PG1), multiplexed with general purpose output (GPO1)

• Power good flags with maskable interrupt

• Programmable window watchdog

• Buck and boost converter overload detection

• Thermal warning with two selectable thresholds

• Thermal shutdown

LP87702-Q1 control interface:

• Up to three enable inputs ( EN1, EN2 and EN3) with programmable power-up/power-down sequence control

• Optional I2C (multiplexed with EN2 and EN3 inputs)

• Interrupt signal (nINT) to host

• Reset input (NRST)

• One dedicated general purpose output (GPO0)

• Watchdog disable WD_DIS, multiplexed with CLKIN/GPO2

Product Folder Links: LP87702-Q1

Diagnostics

UVLO

Reset

Digital

Logic

Registers

I2C

Enable/

Disable,

Delay

Control

Slew-Rate

Control

Interrupts

nINT

SDA / EN3

SCL / EN2

EN1

VANA

OTP

EPROM

Thermal

Monitor

Oscillator

Buck0

ILIM Det

Pwrgood

Det

Overload

and SC

Det

Buck1

Boost

ILIM Det Pwrgood

Det

Overload

and SC Det

ILIM Det

Pwrgood Det

Overload and

SC Det

Ref &

Bias

Iload ADC

CLKIN / GPO2/ WD_DIS

GPO0

Ref &

Bias

PG0

PG1/ GPO1

VMON1

VMON2

Window

Watchdog

WD_RESET

WDI

NRST

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7.2 Functional Block Diagram

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

7.3 Feature Descriptions

7.3.1 Step-Down DC/DC Converters

7.3.1.1 Overview

The LP87702-Q1 includes two high-efficiency step-down DC/DC converters. The buck converters deliver 0.7-V to

3.36-V regulated voltage rails from 2.8-V to 5.5-V input-supply voltage. The converters are designed for flexibility;

most of the functions are programmable, thus optimizing the converter operation for each application:

• DVS support with programmable slew rate

• Automatic mode control based on the loading (PWM or PFM mode)

• Forced PWM mode option

• Optional external clock input to minimize crosstalk

• Optional spread spectrum technique to reduce EMI

• Synchronous rectification

• Current mode loop with PI compensator

• Soft start

• Programmable output voltage monitoring with maskable interrupt and selectable connection PG0 and/or PG1

• Average output current sensing (for PFM entry and load current measurement)

Product Folder Links: LP87702-Q1

POWER GOOD

LOOP COMP

RAMP

GENERATOR

HS FET

CURRENT

SENSE

LS FET

CURRENT

SENSE

GATE

CONTROL

IADC

VDAC

ERROR

AMP

GND

NEG

CURRENT

LIMIT

ZERO

CROSS

DETECT

POS

CURRENT

LIMIT

VIN

OUT

CONTROL

BLOCK

PROGRAMMABLE

PARAMETERS

VOLTAGE

SETTING

SLEW RATE

CONTROL

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

www.ti.com

Feature Descriptions (continued)

Some of the key parameters that can be programmed via registers (with default values set by OTP bits):

• Output voltage

• Forced PWM operation

• Switch current limit

• Output voltage slew rate

• Enable and disable delays with ENx pin control

There are two modes of operation for the buck converters, depending on the output current required: pulse width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 520 mA or higher. Lighter output current loads will cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load currents. When buck is disabled, buck output is isolated from the input voltage rail. Output has an optional pulldown resistor.

A block diagram of a single buck converter is shown in Figure 7.

Figure 7. Detailed Block Diagram Showing One Buck Converter

7.3.1.2 Transition Between PWM and PFM Modes

The LP87702-Q1 buck converter operates in PWM mode at load current of about 520 mA or higher. At lighter load current levels the device automatically switches into PFM mode for reduced current consumption when forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the PWM modes a high efficiency is achieved over a wide output-load current range.

7.3.1.3 Buck Converter Load Current Measurement

Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the LOAD_CURRENT_BUCK_SELECT bit in SEL_I_LOAD register. A write to this selection register starts a current measurement sequence. The converter is forced to PWM mode during the measurement. The measurement sequence is 50 µs long at maximum. LP87702-Q1 can be configured to give out an I_MEAS_INT interrupt in INT_TOP_1 register after the load current measurement sequence is finished. Load current measurement interrupt can be masked with I_MEAS_MASK bit in TOP_MASK_1 register. The measurement result can be read from I_LOAD_1 and I_LOAD_2 registers. The Buck converter load current measurement result is 9-bit wide, with 8 LSB bits stored in I_LOAD_1 register and 1 MSB bit stored in I_LOAD_2 register. The single bit resolution is 20 mA, with a maximum load current value of 10.22A.

Product Folder Links: LP87702-Q1

LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Feature Descriptions (continued)

7.3.2 Boost Converter

The LP87702-Q1 device integrates a boost converter with programmable output voltage from 4.9V to 5.2V in

0.1V steps, and input voltage range from 2.8V to 4V. The boost converter has flexibility to support wide range of

application conditions:

• Forced PWM operation

• Optional external clock input to minimize crosstalk

• Optional spread spectrum technique to reduce EMI

• Synchronous rectification

• Current mode loop with PI compensator

• Soft start

• Programmable output voltage monitoring with maskable interrupt and selectable connection to PG0 and/or PG1

Following parameters can be programmed via registers, with default values set by OTP bits unless otherwise noted:

• Output voltage level (BOOST_VSET)

• Switch current limit (BOOST_ILIM)

• Enable and disable delays when ENx pin control is used (BOOST_DELAY register)

• Output pulldown resistor enable/disable when boost is disabled (BOOST_RDIS_EN bit, discharge is enabled by default)

• Output voltage monitoring enable/disable and monitoring window thresholds

The boost converter operates in forced PWM mode with fixed switching frequency across all load currents. When boost is disabled, boost output is isolated from the input voltage rail.

Boost converter supports an alternative operating mode as a bypass/load switch, with input voltage range from

4.5V to 5.5V. Operating mode is selected in OTP and is fixed, changing the mode on-the-fly is not supported.

7.3.3 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add EMI-filters and shields to the boards. The LP87702-Q1 device supports spread-spectrum switching frequency modulation mode that is register controlled. This mode minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies between 0.85 × fSWand fSW, where fSWis switching frequency selected in the OTP. Spread spectrum modulation reduces conducted and radiated emissions by the converter and associated passive components and PCB traces (see Figure 8). This feature is available only when internal RC oscillator is used (EN_PLL is 0 in PLL_CTRL register) and it is enabled with the EN_SPREAD_SPEC bit in CONFIG register, and it affects both buck converters and the boost converter.

Product Folder Links: LP87702-Q1

24 MHz

Oscillator

CLKIN

Divider

´(;7_CLK

_)5(4´

PLL

Divider

CLKIN

Detector

Clock Select

Logic

Internal

24 MHz

clock

1 MHz

´(1_3//´

24 MHz

Power Spectrum is

Spread and Lowered

Frequency

Radiated Energy

LP87702-Q1

SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Feature Descriptions (continued)

Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread spectrum architecture of the LP87702-Q1 spreads that energy over a large bandwidth.

Figure 8. Spread Spectrum Modulation

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7.3.4 Sync Clock Functionality

The LP87702-Q1 device contains a CLKIN input to synchronize buck and boost converters' switching clock with the external clock. The block diagram of the clocking and PLL module is shown in Figure 9. Depending on the EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL register and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) for valid clock detection.

The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases the external clock is expected but it is not available. These cases are Startup (Read OTP-to-standby transition) when EN_PLL = 1 and buck or boost converter is enabled (standby-to-active transition) when EN_PLL = 1.

Figure 9. Clock and PLL Module

Product Folder Links: LP87702-Q1

LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

Feature Descriptions (continued)

Table 2. PLL Operation

DEVICE

OPERATION MODE

STANDBY 0 Disabled No Internal RC

ACTIVE 0 Disabled No Internal RC

STANDBY 1 Enabled

ACTIVE 1 Enabled

EN_PLL

7.3.5 Power-Up

The power-up sequence for the LP87702-Q1 is as follows:

• VANA (and VIN_Bx) reach minimum recommended levels (V

• Driving NRST input high initiates OTP read and enables the system I/O interface. Minimum delay from NRST reset input rising edge to I2C write or read access is 1.2ms.

• Device enters STANDBY mode. Watchdog operation starts.

• The host can change the default register setting by I2C if needed.

• The converters can be enabled/disabled and the GPOx signals can be controlled by ENx pins and by I2C interface.

PLL AND CLOCK

DETECTOR STATE

INTERRUPT FOR

EXTERNAL CLOCK

When external clock

disappears or appears

When external clock

disappears or appears

> VANA

VANA

UVLO

CLOCK

Automatic change to internal

RC oscillator when External

clock is not available

Automatic change to internal

RC oscillator when External

clock is not available

7.3.6 Buck and Boost Control

7.3.6.1 Enabling and Disabling Converters

The buck converters can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable and disable the buck converters:

• Using BUCKx_EN bit in BUCKx_CTRL_1 register (BUCKx_EN_PIN_CTRL bit is 00 in BUCKx_CTRL_1 register)

• Using ENx control pin (BUCKx_EN bit is 1 in BUCKx_CTRL_1 register AND BUCKx_EN_PIN_CTRL bit is not 00 in BUCKx_CTRL_1 register)

Similarly there are two ways to enable and disable the boost converter:

• Using BOOST_EN bit in BOOST_CTRL register (BOOST_EN_PIN_CTRL bit is 0 in BOOST_CTRL register)

• Using ENx control pin (BOOST_EN bit is 1 in BOOST_CTRL register AND BOOST_EN_PIN_CTRL bit is not 00 in BOOST_CTRL register)

If the ENx control pin is used to enable and disable then the delay from the control signal rising edge to start-up is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_STARTUP_DELAY[3:0] bits in BOOST_DELAY register. The delay from falling edge of control signal to shutdown is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and BOOST_SHUTDOWN_DELAY[3:0] bits in BOOST_DELAY register. The delays are valid only when ENx pin control is used, not when converters are enabled by I2C write to BUCKx_EN and BOOST_EN bits.

The control of the converters (with 0-ms delays) is shown in Table 3.

Product Folder Links: LP87702-Q1

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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Table 3. Converter Control

BUCKx_EN_PIN_C

TRL /

BOOST_EN_PIN_C

TRL

0 Don't Care Don't Care Don't Care Don't Care Disabled 1 00 Don't Care Don't Care Don't Care BUCKx_VSET[7:0] / BOOST_VSET[1:0]

1 01 Low Don't Care Don't Care Disabled 1 01 High Don't Care Don'tCare BUCKx_VSET[7:0] / BOOST_VSET[1:0] 1 10 Don't Care Low Don't Care Disabled 1 10 Don't Care High Don't Care BUCKx_VSET[7:0] / BOOST_VSET[1:0] 1 11 Don't Care Don't Care Low Disabled 1 11 Don't Care Don't Care High BUCKx_VSET[7:0] / BOOST_VSET[1:0]

EN1 PIN EN2 PIN EN3 PIN

BUCKx OUTPUT VOLTAGE /

BOOST OUTPUT VOLTAGE

Enable/disable control

with

BUCKx_EN/BOOST_EN

bit

Enable/disable control

with EN1 pin

Enable/disable control

with EN2 pin

Enable/disable control

with EN3 pin

BUCKx_EN /

BOOST_EN

BUCKx converter is enabled by an ENx pin or by I2C write access as shown in Figure 10. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is typically 30 mV/μsec during soft start. When the output voltage rises to 0.35-V level, the output voltage becomes slew-rate controlled. If there is a short circuit at the output and the output voltage does not increase above a 0.35-V level in 1 ms, the converter is disabled, and interrupt is set. When the output voltage rises above the undervoltage power-good threshold level the BUCKx_PG_INT interrupt flag in INT_BUCK register is set.

Power-good thresholds are defined by BUCKx_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL register sets the detection method for the valid buck output voltage, either undervoltage detection or undervoltage and overvoltage detection. The powergood interrupt flag when reaching valid output voltage can be masked using BUCKx_PGR_MASK bit in BUCK_MASK register. The power-good interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK register. When window monitoring (under and overvoltage monitoring) is selected, mask bits apply when voltage is crossing either threshold. A BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage; '1' means valid, and '0' means invalid output voltage.

Product Folder Links: LP87702-Q1

0.6V

Enable

Time

Voltage

Soft start

Ramp

BUCKx_SLEW_RATE[2:0]

Resistive pull-down

(if enabled)

BUCKx_VSET[7:0]

INT_BUCK(BUCKx_PG_INT)

nINT

BUCK_STATUS(BUCKx_PG_STAT)

0.35V

Voltage decrease because of load

BUCK_STATUS(BUCKx_STAT)

BUCK_MASK(BUCKx_PGF_MASK) = 0

BUCK_MASK(BUCKx_PGR_MASK) = 0

Host clears

interrupts

Powergood

interrupts

00 1

0 1

10 0 1 0 1 0 1 0

BUCKx_WINDOW[1:0]

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The boost converter is enabled by an ENx pin or by I2C write access as shown in Figure 11. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is less than 100 mV/μsec during soft start. If there is a short circuit at the output and the output voltage does not reach input voltage level in 1 ms, the converter is disabled, and interrupt is set. When the output voltage reaches the power-good threshold level the BOOST_PG_INT interrupt flag in INT_BOOST register is set.

Power-good thresholds are defined by BOOST_WINDOW bits. A PGOOD_WINDOW bit in PGOOD_CTRL register sets the detection method for the valid boost output voltage, either undervoltage detection or undervoltage and overvoltage detection. The power-good interrupt flag when reaching valid output voltage can be masked using BOOST_PGR_MASK bit in BOOST_MASK register. The power-good interrupt flag can be also generated when the output voltage becomes invalid. The interrupt mask for invalid output voltage detection is set by BOOST_PGF_MASK bit in BOOST_MASK register. A BOOST_PG_STAT bit in BOOST_STAT register shows always the validity of the output voltage; '1' means valid and '0' means invalid output voltage.

The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default and host can disable those with ENx_PD bits in CONFIG register.

Figure 10. Buck Converter Enable and Disable

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Enable

Time

Voltage

Resistive pull-down

(if enabled)

BOOST_VSET[1:0]

INT_BOOST(BOOST_PG_INT)

nINT

Host clears

interrupts

Powergood

interrupts

BOOST_STATUS(BOOST_PG_STAT)

00 1

Voltage decrease because of load

BOOST_STATUS(BOOST_STAT)

00 1

0 1

10 0 1 0 1 0

BOOST_MASK(BOOST_PGF_MASK) = 0

BOOST_MASK(BOOST_PGR_MASK) = 0

1 0

BOOST_WINDOW[1:0]

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7.3.6.2 Changing Buck Output Voltage

The output voltage of BUCKx converter can be changed by writing to the BUCKx_VOUT register. The voltage change for buck converter is always slew-rate controlled, and the slew-rate is defined by the BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by load current, and the BUCKx_FPWM bit.

The voltage change and power-good interrupts are shown in Figure 12.

Figure 11. Boost Converter Enable and Disable

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Time

Voltage

Ramp for Buck

BUCKx_CTRL2(BUCKx_SLEW_RATE[2:0])

BUCKx_VSET

INT_BUCK(BUCKx_PG_INT)

nINT

Host clears

interrupt

Powergood

interrupt

Powergood

BUCK_STATUS(BUCKx_STAT)

Powergood

BUCK_STATUS(BUCKx_PG_STAT)

Host clears

interrupt

Powergood

interrupt

1 0 1 0 1

0 1 0 1 0

BUCK_MASK(BUCKx_PGF_MASK)=0

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7.3.7 Enable and Disable Sequences

The LP87702-Q1 device supports programmable start-up and shutdown sequencing. An enable control signal is used to initiate the start-up sequence and to turn off the device according to the programmed shutdown sequence. Up to three enable inputs are available: EN1 is a dedicated enable input and EN2, EN3 are multiplexed with I2C interface. The buck converter is selected for sequence control with:

• BUCKx_CTRL_1(BUCKx_EN) = 1

• BUCKx_CTRL_1(BUCKx_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively

• BUCKx_VOUT.(BUCKx_VSET[7:0]) = Required voltage when EN pin is high

• The delay from rising edge of EN pin to the converter enable is set by BUCKx_DELAY(BUCKx_STARTUP_DELAY[3:0]) bits and

• The delay from falling edge of EN pin to the converter disable is set by BUCKx_DELAY(BUCKx_SHUTDOWN_DELAY[3:0])

In the same way the boost converter is selected for delayed control with:

• BOOST_CTRL(BOOST_EN) = 1

• BOOST_CTRL(BOOST_EN_PIN_CTRL) = 0x1 or 0x2 or 0x3, for EN1 or EN2 or EN3 control, respectively

• BOOST_CTRL(BOOST_VSET[2:0]) = Required voltage when EN pin is high

• The delay from rising edge of EN pin to the converter enable is set by BOOST_DELAY(BOOST_STARTUP_DELAY[3:0]) bits and

• The delay from falling edge of EN pin to the converter disable is set by BOOST_DELAY(BOOST_SHUTDOWN_DELAY[3:0])

Figure 12. Buck Output Voltage Change

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ENx

Internal

ENx

1 ms

3 ms

Internal

1 ms

4 ms

3 ms

1 ms

4 ms

Typical sequence

Sequence with short EN low and high periods

Startup cntr

Shutdown cntr

0 0 1

0 1 2 3 4 5 6 0

0 1 2 0 1 2 3 4 5

Internal

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SNVSAL1B –DECEMBER 2017–REVISED JULY 2019

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An example of start-up and shutdown sequences for buck converters are shown in Figure 13. The start-up and shutdown delays for Buck0 converter are 1 ms and 4 ms and for Buck1 converter 3 ms and 1 ms. The delay settings are used only for enable/disable control with EN signal.

Figure 13. Start-up and Shutdown Sequencing Example

7.3.8 Window Watchdog

Operation of the LP87702-Q1 watchdog is shown in Figure 14 for an example when ENx pin is used for controlling power sequence and ENx pin is active.

WDI is the watchdog function input pin and WD_RESET is the reset output . WDI pin needs to be pulsed within a certain timing window to avoid watchdog expiration. Minimum pulse width is 100 µs. Watchdog expiration always causes a reset pulse at WD_RESET output, otherwise device behavior after watchdog expiration is programmable. WD_RESET output polarity and mode, push-pull or open drain, are also programmable.

Watchdog default settings are read from OTP during device start-up. Default settings in WD_CTRL_1 and WD_CTRL_2 register can be over-written via I2C (as long as WD_LOCK bit is not set to 1). Writing WD_LOCK = 1 in WD_CTRL_2 register locks watchdog settings until NRST input is driven low, power cycle or register reset by SW_RESET.

Long open, close and open window periods are independently programmable as shown in Table 4. When long open or open window expires before WDI input is received, watchdog enters WD Reset state. Also when WDI is received during close window, watchdog enters WD Reset. Long open period can be extended by a I2C write to WD_CTRL_1 or WD_CTRL_2 register; register access initializes the long open counter and the long open period restarts (except in Stop mode).

LP87702-Q1 behavior after WD expiration is programmable :

• When WD_RESET_CNTR_SEL = 00, system restart is disabled and converters are maintained ON. WD_RESET pin is active for 10 ms. Watchdog returns to Long Open mode.

• When WD_RESET_CNTR_SEL = 01 (restart after first reset pulse), LP87702-Q1 performs shutdown

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sequence followed by start-up sequence so the converters are disabled and re-enabled according to the OTP programmed sequences. During start-up, device reloads OTP defaults when WD_EN_OTP_READ = 1. Settings valid before shutdown are maintained when WD_EN_OTP_READ = 0. WD_RESET output pin is active for a period of (10 ms + maximum shutdown delay). Maximum shutdown delay can be selected as 7.5 ms (SHUTDOWN_DELAY_SEL = 0) or 15 ms (SHUTDOWN_DELAY_SEL = 1). After the restart watchdog returns to Long Open mode.

• Status bit WD_SYSTEM_RESTART_FLAG is set to indicate that system restart has happened. Status can be cleared by writing "1" to WD_CLR_SYSTEM_RESTART_FLAG. WD_RESET_CNTR_SEL can be set to 10 or 11 to select restart after 2 or 4 WD expirations, respectively. Current status of reset counter is available in WD_RESET_CNTR_STATUS. Reset counter can be cleared by writing WD_CLR_RESET_CNTR to 1.

• Watchdog can also be programmed to perform shutdown sequence and enter STOP mode after the first WD expiration. In STOP mode converters are OFF. WD_RESET output pin is activated for a period of (10 ms + maximum shutdown delay), in STOP mode WD_RESET is inactive. NRST, power cycle, register reset SW_RESET, writing WD_CLR_SYSTEM_RESTART_FLAG = 1 or writing WD_SYSTEM_RESTART_FLAG_MODE = 0 is required to recover. This WD operating mode is selected by setting OTP bit WD_SYS_RESTART_FLAG_MODE = 1.

Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1.

Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active. Depending on OTP settings and ENx pin state watchdog behavior can be slightly different:

• When ENx pin is used for controlling power sequence and ENx pin is not active, shutdown sequence can not be performed. WD_RESET pulse length is fixed 31 ms.

• When ENx pins are not used for power sequence control and all converters and GPOs enabled via I2C, there is no OTP defined power sequence. WD expiration does not cause converter disable/enable sequence even when OTP settings for watchdog are such that restart is enabled. In this case WD_RESET pulse is 11 ms.

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Long Open

Open

WD Reset

Increase Reset Counter value,

WDI Rising

CloseTime Expired

WDI Rising

LongOpenTime Expired

OpenTime Expired

Shutdown Sequence

WD_RESET output

active for (7.5ms +10ms)

or (15ms+10ms)

Read OTP

Stop

WD_EN_OTP_READ = 0

WD_EN_OTP_READ = 1

WD_SYS_RESTART_FLAG_MODE = 1

Restart Disabled OR

Reset Counter < Counter Select

Restart Enabled AND

Reset Counter >= Counter Select

(from all states except Stop)

Release ENx

pin gating

Shutdown

NRST low OR

VANA < VANA_UVLO

NRST high AND

VANA > VANA_UVLO

(WD_SYSTEM_RESTART_FLAG = 0

WD_SYSTEM_RESTART_FLAG_MODE = 0)

AND

WD_EN_OTP_READ = 1

(WD_SYSTEM_RESTART_FLAG = 0

WD_SYSTEM_RESTART_FLAG_MODE = 0)

AND

WD_EN_OTP_READ = 0

WD_RESET output

active for 10ms

Set

WD_SYSTEM_

RESTART_FLAG = 1

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Figure 14. Watchdog Operation

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Table 4. Watchdog Window Periods

CONTROL BIT DEFAULT VALUES

00 - 200 ms

WD_LONG_OPEN_TIME OTP

WD_CLOSE_TIME OTP

WD_OPEN_TIME OTP

01 - 600 ms 10 - 2000 ms 11 - 5000 ms

00 - 10 ms 01 - 20 ms 10 - 50 ms

11 - 100 ms

00 - 20 ms 01 - 100 ms 10 - 200 ms 11 - 600 ms

LP87702-Q1 supports option to disable watchdog. WD_DIS pin function is multiplexed with CLKIN/GPIO2 functions. Watchdog disable option can be selected by setting register bit WD_DIS_CTRL = 1. When WD_DIS_CTRL = 1, WD is disabled if CLKIN/GPIO2/WD_DIS pin is HIGH and enabled if CLKIN/GPIO2/WD_DIS pin is LOW. If WD_DIS_CTRL is toggled to disable and re-enable WD, WD starts from Long Open window after re-enabling.

Default for WD_DIS_CTRL is set in OTP. WD_DIS_CTRL value can be changed via I2C until WD settings are locked. When WD_LOCK is set to 1, WD is enabled regardless of WD_DIS_CTRL value. WD_DIS_CTRL bit is protected by write lock. Three consecutive codes have to be written to WD_DIS_UNLOCK_CODE to open WD_DIS_CTRL for write access.

7.3.9 Device Reset Scenarios

There are four reset methods implemented on the LP87702-Q1:

• Software reset with SW_RESET bit in RESET register

• NRST input signal low

• Undervoltage lockout (UVLO) reset from VANA supply

• Watchdog expiration (depending on watchdog settings) A SW reset occurs when SW_RESET bit is set to 1. The bit is automatically cleared after writing. This event

disables all the converters immediately, drives GPO signals low, resets all the register bits to the default values and OTP bits are loaded (see Figure 20). I2C interface is not reset during software reset. The host must wait at least 1.2 ms after writing SW reset until making a new I2C read or write to the device.

If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the converters are disabled immediately, GPOx signals are driven low and all the register bits are reset to the default values. When the VANA supply voltage rises above UVLO threshold level and NRST signal rises above threshold level, OTP bits are loaded to the registers and a start-up is initiated according to the register settings. The host must wait at least 1.2 ms before reading or writing to I2C interface.

Depending on watchdog settings, watchdog expiration can reset the device to OTP default values.

7.3.10 Diagnostics and Protection Features

The LP87702-Q1 provides four levels of protection features:

• Information of input and output voltages. Non-valid voltage sets interrupt or PGx signal – Validity of the output voltage of BUCK or BOOST converters – Validity of VANA, VMON1 and VMON2 input voltages

• Warnings causing interrupt – Peak current limit detection in BUCK or BOOST converters – Thermal warning

• Protection events which are disabling the converters – Short-circuit and overload protection for BUCK and BOOST converters – Input overvoltage protection (VANA

OVP

)

– Watchdog expiration (optional, depends on watchdog settings)

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– Thermal shutdown

• Protection events which are causing the device to shutdown – Undervoltage lockout (VANA

UVLO

)

• Protections not causing interrupt or converter disable – Negative current limit detection in BUCK or BOOST converters

7.3.10.1 Voltage Monitorings

The LP87702-Q1 device has programmable voltage monitoring for the BUCKx and BOOST converter output voltages and for VANA, VMON1 and VMON2 inputs. Monitoring of each signal is independently enabled in PGOOD_CTRL register. Voltage monitoring can be under-voltage monitoring only (PGOOD_WINDOW = 0) or overvoltage and undervoltage monitoring (PGOOD_WINDOW = 1). This selection is common for all enabled monitorings. Enabled monitoring signals are combined to generate power-good (PG0, PG1) and/or interrupts as described in Power-Good Information to Interrupt and PG0 and PG1 Pins. Monitoring comparators have a dedicated reference and bias block, which is independent of the main reference and bias block.

Nominal level for the output voltage of BUCKx converter is set with BUCKx_VSET in BUCKx_VOUT register. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected with BUCKx_WINDOW as ± 30 mV, ± 50 mV, ± 70 mV or ± 90 mV. Nominal level for the output voltage of BOOST converter is set with BOOST_VSET in BOOST_CTRL register. Available levels are 4.9 V, 5 V, 5.1 V and 5.2 V. Overvoltage and undervoltage detection levels, with respect to nominal level, are selected with BOOST_WINDOW as ± 2%, ± 4%, ± 6% or ± 8%. Converter monitoring window selection bits are in PGOOD_LEVEL_3 register.

Input voltage of LP87702-Q1 is monitored at VANA pin. Nominal level can be selected as 3.3 V or 5 V with VANA_THRESHOLD bit. Overvoltage and undervoltage detection levels are selected with VANA_WINDOW as ± 4%, ± 5% or ± 10% (nominal). VANA_THRESHOLD and VANA_WINDOW are set in PGOOD_LEVEL_2 register.

VMON1 and VMON2 inputs can be used for monitoring external rails in the system. VMONx settings are defined in PGOOD_LEVEL_1 and PGOOD_LEVEL_2 registers. Nominal value for the input level of VMONx is selected with VMONx_THRESHOLD, between 0.65 V to 1.8 V. Higher voltage levels or levels not directly supported can be monitored using an external resistor divider. In this case VMONx_THRESHOLD must be set as 0.65V to have high-impedance input and the resistor divider must scale the monitored level down to 0.65 V at VMONx pin. Overvoltage and undervoltage detection levels are selected with VMONx_WINDOW as ± 2%, ± 3%, ± 4% or ± 6%.

For more details on the accuracy of the monitoring windows and deglitch filtering see Specifications.

7.3.10.2 Interrupts

The LP87702-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT output pin is driven high after all flag bits and pending interrupts are cleared.

Fault detection is indicated by RESET_REG_INT interrupt flag bit set in INT_TOP_2 register after start-up event.

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+ 71 hidden pages

Texas Instruments LP87702-Q1 Datasheet

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 I2C Serial Bus Timing Parameters

6.7 Typical Characteristics

7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Descriptions

7.3.1 Step-Down DC/DC Converters

7.3.1.1 Overview

7.3.1.2 Transition Between PWM and PFM Modes

7.3.1.3 Buck Converter Load Current Measurement

7.3.2 Boost Converter

7.3.3 Spread-Spectrum Mode

7.3.4 Sync Clock Functionality

7.3.5 Power-Up

7.3.6 Buck and Boost Control

7.3.6.1 Enabling and Disabling Converters

7.3.6.2 Changing Buck Output Voltage

7.3.7 Enable and Disable Sequences

7.3.8 Window Watchdog

7.3.9 Device Reset Scenarios

7.3.10 Diagnostics and Protection Features

7.3.10.1 Voltage Monitorings

7.3.10.2 Interrupts