Texas Instruments LP87561Q1, LP87565Q1, LP87562Q1, LP87563Q1, LP87564Q1 User Manual

User's Guide

SNVU472A–October 2016–Revised February 2017

The LP8756xQ1EVM Evaluation Module

This user’s guide describes the operation of the evaluation module for the LP8756xQ1 multi-phase 4-core step-down converter from Texas Instruments (TI). The LP8756xQ1 can be used in five different output configurations, and this user’s guide includes all these five variants (see Table 1). The user’s guide also provides design information including the schematic and bill of materials (BOM).

Contents

1 Overview...................................................................................................................... 3

2 Quick Setup Guide........................................................................................................... 3

2.1 Installing/Opening the Software .................................................................................. 4

2.2 Power Supply Setup................................................................................................ 8

2.3 Notes on Efficiency Measurement Procedure................................................................. 12

3 GUI Overview............................................................................................................... 12

3.1 Main Tab ........................................................................................................... 12

3.2 Other Tabs and Menus ........................................................................................... 13

3.3 Console............................................................................................................. 20

4 Bill of Materials ............................................................................................................. 22

5 Board Layout................................................................................................................ 24

6 LP8756xQ1EVM Schematics............................................................................................. 30

1 LP8756xQ1EVM ............................................................................................................. 3

2 LP8756 Installer License Agreement...................................................................................... 4

3 Features of LP8756 Installation............................................................................................ 5

4 LP8756 Destination Folder ................................................................................................. 5

5 LP8756 Installation Complete.............................................................................................. 6

6 Evaluation Software Graphical User Interface (GUI) When Board Connected...................................... 7

7 Assert nRST.................................................................................................................. 8

8 Read Registers Buttons..................................................................................................... 9

9 BUCK0 Enabled............................................................................................................ 10

10 Assert EN1.................................................................................................................. 11

11 Accessing Direct Register Write.......................................................................................... 14

12 Direct Register Access View.............................................................................................. 15

13 Selecting Register Values................................................................................................. 16

14 Register Update Mode..................................................................................................... 17

15 Config Tab of the LP8756 GUI ........................................................................................... 18

16 Advanced Tab of LP8756 GUI ........................................................................................... 19

17 Opening Console........................................................................................................... 20

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List of Figures

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18 Example of Command Use in Console.................................................................................. 21

19 Board Stack-Up............................................................................................................. 24

20 Top View of the LP8756xQ1EVM........................................................................................ 25

21 Component Placement Top Layer ....................................................................................... 25

22 Component Placement Bottom Layer ................................................................................... 26

23 Top Layer ................................................................................................................... 26

24 Mid-Layer1 ................................................................................................................. 26

25 Mid-Layer2 .................................................................................................................. 27

26 Mid-Layer3 .................................................................................................................. 27

27 Mid-Layer4, GND Plane................................................................................................... 28

28 Bottom Layer (note mirror view).......................................................................................... 28

29 LP87561Q1EVM Schematic.............................................................................................. 30

30 LP87562Q1EVM Schematic.............................................................................................. 31

31 LP87563Q1EVM............................................................................................................ 32

32 LP87564Q1EVM Schematic.............................................................................................. 33

33 LP87565Q1EVM Schematic.............................................................................................. 34

34 EVM Connectors ........................................................................................................... 35

35 EVM I

2

C Interface .......................................................................................................... 36

List of Tables

1 LP8756xQ1 Configurations................................................................................................. 3

2 Mode Information........................................................................................................... 13

3 I

2

C-Compatible Bus Support.............................................................................................. 13

4 Console Macros ............................................................................................................ 21

5 Bill of Materials for LP8756xQ1EVM .................................................................................... 22

Trademarks

All trademarks are the property of their respective owners.

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The LP8756xQ1EVM Evaluation Module

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1 Overview

The LP8756xQ1EVM customer evaluation module demonstrates the integrated circuit LP8756xQ1 from TI. The LP8756xQ1 is a high-performance, multi-phase step-down converter designed to meet the power management requirements of the latest applications processors and platform needs in automotive infotainment and cluster applications and also in automotive camera power applications. The device contains four step-down converter cores, which are bundled together in all possible configurations between single 4-phase buck converter and four single-phase buck converters. This document covers user software provided with the EVM and design documentation that includes schematics and parts list.

PART NUMBER OUTPUT CONFIGURATION NUMBER OF OUTPUTS EVM NUMBER

LP87561Q1 4-phase 1 LP87561Q1EVM LP87562Q1 3-phase + 1-phase 2 LP87562Q1EVM LP87563Q1 2-phase + 1-phase + 1-phase 3 LP87563Q1EVM LP87564Q1 4 × 1-phase 4 LP87564Q1EVM LP87565Q1 2-phase + 2-phase 2 LP87565Q1EVM

Overview

Table 1. LP8756xQ1 Configurations

2 Quick Setup Guide

Many of the components on the LP8756xQ1 are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.

Upon opening the LP8756xQ1EVM package, ensure that the following items are included:

• LP8756xQ1 Evaluation Board

• USB Cable

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Figure 1. LP8756xQ1EVM

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Quick Setup Guide

If any of the items are missing, contact the closest Texas Instruments Product Information Center to inquire about a replacement.

2.1 Installing/Opening the Software

The EVM software is controlled through a graphical user interface (GUI). The software communicates with the EVM through an available USB port. The minimum hardware requirements for the EVM software are:

• IBM PC-compatible computer running a Microsoft Windows® XP or newer operating system

• Available USB port

• Mouse Software installation

1. Open the LP8756_installer.exe

2. Installer prompts to accept the license agreement (see Figure 2).

3. Installer prompts to choose which features of LP8756x Installer you want to install (see Figure 3).

4. Installer prompts to select Destination Folder (see Figure 4).

5. Press Install and the installation starts.

6. Installer prompts when installation is complete (see Figure 5). Open the LP8756x GUI. Connect the EVM to the PC with the USB cable.

1. With the power supply disconnected from the unit under test (UUT), open LP8756EVM.exe located in

the directory selected during installation.

2. On the Evaluation SW window bottom right corner you should see text “Hardware connected.”. Refer

to Figure 6.

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Figure 2. LP8756 Installer License Agreement

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Quick Setup Guide

Figure 3. Features of LP8756 Installation

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Figure 4. LP8756 Destination Folder

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Quick Setup Guide

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Figure 5. LP8756 Installation Complete

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Quick Setup Guide

Figure 6. Evaluation Software Graphical User Interface (GUI)

When Board Connected

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Quick Setup Guide

2.2 Power Supply Setup

To power up the EVM, one power supply is needed. For full-load testing of the LP8756xQ1EVM, a DCpower supply capable of at least 10 A and 4 V is required. 5 A is suggested as a practical minimum for partial load. The power supply is connected to the EVM using connector X1. The power supply and cabling must present low impedance to the UUT; the length of power supply cables must be minimized. Remote sense, using connector X3, can be used to compensate for voltage drops in the cabling.

With the power supply disconnected from the UUT, set the supply to 3.7 V DC and the current limit to 5 A minimum. Set the power supply output OFF. Connect the power supply's positive terminal (+) to VIN and negative terminal (–) to GND on UUT (X1 power-in terminal block). Check that jumpers on the boards are set as shown in Figure 1 (factory default jumper configuration).

Set power supply output ON, and then continue with the following steps. Note that following steps is only an example. Register values, enable control, mode and multiphase status may differ depending on the LP8756xQ1EVM configuration.

1. On Evaluation software GUI, click on Assert NRST (see Figure 7).

2. Click on either of the two Read Registers buttons. You should see ready message on green

background next to the Read Registers button (see Figure 8).

3. Check that Buck0 is enabled (see Figure 9).

4. Click on Assert EN1 (see Figure 10).

5. Click on either of the two Read Registers buttons.

6. In this example case the GUI indicates "Disabled" under "Mode" until EN1 is asserted. After EN1 is

asserted "Mode" is changed to "Enabled". In case BUCKx is enabled or disabled with bit instead of ENx pin, the "Mode" can be checked by reading registers. GUI indicates also "Master" under "Multiphase status" of Buck 0. Mode of other bucks are "Disabled" and Multiphase status is "Slave to Buck0". The EVM is now ready for testing with default register settings loaded.

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Figure 7. Assert nRST

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Quick Setup Guide

Figure 8. Read Registers Buttons

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Quick Setup Guide

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Figure 9. BUCK0 Enabled

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Quick Setup Guide

Figure 10. Assert EN1

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Quick Setup Guide

2.3 Notes on Efficiency Measurement Procedure

Output Connections: An appropriate electronic load or high-power system source meter instrument, specified for operation down to 500 mV, is desirable for loading the UUT. The maximum load current is specified as 4 A per phase. Be sure to choose the correct wire size when attaching the electronic load. A wire resistance that is too high will cause a voltage drop in the power distribution path which becomes significant compared to the absolute value of the output voltage. Connect an electric load to X7, X8, X9 and/or X10. It is advised that, prior to connecting the load, it be set to sink 0 A to avoid power surges or possible shocks.

Voltage drop across the PCB traces will yield inaccurate efficiency measurements. For the most accurate voltage measurement at the EVM, use TP7 to measure the input voltage and X2 to measure the output voltage.

To measure the current flowing to/from the UUT, use the current meter of the DC power supply/electric load as long as it is accurate. Some power source ammeters may show offset of several milliamps and thus will yield inaccurate efficiency measurements. In order to perform very accurate Iqmeasurements on the UUT, disconnect input protective Zener diode D1 by removing the shunt J3 from the board. When connected, this diode will cause some leakage, especially on high VIN voltages.

3 GUI Overview

The evaluation software has the following tabs: Main, Config, and Advanced. The three tabs together provide the user access to the whole register map of the LP8756x. Additional register control can be obtained from Tools --> Direct Register Access.

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3.1 Main Tab

The Main tab (see for example Figure 10) has the elemental controls for the EVM and provides a view to the chip status. Starting from top, the main controls are:

• I2C mode or 4 Enable mode. If this states I2C mode, device is controlled with I2C. When this states

4EN mode, bucks are controlled with ENx pins.

• Assert NRST: This checkbox will assert high level to LP8756xQ1 NRST pin. This pin enables the chip

internal voltage reference and bias circuitry.

• Assert EN1: This checkbox will assert high level to LP8756xQ1 EN1 pin. Asserting EN1 may enable

the buck regulator(s) or switch to different output voltage level, depending on the register settings.

• Assert EN2: This checkbox will assert high level to LP8756xQ1 EN2 pin. Asserting EN2 may enable

the buck regulator(s) or switch to different output voltage level, depending on the register settings.

• Assert EN3: This checkbox will assert high level to LP8756xQ1 EN3 pin. Asserting EN3 may enable

the buck regulator(s) or switch to different output voltage level, depending on the register settings.

• Assert EN4: In 4 Enable mode, this checkbox will assert high level to LP8756x SCL pin, (alternative

function is EN4). Asserting EN4 may enable the buck regulator(s), depending on the register settings. This checkbox is visible only when device is configured to 4 Enable Signal Mode.

• Assert SW Reset: To perform a complete SW reset to the chip, assert this checkbox. See the LP8756

datasheet for explanation of LP8756 reset scenarios.

NOTE: The recommended start-up sequence for LP8756xQ1 is to first assert NRST, then write all

needed configuration bits by using the GUI, and then enable buck regulator(s) by ENx pin or EN_BUCKx bit.

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The "Bucks" section provides status information and enable controls for all the 4 buck cores. On the left of the section are the check-boxes for the buck enable bits. The "Mode" field provides information on each of the buck core and can have any of the values given in Table 2:

The "Multiphase status" info field tells whether a buck core is configured as a master or a slave. The "Current" field gives the result of the buck converter load current measurement operation. Output currents of each buck core and total output current of master(s) are shown on the fields.

The "System Flags / Interrupts" section as well as the "Interrupt bits" and the "Status bits" sections give data on system faults and warnings. If the interrupt is set for any reason the Interrupt active field shall show ‘1’ on red background. The flag causing the interrupt will also be set on the Main tab. Interrupts on LP8756xQ1 can only be cleared by writing '1’ to associated registers. Any individual flag can be cleared by clicking the "Clear" button next to each flag field. Some of the flags also have a mask bits. If "Mask" check-box of certain flag is checked, the interrupt is not generated. The "Status" bits will show the current status of the faults.

The "Power Good" section is for Power Good pin control and indication. It includes the latched values of buck Power Good Faults. These can be cleared with the Clear -button.

At the bottom of the GUI window is the "Auto Write" checkbox. If "Auto Write" is checked (default) any checking, un-checking or pulldown menu selections will immediately launch I2C writes to the chip register(s). If not checked, the user can update the chip registers to correspond the configuration selected on the GUI by clicking "Write Registers".

If "Poll Status" is selected the software sends a query to the LP8756 at a fixed interval in order to detect the status of the chip, including operation mode, multi-phase status, and output current. If also the "Poll Only Pins" is selected the software is monitoring only the state of Interrupt and Powergood pins. If "Poll Status" is not selected or if "Poll Only Pins" is selected, user can read the registers by applying "Read Registers". "Bus Speed" pulldown menu selections are given in Table 3 below and is instantly applied for System I2C.

GUI Overview

Table 2. Mode Information

BUCK MODE

Disabled Buck state machine in 'disable' Enabled Buck state machine in 'enable'

BUS SPEED SELECTION EXPLANATION

Fast (400 kHz) Fast I2C-compliant operation at 400 kHz High-Speed (3.4 MHz) HS I2C-compliant data transfer with master codes.

3.2 Other Tabs and Menus

The "Tools" pulldown menu hosts another way of accessing the LP8756xQ1 registers (see Figure 11). The "Direct Register Access" tool can be used to read or write any register (see Figure 12). Selecting a register, the bits appear on the right side Field View (see Figure 13). When moving mouse over bits in Field View, bits are highlighted in the register view. Bits can be controlled either from register view or field view. Register settings can also be saved to a file or pre-made register file can be loaded in the Direct Register Access tool. Registers can be updated immediately or manually (see Figure 14).

When using direct register access, TI recommends un-checking the poll status check-box. This way the GUI will only do the reads and writes commanded from the direct access dialog.

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Table 3. I2C-Compatible Bus Support

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GUI Overview

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Figure 11. Accessing Direct Register Write

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GUI Overview

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Figure 12. Direct Register Access View

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GUI Overview

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The LP8756xQ1EVM Evaluation Module

Figure 13. Selecting Register Values

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GUI Overview

The "Config" and "Advanced" tabs provide the user with pulldown menus and check-boxes for the part of the register space that is not covered by the Main tab, such as output voltage control. These controls are self-explanatory. Refer to the LP8756xQ1 data sheet for explanation of the functions. See following images for reference of the Config and Advanced tabs.

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Figure 14. Register Update Mode

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GUI Overview

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Figure 15. Config Tab of the LP8756 GUI

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GUI Overview

Figure 16. Advanced Tab of LP8756 GUI

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GUI Overview

3.3 Console

To show or hide the console, toggle the option in the View pulldown menu (see Figure 17). The console can be used to access the LP8756 registers. Registers can be read or written simply by referring to the logical registers by their name. See an example Figure 18. The console has a number of integrated macros that are listed in Table 4.

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The LP8756xQ1EVM Evaluation Module

Figure 17. Opening Console

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GUI Overview

Figure 18. Example of Command Use in Console

Table 4. Console Macros

Command Parameters Explanation

register_name = register value | - Write a value to writable I2C register or logical register. If no parameter given, will

wait (time) Wait for time given in ms. Useful in loops. iout (buck number) Returns the measured load current of the chosen buck core. 0x address = data

or address[bits] = data

return the current register value. The logical register names are the same as given in the data sheet, and must be in uppercase. Example: BUCK0_VSET = 40

I2C read or write command. addr = value examples: 0x12 = 0xaa 0x12[7] = 1 0x12[3:0] = 15

The console supports use of scripts. If a text file containing commands supported by the console is stored in the same folder with the evaluation software executable, then the script can be launched from the console by typing the text file name, like script.txt.

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Bill of Materials

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4 Bill of Materials

Table 5 lists EVM bill of materials. This includes all output configurations listed in Table 1. Differences are

in device settings, placement of the output shunts (J01, J021, J022, J23) and the feedback connections. See Section 6 for these configuration specific assembly details.

NOTE: The LP8756xQ1 I/O lines are connected to the microcontroller through 0-Ω resistors. These

resistors are assembled to match the default I/O configuration of the LP8756xQ1. If ENx/GPIOx or PGOOD pins are configured as push-pull outputs, corresponding 0-Ω resistors (R18, R20, R21, R22) must be removed to prevent possible damage to the microcontroller I/O pins. In open-drain configuration the microcontroller internal pullups are enabled by the GUI and pullup resistors R7 to R13 are not needed. See also for reference.

Table 5. Bill of Materials for LP8756xQ1EVM

Designator Description Manufacturer Part Number Qty.

PCB Printed Circuit Board Any SV601325 1 C0, C0_1, C1, C1_1, C2, C2_1,

C3, C3_1, C33, C34 C0_2, C1_2, C2_2, C3_2, C32

C0_3, C1_3, C2_3, C3_3

C4, C5, C6, C7

C8, C14, C18, C24, C28

C9, C10, C19, C20

C11, C15, C21, C25 C12, C13, C16, C17, C22, C23,

C26, C27 C30

C31

C36, C54

C37, C38 C39, C41, C42, C43, C44, C45,

C46, C48, C50, C51, C52, C53, C56

C40, C47, C49, C57

C55

C58, C59, C60, C61

C62

D1 Diode, Zener, 5.6V, 5W, SMB D2 Diode, Schottky, 30 V, 0.2 A, SOD-323 Diodes Inc. BAT42WS-7-F 1 FID1, FID2, FID3

H1, H2, H3, H4

CAP, CERM, 22uF, 10V, X7R, 10%, 1206

CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603

CAP, CERM, 3300 pF, 50 V, +/- 10%, X7R, 0402

CAP, CERM, 10 µF, 10 V, +/- 10%, X7R, 0805_140

CAP, CERM, 0.1 µF, 16 V, +/- 5%, X7R, 0402

CAP, CERM, 390 pF, 50 V, +/- 10%, X7R, 0402

CAP, CERM, 6800 pF, 50 V, +/- 10%, X7R, 0402

CAP, CERM, 100 µF, 6.3 V, +/- 20%, X5R, 0805

CAP, TA, 220 µF, 10 V, +/- 10%, 0.05 ohm, SMD

CAP, CERM, 100 µF, 6.3 V, +/- 20%, X5R, 1206

CAP, CERM, 10 pF, 50 V, +/- 5%, C0G/NP0, 0603

CAP, CERM, 15 pF, 100 V, +/- 5%, C0G/NP0, 0603

CAP, CERM, 0.1 µF, 25 V, +/- 10%, X7R, 0603

CAP, CERM, 10 µF, 16 V, +/- 20%, X5R, 0603

CAP, CERM, 10 µF, 16 V, +/- 10%, X5R, 0805

CAP, CERM, 1 µF, 25 V, +/- 10%, X5R, 0603

CAP, CERM, 0.01 µF, 50 V, +/- 10%, X5R, 0603

Fiducial mark. There is nothing to buy or mount.

Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead

MuRata GCM31CR71A226KE02 10

MuRata GRM188R71C104KA01D 5

MuRata GRM155R71H332KA01D 4

MuRata GCM21BR71A106KE22L 4

MuRata GRM155R71C104JA88D 5

MuRata GRM155R71H391KA01D 4

MuRata GRM155R71H682KA88D 4

MuRata GRM21BR60J107M 8

AVX TPSD227K010R0050 1

MuRata GRM31CR60J107ME39L 1

MuRata GRM1885C1H100JA01D 2

MuRata GRM1885C2A150JA01D 2

MuRata GRM188R71E104KA01D 13

Taiyo Yuden EMK107BBJ106MA-T 4

Taiyo Yuden EMK212BJ106KG-T 1

MuRata GRM188R61E105KA12D 4

MuRata GRM188R61H103KA01D 1 Micro Commercial

Components

N/A N/A 3

SMBJ5339B-TP 1

NY PMS 440 0025 PH 4

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Bill of Materials

Table 5. Bill of Materials for LP8756xQ1EVM (continued)

Designator Description Manufacturer Part Number Qty.

H7, H8, H9, H10 Standoff, Hex, 0.5"L #4-40 Nylon Keystone 1902C 4 J0A, J1B, J2, J2B, J3B, J5 RES, 0, 5%, 0.063 W, 0402 Vishay-Dale CRCW04020000Z0ED 1 - 6 J01, J021, J022, J23 JUMPER TIN SMD Harwin S1911-46R 0 - 4 J1 Header, 100mil, 2x2, Gold, TH Samtec TSW-102-07-G-D 1 J3, J7, J8, TP21 Header, 100mil, 2x1, Gold, TH Samtec TSW-102-07-G-S 4

J9 J10 Header, 100mil, 3x1, Gold, TH Samtec HTSW-103-07-G-S 1 L0, L1, L2, L3

L4, L5, L6, L7

L8

LBL1 R1, R2, R3, R4 RES, 3.9, 5%, 0.125 W, 0805 Vishay-Dale CRCW08053R90JNEA 4

R5 RES, 0.01, 1%, 3 W, 2512 Bourns CRA2512-FZ-R010ELF 1 R14, R15, R16, R17, R18, R20,

R21, R22 R24 RES, 6.80 k, 1%, 0.1 W, 0603 Yageo America RC0603FR-076K8L 1 R25, R26 RES, 39.0, 1%, 0.1 W, 0603 Yageo America RC0603FR-0739RL 2 R27 RES, 68.0 k, 1%, 0.1 W, 0603 Yageo America RC0603FR-0768KL 1 R28 RES, 33.0 k, 1%, 0.1 W, 0603 Yageo America RC0603FR-0733KL 1 R29 RES, 1.00, 1%, 0.1 W, 0603 Yageo America RC0603FR-071RL 1 R30 RES, 470 k, 5%, 0.1 W, 0603 Vishay-Dale CRCW0603470KJNEA 1 R31, R32 RES, 1.00 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW06031K00FKEA 2 SH-J1, SH-J2, SH-J3, SH-J4 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA 4 TP5, TP6, TP8, TP9, TP10, TP11,

TP12, TP13, TP16, TP17, TP18, TP19, TP20

TP14, TP15 Terminal, Turret, TH, Double Keystone 1502-2 2

U1

U2

U3

X1, X7, X8, X9, X10 Terminal Block, 5.08 mm, 2x1, TH Phoenix Contact 1715721 5 X2 Terminal Block, 8x1, 2.54 mm, TH Phoenix Contact 1725711 1

X3, X5 Y1 Crystal, 12Mhz, 18pF, SMD AVX CX5032GB12000H0PESZZ 1 C29, C35

H5, H6

H11, H12

Connector, Receptacle, Mini-USB Type B, R/A, Top Mount SMT

Inductor, Shielded, 470 nH, 4.7 A, 0.021 ohm, SMD

Ferrite Bead, 30 ohm @ 100 MHz, 4 A, 0805

Inductor, Wirewound, Ferrite, 10 µH,

0.12 A, 0.5 ohm, SMD Thermal Transfer Printable Labels,

1.250" W x 0.250" H - 10,000 per roll

RES, 0, 5%, 0.1 W, 0603 Vishay-Dale CRCW06030000Z0EA 8

Test Point, TH, Miniature, Yellow Keystone 5004 13

Four-Phase Buck Converter Up to 16-A Total Current With Integrated Switches, RNF0026C

AT91SAM ARM-based Flash MCU, LQFP100

Dual Linear Regulator with 300mA and 150mA Outputs and Power-On-Reset, 10-pin WSON, Pb-Free

Terminal Block, 100mil, 2x1, 6A, 63V, TH

CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R, 0603

Standard Shield Cover, 26.67 x 26.67mmLaird-Signal Integrity

Standard Surface Mount Shield , 26.21 x

26.21 mm, Height 5.08mm

TE Connectivity 1734035-2 1

MuRata Toko DFE252012PD-R47M 4

MuRata BLM21PG300SH1D 4

Taiyo Yuden LB2012T100KR 1

Brady THT-13-457-10 1

LP87561DRNFRQ1 (4-ph)

Texas Instruments

Atmel ATSAM3U2CA-AU 1

Texas Instruments LP3996SD-1833/NOPB 1

Phoenix Contact 1725656 2

MuRata GRM188R71C104KA01D 0

Products Laird-Signal Integrity

Products

LP87562ARNFRQ1 (3+1) LP87563BRNFRQ1 (2+1+1) LP87564FRNFRQ1 (4 x 1) LP87565ARNFRQ1 (2 + 2)

BMI-S-203-C 0

BMI-S-203-F 0

1

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The LP8756xQ1EVM Evaluation Module

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Board Layout

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Table 5. Bill of Materials for LP8756xQ1EVM (continued)

Designator Description Manufacturer Part Number Qty.

J1A, J2A, J3A, J4 RES, 0, 5%, 0.063 W, 0402 Vishay-Dale CRCW04020000Z0ED 0 - 4 R6, R19 RES, 0, 5%, 0.1 W, 0603 Vishay-Dale CRCW06030000Z0EA 0 R7, R8, R9, R10, R11, R12, R13 RES, 1.8 k, 5%, 0.1 W, 0603 Vishay-Dale CRCW06031K80JNEA 0 R23 RES, 50, 1%, 0.1 W, 0603 Vishay-Dale CRCW060350R0FKEA 0 TP1, TP2, TP3, TP4, TP7 Header, 100mil, 2x1, Gold, TH Samtec TSW-102-07-G-S 0 X4, X6 Receptacle, 2.5mm, 3x2, Gold, SMT TE Connectivity 6651712-1 0

5 Board Layout

This section describes the board layout of the LP8756xQ1EVM. See the LP8756xQ1 data sheet for specific PCB layout recommendations.

The board is constructed on a 6-layer PCB. using 60-µm copper on top and bottom layers to reduce resistance and improve heat transfer. Similar layout can be done as a 4-layer board but 6 layers were chosen to improve grounding and reduce DC resistances.

Board stack-up is shown in Figure 19. Figure 20 shows the top view of the entire board and Figure 21 through Figure 28 show the component placement, layout, and 3D view close to the LP8756 device.

The design utilizes dual side placement of the components. This allows placement of the inductors next to the LP8756xQ1 device for reducing SW node area for improved efficiency and reduced EMI. SW nets have also snubber components to reduce SW pin spiking and EMI. The input capacitors can be placed very close to the LP8756xQ1 device, to bottom side, to keep parasitic inductances low, and there is also space for input filters for further EMI reduction. With these modifications, the EVMs can pass CISPR25 radiated and conducted EMI test without (optional) EMI shields H5 and H6.

24

The LP8756xQ1EVM Evaluation Module

Figure 19. Board Stack-Up

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Board Layout

Figure 20. Top View of the LP8756xQ1EVM

Figure 21. Component Placement Top Layer

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LP8752_EVM_mid3_layer

Board Layout

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Figure 22. Component Placement Bottom Layer

VIN nets are connected to bottom layer with multiple vias. This allows closer placement of the inductors, thus reducing SW node size and EMI. Also snubber circuits are placed next to SW nets for EMI reduction. Multiple GND vias are used to provide solid ground around the LP8756xQ1 device.

26

The LP8756xQ1EVM Evaluation Module

Figure 23. Top Layer

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GND plane close to top layer (0.063 mm) helps to reduce parasitic inductance. Holes in the plane are under inductor footprint (SW node) to reduce parasitic capacitance of the SW node, thus reducing noise coupling and improving efficiency.

Figure 24. Mid-Layer1

Board Layout

VIN supply is routed in this layer between the ground planes to reduce radiated emissions. VIN and GND vias are placed in hatched pattern to avoid large gaps in these planes.

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Figure 25. Mid-Layer2

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27

Board Layout

This layer is similar to mid-layer2 to reduce resistance of the VIN net.

Figure 26. Mid-Layer3

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Placed close to bottom layer (0.063 mm) to reduce parasitic inductance.

28

The LP8756xQ1EVM Evaluation Module

Figure 27. Mid-Layer4, GND Plane

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Board Layout

Input capacitors and filters are placed under the LP8756xQ1 into bottom layer. This allows closer placement of the inductors and input components reducing SW and VIN net areas and improving EMI.

Figure 28. Bottom Layer (note mirror view)

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The LP8756xQ1EVM Evaluation Module

29

GND

10µF

C4

10µF

C5

10µF

C6

10µF

C7

VINB0

VINB1

VINB2

VINB3

VINB0

VINB1

VINB2

VINB3

6800pF

C11

100µF

C12

VIN

GND GNDGND

6800pF

C21

100µF

C22

VIN

GND GNDGND

6800pF

C15

100µF

C16

VIN

GND GNDGND

6800pF

C25

100µF

C26

VIN

GND GNDGND

SW0

SW1

SW2

SW3

100µF

C13

GND

100µF

C23

GND

100µF

C17

GND

100µF

C27

GND

0J3B

0J3A

DNP

GND

1 2

TP1

DNP

1 2

TP2

DNP

1 2

TP3

DNP

1 2

TP4

DNP

GND

0J0A

GND

0J1B

0J1A

DNP

FB0

FB1

FB2

FB3

FB1

FB0

FB2

FB3

0J2B

0J2A

DNP

VOUT0

VOUT1

VOUT2

VOUT3

0.1µF

C0_2

0.1µF

C1_2

0.1µF

C2_2

0.1µF

C3_2

SW0

SW1

SW2

SW3

22µF

C0

22µF

C0_1

22µF

C1

22µF

C1_1

22µF

C2

22µF

C2_1

22µF

C3

22µF

C3_1

GND

SDASYS SCLSYS INT NRST PGOOD CLKIN EN1 EN2 EN3

3.9

R1

390pF

C9

3.9

R3

390pF

C19

3.9

R2

390pF

C10

3.9

R4

390pF

C20

3300pF

C0_3

3300pF

C1_3

3300pF

C2_3

3300pF

C3_3

Input filters for reducing EMI

Snubbers

VDDA

30 ohm

L4

BLM21PG300SH1D

30 ohm

L6

BLM21PG300SH1D

30 ohm

L5

BLM21PG300SH1D

30 ohm

L7

BLM21PG300SH1D

470nH

L0

470nH

L1

470nH

L2

470nH

L3

J01

S1911-46R

J021

S1911-46R

J23

S1911-46R

VOUT0

VOUT2

VOUT1

VOUT3

VOUT0

J022

S1911-46R

VOUT2VOUT0

Shunts for Connecting Phases Together

0.1µF

C8

0.1µF

C14

0.1µF

C24

0.1µF

C18

0.1µF

C28

FB_B2

1

EN3

2

CLKIN

3

AGND

4

SCL

5

SDA

6

EN1

7

FB_B0

8

VIN_B0

9

SW_B0

10

PGND_B01

11

SW_B1

12

VIN_B1

13

FB_B1

14

EN2

15

PGOOD

16

AGND

17

VANA

18

INT

19

NRST

20

FB_B3

21

VIN_B3

22

SW_B3

23

PGND_B23

24

SW_B2

25

VIN_B2

26

AGND

27

U1

LP87561DRNFRQ1

LP8756xQ1EVM Schematics

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The LP8756xQ1EVM Evaluation Module

6 LP8756xQ1EVM Schematics

Figure 29. LP87561Q1EVM Schematic

GND

10µF

C4

10µF

C5

10µF

C6

10µF

C7

VINB0

VINB1

VINB2

VINB3

VINB0

VINB1

VINB2

VINB3

6800pF

C11

100µF

C12

VIN

GND GNDGND

6800pF

C21

100µF

C22

VIN

GND GNDGND

6800pF

C15

100µF

C16

VIN

GND GNDGND

6800pF

C25

100µF

C26

VIN

GND GNDGND

SW0

SW1

SW2

SW3

100µF

C13

GND

100µF

C23

GND

100µF

C17

GND

100µF

C27

GND

0J3B

DNP

0J3A

GND

1 2

TP1

DNP

1 2

TP2

DNP

1 2

TP3

DNP

1 2

TP4

DNP

GND

0J0A

GND

0J1B

0J1A

DNP

FB0

FB1

FB2

FB3

FB1

FB0

FB2

FB3

0J2B

0J2A

DNP

VOUT0

VOUT1

VOUT2

VOUT3

0.1µF

C0_2

0.1µF

C1_2

0.1µF

C2_2

0.1µF

C3_2

SW0

SW1

SW2

SW3

22µF

C0

22µF

C0_1

22µF

C1

22µF

C1_1

22µF

C2

22µF

C2_1

22µF

C3

22µF

C3_1

GND

SDASYS SCLSYS INT NRST PGOOD CLKIN EN1 EN2 EN3

3.9

R1

390pF

C9

3.9

R3

390pF

C19

3.9

R2

390pF

C10

3.9

R4

390pF

C20

3300pF

C0_3

3300pF

C1_3

3300pF

C2_3

3300pF

C3_3

Input filters for reducing EMI

Snubbers

VDDA

30 ohm

L4

BLM21PG300SH1D

30 ohm

L6

BLM21PG300SH1D

30 ohm

L5

BLM21PG300SH1D

30 ohm

L7

BLM21PG300SH1D

470nH

L0

470nH

L1

470nH

L2

470nH

L3

J01

S1911-46R

J021

S1911-46R

J23

S1911-46R

DNP

VOUT0

VOUT2

VOUT1

VOUT3

VOUT0

J022

S1911-46R

VOUT2VOUT0

Shunts for Connecting Phases Together

0.1µF

C8

0.1µF

C14

0.1µF

C24

0.1µF

C18

0.1µF

C28

FB_B2

1

EN3

2

CLKIN

3

AGND

4

SCL

5

SDA

6

EN1

7

FB_B0

8

VIN_B0

9

SW_B0

10

PGND_B01

11

SW_B1

12

VIN_B1

13

FB_B1

14

EN2

15

PGOOD

16

AGND

17

VANA

18

INT

19

NRST

20

FB_B3

21

VIN_B3

22

SW_B3

23

PGND_B23

24

SW_B2

25

VIN_B2

26

AGND

27

U1

LP87562ARNFRQ1

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LP8756xQ1EVM Schematics

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The LP8756xQ1EVM Evaluation Module

Figure 30. LP87562Q1EVM Schematic

GND

10µF

C4

10µF

C5

10µF

C6

10µF

C7

VINB0

VINB1

VINB2

VINB3

VINB0

VINB1

VINB2

VINB3

6800pF

C11

100µF

C12

VIN

GND GNDGND

6800pF

C21

100µF

C22

VIN

GND GNDGND

6800pF

C15

100µF

C16

VIN

GND GNDGND

6800pF

C25

100µF

C26

VIN

GND GNDGND

SW0

SW1

SW2

SW3

100µF

C13

GND

100µF

C23

GND

100µF

C17

GND

100µF

C27

GND

0J3B

DNP

0J3A

GND

1 2

TP1

DNP

1 2

TP2

DNP

1 2

TP3

DNP

1 2

TP4

DNP

GND

0J0A

GND

0J1B

0J1A

DNP

FB0

FB1

FB2

FB3

FB1

FB0

FB2

FB3

0J2B

DNP

0J2A

VOUT0

VOUT1

VOUT2

VOUT3

0.1µF

C0_2

0.1µF

C1_2

0.1µF

C2_2

0.1µF

C3_2

SW0

SW1

SW2

SW3

22µF

C0

22µF

C0_1

22µF

C1

22µF

C1_1

22µF

C2

22µF

C2_1

22µF

C3

22µF

C3_1

GND

SDASYS SCLSYS INT NRST PGOOD CLKIN EN1 EN2 EN3

3.9

R1

390pF

C9

3.9

R3

390pF

C19

3.9

R2

390pF

C10

3.9

R4

390pF

C20

3300pF

C0_3

3300pF

C1_3

3300pF

C2_3

3300pF

C3_3

Input filters for reducing EMI

Snubbers

VDDA

30 ohm

L4

BLM21PG300SH1D

30 ohm

L6

BLM21PG300SH1D

30 ohm

L5

BLM21PG300SH1D

30 ohm

L7

BLM21PG300SH1D

470nH

L0

470nH

L1

470nH

L2

470nH

L3

J01

S1911-46R

J021

S1911-46R

DNP

J23

S1911-46R

DNP

VOUT0

VOUT2

VOUT1

VOUT3

VOUT0

J022

S1911-46R

DNP

VOUT2VOUT0

Shunts for Connecting Phases Together

0.1µF

C8

0.1µF

C14

0.1µF

C24

0.1µF

C18

0.1µF

C28

FB_B2

1

EN3

2

CLKIN

3

AGND

4

SCL

5

SDA

6

EN1

7

FB_B0

8

VIN_B0

9

SW_B0

10

PGND_B01

11

SW_B1

12

VIN_B1

13

FB_B1

14

EN2

15

PGOOD

16

AGND

17

VANA

18

INT

19

NRST

20

FB_B3

21

VIN_B3

22

SW_B3

23

PGND_B23

24

SW_B2

25

VIN_B2

26

AGND

27

U1

LP87563BRNFRQ1

LP8756xQ1EVM Schematics

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The LP8756xQ1EVM Evaluation Module

Figure 31. LP87563Q1EVM

GND

10µF

C4

10µF

C5

10µF

C6

10µF

C7

VINB0

VINB1

VINB2

VINB3

VINB0

VINB1

VINB2

VINB3

6800pF

C11

100µF

C12

VIN

GND GNDGND

6800pF

C21

100µF

C22

VIN

GND GNDGND

6800pF

C15

100µF

C16

VIN

GND GNDGND

6800pF

C25

100µF

C26

VIN

GND GNDGND

SW0

SW1

SW2

SW3

100µF

C13

GND

100µF

C23

GND

100µF

C17

GND

100µF

C27

GND

0J3B

DNP

0J3A

GND

1 2

TP1

DNP

1 2

TP2

DNP

1 2

TP3

DNP

1 2

TP4

DNP

GND

0J0A

GND

0J1B

DNP

0J1A

FB0

FB1

FB2

FB3

FB1

FB0

FB2

FB3

0J2B

DNP

0J2A

VOUT0

VOUT1

VOUT2

VOUT3

0.1µF

C0_2

0.1µF

C1_2

0.1µF

C2_2

0.1µF

C3_2

SW0

SW1

SW2

SW3

22µF

C0

22µF

C0_1

22µF

C1

22µF

C1_1

22µF

C2

22µF

C2_1

22µF

C3

22µF

C3_1

GND

SDASYS SCLSYS INT NRST PGOOD CLKIN EN1 EN2 EN3

3.9

R1

390pF

C9

3.9

R3

390pF

C19

3.9

R2

390pF

C10

3.9

R4

390pF

C20

3300pF

C0_3

3300pF

C1_3

3300pF

C2_3

3300pF

C3_3

Input filters for reducing EMI

Snubbers

VDDA

30 ohm

L4

BLM21PG300SH1D

30 ohm

L6

BLM21PG300SH1D

30 ohm

L5

BLM21PG300SH1D

30 ohm

L7

BLM21PG300SH1D

470nH

L0

470nH

L1

470nH

L2

470nH

L3

J01

S1911-46R

DNP

J021

S1911-46R

DNP

J23

S1911-46R

DNP

VOUT0

VOUT2

VOUT1

VOUT3

VOUT0

J022

S1911-46R

DNP

VOUT2VOUT0

Shunts for Connecting Phases Together

0.1µF

C8

0.1µF

C14

0.1µF

C24

0.1µF

C18

0.1µF

C28

FB_B2

1

EN3

2

CLKIN

3

AGND

4

SCL

5

SDA

6

EN1

7

FB_B0

8

VIN_B0

9

SW_B0

10

PGND_B01

11

SW_B1

12

VIN_B1

13

FB_B1

14

EN2

15

PGOOD

16

AGND

17

VANA

18

INT

19

NRST

20

FB_B3

21

VIN_B3

22

SW_B3

23

PGND_B23

24

SW_B2

25

VIN_B2

26

AGND

27

U1

LP87564FRNFRQ1

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LP8756xQ1EVM Schematics

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The LP8756xQ1EVM Evaluation Module

Figure 32. LP87564Q1EVM Schematic

GND

10µF

C4

10µF

C5

10µF

C6

10µF

C7

VINB0

VINB1

VINB2

VINB3

VINB0

VINB1

VINB2

VINB3

6800pF

C11

100µF

C12

VIN

GND GNDGND

6800pF

C21

100µF

C22

VIN

GND GNDGND

6800pF

C15

100µF

C16

VIN

GND GNDGND

6800pF

C25

100µF

C26

VIN

GND GNDGND

SW0

SW1

SW2

SW3

100µF

C13

GND

100µF

C23

GND

100µF

C17

GND

100µF

C27

GND

0J3B

0J3A

DNP

GND

1 2

TP1

DNP

1 2

TP2

DNP

1 2

TP3

DNP

1 2

TP4

DNP

GND

0J0A

GND

0J1B

0J1A

DNP

FB0

FB1

FB2

FB3

FB1

FB0

FB2

FB3

0J2B

DNP

0J2A

VOUT0

VOUT1

VOUT2

VOUT3

0.1µF

C0_2

0.1µF

C1_2

0.1µF

C2_2

0.1µF

C3_2

SW0

SW1

SW2

SW3

22µF

C0

22µF

C0_1

22µF

C1

22µF

C1_1

22µF

C2

22µF

C2_1

22µF

C3

22µF

C3_1

GND

SDASYS SCLSYS INT NRST PGOOD CLKIN EN1 EN2 EN3

3.9

R1

390pF

C9

3.9

R3

390pF

C19

3.9

R2

390pF

C10

3.9

R4

390pF

C20

3300pF

C0_3

3300pF

C1_3

3300pF

C2_3

3300pF

C3_3

Input filters for reducing EMI

Snubbers

VDDA

30 ohm

L4

BLM21PG300SH1D

30 ohm

L6

BLM21PG300SH1D

30 ohm

L5

BLM21PG300SH1D

30 ohm

L7

BLM21PG300SH1D

470nH

L0

470nH

L1

470nH

L2

470nH

L3

J01

S1911-46R

J021

S1911-46R

DNP

J23

S1911-46R

VOUT0

VOUT2

VOUT1

VOUT3

VOUT0

J022

S1911-46R

DNP

VOUT2VOUT0

Shunts for Connecting Phases Together

0.1µF

C8

0.1µF

C14

0.1µF

C24

0.1µF

C18

0.1µF

C28

FB_B2

1

EN3

2

CLKIN

3

AGND

4

SCL

5

SDA

6

EN1

7

FB_B0

8

VIN_B0

9

SW_B0

10

PGND_B01

11

SW_B1

12

VIN_B1

13

FB_B1

14

EN2

15

PGOOD

16

AGND

17

VANA

18

INT

19

NRST

20

FB_B3

21

VIN_B3

22

SW_B3

23

PGND_B23

24

SW_B2

25

VIN_B2

26

AGND

27

U1

LP87565ARNFRQ1

LP8756xQ1EVM Schematics

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The LP8756xQ1EVM Evaluation Module

Figure 33. LP87565Q1EVM Schematic

TP20

GND

1

2

X3

1725656

GND

1

2

TP21

1 2

X5

1725656

Vin_sense+ Vin_sense-

SDASYS

SCLSYS

INT

NRST

PGOOD

CLKIN

EN1

EN2

EN3

VIOSYS

TP8

TP9

TP10

TP11

TP12

TP13

TP16

TP19

TP18

GND

220µF

C30

GND

TP5 TP6

GND

Vin1

1

2

X1

1715721

0

J5

0

J4

DNP

NT1

Net-Tie

1 2

J3

GND

D1

100µF

C31

1 2 3 4

J1

0

J2

1 2

TP7

DNP

0.01

R5

VIN

Vin_sense+

Vin_sense-

GND GND GND

GND

0.1µF

C32

0.1µF

C29

DNP

0.1µF

C35

DNP

GND

22µF

C33

22µF

C34

High dI/dt Power Connectors

Output Power Connectors

1

2

X7

1715721

1

2

X8

1715721

1

2

X9

1715721

1

2

X10

1715721

VOUT0

VOUT1

VOUT3

VOUT2

VOUT1

VOUT0

VOUT3

GND GND

GNDGND

12 34 56

X4

6651712-1

DNP

12 34 56

X6

6651712-1

DNP

VOUT0

VOUT1

VOUT3

VOUT2

GNDGND

Feedback Connector

5 4

1

2

3

6

7

8

X2

GND

FB0

FB1

FB2

FB3

1.8k

R7

DNP

1.8k

R8

DNP

1.8k

R9

DNP

0R14 0R15 0R16 0R17 0R18

0R19

DNP

SDA SCL

HSI2C_SYS

0

R6

DNP

0R21 0R22

0R20

1.8k

R10

DNP

1 2

J7

1 2

J8

50

R23

DNP

VCC1V8

INTB2B

NRSTB2B

EN1B2B

EN2B2B

EN3B2B

PGOODB2B

CLKINB2B

SDASYS SCLSYS INT NRST PGOOD CLKIN EN1 EN2 EN3

EN1B2B

EN2B2B

EN1

EN2

CLKIN

GND

1.8k

R11

DNP

1.8k

R12

DNP

1.8k

R13

DNP

I/O signals

Current Measurement

TP17

GND

TP14 TP15

VDDA

VIOSYS

VIN

www.ti.com

LP8756xQ1EVM Schematics

35

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The LP8756xQ1EVM Evaluation Module

Figure 34. EVM Connectors

VUSB

15pF

C37

15pF

C38

GND GND

XOUT

XIN

DHSDM

0.1µF

C44

0.1µF

C43

0.1µF

C45

0.1µF

C42

0.1µF

C41

GND

10µF

C40

JTAGSEL

48

TCK/SWCLK

56

TDI

51

TDO/TRACESWO

54

TMS/SWDIO

55

U2C

ATSAM3U2CA-AU

GNDBU

46

ADVREF

2

AD12BVREF

4

GNDANA

3

GND

35

GND

61

GND

89

GNDPLL

72

VDDOUT

52

VDDIN

53

VDDIO

60

VDDIO

88

VDDCORE

9

VDDCORE

34

VDDANA

1

VDDBU

45

VDDPLL

73

VDDCORE

59

VDDCORE

83

VDDCORE

87

VDDIO

36

VDDIO

22

U2D

ATSAM3U2CA-AU

XOUT

XIN

GND

VUTMI

6.80k

R24

GND

10pF

C36

39.0

R26

39.0R25

GND

DHSDP

DHSDM

VBG

GND

0.1µF

C51

GND

10µF

C49

HSI2C_SYS

SCL SDA

PU_EN

HS_I2C

1.00k

R31

1.00k

R32

1µF

C61

GND

10µF

C57

1.00

R29

0.1µF

C56

+3.3V VUTMI

GND

10pF

C54

10µF

C55

DHSDP

VBUS_USB

0.1µF

C50

0.1µF

C52

0.1µF

C53

0.1µF

C48

GND

10µF

C47

TP22

PA0/PGMNCMD

26

PA1/PGMRDY

27

PA10/PGMD2

39

PA11/PGMD3

40

PA12/PGMD4

41

PA13/PGMD5

10

PA14/PGMD6

11

PA15/PGMD7

12

PA16/PGMD8

13

PA17/PGMD9

14

PA18/PGMD10

17

PA19/PGMD11

18

PA2/PGMNOE

28

PA20/PGMD12

19

PA21/PGMD13

20

PA22/PGMD14

5

PA23/PGMD15

21

PA24

23

PA25

24

PA26

25

PA27

96

PA28

84

PA29

85

PA3/PGMNVALID

29

PA30

6

PA31

86

PA4/PGMM0

30

PA5/PGMM1

31

PA6/PGMM2

32

PA7/PGMM3

33

PA8/PGMD0

37

PA9/PGMD1

38

PB0

90

PB1

91

PB10

70

PB11

93

PB12

94

PB13

95

PB14

69

PB15

16

PB16

15

PB17

68

PB18

67

PB19

66

PB2

92

PB20

65

PB21

64

PB22

63

PB23

62

PB24

58

PB3

7

PB4

8

PB5

97

PB6

98

PB7

99

PB8

100

PB9

71

U2A

ATSAM3U2CA-AU

DHSDP

76

DHSDM

77

FWUP

42

NRST

57

XOUT32

49

TST

44

ERASE

43

NRSTB

47

XIN32

50

XOUT

74

XIN

75

VBG

78

DFSDM

80

DFSDP

81

VDDUTMI

79

GNDUTMI

82

U2B

ATSAM3U2CA-AU

LDO1: 1.8 V (150 mA), VDDIO for SAM3U LDO2: 3.3 V (300 mA), 3.3V generic supply

IN

1

NC

7

EN12OUT2

9

EN2

3

DAP

11

POR

8

OUT1

10

SET

5

GND

6

CBYP

4

U3

LP3996SD-1833/NOPB

+3.3V

GND

GNDGND

VUSB

GND GND

0.01µF

C62

1µF

C60

1µF

C59

1µF

C58

470k

R30

GND

L8

LB2012T100KR

1

2

3

J10

HTSW-103-07-G-S

VIO +3.3V

+3.3V

VIO

VDDOUT

CLKINB2B

1V8out

D2 BAT42WS-7-F

68.0k

R27

VIO

0.1µF

C39

+3.3V

Diode for clamping voltage to IO level (1.8V/3.3V).

DFSDM DFSDP

12MHz

12

Y1

GND

0.1µF

C46

GND

8

9

VBUS

1

GND

5

6

7

D-

2

D+

3

ID

4

J9

1734035-2

GND

33.0k

R28

GND

VBUS_USB

SCL

HSI2C_SYS

SDA

HSI2C_SYS

PU_EN

VCC1V8

INTB2B

NRSTB2B

EN1B2B EN2B2B EN3B2B

PGOODB2B

I2C Pull-up

I/O supply

LP8756xQ1EVM Schematics

www.ti.com

36

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The LP8756xQ1EVM Evaluation Module

Figure 35. EVM I2C Interface

www.ti.com

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (October 2016) to A Revision .................................................................................................... Page

• Added caution graphic.................................................................................................................... 1

• Changed Changed number of outputs for LP87525Q1 from "5" to "2" ............................................................ 3

SNVU472A–October 2016–Revised February 2017

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Revision History

37

STANDARD TERMS FOR EVALUATION MODULES

1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.

1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions set forth herein but rather shall be subject to the applicable terms that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned, or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production system.

2 Limited Warranty and Related Remedies/Disclaimers:

2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License Agreement.

2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM. User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10) business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.

2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period.

3 Regulatory Notices:

3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:

FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.

3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTION

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

FCC Interference Statement for Class A EVM devices

NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense.

FCC Interference Statement for Class B EVM devices

NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

• Reorient or relocate the receiving antenna.

• Increase the separation between the equipment and receiver.

• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

• Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada

3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210

Concerning EVMs Including Radio Transmitters:

This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.

Concernant les EVMs avec appareils radio:

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:

Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.

Concernant les EVMs avec antennes détachables

Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur

3.3 Japan

3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。

http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified by TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs (which for the avoidance of doubt are stated strictly for convenience and should be verified by User):

1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けていないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。

1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。

2. 実験局の免許を取得後ご使用いただく。

3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。

上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・インスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/

/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

3.4 European Union

3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive): This is a class A product intended for use in environments other than domestic environments that are connected to a

low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.

4 EVM Use Restrictions and Warnings:

4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.

4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information related to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:

4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or property damage. If there are questions concerning performance ratings and specifications, User should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit components may have elevated case temperatures. These components include but are not limited to linear regulators, switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the information in the associated documentation. When working with the EVM, please be aware that the EVM may become very warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees, affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or designees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal, state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local requirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as accurate, complete, reliable, current, or error-free.

6. Disclaimers:

6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES, EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

8. Limitations on Damages and Liability:

8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s) will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s), excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas, without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES

Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice.

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