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LP87564Q1
User Manual
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Texas Instruments LP87561Q1, LP87565Q1, LP87562Q1, LP87563Q1, LP87564Q1 User Manual

User's Guide
SNVU472A–October 2016–Revised February 2017
The LP8756xQ1EVM Evaluation Module
Contents
1 Overview...................................................................................................................... 3
2 Quick Setup Guide........................................................................................................... 3
2.1 Installing/Opening the Software .................................................................................. 4
2.2 Power Supply Setup................................................................................................ 8
2.3 Notes on Efficiency Measurement Procedure................................................................. 12
3 GUI Overview............................................................................................................... 12
3.1 Main Tab ........................................................................................................... 12
3.2 Other Tabs and Menus ........................................................................................... 13
3.3 Console............................................................................................................. 20
4 Bill of Materials ............................................................................................................. 22
5 Board Layout................................................................................................................ 24
6 LP8756xQ1EVM Schematics............................................................................................. 30
1 LP8756xQ1EVM ............................................................................................................. 3
2 LP8756 Installer License Agreement...................................................................................... 4
3 Features of LP8756 Installation............................................................................................ 5
4 LP8756 Destination Folder ................................................................................................. 5
5 LP8756 Installation Complete.............................................................................................. 6
6 Evaluation Software Graphical User Interface (GUI) When Board Connected...................................... 7
7 Assert nRST.................................................................................................................. 8
8 Read Registers Buttons..................................................................................................... 9
9 BUCK0 Enabled............................................................................................................ 10
10 Assert EN1.................................................................................................................. 11
11 Accessing Direct Register Write.......................................................................................... 14
12 Direct Register Access View.............................................................................................. 15
13 Selecting Register Values................................................................................................. 16
14 Register Update Mode..................................................................................................... 17
15 Config Tab of the LP8756 GUI ........................................................................................... 18
16 Advanced Tab of LP8756 GUI ........................................................................................... 19
17 Opening Console........................................................................................................... 20
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18 Example of Command Use in Console.................................................................................. 21
19 Board Stack-Up............................................................................................................. 24
20 Top View of the LP8756xQ1EVM........................................................................................ 25
21 Component Placement Top Layer ....................................................................................... 25
22 Component Placement Bottom Layer ................................................................................... 26
23 Top Layer ................................................................................................................... 26
24 Mid-Layer1 ................................................................................................................. 26
25 Mid-Layer2 .................................................................................................................. 27
26 Mid-Layer3 .................................................................................................................. 27
27 Mid-Layer4, GND Plane................................................................................................... 28
28 Bottom Layer (note mirror view).......................................................................................... 28
29 LP87561Q1EVM Schematic.............................................................................................. 30
30 LP87562Q1EVM Schematic.............................................................................................. 31
31 LP87563Q1EVM............................................................................................................ 32
32 LP87564Q1EVM Schematic.............................................................................................. 33
33 LP87565Q1EVM Schematic.............................................................................................. 34
34 EVM Connectors ........................................................................................................... 35
35 EVM I
2
C Interface .......................................................................................................... 36
List of Tables
1 LP8756xQ1 Configurations................................................................................................. 3
2 Mode Information........................................................................................................... 13
3 I
2
C-Compatible Bus Support.............................................................................................. 13
4 Console Macros ............................................................................................................ 21
5 Bill of Materials for LP8756xQ1EVM .................................................................................... 22
Trademarks
All trademarks are the property of their respective owners.
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The LP8756xQ1EVM Evaluation Module
SNVU472A–October 2016–Revised February 2017
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1 Overview
The LP8756xQ1EVM customer evaluation module demonstrates the integrated circuit LP8756xQ1 from TI. The LP8756xQ1 is a high-performance, multi-phase step-down converter designed to meet the power management requirements of the latest applications processors and platform needs in automotive infotainment and cluster applications and also in automotive camera power applications. The device contains four step-down converter cores, which are bundled together in all possible configurations between single 4-phase buck converter and four single-phase buck converters. This document covers user software provided with the EVM and design documentation that includes schematics and parts list.
PART NUMBER OUTPUT CONFIGURATION NUMBER OF OUTPUTS EVM NUMBER
LP87561Q1 4-phase 1 LP87561Q1EVM LP87562Q1 3-phase + 1-phase 2 LP87562Q1EVM LP87563Q1 2-phase + 1-phase + 1-phase 3 LP87563Q1EVM LP87564Q1 4 × 1-phase 4 LP87564Q1EVM LP87565Q1 2-phase + 2-phase 2 LP87565Q1EVM
Overview
Table 1. LP8756xQ1 Configurations
2 Quick Setup Guide
Many of the components on the LP8756xQ1 are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
Upon opening the LP8756xQ1EVM package, ensure that the following items are included:
• LP8756xQ1 Evaluation Board
• USB Cable
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Figure 1. LP8756xQ1EVM
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Quick Setup Guide
If any of the items are missing, contact the closest Texas Instruments Product Information Center to inquire about a replacement.
2.1 Installing/Opening the Software
The EVM software is controlled through a graphical user interface (GUI). The software communicates with the EVM through an available USB port. The minimum hardware requirements for the EVM software are:
• IBM PC-compatible computer running a Microsoft Windows® XP or newer operating system
• Available USB port
• Mouse Software installation
1. Open the LP8756_installer.exe
2. Installer prompts to accept the license agreement (see Figure 2).
3. Installer prompts to choose which features of LP8756x Installer you want to install (see Figure 3).
4. Installer prompts to select Destination Folder (see Figure 4).
5. Press Install and the installation starts.
6. Installer prompts when installation is complete (see Figure 5). Open the LP8756x GUI. Connect the EVM to the PC with the USB cable.
1. With the power supply disconnected from the unit under test (UUT), open LP8756EVM.exe located in
the directory selected during installation.
2. On the Evaluation SW window bottom right corner you should see text “Hardware connected.”. Refer
to Figure 6.
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Figure 2. LP8756 Installer License Agreement
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Quick Setup Guide
Figure 3. Features of LP8756 Installation
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Figure 4. LP8756 Destination Folder
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Quick Setup Guide
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Figure 5. LP8756 Installation Complete
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Quick Setup Guide
Figure 6. Evaluation Software Graphical User Interface (GUI)
When Board Connected
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Quick Setup Guide
2.2 Power Supply Setup
To power up the EVM, one power supply is needed. For full-load testing of the LP8756xQ1EVM, a DC­power supply capable of at least 10 A and 4 V is required. 5 A is suggested as a practical minimum for partial load. The power supply is connected to the EVM using connector X1. The power supply and cabling must present low impedance to the UUT; the length of power supply cables must be minimized. Remote sense, using connector X3, can be used to compensate for voltage drops in the cabling.
With the power supply disconnected from the UUT, set the supply to 3.7 V DC and the current limit to 5 A minimum. Set the power supply output OFF. Connect the power supply's positive terminal (+) to VIN and negative terminal (–) to GND on UUT (X1 power-in terminal block). Check that jumpers on the boards are set as shown in Figure 1 (factory default jumper configuration).
Set power supply output ON, and then continue with the following steps. Note that following steps is only an example. Register values, enable control, mode and multiphase status may differ depending on the LP8756xQ1EVM configuration.
1. On Evaluation software GUI, click on Assert NRST (see Figure 7).
2. Click on either of the two Read Registers buttons. You should see ready message on green
background next to the Read Registers button (see Figure 8).
3. Check that Buck0 is enabled (see Figure 9).
4. Click on Assert EN1 (see Figure 10).
5. Click on either of the two Read Registers buttons.
6. In this example case the GUI indicates "Disabled" under "Mode" until EN1 is asserted. After EN1 is
asserted "Mode" is changed to "Enabled". In case BUCKx is enabled or disabled with bit instead of ENx pin, the "Mode" can be checked by reading registers. GUI indicates also "Master" under "Multiphase status" of Buck 0. Mode of other bucks are "Disabled" and Multiphase status is "Slave to Buck0". The EVM is now ready for testing with default register settings loaded.
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The LP8756xQ1EVM Evaluation Module
Figure 7. Assert nRST
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Quick Setup Guide
Figure 8. Read Registers Buttons
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Quick Setup Guide
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Figure 9. BUCK0 Enabled
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Quick Setup Guide
Figure 10. Assert EN1
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Quick Setup Guide
2.3 Notes on Efficiency Measurement Procedure
Output Connections: An appropriate electronic load or high-power system source meter instrument, specified for operation down to 500 mV, is desirable for loading the UUT. The maximum load current is specified as 4 A per phase. Be sure to choose the correct wire size when attaching the electronic load. A wire resistance that is too high will cause a voltage drop in the power distribution path which becomes significant compared to the absolute value of the output voltage. Connect an electric load to X7, X8, X9 and/or X10. It is advised that, prior to connecting the load, it be set to sink 0 A to avoid power surges or possible shocks.
Voltage drop across the PCB traces will yield inaccurate efficiency measurements. For the most accurate voltage measurement at the EVM, use TP7 to measure the input voltage and X2 to measure the output voltage.
To measure the current flowing to/from the UUT, use the current meter of the DC power supply/electric load as long as it is accurate. Some power source ammeters may show offset of several milliamps and thus will yield inaccurate efficiency measurements. In order to perform very accurate Iqmeasurements on the UUT, disconnect input protective Zener diode D1 by removing the shunt J3 from the board. When connected, this diode will cause some leakage, especially on high VIN voltages.
3 GUI Overview
The evaluation software has the following tabs: Main, Config, and Advanced. The three tabs together provide the user access to the whole register map of the LP8756x. Additional register control can be obtained from Tools --> Direct Register Access.
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3.1 Main Tab
The Main tab (see for example Figure 10) has the elemental controls for the EVM and provides a view to the chip status. Starting from top, the main controls are:
• I2C mode or 4 Enable mode. If this states I2C mode, device is controlled with I2C. When this states
4EN mode, bucks are controlled with ENx pins.
• Assert NRST: This checkbox will assert high level to LP8756xQ1 NRST pin. This pin enables the chip
internal voltage reference and bias circuitry.
• Assert EN1: This checkbox will assert high level to LP8756xQ1 EN1 pin. Asserting EN1 may enable
the buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN2: This checkbox will assert high level to LP8756xQ1 EN2 pin. Asserting EN2 may enable
the buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN3: This checkbox will assert high level to LP8756xQ1 EN3 pin. Asserting EN3 may enable
the buck regulator(s) or switch to different output voltage level, depending on the register settings.
• Assert EN4: In 4 Enable mode, this checkbox will assert high level to LP8756x SCL pin, (alternative
function is EN4). Asserting EN4 may enable the buck regulator(s), depending on the register settings. This checkbox is visible only when device is configured to 4 Enable Signal Mode.
• Assert SW Reset: To perform a complete SW reset to the chip, assert this checkbox. See the LP8756
datasheet for explanation of LP8756 reset scenarios.
NOTE: The recommended start-up sequence for LP8756xQ1 is to first assert NRST, then write all
needed configuration bits by using the GUI, and then enable buck regulator(s) by ENx pin or EN_BUCKx bit.
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The "Bucks" section provides status information and enable controls for all the 4 buck cores. On the left of the section are the check-boxes for the buck enable bits. The "Mode" field provides information on each of the buck core and can have any of the values given in Table 2:
The "Multiphase status" info field tells whether a buck core is configured as a master or a slave. The "Current" field gives the result of the buck converter load current measurement operation. Output currents of each buck core and total output current of master(s) are shown on the fields.
The "System Flags / Interrupts" section as well as the "Interrupt bits" and the "Status bits" sections give data on system faults and warnings. If the interrupt is set for any reason the Interrupt active field shall show ‘1’ on red background. The flag causing the interrupt will also be set on the Main tab. Interrupts on LP8756xQ1 can only be cleared by writing '1’ to associated registers. Any individual flag can be cleared by clicking the "Clear" button next to each flag field. Some of the flags also have a mask bits. If "Mask" check-box of certain flag is checked, the interrupt is not generated. The "Status" bits will show the current status of the faults.
The "Power Good" section is for Power Good pin control and indication. It includes the latched values of buck Power Good Faults. These can be cleared with the Clear -button.
At the bottom of the GUI window is the "Auto Write" checkbox. If "Auto Write" is checked (default) any checking, un-checking or pulldown menu selections will immediately launch I2C writes to the chip register(s). If not checked, the user can update the chip registers to correspond the configuration selected on the GUI by clicking "Write Registers".
If "Poll Status" is selected the software sends a query to the LP8756 at a fixed interval in order to detect the status of the chip, including operation mode, multi-phase status, and output current. If also the "Poll Only Pins" is selected the software is monitoring only the state of Interrupt and Powergood pins. If "Poll Status" is not selected or if "Poll Only Pins" is selected, user can read the registers by applying "Read Registers". "Bus Speed" pulldown menu selections are given in Table 3 below and is instantly applied for System I2C.
GUI Overview
Table 2. Mode Information
BUCK MODE
Disabled Buck state machine in 'disable' Enabled Buck state machine in 'enable'
BUS SPEED SELECTION EXPLANATION
Fast (400 kHz) Fast I2C-compliant operation at 400 kHz High-Speed (3.4 MHz) HS I2C-compliant data transfer with master codes.
3.2 Other Tabs and Menus
The "Tools" pulldown menu hosts another way of accessing the LP8756xQ1 registers (see Figure 11). The "Direct Register Access" tool can be used to read or write any register (see Figure 12). Selecting a register, the bits appear on the right side Field View (see Figure 13). When moving mouse over bits in Field View, bits are highlighted in the register view. Bits can be controlled either from register view or field view. Register settings can also be saved to a file or pre-made register file can be loaded in the Direct Register Access tool. Registers can be updated immediately or manually (see Figure 14).
When using direct register access, TI recommends un-checking the poll status check-box. This way the GUI will only do the reads and writes commanded from the direct access dialog.
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Table 3. I2C-Compatible Bus Support
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