Texas Instruments LP8728EVM User Manual

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Using the LP8728EVM Evaluation Module

User's Guide

Literature Number: SNVU231

August 2013

Chapter 1

SNVU231–August 2013

Introduction

The Texas Instruments' LP8728EVM evaluation module (EVM) helps designers evaluate the operation and performance of this device. The LP8728EVM uses the LP8728’s four buck converters to provide 3.3 V, 2.65 V, 1.8 V, and 1.25 V output voltages. Information about output voltage and current ratings of the LP8728 can also be found in the LP8728 datasheet.

In order to facilitate ease of testing and evaluation of this circuit, the LP8728EVM contains screw-in terminals for the VIN and all four VOUT connections. Dual connectors are provided for easy four-wire connection.

For evaluation purposes, the LP8728EVM has been tested over a 4.5 V to 5.5 V input range. Users are cautioned to evaluate their specific operating conditions and choose components with the appropriate voltage ratings before designing in LP8728 into a final product.

Introduction SNVU231–August 2013

Figure 1-1. LP8728EVM

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LP8728

FB_B1

SW_B1

OUT1

FB_B2

SW_B2

OUT2

FB_B3

SW_B3

OUT3

FB_B4

SW_B4

OUT4

1.5µH

AGND

GND_B1

GND_B2

GND_B3

GND_B4

EN_B1 EN_B2 EN_B3 EN_B4

PG_B1 PG_B2 PG_B3 PG_B4

Micro

Controller

DEFSEL

AVDD

BYP

VIN_B1

VIN_B2

1.5µH

VIN_B3

VIN_B4

VDDIO

1µF

1µF 10µF

10µF

The LP8728 is a quad output Power Management Unit, optimized for low power FPGAs, microprocessors, and DSPs. This device integrates four highly efficient step-down DC/DC converters into one package. All the converters run at fixed 3.3 MHz switching frequency. Buck converters switching is phase shifted to minimize the input current spiking.

2.1 Features

• Four High-Efficiency Step-Down DC/DC Converters – Max output current 1.0 A – Forced PWM operation – Soft-start control – V

OUT1

– V

OUT2

– V

OUT3

– V

OUT4

• Separate Enable Inputs for each Converter Control

• Separate Power Good Outputs for each Converter

• Output Over-Current and Input Over-Voltage Protection

• Over-Temperature Protection

• Under-Voltage Lockout (UVLO)

• 28-pin 0.5 mm Pitch QFN Package

Chapter 2

SNVU231–August 2013

Description of LP8728

= 3.3 V

- 1.25 V = 1.8 V or 2.65 V (pin selectable) = 1.8 V

2.2 Applications

• Automotive Systems

SNVU231–August 2013 Description of LP8728

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Figure 2-1. Typical Application

Chapter 3

SNVU231–August 2013

LP8728EVM Setup

Figure 3-1 shows the LP8728EVM with input and output connectors and main components on the board.

Input power supply is connected to VIN connectors. Two connectors are provided for easy 4-wire connection. A force line should be connected to connector X1 terminals VIN and GND. Sense wires should be connected to connector X2 terminals VINS and GNDS. If a two-wire connection is used, wires should be connected to connector X1 VIN and GND only. Input voltage needs to be set between 4.5 V to

5.5 V.

Two connectors are also provided for each buck output. This is useful, for example, when connecting the source meter in 4-wire mode for accurate IOUT vs VOUT measurement. Two output terminals are connected in parallel so either one can be used for sense or force lines.

Connector X3 terminals VDDIOX and GND can be used to connect separated pull-up voltage for the EN_Bx and DEFSEL pins. If separated pull-up voltage is not desired, input pins can be pulled up to VIN voltage. Pull-up voltage is selected by changing the shunt position on the J2 terminal. Connecting shunt between VDDIO and VDDIOX selects VDDIOX as the pull-up voltage. Connecting a shunt between VDDIO and AVDD selects VIN as the pull-up voltage.

Extra test points are placed close to the buck output capacitors for convenient probe points for an oscilloscope. Similar test points are also placed close to each input voltage pin (VIN_Bx and AVDD).

Figure 3-1. Evaluation Board Connectors and Setup

LP8728EVM Setup SNVU231–August 2013

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Chapter 4

SNVU231–August 2013

Board Layout

Figure 4-1. Layer 1 Top (Signal)

Figure 4-2. Layer 2 (GND) (Picture in reverse colors)

SNVU231–August 2013 Board Layout

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Figure 4-3. Layer 2 (GND / VIN)

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Board Layout SNVU231–August 2013

Figure 4-4. Layer 4 Bottom (Signal)

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Figure 4-5. Close-up of the LP8728 and Main External Components

SNVU231–August 2013 Board Layout

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Figure 5-1. Evaluation Board Stackup

Details:

• 4-layer board FR4

• Top layer 1 - copper, 35µm

• Prepreg 0.1 mm

• Internal Layer 2, 35 µm

• Core 0.7 mm

• Ground plane Layer 3, 35 µm

• Prepreg 0.1 mm

• Bottom Layer 4 - copper, 35 µm

• Surface finish immersion gold

Chapter 5

SNVU231–August 2013

Board Stackup

Board Stackup SNVU231–August 2013

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The LP8728 has four enable pins (EN_Bx). When any of the enable pins are pulled high, the device activates and starts up corresponding the buck converter (EN_B1 controls buck1, EN_B2 controls buck2, etc). When all EN_Bx pins are low, the device goes to shutdown mode.

DEFSEL is used to select buck 3 output voltage. If the DEFSEL pin is pulled high, buck 3 output voltage is set to 2.65 V. If DEFSEL pin is set low, buck 3 output voltage is set to 1.8 V

EN_Bx pins and the DEFSEL pin have internal pull-down resistors (500 kΩ) which will set the state to low when the EN input is floating.

Power good outputs indicate the status of each buck converter. Once buck output voltage reaches 96% (typ) of the desired output voltage, the power good pin is pulled high. If output voltage drops below 93% (typ) of desired output voltage due to, for example, an overload condition, the corresponding power good pin is set low.

6.1 LP8728EVM Control Interface

Chapter 6

SNVU231–August 2013

Controls

All LP8728 digital input and out signals are routed to 20-pin connector (J3) pins. Pins closer to PCB edge go straight to the LP8728 digital pins. These pins can be used to connect LP8728 pins to any external source (signal generators, external controllers, etc). For simple enable / disable operation pull-up resistors are connected to adjacent pins of the digital inputs. This allows enabling the bucks by setting shunts between the J3 pins.

Indicator LEDs are provided for power good signals PG_Bx. LEDs are connected between VIN and PG_Bx pin so the LED illuminates when power good signal is low (buck is disabled or output voltage out of regulation). Indicator LEDs can be disconnected from the PG_Bx pins by removing the shunts form connector J3.

SNVU231–August 2013 Controls

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Figure 6-1. LP8728EVM Control Pins

Chapter 7

SNVU231–August 2013

Evaluation Board Schematic

Evaluation Board Schematic SNVU231–August 2013

Figure 7-1. Evaluation Board Schematic

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Chapter 8

SNVU231–August 2013

Bill of Materials

Designator QTY Value Description Package Part Number Manufacturer

C001, C003 2 1uF 0603 C1608X7R1C105K TDK

C1, C2 2 22uF 1812 TDK

C002, C27, C102,

C111, C202, C211, C302, 10 0.1uF 0603 C1608X7R1C104K TDK C311, C402,

C411

C101, C110, C201, C210, CAP, CERM, 10uF, 10V, GRM21BR71A106K C301, C310, +/-10%, X7R E51L

C401, C410

D1, D2, D3, D4 4 Orange LED, Orange, SMD 1.6x0.8x0.8mm LTST-C190KFKT Lite-On

J1 1 TSW-102-07-G-S TSW-102-07-G-S Samtec, Inc.

J2 1 TSW-103-07-G-S TSW-103-07-G-S Samtec, Inc.

J3 1 TSW-110-07-G-D TSW-110-07-G-D Samtec, Inc.

L1, L2, L3, L4 4 1.5uH 1.1uH 2.0x2.5x1.2 MDT2520-CN1R5M Toko

R1 1 0.01 High Power Current Sense 2512 Bourns

R2, R3, R4, R5, R6, R7, R8, R9, 9 1.8k 0603 Vishay-Dale

R10

U1 1 LP8728 QFN-28 LP8728

X1, X2, X3, X4, X5, X6, X7, X8, 11 2x1 1715721 Phoenix Contact

X9, X10, X11

8 10uF 0805 MuRata

CAP, CERM, 1uF, 16V, +/-

10%, X7R

CAP, CERM, 22uF, 16V, CGA8N3X7R1C226

+/-20%, X7R M

CAP, CERM, 0.1uF, 16V,

+/-10%, X7R

Header, 100mil, 2x1, Gold

Header, 100mil, 3x1, Gold

Header, 100mil, 10x2, Gold

RES, 0.01 ohm, 1%, 3W,

RES, 1.8k ohm, 5%, 0.1W, CRCW06031K80JN

Conn Term Block, 2POS, PhoenixContact_171

plated

Chip Resistor

0603 EA

5.08mm, TH 5721

CRA2512-FZ-

R010ELF

Texas

Instruments

SNVU231–August 2013 Bill of Materials

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Texas Instruments LP8728EVM User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual