TEXAS INSTRUMENTS INA121 Technical data

®

INA121

INA121

FET-Input, Low Power

INSTRUMENTATION AMPLIFIER

INA121

FEATURES

● LOW BIAS CURRENT: ±4pA

● LOW QUIESCENT CURRENT:

● LOW INPUT OFFSET VOLTAGE:

● LOW INPUT OFFSET DRIFT:

±450µA

±200µV

±2µV/°C

● LOW INPUT NOISE:
20nV/√Hz at f = 1kHz (G =100)

● HIGH CMR: 106dB

● WIDE SUPPLY RANGE:

±2.25V to ±18V

● LOW NONLINEARITY ERROR: 0.001% max

● INPUT PROTECTION TO

±40V

● 8-PIN DIP AND SO-8 SURFACE MOUNT

APPLICATIONS

● LOW-LEVEL TRANSDUCER AMPLIFIERS

Bridge, RTD, Thermocouple

● PHYSIOLOGICAL AMPLIFIERS

ECG, EEG, EMG, Respiratory

● HIGH IMPEDANCE TRANSDUCERS

● CAPACITIVE SENSORS

● MULTI-CHANNEL DATA ACQUISITION

● PORTABLE, BATTERY OPERATED SYSTEMS

● GENERAL PURPOSE INSTRUMENTATION

2

R

G

1

8

3

Over-Voltage

Protection

Over-Voltage

Protection

A

A

–

V

IN

+

V

IN

DESCRIPTION

The INA121 is a FET-input, low power instrumenta­tion amplifier offering excellent accuracy. Its versatile
three-op amp design and very small size make it ideal
for a variety of general purpose applications. Low bias
current (±4pA) allows use with high impedance
sources.

Gain can be set from 1V to 10,000V/V with a single
external resistor. Internal input protection can with­stand up to ±40V without damage.

The INA121 is laser-trimmed for very low offset
voltage (±200µV), low offset drift (±2µV/°C), and
high common-mode rejection (106dB at G = 100). It
operates on power supplies as low as ±2.25V (+4.5V),
allowing use in battery operated and single 5V sys­tems. Quiescent current is only 450µA.

Package options include 8-pin plastic DIP and SO-8
surface mount. All are specified for the –40°C to
+85°C industrial temperature range.

V+

7

INA121

1

2

25kΩ

25kΩ

40kΩ40kΩ

A

3

40kΩ40kΩ

G = 1 +

6

V

O

5

Ref

50kΩ

R

G

SBOS078

4

V–

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

®

©1997 Burr-Brown Corporation PDS-1412A Printed in U.S.A. May, 1998

1

INA121

SPECIFICATIONS: VS = ±15V

At TA = +25°C, VS = ±15V, RL = 10kΩ, and IA reference = 0V, unless otherwise noted.

INA121P, U INA121PA, UA
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
INPUT

Offset Voltage, RTI ±200±200/G ±500±500/G ±300±200/G

vs Temperature ±2±2/G ±5±20/G ✻ ±15±20/G µV/°C
vs Power Supply V
Long-Term Stability ±0.5 ✻ µV/mo

Impedance, Differential 10

Common-Mode V

Input Voltage Range See Text and Typical Curves ✻

= ±2.25V to ±18V ±5±20/G ±50±150/G ✻✻µV/V

S

12

|| 1 ✻ Ω || pF

= 0V 10

O

12

|| 12 ✻ Ω || pF

Safe Input Voltage ±40 ✻ V
Common-Mode Rejection V

= –12.5V to 13.5V

CM

G = 1 78 86 7 2 ✻ dB

G = 10 91 100 85 ✻ dB

G = 100 96 106 90 ✻ dB

G = 1000 106 ✻ dB

BIAS CURRENT V

vs Temperature See Typical Curve ✻

= 0V ±4 ±50 ✻✻pA

CM

Offset Current ±0.5 ✻ pA

vs Temperature See Typical Curve ✻

NOISE, RTI R
Voltage Noise: f = 10Hz G = 100 30 ✻ nV/√Hz

S

= 0Ω

f = 100Hz G = 100 21 ✻ nV/√Hz
f = 1kHz G = 100 20 ✻ nV/√Hz
f

= 0.1Hz to 10Hz G = 100 1 ✻ µVp-p

Current Noise: f = 1kHz 1 ✻ fA/√Hz

GAIN

Gain Equation 1 + (50kΩ/R
Range of Gain 1 10,000 ✻✻V/V
Gain Error V

= –14V to 13.5V

O

G = 1 ±0.01 ±0.05 ✻ ±0.1 %

) ✻ V/V

G

G = 10 ±0.03 ±0.4 ✻ ±0.5 %

G = 100 ±0.05 ±0.5 ✻ ±0.7 %

Gain vs Temperature

(1)

G = 1000 ±0.5 ✻ %

G = 1 ±1 ±10 ✻✻ppm/°C
G > 1 ±25 ±100 ✻✻ppm/°C

Nonlinearity V

= –14V to 13.5V

O

G = 1 ±0.0002 ±0.001 ✻ ± 0.002 % of FSR

G = 10 ±0.0015 ±0.005 ✻ ± 0.008 % of FSR

G = 100 ±0.0015 ±0.005 ✻ ±0.008 % of FSR

G = 1000 ±0.002 ✻ % of FSR

OUTPUT

Voltage: Positive R

Negative R
Positive R
Negative R

Capacitance Load Drive 1000 ✻ pF

= 100kΩ (V+)–0.9 ✻ V

L

= 100kΩ (V–)+0.15 ✻ V

L

= 10kΩ (V+)–1.5 (V+)–0.9 ✻✻ V

L

= 10kΩ (V–)+1 (V–)+0.25 ✻✻ V

L

Short-Circuit Current ±14 ✻ mA

FREQUENCY RESPONSE

Bandwidth, –3dB G = 1 600 ✻ kHz

G = 10 300 ✻ kHz

G = 100 50 ✻ kHz

G = 1000 5 ✻ kHz
Slew Rate V
Settling Time, 0.01% G = 1 to 10 20 ✻ µs

= ±10V, G ≤ 10 0.7 ✻ V/µs

O

G = 100 35 ✻ µs

G = 1000 260 ✻ µs
Overload Recovery 50% Input Overload 5 ✻ µs

POWER SUPPLY

Voltage Range ±2.25 ±15 ±18 ✻✻ ✻ V
Quiescent Current I

= 0V ±450 ±525 ✻✻µA

O

TEMPERATURE RANGE

Specification –40 85 ✻✻°C
Operating –55 125 ✻✻°C
Storage –55 125 ✻✻°C
Thermal Resistance,

8-Lead DIP 100 ✻ °C/W

θ

JA

SO-8 Surface Mount 150 ✻ °C/W

✻ Specification same as INA121P, U.
NOTE: (1) Temperature coefficient of the “Internal Resistor” in the gain equation. Does not include TCR of gain-setting resistor, R

±1000±1000/G

.

G

µV

®

INA121

2

PIN CONFIGURATION

Top View 8-Pin DIP and SO-8

ELECTROSTATIC
DISCHARGE SENSITIVITY

Top View

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with

1

R

G

–

2

V

IN

+

3

V

IN

4

V–

8

R

G

7

V+

6

V

O

5

Ref

appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage .................................................................................. ±18V

Analog Input Voltage Range ............................................................. ±40V

Output Short-Circuit (to ground) .............................................. Continuous

Operating Temperature ................................................. –55°C to +125°C

Storage Temperature ..................................................... –55°C to +125°C

Junction Temperature.................................................................... +150°C

Lead Temperature (soldering, 10s)............................................... +300°C

NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.

(1)

PACKAGE/ORDERING INFORMATION

PACKAGE SPECIFIED

PRODUCT PACKAGE NUMBER(1) RANGE MARKING NUMBER(2) MEDIA
Single

INA121P 8-Pin DIP 006 –40°C to +85°C INA121P INA121P Rails
INA121PA 8-Pin DIP 006 –40°C to +85°C INA121PA INA121PA Rails
INA121U SO-8 Surface-Mount 182 –40°C to +85°C INA121U INA121U Rails

" " " " " INA121U/2K5 Tape and Reel

INA121UA SO-8 Surface-Mount 182 –40°C to +85°C INA121UA INA121UA Rails

" " " " " INA121UA/2K5 Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “INA121U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

3

INA121

®

TYPICAL PERFORMANCE CURVES

At TA = +25°C, VS = ±15V, unless otherwise noted.

60

G = 1000V/V

50
40

G = 100V/V

30
20

G = 10V/V

Gain (dB)

10

0

G = 1V/V

–10
–20

1k 10k 1M 10M100k

GAIN vs FREQUENCY

Frequency (Hz)

COMMON-MODE REJECTION

120

100

80

60

40

20

Common-Mode Rejection (dB)

0

10 100 10k 100k 1M1k

vs FREQUENCY

G = 1000V/V

G = 100V/V

G = 10V/V

G = 1V/V

Frequency (Hz)

POSITIVE POWER SUPPLY REJECTION

120

100

80

60

40

Power Supply Rejection (dB)

20

0

10 100 10k 100k 1M1k

INPUT COMMON-MODE RANGE

vs OUTPUT VOLTAGE, V

15

10

5

0

–5

Common-Mode Voltage (V)

–10

V

D/2

V

D/2

+

V

CM

–15

–15 –10 0 5 15–5

vs FREQUENCY

Frequency (Hz)

+15V

+
–

+
–

Ref

–15V

Output Voltage (V)

G = 1V/V

= ±15V

S

V

O

G = 1000V/V

G = 100V/V

G = 10V/V

G = 1
G ≥ 10

10

NEGATIVE POWER SUPPLY REJECTION

120

G = 100V/V

100

80

G = 1000V/V

G = 10V/V

G = 1V/V

60

40

Power Supply Rejection (dB)

20

0

10 100 10k 100k 1M1k

INPUT COMMON-MODE RANGE

vs OUTPUT VOLTAGE, V

5
4
3
2

G ≥ 10

G = 1

1

0
–1
–2
–3

Common-Mode Voltage (V)

–4
–5

VS = ±5V

= ±2.5V

V

S

–5

–4 –3 –2 –1 0 1 2 3 4 5

vs FREQUENCY

Frequency (Hz)

G ≥ 10

G = 1

Output Voltage (V)

= ±5V, ±2.5V

S

®

INA121

4

TYPICAL PERFORMANCE CURVES (CONT)

INPUT BIAS CURRENT

vs COMMON-MODE INPUT VOLTAGE

1m

100µ

10µ

10p

1p

–10µ

–100µ

–1m

–20 –15 –10 –5 0 5 10 15 20

Common-Mode Voltage (V)

Input Bias Current (A)

At TA = +25°C, VS = ±15V, unless otherwise noted.

10k

INPUT BIAS CURRENT vs TEMPERATURE

1k

100

10

I

1

Bias Current (pA)

0.1

B

I

OS

0.01
–75 –50 –25 0 25 50 75 100 125

Temperature (°C)

INPUT OVER-VOLTAGE V/I CHARACTERISTICS

1

0.8

0.6

0.4

0.2

–0.2
–0.4

Input Current (mA)

–0.6
–0.8

Flat region represents
normal linear operation.

0

G = 1V/V

–1

–50 –40 –30 –20 –10 10 20 30 40050

G = 1000V/V

V

IN

Input Voltage (V)

I

IN

G = 1V/V

G = 1000V/V

+15V

–15V

1000

SETTLING TIME vs GAIN

0.01%

100

0.1%

Settling Time (µs)

10

1 10 100 1000

Gain (V/V)

QUIESCENT CURRENT AND SLEW RATE

500

475

450

425

Quiescent Current (µA)

400

375

–75 –50 –25 0 25 50 75 100 125

vs TEMPERATURE

I

Q

Temperature (°C)

SR

1.4

1.2

1

0.8

0.6

0.4

±15

±14

±13

Slew Rate (V/µs)

±12

Short-Circuit Current (µA)

±11

±10

–75 –50 –25 0 25 50 75 100 125

5

SHORT-CIRCUIT CURRENT

vs TEMPERATURE

+I

SC

–I

SC

Temperature (°C)

INA121

®

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VS = ±15V, unless otherwise noted.

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT

V+
(V+) –0.3
(V+) –0.6
(V+) –0.9
(V+) –1.2
(V+) –1.5
(V–) +1.5
(V–) +1.2
(V–) +0.9

Output Voltage Swing (V)

(V–) +0.6
(V–) +0.3

(V–)

0 ±2 ±4 ±6 ±8 ±10

10

8
6
4
2

0
–2
–4
–6

Offset Voltage Change (µV)

–8

–10

0

+85°C

+25°C
–40°C, –55°C

+125°C

+125°C

+85°C

Output Current (mA)

INPUT OFFSET VOLTAGE WARM-UP

100

200

Time (µs)

+25°C

–40°C, –55°C

300

400

500

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

30

25

G = 1

20

15

10

5

Peak-to-Peak Output Voltage (Vp-p)

0

100 1k 10k 100k 1M

18
16
14
12
10

8
6

Percent of Units (%)

4
2
0

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

G = 10 to 100

G = 1000

Frequency (Hz)

INPUT OFFSET VOLTAGE DRIFT

PRODUCTION DISTRIBUTION

Typical production
distribution of
packaged units.

Offset Voltage Drift (µV/°C)

INPUT-REFERRED NOISE VOLTAGE

1000

100

10

Voltage Noise (nV/√Hz)

1

1 10 1k 10k100

®

INA121

vs FREQUENCY

Frequency (Hz)

G = 1

G = 10

G = 1000

(BW Limit)

G = 100

VOLTAGE NOISE 0.1 TO 10Hz

INPUT-REFERRED, G ≥ 100

0.5µV

1s/div

6

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VS = ±15V, unless otherwise noted.

G = 1

50mV/div

G = 10

G = 1

SMALL-SIGNAL STEP RESPONSE

(G = 1, 10)

10µs/div

LARGE-SIGNAL STEP RESPONSE

(G = 1, 10)

SMALL-SIGNAL STEP RESPONSE

(G = 100, 1000)

G = 100

50mV/div

G = 1000

100µs/div

LARGE-SIGNAL STEP RESPONSE

(G = 100, 1000)

G = 100

5V/div

G = 10

100µs/div

5V/div

G = 1000

100µs/div

®

7

INA121

APPLICATION INFORMATION

Figure 1 shows the basic connections required for operation
of the INA121. Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the device pins as shown.

The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low-impedance
connection to assure good common-mode rejection. A resis­tance of 8Ω in series with the Ref pin will cause a typical
device to degrade to approximately 80dB CMR (G = 1).

SETTING THE GAIN

Gain of the INA121 is set by connecting a single external
resistor, R

Commonly used gains and resistor values are shown in
Figure 1.

, connected between pins 1 and 8:

G

G = 1+

50 kΩ

R

G

(1)

The 50kΩ term in Equation 1 comes from the sum of the two
internal feedback resistors of A

and A2. These on-chip

1

metal film resistors are laser trimmed to accurate absolute
values. The accuracy and temperature coefficient of these
resistors are included in the gain accuracy and drift specifi­cations of the INA121.

The stability and temperature drift of the external gain
setting resistor, R

, also affects gain. RG’s contribution to

G

gain accuracy and drift can be directly inferred from the gain
equation (1). Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring
resistance which will contribute additional gain error (possi­bly an unstable gain error) in gains of approximately 100 or
greater.

DYNAMIC PERFORMANCE

The typical performance curve “Gain vs Frequency” shows
that, despite its low quiescent current, the INA121 achieves
wide bandwidth, even at high gain. This is due to the
current-feedback topology of the INA121. Settling time also
remains excellent at high gain.

V+

0.1µF

DESIRED R

GAIN (Ω )(Ω)

1NC NC
2 50.00k 49.9k

5 12.50k 12.4k
10 5.556k 5.62k
20 2.632k 2.61k
50 1.02k 1.02k

100 505.1 511
200 251.3 249

500 100.2 100
1000 50.05 49.9
2000 25.01 24.9
5000 10.00 10

10000 5.001 4.99

NC: No Connection.

G

NEAREST 1% R

7

2

Over-Voltage

–

V

IN

G

+

V

IN

–

V

IN

+

V

IN

Protection

1

R

G

8

3

Over-Voltage

Protection

Also drawn in simplified form:

R

INA121

G

Ref

A

1

25kΩ

25kΩ

A

2

V

O

INA121

+

50kΩ

R

–

G

+

V

O

–

= G • (VIN – VIN)

V

40kΩ40kΩ

A

3

40kΩ40kΩ

4

0.1µF

V–

O

G = 1 +

6

Load

5
Ref

FIGURE 1. Basic Connections.

®

INA121

8

The INA121 provides excellent rejection of high frequency

common-mode signals. The typical performance curve,

“Common-Mode Rejection vs Frequency” shows this be-

havior. If the inputs are not properly balanced, however,

common-mode signals can be converted to differential sig-

nals. Run the V

+

IN

and V

–

connections directly adjacent each

IN

other, from the source signal all the way to the input pins. If

possible use a ground plane under both input traces. Avoid

running other potentially noisy lines near the inputs.

NOISE AND ACCURACY PERFORMANCE

The INA121’s FET input circuitry provides low input bias

current and high speed. It achieves lower noise and higher

accuracy with high impedance sources. With source imped-

ances of 2kΩ to 50kΩ the INA114, INA128, or INA129 may

provide lower offset voltage and drift. For very low source

impedance (≤1kΩ), the INA103 may provide improved

accuracy and lower noise. At very high source impedances

(> 1MΩ) the INA116 is recommended.

OFFSET TRIMMING

The INA121 is laser trimmed for low offset voltage and

drift. Most applications require no external offset adjust-

ment. Figure 2 shows an optional circuit for trimming the

output offset voltage. The voltage applied to Ref terminal is

summed at the output. The op amp buffer provides low

impedance at the Ref terminal to preserve good common-

mode rejection. Trim circuits with higher source impedance

should be buffered with an op amp follower circuit to assure

low impedance on the Ref pin.

Input circuitry must provide a path for this input bias current
if the INA121 is to operate properly. Figure 3 shows various
provisions for an input bias current path. Without a bias
current return path, the inputs will float to a potential which
exceeds the common-mode range of the INA121 and the
input amplifiers will saturate.

If the differential source resistance is low, the bias current
return path can be connected to one input (see the thermo­couple example in Figure 3). With higher source impedance,
using two resistors provides a balanced input with possible
advantages of lower input offset voltage due to bias current
and better high-frequency common-mode rejection.

Crystal or

Ceramic

Transducer

1MΩ1MΩ

Thermocouple

10kΩ

INA121

INA121

INA121

–

V

IN

INA121

R

G

+

V

IN

±10mV

Adjustment Range

NOTE: (1) For wider trim range required
in high gains, scale resistor values larger

Ref

V

O

OPA277

10kΩ

V+

(1)

V–

100µA

1/2 REF200

(1)

100Ω

(1)

100Ω

100µA

1/2 REF200

FIGURE 2. Optional Trimming of Output Offset Voltage.

INPUT BIAS CURRENT RETURN PATH

The input impedance of the INA121 is extremely high—

approximately 10

12

Ω. However, a path must be provided for

the input bias current of both inputs. This input bias current

is typically 4pA. High input impedance means that this input

bias current changes very little with varying input voltage.

Center-tap provides
bias current return.

INA121

REF

BridgeV

Bridge resistance provides
bias current return.

FIGURE 3. Providing an Input Common-Mode Current Path.

INPUT COMMON-MODE RANGE

The linear input voltage range of the input circuitry of the
INA121 is from approximately 1.2V below the positive
supply voltage to 2.1V above the negative supply. A differ­ential input voltage causes the output voltage to increase.
The linear input range, however, will be limited by the
output voltage swing of amplifiers A

and A2. So the linear

1

common-mode input range is related to the output voltage of
the complete amplifier. This behavior also depends on sup­ply voltage—see typical performance curve “Input Com­mon-Mode Range vs Output Voltage”.

®

9

INA121

A combination of common-mode and differential input
voltage can cause the output of A
4 shows the output voltage swing of A

or A2 to saturate. Figure

1

and A2 expressed in

1

terms of a common-mode and differential input voltages.
For applications where input common-mode range must be
maximized, limit the output voltage swing by connecting the
INA121 in a lower gain (see performance curve “Input
Common-Mode Voltage Range vs Output Voltage”). If
necessary, add gain after the INA121 to increase the voltage
swing.

Input-overload can produce an output voltage that appears
normal. For example, if an input overload condition drives
both input amplifiers to their positive output swing limit, the
difference voltage measured by the output amplifier will be
near zero. The output of A

will be near 0V even though both

3

inputs are overloaded.

LOW VOLTAGE OPERATION

The INA121 can be operated on power supplies as low as
±2.25V. Performance remains excellent with power supplies
ranging from ±2.25V to ±18V. Most parameters vary only
slightly throughout this supply voltage range—see typical

performance curves. Operation at very low supply voltage
requires careful attention to assure that the input voltages
remain within their linear range. Voltage swing requirements
of internal nodes limit the input common-mode range with low
power supply voltage. Typical performance curves, “Input
Common-Mode Range vs Output Voltage” show the range of
linear operation for ±15V, ±5V, and ±2.5V supplies.

INPUT FILTERING

The INA121’s FET input allows use of an R/C input filter
without creating large offsets due to input bias current.
Figure 5 shows proper implementation of this input filter to
preserve the INA121’s excellent high frequency common­mode rejection. Mismatch of the common-mode input time
constant (R

and R2C2), either from stray capacitance or

1C1

mismatched values, causes a high frequency common-mode
signal to be converted to a differential signal. This degrades
common-mode rejection. The differential input capacitor,
C3, reduces the bandwidth and mitigates the effects of
mismatch in C
C

. If properly matched, C1 and C2 also improve ac CMR.

2

and C2. Make C3 much larger than C1 and

1

V

D

2

R

G

V

D

2

V

CM

FIGURE 4. Voltage Swing of A1 and A2.

f

=

−3dB

C

1

R

1

–

V

IN

C

R

2

+

V

IN

3

INA121

Ref

4πR

VCM –

VCM +

1




1C3



V

O

G • V

D

2

A

1

25kΩ

25kΩ

A

2

G • V

D

2

C



1



+



2

V+

40kΩ40kΩ

A

3

40kΩ40kΩ

V–

+10V

Bridge

INA121

G = 1 +

R

G

100Ω

V

O

50kΩ

R

G

= G • V

D

G = 500

INA121

Ref

V

O

C2R1 = R

C1 = C
C3 ≈ 10C

2
2

1

FIGURE 5. Input Low-Pass Filter.

®

INA121

FET input allows use
of large resistors and
small capacitors.

FIGURE 6. Bridge Transducer Amplifier.

10

INA121

Transducer

C

1

C

2

Null

R

2

R

1

R

G

V

O

Ref

V

AC

INA121

OPA277

C

1

50nF

R

G

R

2

R

G

Make G ≤ 10 where G = 1 +

50k

Load

V

IN

G • R

2

IL =

R

1

10kΩ

V

IN

Ref

C

1

R

C

2

R

1

G

R

2

INA121

Ref

f

=

c

NOTE: To preserve good low frequency CMR,

= R2 and C1 = C2.

make R

1

1

2πR1C

±6V to ±18V

Isolated Power

V+ V–

±15V

V

O

–

V

IN

INA121 ISO124

1

+

V

IN

Ref

V

O

Isolated

Common

FIGURE 7. High-Pass Input Filter.

–

V

R

G

INA121

Ref

C

1

0.1µF

OPA277

IN

+

R

1MΩ

FIGURE 8. Galvanically Isolated Instrumentation

Amplifier.

V

O

1

–3dB

1

=

2πR

1C1

f

= 1.59Hz

FIGURE 10. Voltage Controlled Current Source.FIGURE 9. AC-Coupled Instrumentation Amplifier.

FIGURE 11. Capacitive Bridge Transducer Circuit.

11

®

INA121

+

Channel 1

V

IN

–

MPC800

MUX

+

Channel 8

V

IN

–

FIGURE 12. Multiplexed-Input Data Acquisition System.

+5V

V

REF

R

G

INA121

+In
–In

ADS7816

12 Bits Out

Serial

Ref

NOTE: Driving the shield minimizes CMR degradation
due to unequally distributed capacitance on the input
line. The shield is driven at approximately 1V below
the common-mode input voltage.

FIGURE 13. Shield Driver Circuit.

RA

Low bias current
allows use with high
electrode impedances.

RL

LA

390kΩ

–

V

IN

+

V

IN

22.1kΩ

22.1kΩ

511Ω

INA121

V

O

Ref

100Ω

OPA130

For G = 100

= 511Ω // 2(22.1kΩ)

R

G

effective R

R

G

G

= 5.6kΩ

2.8kΩ

/2

R

G

= 505Ω

INA121

G = 10

V

O

Ref

2.8kΩ

390kΩ

1/2

OPA2131

10kΩ

V

G

1/2

OPA2131

V

G

NOTE: Due to the INA121’s current-feedback
topology, V
the common-mode input voltage. This DC offset

is approximately 0.7V less than

G

in this guard potential is satisfactory for many
guarding applications.

FIGURE 14. ECG Amplifier With Right-Leg Drive.

®

INA121

12

PACKAGE OPTION ADDENDUM

www.ti.com

22-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

INA121P ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br)

INA121PA ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br)

INA121PAG4 ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br)

INA121PG4 ACTIVE PDIP P 8 50 Green (RoHS &

no Sb/Br)

INA121U ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br)

INA121U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

INA121U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

INA121UA ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br)

INA121UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

INA121UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

INA121UAE4 ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br)

INA121UG4 ACTIVE SOIC D 8 100 Green(RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

22-Oct-2007

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

INA121U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

INA121UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

INA121U/2K5 SOIC D 8 2500 346.0 346.0 29.0

INA121UA/2K5 SOIC D 8 2500 346.0 346.0 29.0

Pack Materials-Page 2

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