The INA105 is a monolithic Gain = 1 differential
amplifier consisting of a precision op amp and on-chip
metal film resistors. The resistors are laser trimmed
for accurate gain and high common-mode rejection.
Excellent TCR tracking of the resistors maintains
gain accuracy and common-mode rejection over
temperature.
The differential amplifier is the foundation of many
commonly used circuits. The INA105 provides this
precision circuit function without using an expensive
precision resistor network. The INA105 is available in
8-pin plastic DIP, SO-8 surface-mount and TO-99
metal packages.
APPLICATIONS
● DIFFERENTIAL AMPLIFIER
● INSTRUMENTATION AMPLIFIER
BUILDING BLOCK
● UNITY-GAIN INVERTING AMPLIFIER
● GAIN-OF-1/2 AMPLIFIER
● NONINVERTING GAIN-OF-2 AMPLIFIER
● AVERAGE VALUE AMPLIFIER
● ABSOLUTE VALUE AMPLIFIER
● SUMMING AMPLIFIER
● SYNCHRONOUS DEMODULATOR
● CURRENT RECEIVER WITH COMPLIANCE
TO RAILS
● 4mA TO 20mA TRANSMITTER
● VOLTAGE-CONTROLLED CURRENT
SOURCE
● ALL-PASS FILTERS
–In
+In
2
25kΩ25kΩ
3
25kΩ25kΩ
5
Sense
7
V+
6
Output
4
V–
1
Ref
SBOS145
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
✻ Specification same as for INA105AM.
NOTES: (1) Connected as difference amplifier (see Figure 4). (2) Nonlinearity is the maximum peak deviation from the best-fit straight line as a percent of full-scale peak-
to-peak output. (3) 25kΩ resistors are ratio matched but have ±20% absolute value. (4) Maximum input voltage without protection is 10V more than either ±15V supply
(±25V). Limit I
circuit has a gain of 2 for the operational amplifier’s offset voltage and noise voltage. (7) Includes effects of amplifier’s input bias and offset currents. (8) Includes effects
to 1mA. (5) With zero source impedance (see “Maintaining CMR” section). (6) Referred to output in unity-gain difference configuration. Note that this
IN
of amplifier’s input current noise and thermal noise contribution of resistor network.
1✻✻V/V
0.00020.001✻✻✻✻ %
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
Input Voltage Range ............................................................................ ±V
Operating Temperature Range: M .................................. –55°C to +125°C
P, U................................ –40°C to +85°C
Storage Temperature Range: M ..................................... –65°C to +150°C
P, U ................................. –40°C to +125°C
Lead Temperature (soldering, 10s) M, P ....................................... +300°C
Wave Soldering (3s, max) U .......................................................... +260°C
Output Short Circuit to Common.............................................. Continuous
S
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING TEMPERATURE
PRODUCTPACKAGENUMBER
INA105AMTO-99 Metal001–40°C to +85°C
INA105BMTO-99 Metal001–40°C to +85°C
INA105KP8-Pin Plastic DIP006–40°C to +85°C
INA105KU8-Pin SOIC182–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
(1)
RANGE
Top ViewDIP/SOIC
1
Ref
–In
+In
V–
NOTE: (1) Performance grade identifier box for small outline surface mount.
Blank indicates K grade. Part is marked INA105U.
(1)
2
3
4
No Internal Connection
8
V+
7
Output
6
Sense
5
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3
INA105
TYPICAL PERFORMANCE CURVES
At TA = 25°C, VS = ±15V, unless otherwise noted.
STEP RESPONSE
–10 to +10
Output Voltage (V)
+50
0
–50
Output Voltage (mV)
SMALL SIGNAL RESPONSE
(No Load)
0481216
(R
+50
0
–50
Output Voltage (mV)
17.5
15
12.5
10
(V)
OUT
7.5
V
5
2.5
0
0
Time (µs)
SMALL SIGNAL RESPONSE
Ω
LOAD
= , C
∞
= 1000pF)
LOAD
0510
Time (µs)
MAXIMUM V
(Positive Swing)
OUT
vs I
OUT
VS = ±18V
VS = ±15V
VS = ±12V
VS = ±5V
6 1218243036
I
(mA)
OUT
–17.5
–15
–12.5
–10
(V)
OUT
–7.5
V
–5
–2.5
110
100
90
CMR (dB)
80
70
60
0510
Time (µs)
MAXIMUM V
(Negative Swing)
OUT
vs I
OUT
VS = ±18V
VS = ±15V
VS = ±12V
VS = ±5V
0
–2–4–6–8–10–12
0
–I
(mA)
OUT
CMR vs FREQUENCY
BM
AM, KP, U
10
1001k10k100k
Frequency (Hz)
®
INA105
4
TYPICAL PERFORMANCE CURVES (CONT)
V
3
5
6
3
INA105
V
OUT
= V3 – V
2
2
R
3
R
1
R
2
R
4
V
2
25k
Ω
25k
Ω
25k
Ω
25k
Ω
1µF
V–
4
1µF
V+
7
1
At TA = 25°C, VS = ±15V, unless otherwise noted.
140
120
100
80
PSRR (dB)
60
40
1
POWER SUPPLY REJECTION
vs FREQUENCY
V–
V+
101001k10k100k
Frequency (Hz)
36
30
24
18
12
Input Range (V)
6
0
±3
COMMON-MODE INPUT RANGE vs SUPPLY
(Difference Amplifier Connected, V
Negative CMV
Positive CMV
±6±9±12±15±18±21
Supply Voltage (V)
OUT
= 0)
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the INA105. Power supply bypass capacitors should be
connected close to the device pins.
The differential input signal is connected to pins 2 and 3 as
shown. The source impedances connected to the inputs must
be nearly equal to assure good common-mode rejection. A
5Ω mismatch in source impedance will degrade the common-mode rejection of a typical device to approximately
FIGURE 1. Basic Power Supply and Signal Connections.
5
INA105
®
80dB. If the source has a known mismatch in source impedance, an additional resistor in series with one input can be
used to preserve good common-mode rejection.
The output is referred to the output reference terminal (pin
1) which is normally grounded. A voltage applied to the Ref
terminal will be summed with the output signal. This can be
used to null offset voltage as shown in Figure 2. The source
impedance of a signal applied to the Ref terminal should be
less than 10Ω to maintain good common-mode rejection.
nominal resistor values are equal. These resistors are laser
trimmed for precise resistor ratios to achieve accurate gain
Do not interchange pins 1 and 3 or pins 2 and 5, even though
and highest CMR. Interchanging these pins would not provide specified performance.
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