The INA105 is a monolithic Gain = 1 differential
amplifier consisting of a precision op amp and on-chip
metal film resistors. The resistors are laser trimmed
for accurate gain and high common-mode rejection.
Excellent TCR tracking of the resistors maintains
gain accuracy and common-mode rejection over
temperature.
The differential amplifier is the foundation of many
commonly used circuits. The INA105 provides this
precision circuit function without using an expensive
precision resistor network. The INA105 is available in
8-pin plastic DIP, SO-8 surface-mount and TO-99
metal packages.
APPLICATIONS
● DIFFERENTIAL AMPLIFIER
● INSTRUMENTATION AMPLIFIER
BUILDING BLOCK
● UNITY-GAIN INVERTING AMPLIFIER
● GAIN-OF-1/2 AMPLIFIER
● NONINVERTING GAIN-OF-2 AMPLIFIER
● AVERAGE VALUE AMPLIFIER
● ABSOLUTE VALUE AMPLIFIER
● SUMMING AMPLIFIER
● SYNCHRONOUS DEMODULATOR
● CURRENT RECEIVER WITH COMPLIANCE
TO RAILS
● 4mA TO 20mA TRANSMITTER
● VOLTAGE-CONTROLLED CURRENT
SOURCE
● ALL-PASS FILTERS
–In
+In
2
25kΩ25kΩ
3
25kΩ25kΩ
5
Sense
7
V+
6
Output
4
V–
1
Ref
SBOS145
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
✻ Specification same as for INA105AM.
NOTES: (1) Connected as difference amplifier (see Figure 4). (2) Nonlinearity is the maximum peak deviation from the best-fit straight line as a percent of full-scale peak-
to-peak output. (3) 25kΩ resistors are ratio matched but have ±20% absolute value. (4) Maximum input voltage without protection is 10V more than either ±15V supply
(±25V). Limit I
circuit has a gain of 2 for the operational amplifier’s offset voltage and noise voltage. (7) Includes effects of amplifier’s input bias and offset currents. (8) Includes effects
to 1mA. (5) With zero source impedance (see “Maintaining CMR” section). (6) Referred to output in unity-gain difference configuration. Note that this
IN
of amplifier’s input current noise and thermal noise contribution of resistor network.
1✻✻V/V
0.00020.001✻✻✻✻ %
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
Input Voltage Range ............................................................................ ±V
Operating Temperature Range: M .................................. –55°C to +125°C
P, U................................ –40°C to +85°C
Storage Temperature Range: M ..................................... –65°C to +150°C
P, U ................................. –40°C to +125°C
Lead Temperature (soldering, 10s) M, P ....................................... +300°C
Wave Soldering (3s, max) U .......................................................... +260°C
Output Short Circuit to Common.............................................. Continuous
S
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING TEMPERATURE
PRODUCTPACKAGENUMBER
INA105AMTO-99 Metal001–40°C to +85°C
INA105BMTO-99 Metal001–40°C to +85°C
INA105KP8-Pin Plastic DIP006–40°C to +85°C
INA105KU8-Pin SOIC182–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
(1)
RANGE
Top ViewDIP/SOIC
1
Ref
–In
+In
V–
NOTE: (1) Performance grade identifier box for small outline surface mount.
Blank indicates K grade. Part is marked INA105U.
(1)
2
3
4
No Internal Connection
8
V+
7
Output
6
Sense
5
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3
INA105
TYPICAL PERFORMANCE CURVES
At TA = 25°C, VS = ±15V, unless otherwise noted.
STEP RESPONSE
–10 to +10
Output Voltage (V)
+50
0
–50
Output Voltage (mV)
SMALL SIGNAL RESPONSE
(No Load)
0481216
(R
+50
0
–50
Output Voltage (mV)
17.5
15
12.5
10
(V)
OUT
7.5
V
5
2.5
0
0
Time (µs)
SMALL SIGNAL RESPONSE
Ω
LOAD
= , C
∞
= 1000pF)
LOAD
0510
Time (µs)
MAXIMUM V
(Positive Swing)
OUT
vs I
OUT
VS = ±18V
VS = ±15V
VS = ±12V
VS = ±5V
6 1218243036
I
(mA)
OUT
–17.5
–15
–12.5
–10
(V)
OUT
–7.5
V
–5
–2.5
110
100
90
CMR (dB)
80
70
60
0510
Time (µs)
MAXIMUM V
(Negative Swing)
OUT
vs I
OUT
VS = ±18V
VS = ±15V
VS = ±12V
VS = ±5V
0
–2–4–6–8–10–12
0
–I
(mA)
OUT
CMR vs FREQUENCY
BM
AM, KP, U
10
1001k10k100k
Frequency (Hz)
®
INA105
4
TYPICAL PERFORMANCE CURVES (CONT)
V
3
5
6
3
INA105
V
OUT
= V3 – V
2
2
R
3
R
1
R
2
R
4
V
2
25k
Ω
25k
Ω
25k
Ω
25k
Ω
1µF
V–
4
1µF
V+
7
1
At TA = 25°C, VS = ±15V, unless otherwise noted.
140
120
100
80
PSRR (dB)
60
40
1
POWER SUPPLY REJECTION
vs FREQUENCY
V–
V+
101001k10k100k
Frequency (Hz)
36
30
24
18
12
Input Range (V)
6
0
±3
COMMON-MODE INPUT RANGE vs SUPPLY
(Difference Amplifier Connected, V
Negative CMV
Positive CMV
±6±9±12±15±18±21
Supply Voltage (V)
OUT
= 0)
APPLICATION INFORMATION
Figure 1 shows the basic connections required for operation
of the INA105. Power supply bypass capacitors should be
connected close to the device pins.
The differential input signal is connected to pins 2 and 3 as
shown. The source impedances connected to the inputs must
be nearly equal to assure good common-mode rejection. A
5Ω mismatch in source impedance will degrade the common-mode rejection of a typical device to approximately
FIGURE 1. Basic Power Supply and Signal Connections.
5
INA105
®
80dB. If the source has a known mismatch in source impedance, an additional resistor in series with one input can be
used to preserve good common-mode rejection.
The output is referred to the output reference terminal (pin
1) which is normally grounded. A voltage applied to the Ref
terminal will be summed with the output signal. This can be
used to null offset voltage as shown in Figure 2. The source
impedance of a signal applied to the Ref terminal should be
less than 10Ω to maintain good common-mode rejection.
nominal resistor values are equal. These resistors are laser
trimmed for precise resistor ratios to achieve accurate gain
Do not interchange pins 1 and 3 or pins 2 and 5, even though
and highest CMR. Interchanging these pins would not provide specified performance.
R
V
2
10
Ω
V
3
= V3 – V
V
O
Offset Adjustment
3
2
3
1
R
3
1
Range = ±300µV
FIGURE 2. Offset Adjustment.
INA105
R
4
10
V
1
–In
A
R
2
5
6
V
O
1
R
R
1
R
2
2
2
3
A
+15V
499k
Ω
100k
Ω
Ω
–15V
V
+In
For low source impedance applications, an input stage using OPA27 op
amps will give the best low noise, offset, and temperature drift performance.
At source impedances above about 10kΩ, the bias current noise of the
OPA27 reacting with the input impedance begins to dominate the noise
2
1
VO = (1 + 2R2/R1) (V2 –V1)
INA105
5
6
V
0
0utput
1
performance. For these applications, using the OPA111 or dual OPA2111
FET input op amp will provide lower noise performance. For lower cost use
the OPA121 plastic. To construct an electrometer use the OPA128.
FIGURE 23. Isolating Current Source with Buffering Ampli-
fier for Greater Accuracy.
®
INA105
10
Window Span
0 to +5V
Window Center–Window Span
2
5
6
3
INA105
1
Lower Limit
2
5
Window
Center
±10V
3
1
INA105
6
FIGURE 24. Window Comparator with Window Span and Window Center Inputs.
–In
V
1
+In
V
2
(1)
R
2
R
1
R
2
(1)
I
= (E2 – E1) (1 +2R2/R1) (1/25k + 1/R)
O
NOTE: (1) See Figure 5 for op amp recommendation.
2
3
INA105
V
IN
Upper Limit
5
6
1kΩ
1
5
4115
3
Window
Comparator
2
10
9
7
8
Window Center + Window Span
V+
R
R
Load
I
O
HI
GO
LO
FIGURE 25. Precision Voltage-Controlled Current Source with Buffered Differential Inputs and Gain.
INA105
V
1
DG188
2
5
V
O
6
3
1
V
O
0
–V
1
+V
Logic
In
1
Logic In
FIGURE 26. Digitally Controlled Gain of ±1 Amplifier.
11
INA105
1
1
®
INA105
V
1
A
1
R
1
49.5Ω
R
1
R
1
49.5Ω
R
2
R
2
A
3
1
2
5
6
V0 = 200 (V2 – V1)
3
R
A
2
V
2
2
R
2
Conventional
Instrumentation
Amplifier (e.g., INA101 or INA102)
INA105
A = 2
A = 100
FIGURE 27. Boosting Instrumentation Amplifier Common-Mode Range From ±5 to ±7.5V with 10V Full-Scale Output.
INA105
V
Input
R
2
D
1
10pF
3
D
1
OPA111
2
1
R
5
2k
Ω
1
R
3
R
4
R
2
5
6
V0 = |V1|
FIGURE 28. Precision Absolute Value Buffer.
12.5k
0 to 10V
Ω
In
50k
Ω
+15V
OPA27
2
REF10
6
10V
4
FIGURE 29. Precision 4-20mA Current Transmitter.
®
INA105
1k
Ω
2
INA105
5
50.1
Ω
6
50.1
Ω
3
4 to 20mA
1
R
LOAD
Out
12
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
PACKAGING INFORMATION
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
INA105AMNRNDTO-99LMC820Green (RoHS &
no Sb/Br)
INA105BMNRNDTO-99LMC820Green (RoHS &
no Sb/Br)
INA105KPACTIVEPDIPP850Green(RoHS &
no Sb/Br)
INA105KPG4ACTIVEPDIPP850Green(RoHS &
no Sb/Br)
INA105KUACTIVESOICD8100Green (RoHS &
no Sb/Br)
INA105KU/2K5ACTIVESOICD82500 Green (RoHS &
no Sb/Br)
INA105KU/2K5E4ACTIVESOICD82500 Green (RoHS &
no Sb/Br)
INA105KUE4ACTIVESOICD8100Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
AUN / A for Pkg Type
AUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-3-260C-168 HR
CU NIPDAULevel-3-260C-168 HR
CU NIPDAULevel-3-260C-168 HR
CU NIPDAULevel-3-260C-168 HR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.