TEXAS INSTRUMENTS INA103 Technical data

®

INA103

INA103

Low Noise, Low Distortion

INSTRUMENT ATION AMPLIFIER

INA103

FEA TURES

● LOW NOISE: 1nV/√Hz

● LOW THD+N: 0.0009% at 1kHz, G = 100

● HIGH GBW: 100MHz at G = 1000

● WIDE SUPPLY RANGE:

±9V to ±25V

● HIGH CMRR: >100dB

● BUILT-IN GAIN SETTING RESISTORS:

G = 1, 100

● UPGRADES AD625

DESCRIPTION

The INA103 is a very low noise, low distortion mono­lithic instrumentation amplifier. Its current-feedback
circuitry achieves very wide bandwidth and excellent
dynamic response. It is ideal for low-level audio
signals such as balanced low-impedance microphones.
The INA103 provides near-theoretical limit noise per­formance for 200Ω source impedances. Many indus­trial applications also benefit from its low noise and
wide bandwidth.

Unique distortion cancellation circuitry reduces dis­tortion to extremely low levels, even in high gain. Its
balanced input, low noise and low distortion provide
superior performance compared to transformer-coupled
microphone amplifiers used in professional audio
equipment.

The INA103’s wide supply voltage (±9 to ±25V) and
high output current drive allow its use in high-level
audio stages as well. A copper lead frame in the plastic
DIP assures excellent thermal performance.

APPLICATIONS

● HIGH QUALITY MICROPHONE PREAMPS

(REPLACES TRANSFORMERS)

● MOVING-COIL PREAMPLIFIERS

● DIFFERENTIAL RECEIVERS

● AMPLIFICATION OF SIGNALS FROM:

Strain Gages (Weigh Scale Applications)
Thermocouples
Bridge Transducers

The INA103 is available in 16-pin plastic DIP and
SOL-16 surface-mount packages. Commercial and In­dustrial temperature range models are available.

Offset

Null

3 4

9

V+

Offset

6k

–

A

+

6k

Null

Ω

3

Ω

V–

11

Sense

Output

10

Ref

7

8

–Input

–Gain Sense

–R

G = 100

+R

+Gain Sense

+Input

–Gain Drive

12

Ω

1

3kΩ

3k

Ω

2

5

+Gain Drive

6k

Ω

6k

+

16

A

–

15
13

G

60.6Ω

14

6

G

–

2

A

+

1

SBOS003

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

©

1990 Burr-Brown Corporation PDS-1016H Printed in U.S.A. March, 1998

1

INA103

®

SPECIFICATIONS

All specifications at TA = +25°C, VS = ±15V and RL = 2kΩ, unless otherwise noted.

INA103KP, KU
PARAMETER CONDITIONS MIN TYP MAX UNITS
GAIN

Range of Gain 1 1000 V/V
Gain Equation
Gain Error, DC G = 1 ±10V Output 0.005 0.05 %

Gain Temp. Co. G = 1 ±10V Output 10 ppm/°C

Nonlinearity, DC G = 1 ±10V Output 0.0003 0.01 % of FS

OUTPUT

Voltage, R

Current T
Short Circuit Current ±70 mA
Capacitive Load Stability 10 nF

INPUT OFFSET VOLTAGE

Initial Offset RTI
(KU Grade) (250+ 5000/G) µV
vs Temp G = 1 to 1000 T

vs Supply ±9V to ±25V 0.2 + 8/G 4 + 60/G µV/V

INPUT BIAS CURRENT

Initial Bias Current 2.5 12 µA

vs Temp T

Initial Offset Current 0.04 1 µA

vs Temp T

INPUT IMPEDANCE

Differential Mode 60 || 2 MΩ || pF
Common-Mode 60 || 5 MΩ || pF

INPUT VOLTAGE RANGE

Common-Mode Range
CMR

G = 1 DC to 60Hz 72 86 dB
G = 100 DC to 60Hz 100 125 dB

INPUT NOISE

Voltage

10Hz 2 nV/√Hz
100Hz 1.2 nV/√Hz
1kHz 1 nV/√Hz

Current, 1kHz 2 pA/√Hz

OUTPUT NOISE

Voltage 1kHz 65 nV/√Hz
A Weighted, 20Hz-20kHz 20Hz-20kHz –100 dBu

DYNAMIC RESPONSE

–3dB Bandwidth: G = 1 Small Signal 6 MHz

Full Power Bandwidth G = 1

V

OUT

Slew Rate G = 1 to 500 15 V/µs
THD + Noise G = 100, f = 1kHz 0.0009 %
Settling Time 0.1%

G = 1 V
G = 100 1.5 µs

Settling Time 0.01%

G = 1 V
G = 100 3.5 µs

Overload Recovery

NOTES: (1) Gains other than 1 and 100 can be set by adding an external resistor, RG between pins 2 and 15. Gain accuracy is a function of RG. (2) FS = Full Scale.
(3) Adjustable to zero. (4) V
for output to return from saturation to linear operation following the removal of an input overdrive voltage.

(1)

G = 1 + 6kΩ/R

G

V/V

G = 100 0.07 0.25 %
Equation 0.05 %

G = 100 25 ppm/°C
Equation 25 ppm/°C

G = 100 0.0006 0.01 % of FS

= 600Ω TA = T

L

R

= 600Ω VS = ±25, TA = 25°C ±20 ± 21 V

L

(3)

G = 1000 T

(4)

(5)

A

A

A

A

A

= T

= T

= T

= T

= T

to T

MIN

to T

MIN

to T

MIN

to T

MIN

to T

MIN

to T

MIN

RS = 0Ω

MAX

MAX

MAX

MAX

MAX

MAX

±11.5 ± 12 V

±40 mA

(30 + 1200/G) µV

1 + 20/G µV/°C

µV/°C

15 nA/°C

0.5 nA/°C

±11 ± 12 V

G = 100 Small Signal 800 kHz

= ±10V, RL = 600Ω 240 kHz

= 20V Step 1.7 µs

O

= 20V Step 2 µs

O

(6)

= 0V, see Typical Curves for VCM vs VO. (5) V

O

50% Overdrive 1 µs

2

NOISE RTI

= √V

N INPUT

+ (V

/Gain)2 + 4KTRG. See Typical Curves. (6) Time required

N OUTPUT

(2)

®

INA103

2

SPECIFICATIONS (CONT)

All specifications at TA = +25°C, VS = ±15V and RL = 2kΩ, unless otherwise noted.

INA103KP, KU
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY

Rated Voltage ±15 V
Voltage Range ±9 ±25 V
Quiescent Current 9 12.5 mA

TEMPERATURE RANGE

Specification 0 +70 °C
Operation –40 +85 °C
Storage –40 +100 °C
Thermal Resistance,

θ

JA

100 °C/W

PIN CONFIGURATION

Top View DIP or SOIC

(1)

+R

Ref

V–

1
2
3
4
5
6

G

7
8

+ Input

+ Gain Sense

+ Offset Null

– Offset Null

+ Gain Drive

NOTE: (1) Pin 1 Marking—SOL-16 Package

16
15
14
13
12
11
10

9

– Input
– Gain Sense
G = 100
–R

G

– Gain Drive
Sense
Output
V+

PACKAGE/ORDERING INFORMATION

PACKAGE
DRAWING TEMPERATURE

PRODUCT PACKAGE NUMBER

INA103KP Plastic DIP 180 0°C to +70°C
INA103KU SOL-16 211 0°C to +70°C

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

(1)

RANGE

ELECTROSTATIC
DISCHARGE SENSITIVITY

Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet

published specifications.

ABSOLUTE MAXIMUM RATINGS

Power Supply Voltage ....................................................................... ±25V

Input Voltage Range, Continuous ....................................................... ±V

Operating Temperature Range:........................................–40°C to +85 °C

Storage Temperature Range: ........................................... –40°C to +85°C

Junction Temperature:

P, U Package.............................................................................. +125°C

Lead Temperature (soldering, 10s) ............................................... +300°C

Output Short Circuit to Common ............................................. Continuous

NOTE: (1) Stresses above these ratings may cause permanent damage.

(1)

S

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

3

INA103

®

TYPICAL PERFORMANCE CURVES

At TA = +25°C, VS = ±15V, unless otherwise noted.

±25

±20

±15

±10

Input Voltage Range (V)

±5

±5 ±10 ±15 ±20 ±25

22

16.5

11

5.5

Common-Mode Voltage (V)

INPUT VOLTAGE RANGE vs SUPPLY

Power Supply Voltage (V)

MAX COMMON-MODE VOLTAGE

vs OUTPUT VOLTAGE

V = ±25V

S

V = ±15V

S

±25

±20

±15

Output Voltage (V)

±10

±5

±5 ±10 ±15 ±20 ±25

±16

±12

±8

Output Voltage (V)

±4

OUTPUT SWING vs SUPPLY

Power Supply Voltage (V)

OUTPUT SWING vs LOAD RESISTANCE

0 5.5 11 16.5 22

Output Voltage (V)

OFFSET VOLTAGE vs TIME FROM POWER UP

20

10

OSI

0

Change In V (µV)

–10

–20

012 45

®

(G = 100)

3

Time (min)

INA103

2.60

2.55

2.50

2.45

2.40

2.35

Input Bias Current (µA)

2.30

2.25

4

±0

0 200 400 600 800 1k

Load Resistance ( )

INPUT BIAS CURRENT vs SUPPLY

9 10 15 20 25

Power Supply Voltage (±V)

Ω

TYPICAL PERFORMANCE CURVES (CONT)

SETTLING TIME vs GAIN

(0.1%, 20V STEP)

Settling Time (µs)

Gain

1 10 100 1000

10

8

6

4

2

0

At TA = +25°C, VS = ±15V, unless otherwise noted.

6

5

4

3

Input Bias Current (µA)

2

1

INPUT BIAS CURRENT vs TEMPERATURE

–55

SMALL SIGNAL TRANSIENT RESPONSE

0 50 100 125

Temperature (°C)

(G = 100)

SMALL SIGNAL TRANSIENT RESPONSE

(G = 1)

Output Voltage (V)

Time (µs)

LARGE SIGNAL TRANSIENT RESPONSE

(G = 1)

Output Voltage (V)

Time (µs)

LARGE SIGNAL TRANSIENT RESPONSE

Output Voltage (V)

(G = 100)

Time (µs)

Output Voltage (V)

Time (µs)

®

5

INA103

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VS = ±15V, unless otherwise noted.

SETTLING TIME vs GAIN

10

8

6

4

Settling Time (µs)

2

0

1 10 100 1000

(0.01%, 20V STEP)

Gain

70
60
50
40
30
20
10

0

Gain (dB)

–10
–20
–30
–40
–50

10 100 1k 10k 100k 1M 10M

SMALL-SIGNAL FREQUENCY RESPONSE

G = 1000

G = 100

G = 10

G = 1

Frequency (Hz)

1k

100

√

10

Noise (RTI) (nV/ Hz)

1

10 100 1k 10k

1

0.1

0.010

THD + N (%)

0.001

0.0001
10 100

NOISE VOLTAGE (RTI) vs FREQUENCY

G = 100

Frequency (Hz)

THD + N vs FREQUENCY

G = 1000

G = 1

G = 100

G = 10

1k

Frequency (Hz)

G = 1

G = 10

G = 500

G = 1000

V = +18dBu

OUT

10k 20k

140

120

100

80

60

40

Common-Mode Rejection (dB)

20

0

10 1M

140

G = 100

G = 10

120

G = 1

100

80

60

40

Power Supply Rejection (dB)

20

0

11M10 100 1k 10k 100k

CMR vs FREQUENCY

100 1k 10k 100k

Frequency (Hz)

V+ POWER SUPPLY REJECTION

vs FREQUENCY

G = 1000

Frequency (Hz)

G = 1000

G = 500

G = 100

G = 10

G = 1

®

INA103

6

TYPICAL PERFORMANCE CURVES (CONT)

1

0.1

0.010

0.001

0.0001

CCIF IMD (%)

CCIF IMD vs AMPLITUDE

–60 –50 –40 –30 –20 –10 0 10 20

Output Amplitude (dBu)

5

G = 1000

G = 100

G = 1

G = 10

1

0.1

0.010

0.001

SMPTE IMD (%)

SMPTE IMD vs AMPLITUDE

–60 –50 –40 –30 –20 –10 0 10 20

Output Amplitude (dBu)

5

G = 1000

G = 100

G = 1

G = 10

0.0005

At TA = +25°C, VS = ±15V, unless otherwise noted.

V– POWER SUPPLY REJECTION

140

120

100

80

G = 100, 1000

G = 10

G = 1

vs FREQUENCY

1

0.1

THD + N vs LEVEL

f = 1kHz

60

40

Power Supply Rejection (dB)

20

0

11M10 100 1k 10k 100k

Frequency (Hz)

0.1

0.01

THD + N (%)

0.001

0.0001
200 400 600 800 1k

THD + N vs LOAD

Ω

R ( )

LOAD

G = 1

V = 20Vp-p

OUT

f = 1kHz

0.010

THD + N (%)

0.001

0.0005
–60 –45 –30 –15 0 15

Output Amplitude (dBu)

G = 1

5

1

0.1

0.010

CCIF IMD (%)

0.001

0.0001
2k 10k 20k

CCIF IMD vs FREQUENCY

G = 1000

G = 100
G = 10
G = 1

Frequency (Hz)

®

7

INA103

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°C, VS = ±15V unless, otherwise noted.

5

1

0.1

SMPTE IMD (%)

0.010

0.001

0.0005
2k 10k 20k

SMPTE IMD vs FREQUENCY

G = 1000

G = 100
G = 1

G = 10

Frequency (Hz)

100

10

Current Noise Density (pA/ Hz)

1

CURRENT NOISE SPECTRAL DENSITY

1 10 100 1k 10k

Frequency (Hz)

APPLICATIONS INFORMATION

Figure 1 shows the basic connections required for operation.
Power supplies should be bypassed with 1µF tantalum
capacitors near the device pins. The output Sense (pin 11)
and output Reference (pin 7) should be low impedance
connections. Resistance of a few ohms in series with these
connections will degrade the common-mode rejection of the
amplifier.
To avoid oscillations, make short, direct connection to the
gain set resistor and gain sense connections. Avoid running
output signals near these sensitive input nodes.

INPUT CONSIDERATIONS

Certain source impedances can cause the INA103 to oscil­late. This depends on circuit layout and source or cable
characteristics connected to the input. An input network
consisting of a small inductor and resistor (Figure 2) can
greatly reduce the tendancy to oscillate. This is especially

®

INA103

useful if various input sources are connected to the INA103.
Although not shown in other figures, this network can be
used, if needed, with all applications shown.

GAIN SELECTION

Gains of 1 or 100V/V can be set without external resistors.
For G = 1V/V (unity gain) leave pin 14 open (no connec­tion)—see Figure 4. For G = 100V/V, connect pin 14 to pin
6—see Figure 5.

Gain can also be accurately set with a single external resistor
as shown in Figure 1. The two internal feedback resistors are
laser-trimmed to 3kΩ within approximately ±0.1%. The
temperature coefficient of these resistors is approximately
50ppm/˚C. Gain using an external R

G = 1 +

6kΩ

R

G

resistor is—

G

8

11

16

7

V

OUT

1

50Ω

50Ω

1.2µH

1.2µH

INA103

V+

11

10

7

R

G

V

IN

16
15
13
14

6
2
1

INA103

∆

V

OUT

3

4

10kΩ

V–

Offset Adjust
Range = ±250mV.

G = 1 + —–

6kΩ

R

G

RTI

1µF Tantalum

+

9

16
15

–

V

IN

+

NOTES: (1) No R
See gain-set connections in Figure 4.
(2) R
gain-set connection in Figure 5.

13
14

R

G

6
2
1

for G = 100 is internal. See

G

INA103

8

+

V–

required for G = 1.

G

10

VO = G • V

R

L

11
7

GAIN GAIN (dB) RG (Ω)

1 0 Note 1

3.16 10 2774
10 20 667

31.6 30 196

100 40 60.6
316 50 19

1000 60 6

IN

(2)

FIGURE 1. Basic Circuit Configuration.

Accuracy and TCR of the external R

will also contribute to

G

gain error and temperature drift. These effects can be di­rectly inferred from the gain equation.

Connections available on A

and A2 allow external resistors

1

to be substituted for the internal 3kΩ feedback resistors. A
precision resistor network can be used for very accurate and
stable gains. To preserve the low noise of the INA103, the
value of external feedback resistors should be kept low.
Increasing the feedback resistors to 20kΩ would increase
noise of the INA103 to approximately 1.5nV/√Hz. Due to
the current-feedback input circuitry, bandwidth would also
be reduced.

NOISE PERFORMANCE

The INA103 provides very low noise with low source
impedance. Its 1nV/√Hz voltage noise delivers near theo­retical noise performance with a source impedance of 200Ω.

Relatively high input stage current is used to achieve this
low noise. This results in relatively high input bias current
and input current noise. As a result, the INA103 may not
provide best noise performance with source impedances
greater than 10kΩ. For source impedance greater than 10kΩ,
consider the INA114 (excellent for precise DC applica­tions), or the INA111 FET-input IA for high speed applica­tions.

FIGURE 2. Input Stabilization Network.

Offset voltage can be trimmed with the optional circuit
shown in Figure 3. This offset trim circuit primarily adjusts
the output stage offset, but also has a small effect on input
stage offset. For a 1mV adjustment of the output voltage, the
input stage offset is adjusted approximately 1µV. Use this
adjustment to null the INA103’s offset voltage with zero
differential input voltage. Do not use this adjustment to null
offset produced by a sensor, or offset produced by subse­quent stages, since this will increase temperature drift.

To offset the output voltage without affecting drift, use the
circuit shown in Figure 4. The voltage applied to pin 7 is
summed at the output. The op amp connected as a buffer
provides a low impedance at pin 7 to assure good common­mode rejection.

Figure 5 shows a method to trim offset voltage in AC­coupled applications. A nearly constant and equal input bias
current of approximately 2.5µA flows into both input termi­nals. A variable input trim voltage is created by adjusting the
balance of the two input bias return resistances through
which the input bias currents must flow.

OFFSET ADJUSTMENT

Offset voltage of the INA103 has two components: input
stage offset voltage is produced by A
stage offset is produced by A
offset are laser trimmed and may not need adjustment in
many applications.

and A2; and, output

. Both input and output stage

3

1

FIGURE 3. Offset Adjustment Circuit.

9

®

INA103

Figure 6 shows an active control loop that adjusts the output
offset voltage to zero. A

, R, and C form an integrator that

2

produces an offsetting voltage applied to one input of the
INA103. This produces a –6dB/octave low frequency roll­off like the capacitor input coupling in Figure 5.

COMMON-MODE INPUT RANGE

For proper operation, the combined differential input signal
and common-mode input voltage must not cause the input
amplifiers to exceed their output swing limits. The linear
input range is shown in the typical performance curve
“Maximum Common-Mode Voltage vs Output Voltage.”
For a given total gain, the input common-mode range can be
increased by reducing the input stage gain and increasing the
output stage gain with the circuit shown in Figure 7.

16
15
13
14

V

∆

IN

6
2
1

INA103

NOTE: (1) 1/2 REF200

11
7

OPA27

Offset Adjustment

Range = ±15mV

10

Gain = 1V/V

(0dB)

V

OUT

100µA

–
+

10kΩ

100µA

V+

(1)

150Ω

150Ω

(1)

V–

OUTPUT SENSE

An output sense terminal allows greater gain accuracy in
driving the load. By connecting the sense connection at the
load, I•R voltage loss to the load is included inside the
feedback loop. Current drive can be increased by connect­ing a current booster inside the feedback loop as shown in
Figure 11.

–

+

I

≈ I

≈ 2.5µA

B

–In

+In

50kΩ

B

16

–

I

15

B

13
14

6
2

+

I

B

1

(1)

100kΩ

50kΩ

(1)

(1)

Gain = 100V/V

(40dB)

11

INA103

NOTE: (1) 50k R, 100k pot is
max recommended value. Use
smaller values in this ratio if possible.

ΩΩ

10

V

7

OUT

FIGURE 4. Output Offsetting. FIGURE 5. Input Offset Adjustment for AC-Coupled Inputs.

Gain = 100V/V

INA103

(40dB)

11

7

1/2 OPA1013

Ω

1µF

A

–3dB

=

Gain

12π RC

f

10

C

2

V

OUT

R
100kΩ

–
+

–In

+In

100kΩ

16
15
13
14

6
2
1

(1)

(1)

100kΩ

10kΩ

2kΩ

NOTE: (1) 100k is max recommended
value. Use smaller value if possible.

FIGURE 6. Automatic DC Restoration.

®

INA103

10

R

11

10

7

V

IN

16
15
13
14

6
2
1

INA103

∆

V

OUT

R

G

V+

V–

MJ15012

100

MJ15011

(To headphone
or speaker)

Buffer inside feedback loop

Ω

F

16

R

15
13
14

V

∆

IN

6
2
1

Output Stage Gain =

(R2 || 12k) + R1 + R

(R2 || 12k)

11

INA103

10

7

OUTPUT STAGE R1 and R3R

GAIN (kΩ)(Ω)

3

2 1k 2.4k
5 1.2k 632Ω

10 1.2k 273Ω

1

16

R

2

V

OUT

∆

V

R

3

2

IN

15
13
14

R

G

INA103

6
2
1

R

F

12

11

10

7

5

2R

G = 1+

F

R

G

RF > 10kΩ can increase noise and reduce bandwidth—see text.

NOTE: AD625 equivalent pinout.

FIGURE 7. Gain Adjustment of Output Stage. FIGURE 8. Use of External Resistors for Gain Set.

V

OUT

(a) AD625 G = 1, VIN = ±15V, RL = 600Ω

A common problem with many IC op amps and instrumentation amplifiers is shown in (a). Here, the amplifier’s input is driven beyond its linear common-mode
range, forcing the output of the amplifier into the supply rails. The output then “folds back”, i.e., a more positive input voltage now causes the output of the amplifier
to go negative. The INA103 has protection circuitry to prevent fold-back, and as shown in (b), limits cleanly.

(b) INA103 G = 1, V

= ±15V, RL = 600Ω

IN

FIGURE 9. INA103 Overload Condition Performance.

Gain = 1V/V

16
15
13
14

V

∆

IN

INA103

6
2
1

Introduces

FIGURE 10. Optional Circuit for Externally Trimming CMR.

approximately

+0.2% Gain Error.

(0dB)

20Ω

10Ω

11

10

7

CMR

Trim

FIGURE 11. Increasing Output Circuit Drive.

®

11

INA103

cm

47µF/63V

Phantom

Power

47kΩ

47µF/63V

+

2.2kΩ

240Ω

+

2.2kΩ

240Ω

20dB

Pad

20dB

Pad

10Ω

Gain

Adjust

6.8kΩ

1

3

2

6.8kΩ

+48V

1kΩ

16
15
13
14

6
2
1

INA103

FIGURE 12. Microphone Preamplifier with Provision for Phantom Power Microphones.

16

10kΩ

∆

V

IN

10kΩ

15
13
14

6
2
1

INA103

12

11

10

7

5

11

10

7

1µF

OPA627

Output offset voltage
control loop.

10kΩ

V

OUT

10kΩ

V

OUT

100kΩ

–
+

100Ω

–
+

OPA602

FIGURE 13. Instrumentation Amplifier with Shield Driver.

–
+

OPA627

∆

V

IN

–
+

OPA627

16
15
13
14

6
2
1

FIGURE 14. Gain-of-100 INA103 with FET Buffers.

Shield driver minimizes degradation of CMR due
to distributed capacitance on the input lines.

11

INA103

Gain = 100V/V

(40dB)

10

7

V = 100

OUT

∆

V

IN

®

INA103

12

PACKAGE OPTION ADDENDUM

www.ti.com

22-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

INA103KP ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br)

INA103KPG4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br)

INA103KU ACTIVE SOIC DW 16 48 Green (RoHS &

no Sb/Br)

INA103KU/1K ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br)

INA103KU/1KE4 ACTIVE SOIC DW 16 1000 Green (RoHS &

no Sb/Br)

INA103KUG4 ACTIVE SOIC DW 16 48 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

Type

INA103KU/1K SOIC DW 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

INA103KU/1K SOIC DW 16 1000 346.0 346.0 33.0

Pack Materials-Page 2

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