The INA103 is a very low noise, low distortion monolithic instrumentation amplifier. Its current-feedback
circuitry achieves very wide bandwidth and excellent
dynamic response. It is ideal for low-level audio
signals such as balanced low-impedance microphones.
The INA103 provides near-theoretical limit noise performance for 200Ω source impedances. Many industrial applications also benefit from its low noise and
wide bandwidth.
Unique distortion cancellation circuitry reduces distortion to extremely low levels, even in high gain. Its
balanced input, low noise and low distortion provide
superior performance compared to transformer-coupled
microphone amplifiers used in professional audio
equipment.
The INA103’s wide supply voltage (±9 to ±25V) and
high output current drive allow its use in high-level
audio stages as well. A copper lead frame in the plastic
DIP assures excellent thermal performance.
The INA103 is available in 16-pin plastic DIP and
SOL-16 surface-mount packages. Commercial and Industrial temperature range models are available.
Offset
Null
34
9
V+
Offset
6k
–
A
+
6k
Null
Ω
3
Ω
V–
11
Sense
Output
10
Ref
7
8
–Input
–Gain Sense
–R
G = 100
+R
+Gain Sense
+Input
–Gain Drive
12
Ω
1
3kΩ
3k
Ω
2
5
+Gain Drive
6k
Ω
6k
+
16
A
–
15
13
G
60.6Ω
14
6
G
–
2
A
+
1
SBOS003
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Voltage1kHz65nV/√Hz
A Weighted, 20Hz-20kHz20Hz-20kHz–100dBu
DYNAMIC RESPONSE
–3dB Bandwidth: G = 1Small Signal6MHz
Full Power BandwidthG = 1
V
OUT
Slew RateG = 1 to 50015V/µs
THD + NoiseG = 100, f = 1kHz0.0009%
Settling Time 0.1%
G = 1V
G = 1001.5µs
Settling Time 0.01%
G = 1V
G = 1003.5µs
Overload Recovery
NOTES: (1) Gains other than 1 and 100 can be set by adding an external resistor, RG between pins 2 and 15. Gain accuracy is a function of RG. (2) FS = Full Scale.
(3) Adjustable to zero. (4) V
for output to return from saturation to linear operation following the removal of an input overdrive voltage.
(1)
G = 1 + 6kΩ/R
G
V/V
G = 1000.070.25%
Equation0.05%
G = 10025ppm/°C
Equation25ppm/°C
G = 1000.00060.01% of FS
= 600ΩTA = T
L
R
= 600ΩVS = ±25, TA = 25°C±20± 21V
L
(3)
G = 1000T
(4)
(5)
A
A
A
A
A
= T
= T
= T
= T
= T
to T
MIN
to T
MIN
to T
MIN
to T
MIN
to T
MIN
to T
MIN
RS = 0Ω
MAX
MAX
MAX
MAX
MAX
MAX
±11.5± 12V
±40mA
(30 + 1200/G)µV
1 + 20/GµV/°C
µV/°C
15nA/°C
0.5nA/°C
±11± 12V
G = 100Small Signal800kHz
= ±10V, RL = 600Ω240kHz
= 20V Step1.7µs
O
= 20V Step2µs
O
(6)
= 0V, see Typical Curves for VCM vs VO. (5) V
O
50% Overdrive1µs
2
NOISE RTI
= √V
N INPUT
+ (V
/Gain)2 + 4KTRG. See Typical Curves. (6) Time required
N OUTPUT
(2)
®
INA103
2
SPECIFICATIONS (CONT)
All specifications at TA = +25°C, VS = ±15V and RL = 2kΩ, unless otherwise noted.
INA103KP, KU
PARAMETERCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
Rated Voltage±15V
Voltage Range±9±25V
Quiescent Current912.5mA
INA103KPPlastic DIP1800°C to +70°C
INA103KUSOL-162110°C to +70°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
(1)
RANGE
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ....................................................................... ±25V
Input Voltage Range, Continuous ....................................................... ±V
Operating Temperature Range:........................................–40°C to +85 °C
Storage Temperature Range: ........................................... –40°C to +85°C
Junction Temperature:
P, U Package.............................................................................. +125°C
Lead Temperature (soldering, 10s) ............................................... +300°C
Output Short Circuit to Common ............................................. Continuous
NOTE: (1) Stresses above these ratings may cause permanent damage.
(1)
S
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
INA103
®
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
±25
±20
±15
±10
Input Voltage Range (V)
±5
±5±10±15±20±25
22
16.5
11
5.5
Common-Mode Voltage (V)
INPUT VOLTAGE RANGE vs SUPPLY
Power Supply Voltage (V)
MAX COMMON-MODE VOLTAGE
vs OUTPUT VOLTAGE
V = ±25V
S
V = ±15V
S
±25
±20
±15
Output Voltage (V)
±10
±5
±5±10±15±20±25
±16
±12
±8
Output Voltage (V)
±4
OUTPUT SWING vs SUPPLY
Power Supply Voltage (V)
OUTPUT SWING vs LOAD RESISTANCE
05.51116.522
Output Voltage (V)
OFFSET VOLTAGE vs TIME FROM POWER UP
20
10
OSI
0
Change In V (µV)
–10
–20
01245
®
(G = 100)
3
Time (min)
INA103
2.60
2.55
2.50
2.45
2.40
2.35
Input Bias Current (µA)
2.30
2.25
4
±0
02004006008001k
Load Resistance ( )
INPUT BIAS CURRENT vs SUPPLY
910152025
Power Supply Voltage (±V)
Ω
TYPICAL PERFORMANCE CURVES(CONT)
SETTLING TIME vs GAIN
(0.1%, 20V STEP)
Settling Time (µs)
Gain
1101001000
10
8
6
4
2
0
At TA = +25°C, VS = ±15V, unless otherwise noted.
6
5
4
3
Input Bias Current (µA)
2
1
INPUT BIAS CURRENT vs TEMPERATURE
–55
SMALL SIGNAL TRANSIENT RESPONSE
050100125
Temperature (°C)
(G = 100)
SMALL SIGNAL TRANSIENT RESPONSE
(G = 1)
Output Voltage (V)
Time (µs)
LARGE SIGNAL TRANSIENT RESPONSE
(G = 1)
Output Voltage (V)
Time (µs)
LARGE SIGNAL TRANSIENT RESPONSE
Output Voltage (V)
(G = 100)
Time (µs)
Output Voltage (V)
Time (µs)
®
5
INA103
TYPICAL PERFORMANCE CURVES(CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
SETTLING TIME vs GAIN
10
8
6
4
Settling Time (µs)
2
0
1101001000
(0.01%, 20V STEP)
Gain
70
60
50
40
30
20
10
0
Gain (dB)
–10
–20
–30
–40
–50
101001k10k100k1M10M
SMALL-SIGNAL FREQUENCY RESPONSE
G = 1000
G = 100
G = 10
G = 1
Frequency (Hz)
1k
100
√
10
Noise (RTI) (nV/ Hz)
1
101001k10k
1
0.1
0.010
THD + N (%)
0.001
0.0001
10100
NOISE VOLTAGE (RTI) vs FREQUENCY
G = 100
Frequency (Hz)
THD + N vs FREQUENCY
G = 1000
G = 1
G = 100
G = 10
1k
Frequency (Hz)
G = 1
G = 10
G = 500
G = 1000
V = +18dBu
OUT
10k 20k
140
120
100
80
60
40
Common-Mode Rejection (dB)
20
0
101M
140
G = 100
G = 10
120
G = 1
100
80
60
40
Power Supply Rejection (dB)
20
0
11M101001k10k100k
CMR vs FREQUENCY
1001k10k100k
Frequency (Hz)
V+ POWER SUPPLY REJECTION
vs FREQUENCY
G = 1000
Frequency (Hz)
G = 1000
G = 500
G = 100
G = 10
G = 1
®
INA103
6
TYPICAL PERFORMANCE CURVES(CONT)
1
0.1
0.010
0.001
0.0001
CCIF IMD (%)
CCIF IMD vs AMPLITUDE
–60–50–40–30–20–1001020
Output Amplitude (dBu)
5
G = 1000
G = 100
G = 1
G = 10
1
0.1
0.010
0.001
SMPTE IMD (%)
SMPTE IMD vs AMPLITUDE
–60–50–40–30–20–1001020
Output Amplitude (dBu)
5
G = 1000
G = 100
G = 1
G = 10
0.0005
At TA = +25°C, VS = ±15V, unless otherwise noted.
V– POWER SUPPLY REJECTION
140
120
100
80
G = 100, 1000
G = 10
G = 1
vs FREQUENCY
1
0.1
THD + N vs LEVEL
f = 1kHz
60
40
Power Supply Rejection (dB)
20
0
11M101001k10k100k
Frequency (Hz)
0.1
0.01
THD + N (%)
0.001
0.0001
2004006008001k
THD + N vs LOAD
Ω
R ( )
LOAD
G = 1
V = 20Vp-p
OUT
f = 1kHz
0.010
THD + N (%)
0.001
0.0005
–60–45–30–15015
Output Amplitude (dBu)
G = 1
5
1
0.1
0.010
CCIF IMD (%)
0.001
0.0001
2k10k20k
CCIF IMD vs FREQUENCY
G = 1000
G = 100
G = 10
G = 1
Frequency (Hz)
®
7
INA103
TYPICAL PERFORMANCE CURVES(CONT)
At TA = +25°C, VS = ±15V unless, otherwise noted.
5
1
0.1
SMPTE IMD (%)
0.010
0.001
0.0005
2k10k20k
SMPTE IMD vs FREQUENCY
G = 1000
G = 100
G = 1
G = 10
Frequency (Hz)
100
10
Current Noise Density (pA/ Hz)
1
CURRENT NOISE SPECTRAL DENSITY
1101001k10k
Frequency (Hz)
APPLICATIONS INFORMATION
Figure 1 shows the basic connections required for operation.
Power supplies should be bypassed with 1µF tantalum
capacitors near the device pins. The output Sense (pin 11)
and output Reference (pin 7) should be low impedance
connections. Resistance of a few ohms in series with these
connections will degrade the common-mode rejection of the
amplifier.
To avoid oscillations, make short, direct connection to the
gain set resistor and gain sense connections. Avoid running
output signals near these sensitive input nodes.
INPUT CONSIDERATIONS
Certain source impedances can cause the INA103 to oscillate. This depends on circuit layout and source or cable
characteristics connected to the input. An input network
consisting of a small inductor and resistor (Figure 2) can
greatly reduce the tendancy to oscillate. This is especially
®
INA103
useful if various input sources are connected to the INA103.
Although not shown in other figures, this network can be
used, if needed, with all applications shown.
GAIN SELECTION
Gains of 1 or 100V/V can be set without external resistors.
For G = 1V/V (unity gain) leave pin 14 open (no connection)—see Figure 4. For G = 100V/V, connect pin 14 to pin
6—see Figure 5.
Gain can also be accurately set with a single external resistor
as shown in Figure 1. The two internal feedback resistors are
laser-trimmed to 3kΩ within approximately ±0.1%. The
temperature coefficient of these resistors is approximately
50ppm/˚C. Gain using an external R
G = 1 +
6kΩ
R
G
resistor is—
G
8
11
16
7
V
OUT
1
50Ω
50Ω
1.2µH
1.2µH
INA103
V+
11
10
7
R
G
V
IN
16
15
13
14
6
2
1
INA103
∆
V
OUT
3
4
10kΩ
V–
Offset Adjust
Range = ±250mV.
G = 1 + —–
6kΩ
R
G
RTI
1µF Tantalum
+
9
16
15
–
V
IN
+
NOTES: (1) No R
See gain-set connections in Figure 4.
(2) R
gain-set connection in Figure 5.
13
14
R
G
6
2
1
for G = 100 is internal. See
G
INA103
8
+
V–
required for G = 1.
G
10
VO = G • V
R
L
11
7
GAINGAIN (dB) RG (Ω)
10Note 1
3.16102774
1020667
31.630196
1004060.6
3165019
1000606
IN
(2)
FIGURE 1. Basic Circuit Configuration.
Accuracy and TCR of the external R
will also contribute to
G
gain error and temperature drift. These effects can be directly inferred from the gain equation.
Connections available on A
and A2 allow external resistors
1
to be substituted for the internal 3kΩ feedback resistors. A
precision resistor network can be used for very accurate and
stable gains. To preserve the low noise of the INA103, the
value of external feedback resistors should be kept low.
Increasing the feedback resistors to 20kΩ would increase
noise of the INA103 to approximately 1.5nV/√Hz. Due to
the current-feedback input circuitry, bandwidth would also
be reduced.
NOISE PERFORMANCE
The INA103 provides very low noise with low source
impedance. Its 1nV/√Hz voltage noise delivers near theoretical noise performance with a source impedance of 200Ω.
Relatively high input stage current is used to achieve this
low noise. This results in relatively high input bias current
and input current noise. As a result, the INA103 may not
provide best noise performance with source impedances
greater than 10kΩ. For source impedance greater than 10kΩ,
consider the INA114 (excellent for precise DC applications), or the INA111 FET-input IA for high speed applications.
FIGURE 2. Input Stabilization Network.
Offset voltage can be trimmed with the optional circuit
shown in Figure 3. This offset trim circuit primarily adjusts
the output stage offset, but also has a small effect on input
stage offset. For a 1mV adjustment of the output voltage, the
input stage offset is adjusted approximately 1µV. Use this
adjustment to null the INA103’s offset voltage with zero
differential input voltage. Do not use this adjustment to null
offset produced by a sensor, or offset produced by subsequent stages, since this will increase temperature drift.
To offset the output voltage without affecting drift, use the
circuit shown in Figure 4. The voltage applied to pin 7 is
summed at the output. The op amp connected as a buffer
provides a low impedance at pin 7 to assure good commonmode rejection.
Figure 5 shows a method to trim offset voltage in ACcoupled applications. A nearly constant and equal input bias
current of approximately 2.5µA flows into both input terminals. A variable input trim voltage is created by adjusting the
balance of the two input bias return resistances through
which the input bias currents must flow.
OFFSET ADJUSTMENT
Offset voltage of the INA103 has two components: input
stage offset voltage is produced by A
stage offset is produced by A
offset are laser trimmed and may not need adjustment in
many applications.
and A2; and, output
. Both input and output stage
3
1
FIGURE 3. Offset Adjustment Circuit.
9
®
INA103
Figure 6 shows an active control loop that adjusts the output
offset voltage to zero. A
, R, and C form an integrator that
2
produces an offsetting voltage applied to one input of the
INA103. This produces a –6dB/octave low frequency rolloff like the capacitor input coupling in Figure 5.
COMMON-MODE INPUT RANGE
For proper operation, the combined differential input signal
and common-mode input voltage must not cause the input
amplifiers to exceed their output swing limits. The linear
input range is shown in the typical performance curve
“Maximum Common-Mode Voltage vs Output Voltage.”
For a given total gain, the input common-mode range can be
increased by reducing the input stage gain and increasing the
output stage gain with the circuit shown in Figure 7.
16
15
13
14
V
∆
IN
6
2
1
INA103
NOTE: (1) 1/2 REF200
11
7
OPA27
Offset Adjustment
Range = ±15mV
10
Gain = 1V/V
(0dB)
V
OUT
100µA
–
+
10kΩ
100µA
V+
(1)
150Ω
150Ω
(1)
V–
OUTPUT SENSE
An output sense terminal allows greater gain accuracy in
driving the load. By connecting the sense connection at the
load, I•R voltage loss to the load is included inside the
feedback loop. Current drive can be increased by connecting a current booster inside the feedback loop as shown in
Figure 11.
–
+
I
≈ I
≈ 2.5µA
B
–In
+In
50kΩ
B
16
–
I
15
B
13
14
6
2
+
I
B
1
(1)
100kΩ
50kΩ
(1)
(1)
Gain = 100V/V
(40dB)
11
INA103
NOTE: (1) 50k R, 100k pot is
max recommended value. Use
smaller values in this ratio if possible.
NOTE: (1) 100k is max recommended
value. Use smaller value if possible.
FIGURE 6. Automatic DC Restoration.
®
INA103
10
R
11
10
7
V
IN
16
15
13
14
6
2
1
INA103
∆
V
OUT
R
G
V+
V–
MJ15012
100
MJ15011
(To headphone
or speaker)
Buffer inside feedback loop
Ω
F
16
R
15
13
14
V
∆
IN
6
2
1
Output Stage Gain =
(R2 || 12k) + R1 + R
(R2 || 12k)
11
INA103
10
7
OUTPUT STAGE R1 and R3R
GAIN(kΩ)(Ω)
3
21k2.4k
51.2k632Ω
101.2k273Ω
1
16
R
2
V
OUT
∆
V
R
3
2
IN
15
13
14
R
G
INA103
6
2
1
R
F
12
11
10
7
5
2R
G = 1+
F
R
G
RF > 10kΩ can increase noise and reduce bandwidth—see text.
NOTE: AD625 equivalent pinout.
FIGURE 7. Gain Adjustment of Output Stage.FIGURE 8. Use of External Resistors for Gain Set.
V
OUT
(a) AD625 G = 1, VIN = ±15V, RL = 600Ω
A common problem with many IC op amps and instrumentation amplifiers is shown in (a). Here, the amplifier’s input is driven beyond its linear common-mode
range, forcing the output of the amplifier into the supply rails. The output then “folds back”, i.e., a more positive input voltage now causes the output of the amplifier
to go negative. The INA103 has protection circuitry to prevent fold-back, and as shown in (b), limits cleanly.
(b) INA103 G = 1, V
= ±15V, RL = 600Ω
IN
FIGURE 9. INA103 Overload Condition Performance.
Gain = 1V/V
16
15
13
14
V
∆
IN
INA103
6
2
1
Introduces
FIGURE 10. Optional Circuit for Externally Trimming CMR.
approximately
+0.2% Gain Error.
(0dB)
20Ω
10Ω
11
10
7
CMR
Trim
FIGURE 11. Increasing Output Circuit Drive.
®
11
INA103
cm
47µF/63V
Phantom
Power
47kΩ
47µF/63V
+
2.2kΩ
240Ω
+
2.2kΩ
240Ω
20dB
Pad
20dB
Pad
10Ω
Gain
Adjust
6.8kΩ
1
3
2
6.8kΩ
+48V
1kΩ
16
15
13
14
6
2
1
INA103
FIGURE 12. Microphone Preamplifier with Provision for Phantom Power Microphones.
16
10kΩ
∆
V
IN
10kΩ
15
13
14
6
2
1
INA103
12
11
10
7
5
11
10
7
1µF
OPA627
Output offset voltage
control loop.
10kΩ
V
OUT
10kΩ
V
OUT
100kΩ
–
+
100Ω
–
+
OPA602
FIGURE 13. Instrumentation Amplifier with Shield Driver.
–
+
OPA627
∆
V
IN
–
+
OPA627
16
15
13
14
6
2
1
FIGURE 14. Gain-of-100 INA103 with FET Buffers.
Shield driver minimizes degradation of CMR due
to distributed capacitance on the input lines.
11
INA103
Gain = 100V/V
(40dB)
10
7
V = 100
OUT
∆
V
IN
®
INA103
12
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
PACKAGING INFORMATION
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
INA103KPACTIVEPDIPN1625Green (RoHS &
no Sb/Br)
INA103KPG4ACTIVEPDIPN1625Green (RoHS &
no Sb/Br)
INA103KUACTIVESOICDW1648Green (RoHS &
no Sb/Br)
INA103KU/1KACTIVESOICDW161000 Green (RoHS &
no Sb/Br)
INA103KU/1KE4ACTIVESOICDW161000 Green (RoHS &
no Sb/Br)
INA103KUG4ACTIVESOICDW1648Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-3-260C-168 HR
CU NIPDAULevel-3-260C-168 HR
CU NIPDAULevel-3-260C-168 HR
CU NIPDAULevel-3-260C-168 HR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.