Texas Instruments FlatLink SN75LVDS83B User Manual
User's Guide
SNLU233–October 2017
LVDS83BTSSOPEVM User’s Guide
The SN75LVDS83B FlatLink™ transmitter contains the following functions within a single integrated
circuit:
• Four 7-bit, parallel-load, serial-out, shift registers
• A 7x clock synthesizer
• Five low-voltage differential signaling (LVDS) line drivers
These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five
balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels
with integrated LVDS receivers.
This evaluation module (EVM) acts as a reference design that can be easily modified for any projected
application. Target applications include the following:
• LCD panel drivers
• Ultra-mobile PCs (UMPCs)
• Netbook PCs
• Digital picture frames
Schematics and layout information are included at the end of the manual.
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LVDS83BTSSOPEVM User’s Guide
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Contents
1 Introduction ................................................................................................................... 3
2 LVDS83BTSSOPEVM Configuration...................................................................................... 3
2.1 LVDS83BTSSOPEVM Kit Contents.............................................................................. 3
2.2 Description of EVM Board ......................................................................................... 3
2.3 Power-Up Sequence ............................................................................................... 4
2.4 Signal Connectivity ................................................................................................. 5
3 PCB Construction .......................................................................................................... 10
3.1 LVDS83BTSSOPEVM Board Layout ........................................................................... 10
4 LVDS83BTSSOPEVM Bill of Materials.................................................................................. 17
5 LVDS83BTSSOPEVM Schematics ...................................................................................... 18
List of Figures
1 LVDS83BTSSOPEVM ...................................................................................................... 3
2 Clock Rising Edge (High) Jumper Setting................................................................................ 4
3 Clock Falling Edge (Low) Jumper Setting................................................................................ 4
4 Active Shutdown/Clear Jumper Setting................................................................................... 4
5 24-Bit Color Host to 24-Bit LCD Panel Application With 2 MSB Transfer Over Fourth Data Channel .......... 6
6 24-Bit Color Host to 24-Bit LCD Panel Application With 2 LBS Transfer Over Fourth Data Channel............ 7
7 18-Bit Color Host to 18-Bit LCD Panel Application...................................................................... 8
8 12-Bit Color Host to 18-Bit LCD Panel Application...................................................................... 9
9 24-Bit Color Host to 18-Bit LCD Panel Application .................................................................... 10
10 LVDS83BTSSOPEVM Top Layer........................................................................................ 11
11 LVDS83BTSSOPEVM Layer 2 – GND.................................................................................. 12
12 LVDS83BTSSOPEVM Layer 3 – DUT GND............................................................................ 13
13 LVDS83BTSSOPEVM Layer 4 – V
.................................................................................... 14
CC
14 LVDS83BTSSOPEVM Layer 5 – GND.................................................................................. 15
15 LVDS83BTSSOPEVM Bottom Layer .................................................................................... 16
16 LVDS83BTSSOPEVM Schematics (1/3)................................................................................ 18
17 LVDS83BTSSOPEVM Schematics (2/3)................................................................................ 19
18 LVDS83BTSSOPEVM Schematic (3/3) ................................................................................. 20
1 BOM.......................................................................................................................... 17
Trademarks
FlatLink is a trademark of Texas Instruments.
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LVDS83BTSSOPEVM User’s Guide
List of Tables
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CLKIN
CLKSEL
DUT_GND
SHTDN
DUT_GND
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN 1
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
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1 Introduction
The SN75LVDS83B FlatLink transmitter is a single integrated circuit which contains four 7-bit, parallelload, serial-out, shift registers, a 7x clock synthesizer, and LVDS line drivers. This user’s guide describes
the construction and handling of the EVM for the SN75LVDS83B. The guide serves as an evaluation tool
for the SN75LVDS83B, as well as a reference design for the device.
Introduction
2 LVDS83BTSSOPEVM Configuration
2.1 LVDS83BTSSOPEVM Kit Contents
This EVM kit contains the following items:
• LVDS83BTSSOPEVM board
• LVDS83BTSSOPEVM User’s Guide
2.2 Description of EVM Board
The LVDS83BTSSOPEVM is designed to provide straightforward evaluation of the SN75LVDS83B device
using four 7-bit, parallel-load, serial-out, shift registers. Power to the board is provided through banana
jacks P4 for VCC and P1 for VCCIO. For correct board operation, power must be fixed at VCC = 3.3 V,
and the I/O power (VCCIO) may be adjusted at 1.8 V, 2.5 V, or 3.3 V.
The transmission of data bits D0 through D27 occurs as each bit is loaded into registers upon the edge of
the CLKIN signal (JMP5), where the rising or falling edge of the clock may be selected using CLKSEL
(JMP7). To select a clock rising edge, input a high level to CLKSEL. Removing the strap on the jumper
allows the pull-up resistor to pull CLKSEL=high (see Figure 2). To input a low level to select a clock falling
edge, place the strap on the jumper to allow a path to GND (see Figure 3).
Additionally, use of SHTDN (JMP8) for possible Shutdown/Clear settings can be obtained with an activelow input, by placing the strap on the jumper to allow a path to GND, which inhibits the clock and shuts off
the LVDS output drivers for lower power consumption (see Figure 4). A low-level on this signal clears all
internal registers to a low-level. Remove the strap on JMP8 to enable the device for normal operation.
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Figure 1. LVDS83BTSSOPEVM
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LVDS83BTSSOPEVM User’s Guide
3
R2
SHTDN
DUT_GND
JMP8
Pull-up resistor
R1
CLKSEL
DUT_GND
JMP7
Pull-up resistor
R1
CLKSEL
DUT_GND
JMP7
Pull-up resistor
LVDS83BTSSOPEVM Configuration
Figure 2. Clock Rising Edge (High) Jumper Setting
Figure 3. Clock Falling Edge (Low) Jumper Setting
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2.3 Power-Up Sequence
The SN75LVDS83B does not require a specific power-up sequence; however, it is permitted to power up
the IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND. The input
level of Shutdown/Clear during this time does not matter because only the input stage is powered up while
all other devices blocks are still powered down.
Additionally, it is also permitted to power up all 3.3 V power domains while IOVCC is still powered down to
GND. The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH,
regardless of the input voltage level. Therefore connecting Shutdown/Clear to GND will still be interpreted
as logic HIGH, consequently turning the LVDS output stage on. The power consumption at this stage is
significantly higher that in standby mode, but lower than normal mode.
The user experience may be impacted by the way a system powers up and powers down an LCD screen.
The following sequences are suggested:
Power-up sequence (SN75LVDS83B SHTDN input initially LOW):
1. Ramp up the LCD power (0.5 ms to 10 ms) with the backlight turned off.
2. Wait an additional 0 to 200 ms to avoid display noise.
3. Enable the video source output – start sending black video data.
4
LVDS83BTSSOPEVM User’s Guide
Figure 4. Active Shutdown/Clear Jumper Setting
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4. Toggle SN75LVDS83B shutdown to SHTDN = VIH.
5. Send > 1 ms of black data to allow the SN75LVDS83B to be phase-locked and allow the display to
show black data first.
6. Start sending true imaging data.
7. Enable the backlight.
Power-down sequence (SN75LVDS83B SHTDN input initially HIGH):
1. Disable the LCD backlight and wait for the minimum time specified in the LCF data sheet for the
backlight to go low.
2. Switch the video source output data from active video to black data image (all visible pixels turn black)
on a drive > 2 frame times.
3. Set SN75LVDS83B SHTDN = GND and wait for 250 ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for the lowest system power.
2.4 Signal Connectivity
While there is no formal, industrial standardization for the input interface of LVDS LCD panels, over the
years the industry has aligned a specific data bit order format. Figure 5 through Figure 9 show how each
signal must be connected from the graphic source through the SN75LVDS83B input/output and LVDS
LCD panel input.
The outputs are available at J1 to J10 for direct connection to oscilloscope inputs. Matched length cables
must be used when connecting the EVM to a scope to avoid inducing skew between the noninverting (+)
and inverting (-) outputs.
Power jacks P1 to P4 are used to provide power, ground, and signal ground reference for the EVM. The
power connections to the EVM determine the common-mode load to the device, because LVDS drivers
have limited common-mode driver capability. When connecting the EVM outputs directly to oscilloscope
inputs, setting the common-mode offset voltage of the oscilloscope is required, because it presents low
common-mode load impedance to the device.
In Figure 5 through Figure 9, the power supply is used to provide the required 3.3 V to the EVM.
Additionally, the signal ground input from the power supply is used to offset the EVM ground relative to the
DUT ground. Obtain optimum device setup by adjusting the signal ground voltage on the power supply
until its current is minimized. It is important to note that use of the dual supplies and offsetting the EVM
ground relative to the DUT ground are simply steps needed for the test and evaluation of devices. Actual
designs would include receivers 100-Ω termination resistor across each differential input while keeping a
high-impedance between each RX input signal and GND, which would not require the setup steps
previously outlined.
LVDS83BTSSOPEVM Configuration
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LVDS83BTSSOPEVM User’s Guide
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CLKIN
CLKSEL
DUT_GND
SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V
1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN 1
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
24bpp LCD Display
FPC Cable
LVDS
Timing
Controller
(8bpc, 24bpp)
Notes:
Current setup uses rising edge triggered clocking. If
rising edge triggered clocking is desired, place jumper
to create LOW level input at JMP7.
100
To Column Driver
Panel Connector
Main Board Connector
100
100
100
100
To Row Driver
24-bpc GPU
R0 (LSB)
R1
R2
R3
R4
R5
R6
R7 (MSB)
G0 (LSB)
G1
G2
G3
G4
G5
G6
G7 (MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7 (MSB)
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
LVDS83BTSSOPEVM Configuration
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This configuration is most popular for 24-bit panels.
6
LVDS83BTSSOPEVM User’s Guide
Figure 5. 24-Bit Color Host to 24-Bit LCD Panel Application
With 2 MSB Transfer Over Fourth Data Channel
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CLKSEL
DUT_GND
SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V
1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN 1
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
24bpp LCD Display
FPC Cable
LVDS
Timing
Controller
(8bpc, 24bpp)
Notes:
Current setup uses rising edge triggered clocking. If
rising edge triggered clocking is desired, place jumper
to create LOW level input at JMP7.
100
To Column Driver
Panel Connector
Main Board Connector
100
100
100
100
To Row Driver
24-bpc GPU
R0 (LSB)
R1
R2
R3
R4
R5
R6
R7 (MSB)
G0 (LSB)
G1
G2
G3
G4
G5
G6
G7 (MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7 (MSB)
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
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LVDS83BTSSOPEVM Configuration
This configuration is fairly uncommon.
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Figure 6. 24-Bit Color Host to 24-Bit LCD Panel Application
With 2 LBS Transfer Over Fourth Data Channel
Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM User’s Guide
7
CLKSEL
DUT_GND
SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V
1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
U1
PIN 1
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
LVDS
Timing
Controller
(8bpc, 18bpp)
Notes:
Current setup uses rising edge triggered clocking. If
rising edge triggered clocking is desired, place jumper
to create LOW level input at JMP7.
100
Panel Connector
Main Board Connector
100
100
100
18-bpc GPU
R0 (LSB)
R1
R2
R3
R4
R5 (MSB)
G0 (LSB)
G1
G2
G3
G4
G5 (MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0 (LSB)
B1
B2
B3
B4
B5 (MSB)
24bpp LCD Display
FPC Cable
To Column Driver
To Row Driver
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
SIGNAL_GNDSIGNAL_GND
SIGNAL_GNDSIGNAL_GND
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
LVDS83BTSSOPEVM Configuration
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Figure 7. 18-Bit Color Host to 18-Bit LCD Panel Application
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LVDS83BTSSOPEVM User’s Guide
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