Texas Instruments DP83640 Reference Manual
Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
HSMC
Ethernet 2-Port
1588 Precision Timing
PHY
Daughter Board
Reference Guide
1
Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
Table of Contents
1 INTRODUCTION ...................................................................................................................... 4
2 FEATURES .............................................................................................................................. 5
3 BOARD DESCRIPTION ........................................................................................................... 6
3.1 BLOCK DIAGRAM ................................................................................................................... 6
3.2 BOARD COMPONENTS ........................................................................................................... 7
3.2.1 LEDs .......................................................................................................................... 8
3.2.2 PHY Generic I/O (GPIO), J2, J3 ................................................................................ 8
3.2.3 Application (HSMC) General Purpose I/O, J4 ........................................................... 9
4 CLOCK DISTRIBUTION - MAC INTERFACE CLOCKING .................................................. 10
5 POWER-UP STRAP OPTIONS ............................................................................................. 11
5.1 PHY 1 STRAP OPTIONS ...................................................................................................... 11
5.2 PHY 2 STRAP OPTIONS ...................................................................................................... 12
6 MDIO MANAGEMENT ........................................................................................................... 13
7 HIGH SPEED MEZZANINE CARD (HSMC) CONNECTOR ................................................. 14
7.1 HSMC CONNECTOR PIN OUT TABLE .................................................................................... 14
7.2 PIN OUT DESCRIPTION ......................................................................................................... 17
8 PLCC-44 SOCKET ................................................................................................................ 19
9 PIN OUT FOR ALTERA STRATIX II GX PCIE BOARD ....................................................... 21
10 PIN OUT FOR ALTERA CYCLONE-III STARTER KIT BOARD ..................................... 23
11 REFERENCES ................................................................................................................. 25
12 CONTACT ........................................................................................................................ 26
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Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
List of Tables
Table 1: RJ45 LEDs .................................................................................................................................... 8
Table 2: PHY 1 Power-Up Strap Options ................................................................................................11
Table 3: PHY 2 Power-Up Strap Options ................................................................................................12
Table 4: PHY MDIO Addresses ................................................................................................................13
Table 5: HSMC Connector Pin out ...........................................................................................................14
Table 6: HSMC Connector Pin out Description ......................................................................................17
Table 7: PLCC-44 Socket Pin Description ..............................................................................................20
Table 8: HSMC Interface Signals (Stratix II GX PCIe Board) ..............................................................21
Table 9: HSMC Interface Signals (Cyclone-III Starter Kit Board) ........................................................23
List of Figures
Figure 1: Daughter Board ........................................................................................................................... 4
Figure 2: Board Block Diagram.................................................................................................................. 6
Figure 3: Board Components ..................................................................................................................... 7
Figure 4: GPIO Connector (J2, J3) ........................................................................................................... 8
Figure 5: Application General Purpose I/O Connector (J4) ................................................................... 9
Figure 6: Clock Distribution .......................................................................................................................10
Figure 7: Samtec ASP - 122952 - 01 .......................................................................................................14
Figure 8: PLCC-44 Top View ....................................................................................................................19
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Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
1 Introduction
The Nine Ways PhyworkX DP83640 Ethernet Development Kit provides an Ethernet PHY
Daughter Board implementing two 10/100 Ethernet copper ports with high precision IEEE
1588 time synchronization support.
The board implements two independent Ethernet interfaces with several system interface
options and can be used in single and multi-channel applications.
The daughter board implements a High Speed Mezzanine Card (HSMC) connector to the
main board that implements parallel RMII and provides the necessary 3.3V power supply.
In combination with the MorethanIP/Nine Ways Ethernet Cores (e.g. MAC, Switch, IEEE 1588)
the PHY daughter board can be used to quickly design, implement, prototype and test
embedded Ethernet Telecom or Industrial applications with support for precise timing
according to the IEEE 1588 standard.
The board is optionally available with reference designs using a MAC, with support for
IEEE1588, for precise time synchronization applications, or with a 3-port Switch application.
The board can be used with any Altera (e.g. Arria GX, Stratix II GX, Cyclone III) or Nine Ways
board that implements a HSMC connector.
Figure 1: Daughter Board
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2 Features
Two High Performance National DP83640 10/100 Ethernet PHY
o Integrated IEEE 1588 support with synchronizable timer
o Auto negotiation for automatic speed selection
o Automatic cable crossover configuration
o Reduced Media Independent Interface (RMII)
o PHY Management Interface (MDIO/MDC) for configuration/status
2x Standard Ethernet Copper RJ45 connector (10/100 Base-T)
Status LEDs for current speed, link and traffic indications
Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
4 General Purpose I/Os for timing event generation and capture
5 General Purpose I/Os available to the application
168pin High Speed Mezzanine Card (HSMC) Connector to main board providing
power supply and I/O interfaces
Single 3.3V power supply from HSMC Connector
2.5V and 3.3V I/O interfaces support
Example Reference Designs available for several Main boards upon request
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Dual DP83640 Ethernet PHY HSMC Daughter Board
HSMC Connector
National PHY1
DP83640
National PHY2
DP83640
RJ45
(integrated
Transformer)
General Purpose
Connector 5x2
Connector 4x2
RMII
Connector 4x2
Testsignals
Testsignals
PLCC-44
Socket
Optional
OTP Device
50MHz
RJ45
(integrated
Transformer)
25MHz
Refclk
3.3V
Power
Reference Guide
V1.0 - October 2013
3 Board Description
3.1 Block Diagram
The Board implements the copper line interfaces using a 2x RJ45 array with integrated
magnetics. The MAC interfaces are available at the HSMC connector using 2.5V/3.3V
LVTTL/LVCMOS signaling.
Figure 2: Board Block Diagram
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Dual DP83640 Ethernet PHY HSMC Daughter Board
Port0 Port1
genio
3.2 Board Components
Reference Guide
V1.0 - October 2013
Figure 3: Board Components
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Dual DP83640 Ethernet PHY HSMC Daughter Board
LED
Description
green (l)
LED_LINK from PHY: Lit when link up
orange (r)
LED_SPEED from PHY: On in 100Mbps mode, Off in
10Mbps mode.
1
3
5
7
9
2
4
6
8
10
(5x2)
GND
gpio1
GND
GND
GND
gpio2
gpio3
gpio4
to HSMC
to PHY 1/2
gpio8
clk_out
GND
Reference Guide
V1.0 - October 2013
3.2.1 LEDs
The RJ45 connector provides a green and orange LED on its front side individual per port.
Table 1: RJ45 LEDs
Note: The PHY powers up in Mode 1 for the LEDs (see strap options). That is, the LEDs are showing
the above information. Line activity is not visible in this mode as there is no separate activity LED. It
is possible to configure the PHY to operate the LEDs in Mode 2 by writing into MDIO register 0x19
clearing bits 5,6. In this mode, the link led will be on when the link is established and then blink on
activity.
3.2.2 PHY Generic I/O (GPIO), J2, J3
Each PHY provides several general-purpose I/O pins for event generation and event capture.
Four of these (gpio1-4) are available on a 5x2 connector on the daughter board per
PHY device.
In addition, the gpio4 is also available at the HSMC connector.
Gpio8 of the PHY is wired to HSMC only.
clk_out of the PHY is wired to HSMC and to the connector
Figure 4: GPIO Connector (J2, J3)
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