Texas Instruments CY74FCT823ATSOC, CY74FCT823ATQCT, CY74FCT823ATQC, CY74FCT823ATPC, CY74FCT821CTSOCT Datasheet
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8-/9-/10-Bit Bus Interface Registers
CY74FCT821T
CY74FCT823T
CY74FCT825T
SCCS033 - May 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Function,pinout,anddrivecompatiblewithFCT,F,and
Am29821/23/25 logic
• FCT-C speed at 6.0 ns max.
FCT-B speed at 7.5 ns max.
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current 64 mA
Source current 32 mA
• High-speed parallel registers with positive
edge-triggered D-type flip-flops
• Bufferedcommonclockenable(EN)and asynchronous
clear input (CLR)
• Extended commercial range of −40˚C to +85˚C
Functional Description
These bus interface registers are designed to eliminate the
extra packages required to buffer existing registers and
provideextradata width for wideraddress/data paths orbuses
carrying parity.TheFCT821T is a buffered,10-bit wideversion
of the popular FCT374 function. The FCT823T is a 9-bit wide
buffered register with clock enable (
EN) and clear (CLR) ideal
for parity bus interfacing in high-performance microprogrammed systems. The FCT825T is an 8-bit buffered register
with all the FCT823T controls plus multiple enables (
OE1,
OE2, OE3) to allow multiuser control of the interface, e.g., CS,
DMA, and RD/
WR. They are ideal for use as an output port
requiring high I
OL/IOH
.
These devices are designed for high-capacitance load drive
capability, while providing low-capacitancebus loading at both
inputs and outputs. Outputs are designed for low-capacitance
busloadinginthehigh-impedance state and are designed with
a power-off disablefeature to allow for live insertion of boards.
Note:
1. Not on FCT821.
CL
D
Y
0
CP
OE
CLR
EN
D
0
Q
CP
Q
CL
D
Y
1
D
1
Q
CP
Q
CL
D
Y
2
D
2
Q
CP
Q
CL
D
Y
3
D
3
Q
CP
Q
CL
D
Y
4
D
4
Q
CP
Q
CL
D
Y
5
D
5
Q
CP
Q
CL
D
Y
n- 1
D
N- 1
Q
CP
Q
CL
D
Y
n
D
N
Q
CP
Q
[1]
[1]
Logic Block Diagram
CY74FCT821T
CY74FCT823T
CY74FCT825T
2
FCT821T(10-Bit Register)
FCT823T(9-Bit Register)
FCT825T(8-Bit Register)
D
Y
Q
CP
D
OE
D
YQ
CP
D
CP
OE
CP
EN CLR
10
10
9
9
EN
CLR
D
Y
Q
CP
D
OE
1
CP
EN CLR
8
8
EN
CLR
OE
2
OE
3
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
15
DIP/QSOP/SOIC
Top View
OE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
GND
D
0
D
9
Y
0
Y
9
CP
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
15
DIP/QSOP/SOIC
Top View
OE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
GND
D
0
CLR
Y
0
EN
CP
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
15
DIP/QSOP/SOIC
Top View
OE
1
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
GND
D
0
CLR
Y
0
EN
CP
OE
2
OE
3
Logic Diagrams PinConfigurations
FCT821T
FCT823T
FCT825T
CY74FCT821T
CY74FCT823T
CY74FCT825T
3
Maximum Ratings
[3,4]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature
.............................−65°C to +150°C
Ambient Temperature with
Power Applied
........................................−65°C to +135°C
Supply Voltage to Ground Potential
.............−0.5V to +7.0V
DC Input Voltage
.......................................−0.5V to +7.0V
DC Output Voltage
.....................................−0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Notes:
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change, = LOW-to-HIGH Transition, Z = HIGH Impedance.
3. Unless otherwise noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
Pin Description
Name I/O Description
D I The D flip-flop data inputs.
CLR I When CLR is LOWand OE is LOW, the Q outputs are LOW. When CLR is HIGH, data can be
entered into the register.
CP O Clock Pulse for the register; enters data into the register on the LOW-to-HIGH transition.
Y O The register three-state outputs.
EN I Clock Enable. When EN is LOW, data on the D input is transferred to the Q output on the
LOW-to-HIGH clock transition. When
EN is HIGH, the Q outputs do not change state,
regardless of the data or clock input transitions.
OE I Output Control. When OE is HIGH, the Y outputs are in the high-impedance state. When OE
is LOW, the TRUE register data is present at the Y outputs.
Function Table
[2]
Inputs Internal Outputs
FunctionOE CLR EN D CP Q Y
H
H
H
H
L
L
L
H
L
H
Z
Z
High Z
H
L
L
L
X
X
X
X
X
X
L
L
Z
L
Clear
H
L
H
H
H
H
X
X
X
X
NC
NC
Z
NC
Hold
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
L
H
L
H
Z
Z
L
H
Load
Operating Range
Range Range
Ambient
Temperature V
CC
Commercial All −40°C to +85°C 5V ± 5%
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