Texas Instruments CY74FCT823ATSOC, CY74FCT823ATQCT, CY74FCT823ATQC, CY74FCT823ATPC, CY74FCT821CTSOCT Datasheet

8-/9-/10-Bit Bus Interface Registers

CY74FCT821T

CY74FCT823T
CY74FCT825T

SCCS033 - May 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

Features

• Function,pinout,anddrivecompatiblewithFCT,F,and
Am29821/23/25 logic

• FCT-C speed at 6.0 ns max.
FCT-B speed at 7.5 ns max.

• Reduced V

OH

(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for significantly improved
noise characteristics

• Power-off disable feature

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• ESD > 2000V

• Sink current 64 mA
Source current 32 mA

• High-speed parallel registers with positive
edge-triggered D-type flip-flops

• Bufferedcommonclockenable(EN)and asynchronous
clear input (CLR)

• Extended commercial range of −40˚C to +85˚C

Functional Description

These bus interface registers are designed to eliminate the
extra packages required to buffer existing registers and
provideextradata width for wideraddress/data paths orbuses
carrying parity.TheFCT821T is a buffered,10-bit wideversion
of the popular FCT374 function. The FCT823T is a 9-bit wide
buffered register with clock enable (

EN) and clear (CLR) ideal
for parity bus interfacing in high-performance micropro­grammed systems. The FCT825T is an 8-bit buffered register
with all the FCT823T controls plus multiple enables (

OE1,
OE2, OE3) to allow multiuser control of the interface, e.g., CS,
DMA, and RD/

WR. They are ideal for use as an output port

requiring high I

OL/IOH

.

These devices are designed for high-capacitance load drive
capability, while providing low-capacitancebus loading at both
inputs and outputs. Outputs are designed for low-capacitance
busloadinginthehigh-impedance state and are designed with
a power-off disablefeature to allow for live insertion of boards.

Note:

1. Not on FCT821.

CL

D

Y

0

CP

OE

CLR

EN

D

0

Q

CP

Q

CL

D

Y

1

D

1

Q

CP

Q

CL

D

Y

2

D

2

Q

CP

Q

CL

D

Y

3

D

3

Q

CP

Q

CL

D

Y

4

D

4

Q

CP

Q

CL

D

Y

5

D

5

Q

CP

Q

CL

D

Y

n- 1

D

N- 1

Q

CP

Q

CL

D

Y

n

D

N

Q

CP

Q

[1]

[1]

Logic Block Diagram

CY74FCT821T

CY74FCT823T
CY74FCT825T

2

FCT821T(10-Bit Register)

FCT823T(9-Bit Register)

FCT825T(8-Bit Register)

D

Y

Q

CP

D

OE

D

YQ

CP

D

CP

OE

CP

EN CLR

10

10

9

9

EN

CLR

D

Y

Q

CP

D

OE

1

CP

EN CLR

8

8

EN

CLR

OE

2

OE

3

1
2
3
4
5
6
7
8
9
10
11
12

16

17

18

19

20

24
23
22
21

13

14

V

CC

15

DIP/QSOP/SOIC

Top View

OE

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

Y

8

GND

D

0

D

9

Y

0

Y

9

CP

1
2
3
4
5
6
7
8
9
10
11
12

16

17

18

19

20

24
23
22
21

13

14

V

CC

15

DIP/QSOP/SOIC

Top View

OE

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

Y

8

GND

D

0

CLR

Y

0

EN
CP

1
2
3
4
5
6
7
8
9
10
11
12

16

17

18

19

20

24
23
22
21

13

14

V

CC

15

DIP/QSOP/SOIC

Top View

OE

1

D

1

D

2

D

3

D

4

D

5

D

6

D

7

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

GND

D

0

CLR

Y

0

EN
CP

OE

2

OE

3

Logic Diagrams PinConfigurations

FCT821T

FCT823T

FCT825T

CY74FCT821T

CY74FCT823T
CY74FCT825T

3

Maximum Ratings

[3,4]

(Above which the useful life may be impaired. For user
guidelines, not tested.)

Storage Temperature

.............................−65°C to +150°C

Ambient Temperature with
Power Applied

........................................−65°C to +135°C

Supply Voltage to Ground Potential

.............−0.5V to +7.0V

DC Input Voltage

.......................................−0.5V to +7.0V

DC Output Voltage

.....................................−0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Notes:

2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change, = LOW-to-HIGH Transition, Z = HIGH Impedance.

3. Unless otherwise noted, these limits are over the operating free-air temperature range.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

CC

or ground.

Pin Description

Name I/O Description

D I The D flip-flop data inputs.
CLR I When CLR is LOWand OE is LOW, the Q outputs are LOW. When CLR is HIGH, data can be

entered into the register.
CP O Clock Pulse for the register; enters data into the register on the LOW-to-HIGH transition.
Y O The register three-state outputs.
EN I Clock Enable. When EN is LOW, data on the D input is transferred to the Q output on the

LOW-to-HIGH clock transition. When

EN is HIGH, the Q outputs do not change state,

regardless of the data or clock input transitions.
OE I Output Control. When OE is HIGH, the Y outputs are in the high-impedance state. When OE

is LOW, the TRUE register data is present at the Y outputs.

Function Table

[2]

Inputs Internal Outputs

FunctionOE CLR EN D CP Q Y

H
H

H
H

L
L

L
H

L
H

Z
Z

High Z

H

L

L
L

X
X

X
X

X
X

L
L

Z
L

Clear

H

L

H
H

H
H

X
X

X
X

NC
NC

Z

NC

Hold

H
H

L
L

H
H
H
H

L
L
L
L

L
H
L
H

L
H
L
H

Z
Z
L

H

Load

Operating Range

Range Range

Ambient

Temperature V

CC

Commercial All −40°C to +85°C 5V ± 5%

CY74FCT821T

CY74FCT823T
CY74FCT825T

4

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

[5]

Max. Unit

V

OH

Output HIGH Voltage VCC= Min., IOH= −32 mA 2.0 V

V

OH

Output HIGH Voltage VCC= Min., IOH= −15 mA 2.4 3.3 V

V

OL

Output LOW Voltage VCC= Min., IOL= 64 mA 0.3 0.55 V

V

IH

Input HIGH Voltage 2.0 V

V

IL

Input LOW Voltage 0.8 V

V

H

Hysteresis

[6]

All inputs 0.2 V

V

IK

Input Clamp Diode Voltage VCC= Min., IIN= −18 mA −0.7 −1.2 V

I

I

Input HIGH Current VCC= Max., VIN= V

CC

5 µA

I

IH

Input HIGH Current VCC= Max., VIN= 2.7V ±1 µA

I

IL

Input LOW Current VCC= Max., VIN= 0.5V ±1 µA

I

OZH

Off State HIGH-Level Output
Current

VCC= Max., V

OUT

= 2.7V 10 µA

I

OZL

Off State LOW-Level
Output Current

VCC = Max., V

OUT

= 0.5V −10 µA

I

OS

Output Short Circuit Current

[7]

VCC= Max., V

OUT

= 0.0V −60 −120 −225 mA

I

OFF

Power-Off Disable VCC= 0V, V

OUT

= 4.5V ±1 µA

Capacitance

[6]

Parameter Description Typ.

[5]

Max. Unit

C

IN

Input Capacitance 5 10 pF

C

OUT

Output Capacitance 9 12 pF

Notes:

5. Typical values are at V

CC

=5.0V, TA=+25˚C ambient.

6. This parameter is specified but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferablein order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalidreadings in other parametric tests. In any sequence of parameter
tests, I

OS

tests should be performed last.

CY74FCT821T

CY74FCT823T
CY74FCT825T

5

Power Supply Characteristics

Parameter Description Test Conditions Typ.

[5]

Max. Unit

I

CC

Quiescent Power Supply
Current

VCC=Max., VIN≤0.2V, VIN≥VCC−0.2V 0.1 0.2 mA

∆I

CC

Quiescent Power Supply
Current (TTL inputs HIGH)

VCC=Max., VIN=3.4V,

[8]

f1=0, Outputs Open

0.5 2.0 mA

I

CCD

Dynamic Power Supply
Current

[9]

VCC=Max., One Bit Toggling,50%Duty Cycle,
Outputs Open,

OE=EN=GND,

V

IN

≤0.2V or VIN≥VCC−0.2V

0.06 0.12 mA/MHz

I

C

Total Power Supply Current

[10]

VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling
at f

1

=5 MHz, OE=EN=GND,

V

IN

≤0.2V or VIN≥VCC−0.2V

0.7 1.4 mA

VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f

1

=5 MHz,

OE=EN=GND, VIN=3.4V or VIN=GND

1.2 3.4 mA

VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f

1

=2.5 MHz, OE=EN=GND,

V

IN

≤0.2V or VIN≥VCC−0.2V

1.6 3.2

[11]

mA

VCC=Max., f0=10 MHz,50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f

1

=2.5 MHz, OE=EN=GND,

V

IN

=3.4V or VIN=GND

3.9 12.2

[11]

mA

Notes:

8. Per TTL driven input (V

IN

=3.4V); all other inputs at VCC or GND.

9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

10. I

C=IQUIESCENT

+ I

INPUTS

+ I

DYNAMIC

IC=ICC+∆ICCDHNT+I

CCD(f0

/2 + f1N1)

I

CC

= Quiescent Current with CMOS input levels

∆I

CC

= Power Supply Current for a TTL HIGH input (VIN=3.4V)

D

H

= Duty Cycle for TTL inputs HIGH

N

T

= Number of TTL inputs at D

H

I

CCD

= Dynamic Current caused by an input transition pair (HLH or LHL)

f

0

= Clock frequency for registered devices, otherwise zero

f

1

= Input signal frequency

N

1

= Number of inputs changing at f

1

All currents are in milliamps and all frequencies are in megahertz.

11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.

CY74FCT821T

CY74FCT823T
CY74FCT825T

6

Switching Characteristics Over the Operating Range

[12]

Param. Description Test Load

CY74FCT821AT
CY74FCT823AT
CY74FCT825AT

CY74FCT821BT
CY74FCT823BT
CY74FCT825BT

CY74FCT821CT
CY74FCT823CT
CY74FCT825CT

Unit Fig. No.

[13]

Commercial Commercial Commercial
Min. Max. Min. Max. Min. Max.

t

PLH

t

PHL

Propagation Delay
CP to Y, (

OE=LOW)

CL=50 pF
R

L

=500Ω

10.0 7.5 6.0 ns 1, 5

t

PLH

t

PHL

Propagation Delay
CP to Y, (

OE=LOW)

[6]

CL=300pF

R

L

=500Ω

20.0 15.0 12.5 ns 1, 5

t

PLH

Propagation Delay
CLR to Y

CL=50 pF
R

L

=500Ω

14.0 9.0 8.0 ns 1, 5

t

PZH

t

PZL

Output Enable Time
OE to Y

CL=50 pF
R

L

=500Ω

12.0 8.0 7.0 ns 1, 7, 8

t

PZH

t

PZL

Output Enable Time
OE to Y

[6]

CL=300pF

R

L

=500Ω

23.0 15.0 12.5 ns 1, 7, 8

t

PHZ

t

PHL

Output Disable Time
OE to Y

[6]

CL=5 pF

R

L

=500Ω

7.0 6.5 6.0 ns 1, 7, 8

t

PHZ

t

PHL

Output Disable Time
OE to Y

CL=50 pF
R

L

=500Ω

8.0 7.5 6.5 ns 1, 7, 8

t

SU

Data to CP, Set-Up Time

CL=50 pF
R

L

=500Ω

4.0 3.0 3.0 ns 4

t

H

Data to CP, Hold Time 2.0 1.5 1.5 ns 4

t

SU

Enable EN to CP,
Set-Up Time

4.0 3.0 3.0 ns 4

t

H

Enable EN to CP,
Hold Time

2.0 0.0 0.0 ns 4

t

REM

Clear Recovery Time,
CLR to CP

6.0 6.0 6.0 ns 6

t

W

Clock Pulse Width 7.0 6.0 6.0 ns 5

t

W

CLR Pulse Width LOW 6.0 6.0 6.0 ns 5

Notes:

12. Minimum limits are specified but not tested on Propagation Delays.

13. See “Parameter Measurement Information.”

CY74FCT821T

CY74FCT823T
CY74FCT825T

7

Document #: 38−00282−B

Ordering Information—FCT821T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

6.0 CY74FCT821CTQCT Q13 24-Lead (150-Mil) QSOP Commercial
CY74FCT821CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

7.5 CY74FCT821BTPC P13/13A 24-Lead (300-Mil) Molded DIP Commercial
CY74FCT821BTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

10.0 CY74FCT821ATQCT Q13 24-Lead (150-Mil) QSOP Commercial
CY74FCT821ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

Ordering Information—FCT823T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

6.0 CY74FCT823CTQCT Q13 24-Lead (150-Mil) QSOP Commercial
CY74FCT823CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

7.5 CY74FCT823BTPC P13/13A 24-Lead (300-Mil) Molded DIP Commercial

10.0 CY74FCT823ATPC P13/13A 24-Lead (300-Mil) Molded DIP Commercial
CY74FCT823ATQCT Q13 24-Lead (150-Mil) QSOP
CY74FCT823ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

Ordering Information—FCT825T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

6.0 CY74FCT825CTQCT Q13 24-Lead (150-Mil) QSOP Commercial

CY74FCT821T

CY74FCT823T
CY74FCT825T

8

Package Diagrams

24-Lead (300-Mil) Molded DIP P13/P13A

24-Lead Quarter Size Outline

Q13

CY74FCT821T

CY74FCT823T
CY74FCT825T

9

Package Diagrams (continued)

24-Lead (300-Mil) Molded SOIC

S13

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Copyright  2000, Texas Instruments Incorporated