Texas Instruments CY74FCT16841CTPVCT, CY74FCT16841CTPVC, CY74FCT16841ATPVC, CY74FCT162841CTPVC, CY74FCT162841CTPAC Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

CY74FCT16841T

CY74FCT162841T

SCCS067 - July 1994 - Revised March 2000

Features

• FCT-C speed at 5.5 ns (FCT16841T Com’l)

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for significantly improved
noise characteristics

• Typical output skew < 250 ps

• ESD > 2000V

• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages

• Industrial temperature range of −40˚C to +85˚C

•V

= 5V ± 10%

CC

CY74FCT16841T Features:

• 64 mA sink current, 32 mA source current

• Typical V
TA = 25˚C

(ground bounce) <1.0V at VCC = 5V,

OLP

CY74FCT162841T Features:

• Balanced 24 mA output drivers

• Reduced system switching noise

• Typical V
TA= 25˚C

(ground bounce) <0.6V at VCC = 5V,

OLP

Logic Block Diagrams

OE

1

LE

1

1D1

2

OE

2

2D1

LE

D

C

TO 9 OTHER CHANNELS

D

C

TO 9 OTHER CHANNELS

1Q1

FCT16841-1

2Q1

FCT16841-2

20-Bit Latches

Functional Description

The CY74FCT16841T and CY74FCT162841T are 20-bit
D-type latches designed for use in bus applications requiring
high speedand low power. These devices can be used as two
independent 10-bit latches, or as a single 10-bit latch, or as a
single 20-bit latch by connecting the Output Enable (
Latch (LE) inputs. Flow-through pinout and small shrink
packaging aid in simplifying board layout. The output buffers
are designed with a power-off disable feature to allow live
insertion of boards.

The CY74FCT16841T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.

The CY74FCT162841T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162841T is ideal for driving transmission lines.

Pin Configuration

SSOP/TSSOP

Top View

OE

1

1Q1
1Q2

GND

1Q3

1Q4

V

1Q5

1Q6

1Q7

GND

1Q8
1Q9

1Q10

2Q1
2Q2

2Q3

GND

2Q4
2Q5
2Q6

V

2Q7
2Q8

GND

2Q9

2Q10

OE

2

1
2
3
4
5
6

CC

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

CC

23
24
25
26
27
28

LE

1

56
55

1D1
1D2

54
53

GND

1D3

52
51

1D4

V

CC

50

1D5

49

1D6

48
47

1D7

GND

46
45

1D8

44

1D9

43

1D10

42

2D1

41

2D2

40

2D3

39

GND

38

2D4
2D5

37
36

2D6

V

35

CC

34

2D7

33

2D8

32

GND

31

2D9

30

2D10

29

LE

2

OE) and

FCT16841-3

Copyright © 2000, Texas Instruments Incorporated

CY74FCT16841T

CY74FCT162841T

Pin Description

Name Description

D Data Inputs
LE Latch Enable Input (Active HIGH)
OE Output Enable Input (Active LOW)
O Three-State Outputs

Function Table

D LE OE Q

H H L H

L H L L

X L L Q

[1]

Inputs Outputs

[2]

X X H Z

Maximum Ratings

(Above which the useful life may be impaired. For user
guidelines, not tested.)

Storage Temperature......................................−55°C to +125°C

Ambient Temperature with

Power Applied..................................................−55°C to +125°C

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current

[3, 4]

Power Dissipation..........................................................1.0W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Operating Range

Range

Industrial −40°C to +85°C 5V ± 10%

Ambient

Temperature V

CC

(Maximum Sink Current/Pin)...........................−60 to +120 mA

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

V

IH

V

IL

V

H

V

IK

I

IH

I

IL

I

OZH

I

OZL

I

OS

I

O

I

OFF

Notes:

1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance.

2. Output level before LE HIGH-to-LOW Transition.

3. Operation beyondthe limits set forth may impair the useful life of the device.Unless otherwise noted, these limits are over the operating free-air temperature
range.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

5. Typical values are at V

6. This parameter is specified but not tested.

7. Not more thanoneoutput should be shorted at a time. Duration ofshort should not exceedone second. The use of high-speed testapparatusand/or sample
and hold techniquesare preferable in ordertominimize internal chip heating and more accuratelyreflect operational values. Otherwise prolongedshorting of
a high output may raise the chip temperature well above normal and thereby cause invalidreadingsin other parametric tests. In any sequence of parameter
tests, I

8. Tested at +25˚C.

Input HIGH Voltage Logic HIGH Level 2.0 V
Input LOW Voltage Logic LOW Level 0.8 V
Input Hysteresis

[6]

Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
Input HIGH Current VCC=Max., VI=V

CC

Input LOW Current VCC=Max., VI=GND ±1 µA
High Impedance Output

Current (Three-State Output pins)
High Impedance Output

Current (Three-State Output pins)
Short Circuit Current
Output Drive Current

[7]
[7]

Power-Off Disable VCC=0V, V

= 5.0V, TA= +25˚C ambient.

CC

tests should be performed last.

OS

VCC=Max., V

VCC=Max., V

VCC=Max., V
VCC=Max., V

OUT

=2.7V ±1 µA

OUT

=0.5V ±1 µA

OUT

=GND −80 −140 −200 mA

OUT

=2.5V −50 −180 mA

OUT

[8]

≤4.5V

or ground.

CC

[5]

Max. Unit

100 mV

±1 µA

±1 µA

2