Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16827T
CY74FCT162827T
SCCS064 - August 1994 - Revised March 2000
Features
• FCT-E speed at 3.2 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
•V
= 5V ± 10%
CC
CY74FCT16827T Features:
• 64 mA sink current, 32 mA source current
• Typical V
TA = 25˚C
(ground bounce) <1.0V at VCC = 5V,
OLP
CY74FCT162827T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical V
Functional Description
The CY74FCT16827T 20-bit buffer/line driver and the
CY74FCT162827T20-bitbuffer/linedriverprovide
high-performance bus interf ace b uff ering for wide data/address
pathsor busescarrying parity .Thesepartscanbeusedas a single
20-bit buffer or two 10-bit buff ers . Each 10-bit buffer has a pair of
NANDed
a power-off disable f eature to allo w for liv e insertion of boards.
TheCY74FCT16827Tisideallysuitedfordriving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162827T has 24-mA balanced output drivers
20-Bit Buffers/Line Drivers
(ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
OLP
OEforincreasedflexibility. The outputs are designed with
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162827T is ideal for driving transmission lines.
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.Z = HIGH Impedance.
2. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. Typical values are at V
5. This parameter is specified but not tested.
6. Not more than one output should be shorted at a time. Duration ofshort should notexceedone second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heatingandmoreaccuratelyreflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
7. Tested at +25˚C.
Output LOW VoltageVCC=Min., IOL=64 mA0.20.55V
= 5.0V, TA= +25˚C ambient.
CC
tests should be performed last.
OS
2
[4]
Max.Unit
CY74FCT16827T
CY74FCT162827T
Output Drive Characteristics for CY74FCT162827T
ParameterDescriptionTest ConditionsMin.Typ.
I
ODL
I
ODH
V
V
OH
OL
Output LOW Current
Output HIGH Current
Output HIGH VoltageVCC=Min., IOH=−24 mA2.43.3V
Output LOW VoltageVCC=Min., IOL=24 mA0.30.55V
[6]
[6]
VCC=5V, VIN=VIH or VIL, V
VCC=5V, VIN=VIH or VIL, V
= Quiescent Current with CMOS input levels
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
CC
= Duty Cycle for TTL inputs HIGH
H
= Number of TTL inputs at D
T
= Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
= Number of inputs changing at f
1
+ I
INPUTS
CCD(f0
+ I
DYNAMIC
/2 + f1N1)
H
1
formula. These limits are specified but not tested.
CC
V
IN>VCC
−0.2V
[8]
VIN=VCC or
V
=GND
IN
VIN=VCC or
V
=GND
IN
VIN=3.4V or
V
=GND
IN
VIN=VCC or
V
=GND
IN
VIN=3.4V or
V
=GND
IN
—5500µA
—0.51.5mA
—60100µA/MHz
—0.61.5mA
—0.92.3
—3.05.5
—8.020.5
[4]
Max.Unit
[4]
Max.Unit
[11]
[11]
3
CY74FCT16827T
CY74FCT162827T
Switching Characteristics Over the Operating Range
[12]
CY74FCT16827AT
CY74FCT162827ATCY74FCT162827BT
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
=500Ω
L
[13]
Min.Max.Min.Max.UnitFig. No.
1.58.01.55.0ns1, 3
1.515.01.513.0
1.512.01.58.0ns1, 7, 8
1.523.01.515.0
1.59.01.56.0ns1, 7, 8
1.510.01.57.0
—0.5—0.5ns—
CY74FCT16827CT
CY74FCT162827CT
[12]
Min.Max.Min.Max.Unit Fig. No.
1.54.21.53.2ns1, 3
1.510.01.57.0
1.55.61.54.8ns1, 7, 8
1.514.01.59.0
1.55.71.54.0ns1, 7, 8
1.56.01.54.0
—0.5—0.5ns—
CY74FCT16827ET
CY74FCT162827ET
ParameterDescriptionCondition
t
PLH
t
PHL
Propagation Delay
A to Y
CL=50 pF
R
CL=300 pF
R
t
PZH
t
PZL
Output Enable Time
OE to Y
CL=50 pF
R
CL=300 pF
R
t
PHZ
t
PLZ
Output Disable Time
OE to Y
CL=5 pF
R
CL=50 pF
R
t
SK(O)
Output Skew
[14]
ParameterDescriptionCondition
t
PLH
t
PHL
Propagation Delay
A to Y
CL=50 pF
R
CL=300 pF
R
t
PZH
t
PZL
Output Enable Time
OE to Y
CL=50 pF
R
CL=300 pF
R
t
PHZ
t
PLZ
Output Disable Time
OE to Y
CL=5 pF
R
CL=50 pF
R
t
SK(O)
Notes:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
14. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated
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