Texas Instruments CY74FCT16501ETPVCT, CY74FCT16501ETPVC, CY74FCT16501ETPAC, CY74FCT16501ATPVCT, CY74FCT16501ATPVC Datasheet

18-Bit Registered Transceivers

CY74FCT16501T

CY74FCT162501T

CY74FCT162H501T

SCCS057 - August 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

1CY74FCT162H501
T

Features

• FCT-E speed at 3.8 ns

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for significantly improved
noise characteristics

• Typical output skew < 250 ps

• ESD > 2000V

• TSSOP (19.6 mil pitch) and SSOP (25-mil pitch)
packages

• Industrial temperature range of −40˚C to +85˚C

•V

CC

= 5V ± 10%

CY74FCT16501T Features:

• 64 mA sink current, 32 mA source current

• Typical V

OLP

(ground bounce) <1.0V at VCC = 5V,

TA = 25˚C

CY74FCT162501T Features:

• Balanced 24 mA output drivers

• Reduced system switching noise

• Typical V

OLP

(ground bounce) <0.6V at VCC = 5V,

TA= 25˚C

CY74FCT162H501T Features:

• Bus hold retains last active state

• Eliminates the need for external pull-up or pull-down
resistors

Functional Description

These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and

OEBA), latch enable
(LEAB and LEBA), andclock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH.When LEAB is LOW,the A data islatched
if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW,
the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGHtransition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
tothat of A-to-B and iscontrolled by

OEBA,LEBA, and CLKBA.
The output buffers are designed with a power-off disable
feature to allow live insertion of boards.

The CY74FCT16501T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.

THE CY74FCT162501T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
needforexternalterminating resistors andprovidesforminimal
undershoot and reduced ground bounce. The
CY74FCT162501T is ideal for driving transmission lines.

The CY74FCT162H501T is a24-mA balanced output part, that
has “bus hold” on thedata inputs. The deviceretainsthe input’s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.

GND

Functional Block Diagram

Pin

Configuration

1
2

3
4

5
6
7
8
9
10
11
12

OEAB

SSOP/TSSOP

Top View

13
14
15
16
17
18
19
20
21
22
23
24

LEAB

A

1

GND

GND

V

CC

GND

GND

FCT16501-1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

GND

25
26
27
28

GND

A

10

A

11

A

12

V

CC

A

13

A

14

A

15

A

16

A

17

A

18

OEBA

LEBA

56
55

54
53

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

GND
CLKAB
B

1

GND
B

2

B

3

V

CC

B

4

B

5

B

6

GND

B

7

B

8

B

9

B

10

B

11

B

12

B

13

B

14

B

15

V

CC

B

16

B

17

B

18

CLKBA

OEAB

CLKBA

LEBA

OEBA

CLKAB

LEAB

C
D

C
D

C
D

A

1

B

1

C
D

TO 17 OTHER CHANNELS

FCT16501-2

CY74FCT16501T

CY74FCT162501T

CY74FCT162H501T

2

Maximum Ratings

[6, 7]

(Above which the useful life may be impaired. For user
guidelines, not tested.)

Storage Temperature .................................... −55°C to +125°C

Ambient Temperature with

Power Applied..................................................−55°C to +125°C

DC Input Voltage.................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)........................... −60 to +120 mA

Power Dissipation..........................................................1.0W

Static Discharge Voltage...........................................>2001V

(per MIL-STD-883, Method 3015)

Notes:

1. On the 74FCT162H501T these pins have bus hold.

2. A-to-B data flow is shown. B-to-A data flow is similar but uses

OEBA, LEBA, and CLKBA.

3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance

= LOW-to-HIGH Transition

4. Output level before the indicated steady-state input conditions were established.

5. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.

6. Operationbeyondthe limits set forthmay impair the useful lifeof the device.Unless otherwise noted, these limits areover the operatingfree-air temperature range.

7. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

CC

or ground.

Pin Description

Name Description

OEAB A-to-B Output Enable Input
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
A A-to-B Data Inputs or B-to-A Three-State

Outputs

[1]

B B-to-A Data Inputs or A-to-B Three-State

Outputs

[1]

Function Table

[2, 3]

Inputs Outputs

OEAB LEAB CLKAB A B

L X X X Z
H H X L L
H H X H H
H L L L

H L H H
H L L X B

[4]

H L H X B

[5]

Operating Range

Range

Ambient

Temperature V

CC

Industrial −40°C to +85°C 5V ± 10%

CY74FCT16501T

CY74FCT162501T

CY74FCT162H501T

3

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

[8]

Max. Unit

V

IH

Input HIGH Voltage 2.0 V

V

IL

Input LOW Voltage 0.8 V

V

H

Input Hysteresis

[9]

100 mV

V

IK

Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V

I

IH

Input HIGH Current Standard VCC=Max., VI=V

CC

±1 µA

Bus Hold ±100

I

IL

Input LOW Current Standard VCC=Max., VI=GND ±1 µA

Bus Hold ±100 µA

I

BBH

I

BBL

Bus Hold Sustain Current on Bus Hold Input

[10]

VCC=Min., VI=2.0V −50 µA

VI=0.8V +50 µA

I

BHHO

I

BHLO

Bus Hold Overdrive Current on Bus Hold In­put

[10]

VCC=Max., VI=1.5V TBD mA

I

OZH

High Impedance Output Current
(Three-State Output pins)

VCC=Max., V

OUT

=2.7V ±1 µA

I

OZL

High Impedance Output Current
(Three-State Output pins)

VCC=Max., V

OUT

=0.5V ±1 µA

I

OS

Short Circuit Current

[11]

VCC=Max., V

OUT

=GND −80 −140 −200 mA

I

O

Output Drive Current

[11]

VCC=Max., V

OUT

=2.5V −50 −180 mA

I

OFF

Power-Off Disable VCC=0V, V

OUT

≤4.5V

[12]

±1 µA

Output Drive Characteristics for CY74FCT16501T

Parameter Description Test Conditions Min. Typ.

[8]

Max. Unit

V

OH

Output HIGH Voltage VCC=Min., IOH=−3 mA 2.5 3.5 V

VCC=Min., IOH=−15 mA 2.4 3.5
VCC=Min., IOH=−32 mA 2.0 3.0

V

OL

Output LOW Voltage VCC=Min., IOL=64 mA 0.2 0.55 V

Output Drive Characteristics for CY74FCT162501T, CY74FCT162H501T

Parameter Description Test Conditions Min. Typ.

[8]

Max. Unit

I

ODL

Output LOW Current

[11]

VCC=5V, VIN=VIH or VIL, V

OUT

=1.5V 60 115 150 mA

I

ODH

Output HIGH Current

[11]

VCC=5V, VIN=VIH or VIL, V

OUT

=1.5V −60 −115 −150 mA

V

OH

Output HIGH Voltage VCC=Min., IOH=−24 mA 2.4 3.3 V

V

OL

Output LOW Voltage VCC=Min., IOL=24 mA 0.3 0.55 V

Notes:

8. Typical values are at V

CC

= 5.0V, TA= +25˚C ambient.

9. This parameter is specified but not tested.

10. Pins with bus hold are described in Pin Description.

11. Not more than one output should be shorted at a time. Duration of short should not exceed one second.The use of high-speed test apparatus and/or sample
and hold techniques are preferablein order to minimize internal chip heating and more accuratelyreflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I

OS

tests should be performed last.

12. Tested at +25˚C.

CY74FCT16501T

CY74FCT162501T

CY74FCT162H501T

4

Capacitance

[9]

(TA = +25˚C, f = 1.0 MHz)

Parameter Description Test Conditions Typ.

[8]

Max. Unit

C

IN

Input Capacitance VIN = 0V 4.5 6.0 pF

C

OUT

Output Capacitance V

OUT

= 0V 5.5 8.0 pF

Power Supply Characteristics

Sym. Parameter Test Conditions

[13]

Min. Typ.

[8]

Max. Unit

I

CC

Quiescent Power Supply
Current

VCC=Max. VIN<0.2V

V

IN>VCC

−0.2V

— 5 500 µA

∆I

CC

Quiescent Power Supply
Current TTL inputs HIGH

VCC= Max., V

IN =

3.4V

[14]

— 0.5 1.5 mA

I

CCD

Dynamic Power Supply
Current

[15]

VCC=Max., Outputs Open
OEAB=

OEBA=VCCor GND
One Input Toggling,
50% Duty Cycle

VIN=VCC or
V

IN

=GND

— 75 120 µA/

MHz

I

C

Total Power Supply
Current

[16]

VCC=Max., Outputs Open
f

0

=10MHz (CLKAB)
50% Duty Cycle
OEAB=

OEBA=V

CC

LEAB = GND, One Bit Toggling
f

1

= 5MHz, 50% Duty Cycle

VIN=VCC or
V

IN

=GND

— 0.8 1.7 mA

VIN=3.4V or
V

IN

=GND

— 1.3 3.2

VCC=Max., Outputs Open
f

0

= 10MHz (CLKAB)
50% Duty Cycle
OEAB=

OEBA=V

CC

LEAB=GND
Eighteen Bits Toggling
f

1

=2.5MHz, 50% Duty Cycle

VIN=VCC or
V

IN

=GND

— 3.8 6.5

[17]

VIN=3.4V or
V

IN

=GND

— 8.5 20.8

[17]

Notes:

13. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

14. Per TTL driven input (V

IN

=3.4V); all other inputs at VCC or GND.

15. This parameter is not directly testable, but is derived for use in Total Power Supply.

16. I

C

=I

QUIESCENT

+ I

INPUTS

+ I

DYNAMIC

IC=ICC+∆ICCDHNT+I

CCD(f0

/2 + f1N1)

I

CC

= Quiescent Current with CMOS input levels

∆I

CC

= Power Supply Current for a TTL HIGH input (VIN=3.4V)

D

H

= Duty Cycle for TTL inputs HIGH

N

T

= Number of TTL inputs at D

H

I

CCD

= Dynamic Current caused by an input transition pair (HLH or LHL)

f

0

= Clock frequency for registered devices, otherwise zero

f

1

= Input signal frequency

N

1

= Number of inputs changing at f

1

All currents are in milliamps and all frequencies are in megahertz.

17. Values for these conditions are examples of the I

CC

formula. These limits are specified but not tested.

CY74FCT16501T

CY74FCT162501T

CY74FCT162H501T

5

Switching Characteristics Over the Operating Range

[18]

CY74FCT16501AT
CY74FCT162501AT

CY74FCT162501CT
CY74FCT162H501CT

CY74FCT16501ET
CY74FCT162501ET
CY74FCT162H501ET

Fig.

No.

[19]

Parameter Description

Min. Max. Min. Max. Min. Max.

Unit

f

MAX

CLKAB or CLKBA
frequency

[20]

— 150 — 150 — 150 MHz —

t

PLH

t

PHL

Propagation Delay
A to B or B to A

1.5 5.1 1.5 4.6 1.5 3.8 ns 1,3

t

PLH

t

PHL

Propagation Delay
LEBA to A, LEAB to B

1.5 5.6 1.5 5.3 1.5 4.2 ns 1,5

t

PLH

t

PHL

Propagation Delay
CLKBA to A,
CLKAB to B

1.5 5.6 1.5 5.3 1.5 4.2 ns 1,5

t

PZH

t

PZL

Output Enable Time
OEBAto A, OEAB to B

1.5 6.0 1.5 5.6 1.5 4.8 ns 1,7,8

t

PHZ

t

PLZ

Output Disable Time
OEBAto A, OEAB to B

1.5 5.6 1.5 5.2 1.5 5.2 ns 1,7,8

t

SU

Set-Up Time,
HIGH or LOW
A to CLKAB,
B to CLKBA

3.0 — 3.0 — 2.4 — ns 4

t

H

Hold Time
HIGH or LOW
A to CLKAB,
B to CLKBA

0 — 0 — 0 — ns 4

t

SU

Set-Up Time,
HIGH or LOW
A to LEAB,
B to LEBA

Clock
LOW

3.0 — 3.0 — 2.0 — ns 4

Clock
HIGH

1.5 — 1.5 — 1.5 — ns 4

t

H

Hold Time, HIGH or
LOW, A to LEAB,
B to LEBA

1.5 — 1.5 — 0.5 — ns 4

t

W

LEAB or LEBA Pulse
Width HIGH

[20]

3.0 — 3.0 — 3.0 — ns 5

t

W

CLKAB or CLKBA
Pulse Width HIGH or
LOW

[20]

3.0 — 3.0 — 3.0 — ns 5

t

SK(O)

Output Skew

[21]

— 0.5 — 0.5 — 0.5 ns —

Notes:

18. Minimum limits are specified, but not tested, on propagation delays.

19. See “Parameter Measurement Information” in the General Information section.

20. This parameter is guaranteed but not tested.

21. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.

CY74FCT16501T

CY74FCT162501T

CY74FCT162H501T

6

Ordering Information CY74FCT16501T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

3.8 CY74FCT16501ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT16501ETPVC/PVCT O56 56-Lead (300-Mil) SSOP

5.1 CY74FCT16501ATPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial

Ordering Information CY74FCT162501T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

3.8 74FCT162501ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162501ETPVC O56 56-Lead (300-Mil) SSOP
74FCT162501ETPVCT O56 56-Lead (300-Mil) SSOP

4.6 74FCT162501CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162501CTPVC O56 56-Lead (300-Mil) SSOP
74FCT162501CTPVCT O56 56-Lead (300-Mil) SSOP

5.1 74FCT162501ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162501ATPVC O56 56-Lead (300-Mil) SSOP
74FCT162501ATPVCT O56 56-Lead (300-Mil) SSOP

Ordering Information CY74FCT162H501T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

3.8 74FCT162H501ETPACT Z56 56-Lead (240-Mil) TSSOP Industrial
74FCT162H501ETPVC/PVCT O56 56-Lead (300-Mil) SSOP

4.6 74FCT162H501CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial
74FCT162H501CTPVC/PVCT O56 56-Lead (300-Mil) SSOP

CY74FCT16501T

CY74FCT162501T

CY74FCT162H501T

7

Package Diagrams

56-Lead Shrunk Small Outline Package O56

56-Lead Thin Shrunk Small Outline Package

Z56

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Copyright  2000, Texas Instruments Incorporated