Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163501
CY74FCT163H501
SCCS047 - January 1998 - Revised March 2000
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceedsJEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• TypicalV
Std 883D
•V
= 2.7V to 3.6V
CC
CY74FCT163501 Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical V
TA= 25˚C
CY74FCT163H501 Features:
• Bus hold retains the last active state
• Devices with bus hold are not recommended for translating rail-to-rail CMOS signals to 3.3V logic levels
(groundbounce)performanceexceedsMil
olp
(ground bounce) <0.6V at VCC = 3.3V,
OLP
18-Bit Registered Transceivers
• Eliminates the need for external pull-up or pull-down
resistors
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and
(LEAB and LEBA), and clock inputs (CLKAB andCLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGHor LOWlogiclevel.IfLEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGHtransition of CLKAB.OEABperformstheoutput
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by
CLKBA. The output buffers are designed with a power-off
disable feature to allow live insertion of boards.
THE CY74FCT163501 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors, as well as provides for
minimal undershoot and reduced ground bounce. The
CY74FCT163501 is ideal for driving transmission lines.
The CY74FCT163H501 is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
OEBA), latch enable
OEBA, LEBA, and
Functional Block Diagram; CY74FCT163501, CY74FCT163H501
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A
1
C
D
C
D
C
D
TO 17 OTHER CHANNELS
C
D
FCT163501-1
Configuration
Pin
SSOP/TSSOP
Top View
OEAB
1
2
LEAB
A
3
1
4
GND
A
5
2
6
A
3
7
V
CC
A
8
4
9
A
5
A
6
10
11
GND
12
A
7
13
A
8
14
A
9
A
15
10
A
B
1
A
GND
A
A
A
V
CC
A
A
GND
A
OEBA
LEBA
16
11
17
12
18
19
13
20
14
21
15
22
23
16
24
17
25
26
18
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLKBA
GND
FCT163501-2
Copyright © 2000, Texas Instruments Incorporated
CY74FCT163501
CY74FCT163H501
Pin Description
Name Description
OEAB A-to-B Output Enable Input
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
A A-to-B Data Inputs or B-to-A Three-State
Outputs
B B-to-A Data Inputs or A-to-B Three-State
Outputs
Function Table
OEAB LEAB CLKAB A B
L X X X Z
H H X L L
H H X H H
H L L L
[1]
[1]
[2, 3]
Inputs Outputs
Maximum Ratings
[6, 7]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature .....................................−55°C to +125°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Operating Range
Range
Industrial −40°C to +85°C 2.7V to 3.6V
Ambient
Temperature V
CC
H L H H
H L L X B
H L H X B
1. On the 74FCT163H501 these pins have bus hold.
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance
= LOW-to-HIGH Transition
4. Output level before the indicated steady-state input conditions were established.
5. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
6. Operationbeyondthe limits setforth may impair theusefullife of thedevice.Unlessotherwise noted,theselimits are overtheoperating free-air temperaturerange.
7. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
[4]
[5]
2
CY74FCT163501
CY74FCT163H501
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range V
Parameter Description Test Conditions Min. Typ.
V
IH
V
IL
V
H
V
IK
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
OFF
I
CC
∆I
CC
Notes:
8. Typical values are at V
9. This parameter is specified but not tested.
10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferablein order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
11. Per TTL driven input (V
Input HIGH Voltage All Inputs 2.0 5.5 V
Input LOW Voltage 0.8 V
Input Hysteresis
[9]
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
Input HIGH Current VCC=Max., VI=5.5 ±1 µA
Input LOW Current VCC=Max., VI=GND ±1 µA
High Impedance Output Current
(Three-State Output pins)
High Impedance Output Current
(Three-State Output pins)
Short Circuit Current
[10]
Power-Off Disable VCC=0V, V
Quiescent Power Supply Current VIN≤0.2V,
Quiescent Power Supply Current
VCC=Max., V
VCC=Max., V
VCC=Max., V
OUT
V
IN>VCC
–0.2V
VIN=VCC–0.6V
=5.5V ±1 µA
OUT
=GND ±1 µA
OUT
=GND –60 –135 –240 mA
OUT
≤4.5V ±100 µA
VCC=Max. 0.1 10 µA
[11]
VCC=Max. 2.0 30 µA
(TTL inputs HIGH)
=3.3V, TA = +25˚C ambient.
CC
tests should be performed last.
OS
=3.4V); all other inputs at VCC or GND.
IN
= 2.7V to 3.6V
CC
[8]
100 mV
Max. Unit
3
CY74FCT163501
CY74FCT163H501
Electrical Characteristics For Bus Hold Devices Over the Operating Range V
=2.7V to 3.6V
CC
Parameter Description Test Conditions Min. Typ.
V
IH
V
IL
V
H
V
IK
I
IH
I
IL
I
BBH
I
BBL
I
BHHO
I
BHLO
I
OZH
I
OZL
I
OS
I
OFF
I
CC
∆
ICC
Input HIGH Voltage All Inputs 2.0 V
Input LOW Voltage 0.8 V
Input Hysteresis
[9]
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
Input HIGH Current VCC=Max., VI=V
CC
Input LOW Current VCC=Max., VI=GND ±100 µA
Bus Hold Sustain Current on Bus Hold Input
[12]
VCC=Min. VI=2.0V –50 µA
VI=0.8V +50 µA
BusHoldOverdrive CurrentonBusHold Input
High Impedance Output Current
(Three-State Output pins)
High Impedance Output Current
(Three-State Output pins)
Short Circuit Current
[10]
Power-Off Disable VCC=0V, V
Quiescent Power Supply Current VIN≤0.2V,
Quiescent Power supply Current
[12]
VCC=Max., VI=1.5V ±500 µA
VCC=Max., V
VCC=Max., V
VCC=Max., V
OUT=VCC
=GND ±1 µA
OUT
=GND –60 –135 –240 mA
OUT
≤4.5V ±100 µA
OUT
VCC=Max. +40 µA
V
VIN=VCC–0.6V
IN>VCC
–0.2V
[11]
VCC=Max. +350 µA
(TTL inputs HIGH)
[8]
Max. Unit
CC
V
100 mV
±100 µA
±1 µA
Electrical Characteristics For Balanced Drive Devices Over the Operating Range V
CC
Parameter Description Test Conditions Min. Typ.
I
ODL
I
ODH
V
OH
Output LOW Dynamic Current
Output HIGH Dynamic Current
Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V
[10]
[10]
VCC=3.3V, VIN=V
or VIL, V
OUT
VCC=3.3V, VIN=V
or VIL, V
OUT
=1.5V
=1.5V
IH
IH
–45 –180 mA
VCC=3.0V, IOH= –8 mA 2.4
45 180 mA
[13]
VCC=3.0V, IOH= –24 mA 2.0 3.0 V
V
OL
Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V
VCC=Min., IOL= 24 mA 0.3 0.55
Capacitance
Parameter Description Test Conditions Typ.
C
IN
C
OUT
Notes:
12. Pins with bus hold are described in Pin Description.
13. V
OH=VCC
[9]
(TA = +25˚C, f = 1.0 MHz)
[8]
Input Capacitance VIN = 0V 4.5 6.0 pF
Output Capacitance V
– 0.6V at rated current.
= 0V 5.5 8.0 pF
OUT
=2.7V to 3.6V
[8]
Max. Unit
3.0 V
Max. Unit
4
CY74FCT163501
CY74FCT163H501
Power Supply Characteristics
Sym. Parameter Test Conditions
I
Dynamic Power Supply
CCD
Current
[15]
VCC=Max., Outputs Open
OEAB=
OEBA=VCCor GND
One Input Toggling,
50% Duty Cycle
I
Total Power Supply
C
Current
[16]
VCC=Max., Outputs Open
f
=10MHz (CLKAB)
0
50% Duty Cycle
OEAB=
LEAB = GND, One Bit Toggling
f
OEBA=V
= 5MHz, 50% Duty Cycle
1
CC
VCC=Max., Outputs Open
f
= 10MHz (CLKAB)
0
50% Duty Cycle
OEAB=
LEAB=GND
OEBA=V
CC
Eighteen Bits Toggling
f
=2.5MHz, 50% Duty Cycle
1
Notes:
14. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
15. This parameter is not directly testable, but is derived for use in Total Power Supply Current.
16. I
=I
C
QUIESCENT
IC=ICC+∆ICCDHNT+I
= Quiescent Current with CMOS input levels
I
CC
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
∆I
CC
= Duty Cycle for TTL inputs HIGH
D
H
= Number of TTL inputs at D
N
T
I
= Dynamic Current caused by an input transition pair (HLH or LHL)
CCD
= Clock frequency for registered devices, otherwise zero
f
0
= Input signal frequency
f
1
= Number of inputs changing at f
N
1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the I
+ I
INPUTS
+ I
DYNAMIC
CCD(f0
/2 + f1N1)
H
1
formula. These limits are specified but not tested.
CC
[14]
VIN=VCC or
V
=GND
IN
VIN=VCC or
V
=GND
IN
VIN=3.4V or
V
=GND
IN
VIN=VCC or
V
=GND
IN
VIN=3.4V or
V
=GND
IN
Min. Typ.
— 75 120 µA/
— 0.8 1.7 mA
— 1.3 3.2
— 3.8 6.5
— 8.5 20.8
[8]
Max. Unit
MHz
[17]
[17]
5
CY74FCT163501
CY74FCT163H501
Switching Characteristics Over the Operating Range V
=3.0V to 3.6V
CC
[18]
CY74FCT163501C
CY74FCT163H501C
Parameter Description Min. Max. Unit
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
CLKAB or CLKBA frequency
Propagation Delay
A to B or B to A
Propagation Delay
LEBA to A, LEAB to B
Propagation Delay
CLKBA to A,
CLKAB to B
Output Enable Time
OEBA to A, OEAB to B
Output Disable Time
OEBA to A, OEAB to B
Set-Up Time,
HIGH or LOW
[9]
— 150 MHz —
1.5 4.6 ns 1,3
1.5 5.3 ns 1,5
1.5 5.3 ns 1,5
1.5 5.6 ns 1,7,8
1.5 5.2 ns 1,7,8
3.0 — ns 4
A to CLKAB,
B to CLKBA
t
H
Hold Time
HIGH or LOW
0 — ns 4
A to CLKAB,
B to CLKBA
t
SU
t
H
t
W
t
W
t
SK(O)
Notes:
18. Minimum limits are specified, but not tested, on propagation delays.
19. See “Parameter Measurement Information” in the General Information section.
20. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
Set-Up Time, HIGH or LOW
A to LEAB,
B to LEBA
Hold Time, HIGH or LOW, A to LEAB,
B to LEBA
LEAB or LEBA Pulse Width HIGH
[9]
CLKAB or CLKBA Pulse Width HIGH or LOW
Output Skew
[20]
Clock LOW 3.0 — ns 4
Clock HIGH 1.5 — ns 4
1.5 — ns 4
3.0 — ns 5
[9]
3.0 — ns 5
— 0.5 ns —
Fig.No.
[19]
6
CY74FCT163501
CY74FCT163H501
Ordering Information CY74FCT163501T
Speed
(ns) Ordering Code
4.6 CY74FCT163501CPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT163501CPVC/PVCT O56 56-Lead (300-Mil) SSOP
Ordering Information CY74FCT163H501T
Speed
(ns) Ordering Code
4.6 74FCT163H501CPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT163H501CPVC O56 56-Lead (300-Mil) SSOP
74FCT163H501CPVCT O56 56-Lead (300-Mil) SSOP
Package Diagrams
56-Lead Shrunk Small Outline Package O56
Package
Name Package Type
Package
Name Package Type
Operating
Range
Operating
Range
7
Package Diagrams (continued)
CY74FCT163501
CY74FCT163H501
56-Lead Thin Shrunk Small Outline Package
Z56
8
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Copyright 2000, Texas Instruments Incorporated
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