Texas Instruments CD74FCT822AEN, CD74FCT821AM96, CD74FCT821AM, CD74FCT821AEN Datasheet

8-1

Data sheet acquired from Harris Semiconductor
SCHS264

Features

• Buffered Inputs

• Typical Propagation Delay: 7.5ns at V

CC

= 5V,

T

A

= 25oC, CL = 50pF

• CD74FCT821A

- Noninverting

• CD74FCT822A

- Inverting

• SCR Latchup Resistant BiCMOS Process and
Circuit Design

• Speed of Bipolar FAST™/AS/S

• 48mA Output Sink Current

• Output Voltage Swing Limited to 3.7V at V

CC

= 5V

• Controlled Output Edge Rates

• Input/Output Isolation to V

CC

• BiCMOS Technology with Low Quiescent Power

Description

The CD74FCT821A and CD74FCT822A ten bit, D-Type,
three-state, positive edge triggered flip-flops use a small
geometry BiCMOS technology. The output stage is a combi­nation of bipolar and CMOS transistors that limits the output
HIGH level to two diode drops below V

CC

. This resultant
lowering of output swing (0V to 3.7V) reduces power bus
ringing (a source of EMI) and minimizes V

CC

bounce and
ground bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 48 milliamperes.

The ten flip-flops enter data into their registers on the LOW
to HIGH transition of the clock(CP). The Output Enable (

OE)
controls the three state outputs and is independent of the
register operation. When the Output Enable (

OE) is HIGH,
the outputs are in the high impedance state. The
CD74FCT821A and CD74FCT822A share the same config­urations, but the CD74FCT821A outputs are noninverted
while the CD74FCT822A devices have inverted outputs.

Ordering Information

Pinouts

PART NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74FCT821AEN 0 to 70 24 Ld PDIP E24.3
CD74FCT822AEN 0 to 70 24 Ld PDIP E24.3
CD74FCT821AM 0 to 70 24 Ld SOIC M24.3

NOTE: When ordering the suffix M packages, use the entire part
number. Add the suffix 96 to obtain the variant in the tape and reel.

CD74FCT821A

(PDIP, SOIC)

TOP VIEW

CD74FCT822A

(PDIP, SOIC)

TOP VIEW

1
2
3
4
5
6
7
8

9
10
11
12

OE

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

GND

16

17

18

19

20

21

22

23

24

15
14
13

V

CC

Q1
Q2
Q3
Q4

Q6

Q8
Q9
CP

Q0

Q5

Q7

1
2
3
4
5
6
7
8

9
10
11
12

16

17

18

19

20

21

22

23

24

15
14
13

OE

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

GND

V

CC

Q1
Q2
Q3
Q4

Q6

Q8
Q9
CP

Q0

Q5

Q7

January 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1997

CD74FCT821A,

CD74FCT822A

BiCMOS FCT Interface Logic,

10- Bit D-Type Flip-Flops, Three-State

File Number 2390.2

NOT RECOMMENDED

FOR NEW DESIGNS

Use CMOS Technology

8-2

Functional Diagram

IEC Logic Symbol

TRUTH TABLE

INPUTS

OUTPUTS

CD74FCT821A CD74FCT822A

OE CP DN QN QN

L ↑ HH L
L↑LL H
LLX NC NC
HXX Z Z

NOTE:

1. H = HIGH level (steady state)
L = LOW level (steady state)
X = Immaterial
↑ = Transition from LOW to HIGH level
Z = HIGH impedance
NC = No change

2
3
4
5
6
7
8
9

D0
D1
D2
D3
D4
D5
D6
D7

1

GND = PIN 12
V

CC

= PIN 24

13

OE
CP

10
11

D8
D9

23
22
21
20
19
18
17
16
15
14

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9

821A

822A

CD74FCT821A CD74FCT822A

EN

1

2
3
4
5
6
7
8
9

>C1

13

1D

10
11

23
22
21
20
19
18
17
16
15
14

EN

1

2
3
4
5
6
7
8
9

>C1

13

1D

10
11

23
22
21
20
19
18
17
16
15
14

CD74FCT821A, CD74FCT822A

8-3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Diode Current, IIK (For VI < -0.5V). . . . . . . . . . . . . . . . . . -20mA

DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA

DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA

DC Output Source Current per Output Pin, IO. . . . . . . . . . . . -30mA

DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260mA

DC Ground Current (I

GND

). . . . . . . . . . . . . . . . . . . . . . . . . . .500mA

Operating Conditions

Operating Temperature Range, TA. . . . . . . . . . . . . . . . .0oC to 70oC

Supply Voltage Range, VCC. . . . . . . . . . . . . . . . . . . .4.75V to 5.25V

DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V

CC

DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V

CC

Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC-Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Commercial Temperature Range 0

o

C to 70oC, VCC Max = 5.25V, VCC, Min = 4.75V

PARAMETER SYMBOL

TEST CONDITIONS

V

CC

(V)

AMBIENT TEMPERATURE (TA)

UNITS

25oC0

o

C TO 70oC

VI (V) IO (mA) MIN MAX MIN MAX

High Level Input Voltage V

IH

4.75 to

5.25

2-2-V

Low Level Input Voltage V

IL

4.75 to

5.25

- 0.8 - 0.8 V

High Level Output Voltage V

OH

VIH or V

IL

-15 Min 2.4 - 2.4 - V

Low Level Output Voltage V

OL

VIH or V

IL

48 Min - 0.55 - 0.55 V

High Level Input Current I

IH

V

CC

Max - 0.1 - 1 µA

Low Level Input Current I

IL

GND Max - -0.1 - -1 µA

Three-State Leakage Current I

OZH

V

CC

Max - 0.5 - 10 µA

I

OZL

GND Max - -0.5 - -10 µA

Input Clamp Voltage V

IK

VCC or

GND

-18 Min - -1.2 - -1.2 V

Short Circuit Output Current
(Note 3)

I

OS

VO = 0

VCC or

GND

Max -75 - -75 - mA

Quiescent Supply Current,
MSI

I

CC

VCC or

GND

0 Max - 8 - 80 µA

Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load

∆I

CC

3.4V

(Note 4)

Max - 1.6 - 1.6 mA

NOTES:

3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.

4. Inputs that are not measured are at VCC or GND.

5. FCT Input Loading: All inputsare 1 unit load. Unit load is ∆ICClimit specified in ElectricalSpecifications table, e.g., 1.6mA Max. at 70oC.

CD74FCT821A, CD74FCT822A