Texas Instruments CD74ACT74M96, CD74ACT74M, CD74ACT74E, CD74AC74M96, CD74AC74M Datasheet

CD74AC74,

/
j

/

/

[ /Title
(CD74
AC74,
CD74
ACT74
)

Sub-

ect
(Dual
D­Type
Flip­Flop
with
Setand
Reset
Posi­tive­Edge­Trig­gered)

Autho
r ()

Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan

Data sheet acquired from Harris Semiconductor
SCHS231

September 1998

Features

• Buffered Inputs

• Typical Propagation Delay (AC00)

- 4.9ns at V

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Lachup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

= 5V, TA = 25oC, CL = 50pF

CC

Pinout

1CP

GND

Dual D-Type Flip-Flop with Set and Reset

Description

The Harris CD74AC74 and CD74ACT74 dual D-type, posi­tive edge triggered flip-flops use the Harris ADVANCED
CMOS technology. These flip-flops have independent DATA,
SET, RESET, and CLOCK inputs and Q and Q outputs. The
logic level present at the data input is transferred to the out­put during the positive going transition of the clock pulse.
SET and RESET are independent of the clock and are
accomplished by a low level at the appropriate input.

Ordering Information

PART

NUMBER

CD74AC74E 0 to 70, -40 to 85

CD74ACT74E 0 to 70, -40 to 85

CD74AC74EX 0 to 70, -40 to 85

CD74ACT74EX 0 to 70, -40 to 85

CD74AC74M 0 to 70, -40 to 85

CD74ACT74M 0 to 70, -40 to 85

NOTES:

1. When ordering, use the entire part number. Add thesuffix96to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all elec­trical specifications. Please contact your local sales office or Harris
customer service for ordering information.

CD74AC74, CD74ACT74

(PDIP, SOIC)

TOP VIEW

1R
1D

1S
1Q
1Q

1
2
3
4
5
6
7

14
13
12
11
10

9
8

V

CC

2R
2D
2CP
2S
2Q
2Q

CD74ACT74

Positive-Edge-Triggered

TEMP.

RANGE (oC) PACKAGE

14 Ld PDIP E14.3

-55 to 125
14 Ld PDIP E14.3

-55 to 125
14 Ld PDIP E14.3

-55 to 125
14 Ld PDIP E14.3

-55 to 125
14 Ld SOIC M14.15

-55 to 125
14 Ld SOIC M14.15

-55 to 125

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

1

File Number 1881.1

CD74AC74, CD74ACT74

Functional Diagram

1

1R

2

R

1D

1CP

1S
2R

2D

2CP

2S

D

FF1

3

CP

4

13

12

D

FF2

11

CP

10

TRUTH TABLE

INPUTS OUTPUTS

SET RESET CP D Q Q

LHXXH L

HLXX L H

L L X X H (Note 5) H (Note 5)
HH↑HH L
HH↑LLH
HHLXQ0Q0

NOTES:

3. H = High level (steady state), L = Low level (steady state), X =
Don’t care, ↑ = Transition from Low to High level.

4. Q0 = the level of Q before the indicated input conditions were es­tablished.

5. This configuration is nonstable,that is, itwill not persist when set
and reset inputs return to their inactive (high) level.

5

1Q

6

1Q

S

9

R

S

2Q

8

2Q

2

CD74AC74, CD74ACT74

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 6) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 7)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

6. For up to 4 outputs per device, add ±25mA for each additional output.

7. Unless otherwise specified, all voltages are referenced to ground.

8. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 8) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS
(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 9, 10)

-50

5.5----3.85 - V

(Note 9, 10)

UNITSV

3

CD74AC74, CD74ACT74

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS
(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 9, 10)

50

5.5-----1.65 V

(Note 9, 10)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current,
FF

I

CC

VCC or

GND

0 5.5 - 4 - 40 - 80 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 9, 10)

-50

5.5----3.85 - V

(Note 9, 10)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 9, 10)

50

5.5-----1.65 V

(Note 9, 10)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current,
FF

AdditionalSupply Current per
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 4 - 40 - 80 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

9. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

o

10. Test verifies a minimum 50Ω transmission-line-drive capability at 85

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

D 0.53

R, S 0.58

CP 1

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

4

CD74AC74, CD74ACT74

Prerequisite For Switching Function

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

AC TYPES

Data to CP Setup Time t

Hold Time t

Removal Time, R, S to CP t

Pulse Width, R, St

Pulse Width, CP t

CP Frequency f

SU

H

REM

W

W

MAX

ACT TYPES

Data to CP Setup Time t
Hold Time t
Removal Time, R, S to CP t
Pulse Width, R, St
Pulse Width, CP t
CP Frequency f

SU

H

REM

W
W

MAX

NOTES:

11. 3.3V Min at 3.6V.

12. 5V Min at 4.5V.

1.5 39 - 44 - ns

3.3 (Note 11) 4.3 - 4.9 - ns
5 (Note 12) 3.1 - 3.5 - ns

1.5 0 - 0 - ns

3.3 0 - 0 - ns
50-0-ns

1.5 30 - 34 - ns

3.3 4.1 - 4.7 - ns
5 2.4 - 2.7 - ns

1.5 44 - 50 - ns

3.3 4.9 - 5.6 - ns
5 3.5 - 4 - ns

1.5 49 - 56 - ns

3.3 5.5 - 6.3 - ns
5 3.9 - 4.5 - ns

1.5 10 - 9 - MHz

3.3 90 - 79 - MHz
5 125 - 110 - MHz

5 (Note 12) 3.5 - 4 - ns

50-0-ns
5 2.4 - 2.7 - ns
5 4.4 - 5 - ns
5 5 - 5.7 - ns
5 97 - 85 - MHz

UNITSMIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL V

AC TYPES

Propagation Delay, CP to Q, Qt

PLH

, tf = 3ns, CL= 50pF (Worst Case)

r

(V)

CC

, t

PHL

1.5 - - 114 - - 125 ns

3.3

3.6 - 12.7 3.5 - 14 ns

(Note 14)

5

2.6 - 9.1 2.5 - 10 ns

(Note 15)

5

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

CD74AC74, CD74ACT74

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

r

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL V

Propagation Delay, R, StoQ,Qt

PLH

(V)

CC

1.5 - - 120 - - 132 ns

3.3 3.8 - 13.4 3.7 - 14.7 ns
5 2.7 - 9.5 2.6 - 10.5 ns

t

PHL

1.5 - - 131 - - 144 ns

3.3 4.1 - 14.6 4 - 16.1 ns
5 3 - 10.4 2.9 - 11.5 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 55 - - 55 - pF

(Note 16)

ACT TYPES

Propagation Delay, CP to Q, Qt

Propagation Delay, R, StoQ,Qt

Input Capacitance C
Power Dissipation Capacitance C

PHL

t

PLH
PLH

t

PHL

I

PD

5

2.5 - 8.6 2.4 - 9.5 ns

(Note 15)

5 3 - 10.5 2.9 - 11.5 ns
5 3.2 - 11.4 3.1 - 12.5 ns

- - -10- -10pF

- - 55 - - 55 - pF

(Note 16)

NOTES:

13. Limits tested 100%.

14. 3.3V Min at 3.6V, Max at 3V.

15. 5V Min at 5.5V, Max at 4.5V.

16. CPD is used to determine the dynamic power consumption per flip-flop.
PD=CPDV

CC

2

fi+ Σ (CLV

2

fo)+VCC∆ICCwhere fi= input frequency, fo= output frequency, CL= output load capacitance, VCC=

CC

supply voltage.

UNITSMIN TYP MAX MIN TYP MAX

INPUT LEVEL

GND

CP

INPUT LEVEL

GND

Q OR

V

S

t

PHL

Q

V

t

S

W

V

S

t

V

PLH

S

V

S

INPUT

CP

(

Q)

Q

(Q)

Q

FIGURE 1. FIGURE 2.

INPUT LEVEL

INPUT LEVEL

GND

GND

CP

D

V

S

tSU(L)

V

S

V

S

V

S

(L)

t

H

(H)

t

SU

V

FIGURE 3.

R (S)

V

S

S

tH(H)

t

V

PLH

V

S

t

S

t

W

V

S

REM

V

S

6

DUT

OUTPUT

R

L

CD74AC74, CD74ACT74

(NOTE)
500Ω

OUTPUT

LOAD

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

CD74AC CD74ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 4. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

7

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