Texas Instruments CD74ACT253M96, CD74ACT253M, CD74ACT253E, CD74AC253M96, CD74AC253M Datasheet

Data sheet acquired from Harris Semiconductor
SCHS247A

CD74AC253,

CD54/74ACT253

August 1998 - Revised May 2000

Features

• Buffered Inputs

• Typical Propagation Delay

- 6.3ns at V

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

= 5V, TA = 25oC, CL = 50pF

CC

Dual 4-Input Multiplexer, Three-State

Description

The CD74AC253 and ’ACT253 dual 4-input multiplexers that
utilize Advanced CMOS Logic technology. One of the four
sources for each section is selected by the common Select
inputs, S0 and S1. When theOutputEnable (
HIGH, the output is in the high-impedance state.

Ordering Information

PART

NUMBER

CD74AC253E 0 to 70oC, -40 to 85,

CD74AC253M 0 to 70oC, -40 to 85,

CD54ACT253F3A -55 to 125 16 Ld CERDIP
CD74ACT253E 0 to 70oC, -40 to 85,

CD74ACT253M 0 to 70oC, -40 to 85,

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waferanddieforthispart number is availablewhichmeetsall elec­trical specifications. Please contact yourlocal TI sales office or cus­tomer service for ordering information.

TEMP.

RANGE (oC) PACKAGE

-55 to 125

-55 to 125

-55 to 125

-55 to 125

1OE or 2OE) is

16 Ld PDIP

16 Ld SOIC

16 Ld PDIP

16 Ld SOIC

Pinout

CD54ACT253

(CERDIP)

CD74AC253, CD74ACT253

(PDIP, SOIC)

TOP VIEW

V

1

1OE

2

S

1

3

1I

3

4

1I

2

5

1I

1

6

1I

0

1Y

7
8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated.

16

CC

15

2OE

14

S

0

13

2I

3

12

2I

2

11

2I

1

10

2I

0

9

2Y

1

Functional Diagram

SELECT INPUTS DATA INPUTS
S1 S0 nI

XXXXXXHZ
LLLXXXLL
LLHXXXLH
LHXLXXLL
LHXHXXLH
HLXXLXLL
HLXXHXLH
HHXXXLLL
HHXXXHLH

Select inputs S1 and S0 are common to both sections. H = High level, L = Low inputs, X = Don’t care, Z = High imped­ance.

CD74AC253, CD54/74ACT253

1

1OE

6

1I

0

5

1I
1I
1I
S0

S1

2I
2I
2I
2I

2OE

1

2

3

14

10

0

11

1

12

2

13

3

15

SEL/MUX

4
3

2

SEL/MUX

TRUTH TABLE

0

nI

1

nI

7

9

GND = 8
V

CC

2

1Y

2Y

= 16

nI

ENABLE

INPUTS OUTPUT

3

nOE nY

2

CD74AC253, CD54/74ACT253

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

IK

OK

CC orIGND

O

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . 150C

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

- - 1.5 1.2 - 1.2 - 1.2 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

-50

(Note 6, 7)

V

CC

(V)

3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

5.5 - - 3.85 - - - V

5.5----3.85 - V

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

3

CD74AC253, CD54/74ACT253

DC Electrical Specifications (Continued)

TEST

PARAMETER SYMBOL

Low Level Output Voltage V

OL

CONDITIONS

VIH or V

V

CC

(V)

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

25oC

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Three-State Leakage
Current

I

OZ

VIH or V
VO=V

CC

IL

- 5.5 - ±0.5 - ±5-±10 µA

or GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Three-State or Leakage
Current

I

OZ

VIH or V
VO=V

CC

IL

- 5.5 - ±0.5 - ±5-±10 µA

or GND

Quiescent Supply Current
MSI

AdditionalSupplyCurrentper
Input Pin TTL Inputs High

I

CC

VCC or

0 5.5 - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

1 Unit Load

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

4

CD74AC253, CD54/74ACT253

ACT Input Load Table

INPUT UNIT LOAD

S0, S1, nI0, nI

1

nOE 0.83

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

1

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case)

r

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay,
S0, S1, to Y

t

PLH

, t

PHL

1.5 - - 227 - - 250 ns

3.3

7.2 -257-28ns

(Note 9)

5

5.2 - 18.2 5 - 20 ns

(Note 10)

Propagation Delay,
nI to Y

t

PLH

, t

PHL

1.5 - - 151 - - 166 ns

3.3 4.8 - 16.9 4.7 - 18.6 ns
5 3.4 - 12.1 3.3 - 13.3 ns

Propagation Delay,
Output Enable,
Output Disable to Y

t

PLZ

t

PZL

, t

, t

PHZ

PZH

,

1.5 - - 131 - - 144 ns

3.3 4.5 - 15.7 4.3 - 17.3 ns
5 3 - 10.5 2.9 - 11.5 ns

Three-State Output

C

O

- - -15- -15pF

Capacitance
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 107 - - 107 - pF

(Note 11)

ACT TYPES

Propagation Delay,
S0, S1, to Y

Propagation Delay,

t

PLH

t

PLH

, t

PHL

5

5.7 - 20 5.5 - 22 ns

(Note 10)

, t

PHL

5 4.6 - 16.4 4.5 - 18 ns

nI to Y
Propagation Delay,

Output Enable,

t

PLZ

t

PZL

, t

, t

PHZ

PZH

,

5 3.2 - 11.5 3.2 - 12.6 ns

Output Disable to Y
Three-State Output

C

O

- - -15- -15pF

Capacitance
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 107 - - 107 - pF

(Note 11)

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per multiplexer.
AC: PD = V
ACT: PD = V

2

fi(CPD + CL)

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

UNITSMIN TYP MAX MIN TYP MAX

5

CD74AC253, CD54/74ACT253

C

L

50pF

t

f

t

PZL

t

PZH

500Ω
R

L

= 3ns

†

500Ω†
R

V

S

0.2V

0.8 V
V

S

OUTPUTS

ENABLED
GND (t
OPEN (t

(t

2 V

CC

(OPEN DRAIN)

OUT

L

INPUT LEVEL

90%
V
10%

GND

CC

VOL (≠ GND)

(≠ VCC)

V

OH

CC

PHL,tPLH
PLZ,tPZL

)

)

PHZ,tPZH

S

)

= 3ns

t

r

OUTPUT

DISABLE

t

PLZ

OUTPUT: LOW

TO OFF TO LOW

t

PHZ

OUTPUT: HIGH

TO OFF TO HIGH

OUTPUTS
ENABLED

OTHER

INPUTS

(TIED HIGH

OR LOW)

OUTPUT

DISABLE

THREE-

OUTPUT

†FOR AC SERIES ONLY: WHEN V

DUT

WITH

STATE

OUTPUTS

DISABLED

= 1.5V, RL = 1kΩ

CC

FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT

INPUT

LEVEL

I OR S

tr = 3ns tf = 3ns

OUTPUT Y

t

PLH

t

PHL

FIGURE 2. PROPAGATION DELAY TIMES

OUTPUT

R

(NOTE)

L

DUT

OUTPUT

LOAD

500Ω

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 3. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

90%
V

S

10%

V

S

CC

6

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Copyright  2000, Texas Instruments Incorporated