Texas Instruments 74ACT11373NT, 74ACT11373DWR, 74ACT11373DW, 74ACT11373DBR Datasheet
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Eight Latches in a Single Package
D
3-State Bus Driving True Outputs
D
Full Parallel Access for Loading
D
Buffered Input and Output-Enable Pins
D
Inputs Are TTL-Voltage Compatible
D
Flow-Through Architecture Optimizes
PCB Layout
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
description
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the 74ACT1 1373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels
that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impendance third state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The 74ACT11373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L H H H
L HL L
L LX Q
0
H X X Z
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DB, DW, OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
OE
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
LE
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
8D
7D
6D
5D
4D
3D
2D
1D
LE
OE
14
16
17
20
21
22
23
13
24
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
11
10
9
4
3
2
1
1D
C1
EN
15
logic diagram (positive logic)
8D
7D
6D
5D
4D
3D
2D
1D
LE
OE
14
15
16
17
20
21
22
23
13
24
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
11
10
9
4
3
2
1
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
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