54AC16821,74AC16821
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS401 – SEPTEMBER 1991
• Members of the Texas Instruments
Widebus Family
• Packaged in Shrink Small-Outline 300-mil
Packages (DL) and 380-mil Fine-Pitch
Ceramic Flat Packages Using 25-mil
Center-to-Center Pin Spacings
• Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses with
Parity
• Flow-Through Architecture to Optimize
Printed-Circuit-Board (PCB) Layout
• Distributed V
and GND Pin Configuration
CC
to Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C
description
These 20-bit flip-flops feature three-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
These devices can be used as two 10-bit flip-flops
or one 20-bit flip-flop.
On the positive transition of the clock the Q outputs
will follow the D inputs. A buffered output enable
(OE
) input can be used to place the twenty outputs
in either a normal logic state (high or low) or a
high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus
lines significantly. The output enable (OE
not affect the internal operation of the flip-flops.
Old data can be retained or new data can be
entered while the outputs are in the
high-impedance state.
) does
6821...WD PACKAGE
6821...DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
2Q7
2Q8
GND
2Q9
2Q10
2OE
(TOP VIEW)
CC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2CLK
PRODUCT PREVIEW
The 74AC16821 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16821 is characterized over the full military temperature range of –55°C to 125°C. The 74AC16821
is characterized for operation from –40°C to 85°C.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1991, Texas Instruments Incorporated
1
54AC16821,74AC16821
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
DXXXX, SEPTEMBER 1991
FUNCTION TABLE
INPUTS
OE CLK D Q
L ↑ H H
L ↑ LL
LLX Q
HXX Z
OUTPUT
0
logic symbol
1
1OE
56
1CLK
28
2OE
29
2CLK
PRODUCT PREVIEW
55
1D1
54
1D2
52
1D3
51
1D4
49
1D5
48
1D6
47
1D7
45
1D8
44
1D9 1Q9
43
1D10
42
2D1
41
2D2
40
2D3
38
2D4
37
2D5
36
2D6
34
2D7
33
2D8
31
2D9
30
2D10
†
EN2
EN4
1D
3D
C1
C3
1
2
4
1
10
12
13
14
15
16
17
19
20
21
23
24
26
27
logic diagram (positive logic)
1
1OE
1D1
2OE
2D1
56
55
28
29
42
C1
1D
To 9 Other Channels
C1
1D
To 9 Other Channels
15
2
1Q1
2Q1
1CLK
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2CLK
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
†
This symbol is in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16821,74AC16821
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
DXXXX, SEPTEMBER 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Maximum package power dissipation at T
CC
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
IK
OK
I
< 0 or V
(VO < 0 or V
O
CC
> VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
> VCC) ± 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VO = 0 to VCC) ± 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND pins ± 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
= 55°C (in still air) 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions (see Note 2)
54AC16821 74AC16821
MIN NOM MAX MIN NOM MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
A
NOTE 2: Unused or floating (input or I/O) must be held high or low
Supply voltage 3 5 5.5 3 5 5.5 V
VCC = 3 V 2.1 2.1
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 5.5 V 1.65 1.65
Input voltage 0 V
Output voltage 0 V
VCC = 3 V –4 –4
High-level output current VCC = 4.5 V –24 –24 mA
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
Low-level output current VCC = 4.5 V 24 24 mA
VCC = 5.5 V 24 24
Operating free-air temperature –55 125 –40 85 °C
CC
CC
0 V
0 V
CC
CC
UNIT
V
V
†
PRODUCT PREVIEWPRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
54AC16821,74AC16821
Header line 2
WITH 3-STATE OUTPUTS
DXXXX, SEPTEMBER 1991
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
IOH = –50 µA 4.5 V 4.4 4.4 4.4
V
OH
V
OL
PRODUCT PREVIEWPRODUCT PREVIEW
I
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
I
I
A or B ports
OZ
I
CC
C
Control inputs VI = VCC or GND 5 V 4.5 pF
i
C
A or B ports VO = VCC or GND 5 V 16 pF
io
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
IOH = –4 mA 3 V 2.58 2.4 2.48
IOH = –24 mA
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA 4.5 V 0.1 0.1 0.1
IOL = 12 mA 3 V 0.36 0.5 0.44
IOL = 24 mA
IOL = 50 mA
IOL = 75 mA
‡
VO = VCC or GND 5.5 V ±0.5 ±10 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 8 160 80 µA
CC
3 V 2.9 2.9 2.9
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.7 3.8
5.5 V 4.94 4.7 4.8
†
†
†
†
5.5 V 3.85
5.5 V 3.85
3 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
5.5 V 1.65
5.5 V 1.65
TA = 25°C 54AC16821 74AC16821
MIN TYP MAX MIN MAX MIN MAX
UNIT
V
V
timing requirements over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V
V
CC
TA = 25°C 54AC16821 74AC16821
MIN MAX MIN MAX MIN MAX
f
Clock frequency MHz
clock
t
Pulse duration, CLK high or low ns
w
t
Setup time, data before CLK↑ ns
su
t
Hold time, data after CLK↑ ns
h
timing requirements over recommended operating free-air temperature range,
= 5 V ± 0.5 V
V
CC
TA = 25°C 54AC16821 74AC16821
MIN MAX MIN MAX MIN MAX
f
Clock frequency MHz
clock
t
Pulse duration, CLK high or low ns
w
t
Setup time, data before CLK↑ ns
su
t
Hold time, data after CLK↑ ns
h
UNIT
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC16821,74AC16821
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
DXXXX, SEPTEMBER 1991
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
PARAMETER
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO TA = 25°C 54AC16821 74AC16821
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
CLK
OE
OE
FROM TO TA = 25°C 54AC16821 74AC16821
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
CLK
OE
OE
Any Q
Any Q
Any Q
Any Q
Any Q
Any Q
UNIT
MHz
ns
ns
ns
UNIT
MHz
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per flip-flop CL = 50 pF, f = 1 MHz
Outputs enabled
Outputs disabled
pF
PRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
54AC16821,74AC16821
20-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
DXXXX, SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500 Ω
S1
2 x V
Open
GND
CC
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
S1
Open
2 x V
GND
CC
500 Ω
t
su
(see Note A)
Timing Input
(See Note B)
CL = 50 pF
LOAD CIRCUIT FOR OUTPUTS
PRODUCT PREVIEW
Data Input
Input
(See Note B)
Output
t
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
50% V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
t
CC
t
w
3 V
Input
3 V
0 V
h
3 V
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 x V
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
t
PHL
50% V
0 V
3 V
0 V
V
CC
V
OH
OL
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V1.5 V
t
CC
PZL
t
PZH
ENABLE AND DISABLE TIMES
t
PLZ
50% V
t
PHZ
50% V
CC
CC
20% V
80% V
CC
CC
0 V
3 V
0 V
≈
V
V
0 V
V
OL
OH
CC
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf≤ 3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1996, Texas Instruments Incorporated
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