SUMMIT
MICROELECTRONICS, Inc. SMS2902/SMS2904/SMS2916
Voltage Supervisory Circuit With Watchdog Timer
FEATURES
•Precision Voltage Monitor
–VCC Supply Monitor
-Complementary reset outputs for complex microcontroller systems
-Integrated memory write lockout function
-No external components required
•Watchdog Timer
–1600 ms, internal
•Two Wire Serial Interface (I2C™)
•Extended Programmable Functions available on SMS24
•High Reliability
–Endurance: 100,000 erase/write cycles
–Data retention: 100 years
•8-Pin PDIP or SOIC Packages
OVERVIEW
The SMS29xx is a power supervisory circuit that monitors VCC and will generate complementary reset outputs. The reset pins also act as I/Os and may be used for signal conditioning. The SMS29xx also has an on-board watchdog timer.
The SMS29xx integrates a nonvolatile serial memory. It features the industry standard I2C serial interface allowing quick implementation in an end-users’ system.
BLOCK DIAGRAM
VCC 8
SCL |
6 |
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NONVOLATILE |
SDA |
5 |
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MEMORY |
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ARRAY |
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WRITE |
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CONTROL |
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PROGRAMMABLE |
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RESET PULSE |
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GENERATOR |
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+ |
VTRIP |
RESET |
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– |
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CONTROL |
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1.26V |
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WATCHDOG |
WDI# |
1 |
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TIMER |
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4
GND |
2028 T BD 2.0 |
2 RESET#
7 RESET
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 |
• Campbell, CA 95008 • Telephone 408-378- 6461 • Fax 408-378-6586 • www.summitmicro.com |
© SUMMIT MICROELECTRONICS, Inc. 2000 |
Characteristics subject to change without notice |
2028 5.0 4/18/00 |
1 |
SMS2902/SMS2904/SMS2916
PIN CONFIGURATIONS |
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PIN NAMES |
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8-Pin PDIP |
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Symbol |
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Description |
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WDI# |
1 |
Watchdog Input /a high to |
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or 8-Pin SOIC |
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low transition will clear the |
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watchdog timer |
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WDI# |
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1 |
8 |
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VCC |
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RESET# |
2 |
Active Low RESET Input/Output |
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RESET# |
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2 |
7 |
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RESET |
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NC |
3 |
No Connect, tie to ground |
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NC |
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3 |
6 |
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SCL |
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or leave open |
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GND |
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4 |
5 |
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SDA |
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GND |
4 |
Analog and Digital Ground |
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2028 T PCon 2.0 |
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SDA |
5 |
Serial Memory Input/ |
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Output data line |
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SCL |
6 |
Serial Memory clock input |
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RESET |
7 |
Active High RESET Input/ |
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Output |
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VCC |
8 |
Supply Voltage |
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2028 PGM T1.1
CAPACITANCE |
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TA = 25°C, f = 100KHz |
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Symbol |
Parameter |
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Max |
Units |
CIN |
Input Capacitance |
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5 |
pF |
LOUT |
Output Capacitance |
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8 |
pF |
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2028 PGM T2..0 |
tR |
tH IGH |
tLOW |
tSU:STO |
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tF |
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SCL |
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tSU:SDA |
tHD:SDA |
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tHD:DAT |
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tSU:DAT |
tBUF |
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SDA In |
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tAA |
tDH |
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SDA Out |
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2028 ILL5.0 |
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FIGURE 1. SERIAL BUS TIMING DIAGRAM |
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2028 5.0 4/18/00 |
2 |
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SMS2902/SMS2904/SMS2916 |
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ABSOLUTE MAXIMUM RATINGS |
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Temperature Under Bias ............................................................................................................................... |
-40°C to +85°C |
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Storage Temperature ..................................................................................................................................... |
-65°C to +125°C |
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Soldering Temperature (less than 10 seconds) ................................................................................................................... |
300°C |
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Supply Voltage ............................................................................................................................................................. |
0 to 6.5V |
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Voltage on Any Pin ....................................................................................................................................... |
-0.3V to VCC+0.3V |
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ESD Voltage (JEDEC method) .......................................................................................................................................... |
2,000V |
NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature |
Min |
Max |
Commercial |
0°C |
+70°C |
Industrial |
-40°C |
+85°C |
2028 PGM T3.0
DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified)
Symbol |
Parameter |
Conditions |
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Min |
Max |
Units |
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SCL = CMOS Levels @ 100KHz |
VCC =5.5V |
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3 |
mA |
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ICC |
Supply Current (CMOS) |
SDA = Open |
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All other inputs = GND or VCC |
VCC =3.3V |
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2 |
mA |
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ISB |
Standby Current (CMOS) |
SCL = SDA = VCC |
VCC =5.5V |
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50 |
µA |
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All other inputs = GND |
VCC =3.3V |
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25 |
µA |
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ILI |
Input Leakage |
VIN = 0 To VCC |
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10 |
µA |
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ILO |
Output Leakage |
VOUT = 0 To VCC |
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10 |
µA |
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VIL |
Input Low Voltage |
S0, S1, S2, SCL, SDA, RESET# |
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0.3xVCC |
V |
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VIH |
Input High Voltage |
S0, S1, S2, SCL, SDA, RESET |
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0.7xVCC |
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V |
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VOL |
Output Low Voltage |
IOL = 3mA SDA |
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0.4 |
V |
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2028 PGM T4.0
AC ELECTRICAL CHARACTERISTICS |
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(over recommended operating conditions unless otherwise specified) |
2.7V to 4.5V |
4.5V to 5.5V |
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Symbol |
Parameter |
Conditions |
Min |
Max |
Min |
Max |
Units |
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fSCL |
SCL Clock Frequency |
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0 |
100 |
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400 |
KHz |
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tLOW |
Clock Low Period |
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4.7 |
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1.3 |
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µs |
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tHIGH |
Clock High Period |
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4.0 |
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0.6 |
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µs |
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tBUF |
Bus Free Time |
Before New Transmission |
4.7 |
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1.3 |
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µs |
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tSU:STA |
Start Condition Setup Time |
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4.7 |
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0.6 |
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µs |
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tHD:STA |
Start Condition Hold Time |
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4.0 |
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0.6 |
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µs |
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tSU:STO |
Stop Condition Setup Time |
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4.7 |
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0.6 |
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µs |
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tAA |
Clock to Output |
SCL Low to SDA Data Out Valid |
0.3 |
3.5 |
0.2 |
0.9 |
µs |
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tDH |
Data Out Hold Time |
SCL Low to SDA Data Out Change |
0.3 |
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0.2 |
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µs |
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tR |
SCL and SDA Rise Time |
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1000 |
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300 |
ns |
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tF |
SCL and SDA Fall Time |
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300 |
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300 |
ns |
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tSU:DAT |
Data In Setup Time |
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250 |
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100 |
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tHD:DAT |
Data In Hold Time |
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0 |
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0 |
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ns |
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TI |
Noise Spike Width |
Noise Suppression Time Constant |
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100 |
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100 |
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@ SCL, SDA Inputs |
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tWR |
Write Cycle Time |
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10 |
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10 |
ms |
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2028 PGM T5.0 |
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3 |
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2028 5.0 4/18/00 |
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SMS2902/SMS2904/SMS2916 |
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tGLITCH |
VTRIP |
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VRVALID |
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tRPD |
VCC |
tPURST |
tPURST |
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RESET# |
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tRPD |
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RESET |
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2028 T fig02 2.0 |
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FIGURE 2. RESET OUTPUT TIMING |
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
TA=-40°C to +85°C
Symbol |
Parameter |
Part no. |
Min. |
Typ. |
Max. |
Unit |
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Suffix |
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VTRIP |
Reset Trip Point |
A (or) Blank |
4.250 |
4.375 |
4.5 |
V |
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B |
4.50 |
4.625 |
4.75 |
V |
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2.7 |
2.55 |
2.65 |
2.75 |
V |
tPURST |
Reset Timeout |
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200 |
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tRPD |
VTRIP to RESET Output Delay |
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5 |
µs |
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VRVALID |
RESET Output Valid to VCC min. Guarantee |
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1 |
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V |
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tGLITCH |
Glitch Reject Pulse Width note 1 |
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30 |
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VOLRS |
RESET Output Low Voltage IOL = 1mA |
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0.4 |
V |
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VOHRS |
RESET High Voltage Output IOH = 800µA |
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VCC-.75 |
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V |
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VULH |
VSENSE Under-voltage threshold low to high |
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1.20 |
1.25 |
1.30 |
V |
VUHL |
VSENSE Under-voltage threshold high to low |
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1.20 |
1.25 |
1.30 |
V |
VOLH |
VSENSE Over-voltage threshold low to high |
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1.20 |
1.25 |
1.30 |
V |
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VOHL |
VSENSE Over-voltage threshold high to low |
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1.20 |
1.25 |
1.30 |
V |
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tVD1 |
Delay to VLOW Active |
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5 |
µs |
tVD2 |
Delay to VLOW Released |
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5 |
µs |
tWDTO |
Watchdog timeout Period |
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1600 |
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ms |
2028 5.0 4/18/00
4
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SMS2902/SMS2904/SMS2916 |
WDI# |
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tWDTO |
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tPURST |
RESET# |
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WDI# |
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tWDTO |
tPURST |
tWDTO |
tPURST |
RESET# |
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2028 T fig03 2.0 |
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FIGURE 3. WATCHDOG TIMER TIMING DIAGRAM |
RESET# (in) |
RESET# (out) |
tPURST |
tPURST |
RESET (out) |
2028 T fig04 2.0 |
FIGURE 4. RESET AS AN INPUT FUNCTION |
2028 5.0 4/18/00 |
5 |