STMicroelectronics M41T94 User Guide

512 Bit (64 bit x8) Serial RTC (SPI) SRAM

FEATURES SUMMARY

2.7 TO 5.5V OPERATING VOLTAGE
SERIAL PERIPHERAL INTERFACE (SPI)
2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
DESELECT CIRCUITRY
CHOICE OF POWER-FAIL DESELECT
VOLTAGES (V –THS = V –THS = V
COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR, AND CENTURY
44 BYTES OF GENERAL PURPOSE RAM
PROGRAMMABLE ALARM AND
INTERRUPT FUNCTION (VALID EVEN DURING BATTERY BACK-UP MODE)
WATCHDOG TIMER
MICROPROCESSOR POWER-ON RESET
BATTERY LOW FLAG
POWER-DOWN TIME-STAMP (HT Bit)
LOW OPERATING CURRENT OF 2.0mA
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (MAX)
PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT separately) or 16-LEAD SOIC
28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY AND CRYSTAL
= 2.7 to 5.5V):
CC
; 2.55V ≤ V
SS
; 4.20V ≤ V
CC
®
TOP (to be ordered
PFD
PFD
2.70V
4.50V
M41T94

Figure 1. 16-pin SOIC Package

16
1
SO16 (MQ)

Figure 2. 28-pin SOIC Package

SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
1/32June 2004
M41T94
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 16-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. 16-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Function Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. Data and Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10.Output Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ and WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Alarm Repeat Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13.Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14.Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Square Wave Output Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15.RSTIN1
and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/32
M41T94
Table 7. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
t
Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REC
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. t
Table 9. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Crystal Electrical Characteristics (Externally Supplied). . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REC
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20.SO16 – 16-lead Plastic Small Outline Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. SO16 – 16-lead Plastic Small Outline Package Mechanical Data. . . . . . . . . . . . . . . . . . 26
Figure 21.SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline. . . . . . . . 27
Table 17. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 27
Figure 22.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 28
Table 18. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data28
Figure 23.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 29
Table 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
M41T94

SUMMARY DESCRIPTION

The M41T94 Serial TIMEKEEPER® SRAM is a low power, 512-bit stat ic CMO S SR AM or ganized as 64 words by 8 bits. A built-i n 32,768H z osc illa­tor (external crys tal con trolled) a nd 8 byte s of the SRAM (see Table 4., page 14) are used for the clock/calendar function and are configured in bina­ry coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/con­trol of Alarm, Watchdog and Square Wave func­tions. Addresses and data are transfer red seria lly via a serial SPI interface. The built-in address reg­ister is incremented automatically after each WRITE or READ data byte. The M41T94 has a built-in power sense circuit which detects power failures and automatica lly switches to the battery supply when a power fai lure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell sup­ply when a power failure occurs. Function s avail­able to the user include a non-volatile, time-of-day clock/calendar, Alar m inte rrupts , Watch dog Time r and programmable Square Wave output. Other features include a Power-On Reset as well as two additional debounced inputs (RSTIN1 RSTIN2 (RST the century, year, month, date , day, hou r, minute, second and tenths/hundre dths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
) which can also generate an output Reset
). The eight c lock address locati ons contain
and
made automatically. The ninth clock address loca­tion controls user ac cess to the cl ock information and also stores the clock softwar e calibr ation set­ting.
The M41T94 is supplied in either a 16-lead plastic SOIC (requiring user suppl ied crys tal and ba tter y) or a 28-lead SOIC SNAPHAT tegrates both crystal and battery in a single SNAPHAT top). The 28-pin, 330mil SOIC provides sockets with gold pl ate d co ntac ts a t b oth en ds fo r direct connection to a separ ate SNAPHAT hous­ing containing the battery and crystal. The unique design allows the SNAPHAT bat tery/ crysta l pack­age to be mounted on top of the SOIC package af­ter the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperature s required for device s ur­face-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the bat­tery/crystal package (e .g., SNAPHAT) part num­ber is “M4TXX-BR12SH” (see Table
21., page 30).
Caution: Do not place the SNAPHAT battery/crys­tal top in conductive foam, as this will drain the lith­ium button-cell battery.
®
package (which in-
4/32
M41T94

Figure 3. Logic Diagram

V
V
CC
(1)
XI
(1)
XO
SCL
SDI
E RSTIN1 RSTIN2
WDI THS
M41T94
V
SS
BAT
(1)
RST IRQ/FT/OUT SQW SDO
AI03683

Table 1. Signal Names

E Chip Enable
/FT/OUT
IRQ
RST RSTIN1 RSTIN2 SCL Serial Clock Input SDI Serial Data Input SDO Serial Data Output SQW Square Wave Output THS Threshold Select Pin WDI Watchdog Input
(1)
XI
(1)
XO
(1)
V
BAT
Interrupt/Frequency Test/Out Output (Open Drain)
Reset Output (Open Drain) Reset 1 Input Reset 2 Input
Oscillator Input
Oscillator Output
Battery Supply Voltage
Note: 1. For SO16 package only.

Figure 4. 16-pin SOIC Connections

XI V
1
XO RST WDI
RSTIN1 RSTIN2
V
BAT V
SS
2 3 4 5 6 7 8
M41T94
16 15 14 13 12 11 10
9
AI03684
CC
E IRQ/FT/OUT THS SDI SQW SCL SDO
V
CC
V
SS
Note: 1. For SO16 package only.
Supply Voltage Ground

Figure 5. 28-pin SOIC Connections

SQW V
NC NC NC NC NC NC
WDI RSTIN1 RSTIN2
NC
1 2 3 4 5 6 7 8 9 10 11
M41T94
12
V
NC
SS
13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AI03685
CC
E IRQ/FT/OUT NC NC THS NC NC SCL NC RST SDINC SDO NC
5/32
M41T94

Figure 6. Block Diagram

Crystal
RSTIN1 RSTIN2
SDO
SDI
SCL
WDI
V
CC
E
SPI
INTERFACE
32KHz
OSCILLATOR
V
BAT
VBL= 2.5V
V
SO
V
PFD
= 2.5V
= 4.4V
COMPARE
COMPARE
COMPARE
(2.65V if THS = VSS)
REAL TIME CLOCK
CALENDAR
44 BYTES
USER RAM
RTC w/ALARM
& CALIBRATION
WATCHDOG
SQUARE W AVE
BL
POR
AF
WDF
IRQ/FT/OUT
SQW
(1)
RST
AI04785
(1)
Note: 1. Open drain output

Figure 7. Hardware Hookup

SPI Interface with (CPOL, CPHA) ('0','0') or ('1','1')
Master
(ST6, ST7, ST9,
ST10, Others)
CS3
Note: 1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU.
CS2
(1)
=
CS1
D Q C
CQD
M41T94
E
CQD
XXXXX
E E
CQD
XXXXX
AI03686
6/32

Table 2. Function Table

Mode E SCL SDI SDO
Disable Reset H Input Disabled Input Disabled High Z
M41T94
WRITE L Data Bit latch High Z
READ L X
Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
AI04630
AI04631

Figure 8. Data and Clock Timing

CPOL
CPHA
0
1
0
1
C
C
SDI
SDO
MSB
MSB
Next data bit shift
LSB
LSB
AI04632
(1)
Signal Description Serial Data Output (SDO). The output pin is
used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock.
Serial Data Input (SDI). The input pin is used to transfer data serially into the de vice. Instruction s, addresses, and the data to be written, are each re­ceived this way. Input is latched on the rising edge of the serial clock.
Serial Clock (SCL). The serial clock provides the timing for the serial inter face (as shown in Figure
9., page 9 and Figure 10., page 9). The W/R Bit,
addresses, or data are latched, from the input pin, on the rising edge of the clock input. The out put data on the SDO pin changes state after the falling edge of the clock input.
The M41T94 can be driven by a microcontroller with its SPI peripheral runnin g in either of the two following modes:
(CPOL, CPHA) = ('0', '0') or (CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and out­put data (SDO) is shifted out on the high-to-low transitio n of SC L (se e T abl e 2. , page 7 and Figure
8., page 7).
Chip Enable (E
). When E is high, the memory
device is deselect ed, and the SDO output pin is held in its high impedance state.
After power-on, a high-to-low transition on E
is re-
quired prior to the start of any operation.
7/32
M41T94

OPERATION

The M41T94 clock operates as a slave devic e on the SPI serial bu s. Each memory d evice is access­ed by a simple serial interface that is SPI bus com­patible. The bus signals ar e SCL, SDI and SDO (see Table 1., page 5 and Figure 7., page 6). The device is selected when the Chip Enable input (E is held low. All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (SDI) sampled on the fir st r i si ng edg e o f t he cl oc k (SCL) after the Chip Enable (E bytes contained in the device can then be access­ed sequentially in the following order:
1. Tenths/Hundredths of a Second Registe r
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register 11 - 16.Alarm Registers 17 - 19.Reserved
20. Square Wave Register 21 - 64.User RAM The M41T94 clock continually monitors V
out-of tolerance condition. Should V
, the device t erminat es an ac cess in pr ogress
V
PFD
and resets the device add ress counter. Inputs to the device will not be recognized at this time to prevent erroneous data from be ing written to the device from a an out-of-tol erance system. When V
falls below VSO, the device automatically
CC
switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power ret ur ns and V es above V
, the battery is disconnected, and the
SO
power supply is switched to external V
) goes low. The 64
for an
CC
fall below
CC
ris-
CC
.
CC
Write protection continues until V V
(min) plus t
PFD
(min). Fo r more inform ation
REC
on Battery Storage Life r efer to Application Note AN1012.

SPI Bus Characteristics

)
The Serial Peripheral interface (SPI) bus is intend­ed for synchronous communication between dif­ferent ICs. It consists of four signal lines: Serial Data Input (SDI), Serial Data Output (SDO), Serial Clock (SCL) and a Chip Enable (E
).
By definition a dev ic e tha t gi v es out a message is called “transmitter,” the receiving device th at gets the message is call ed “receiver.” The de vice that controls the messag e is called “master. ” The de­vices that are controlled by the master are called “slaves.”
The E
input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the maste r (micro) and the slave (M41T94) devices.
The SCL input, which is gen erated by the micro­controller, is ac tive only during address and data transfer to any de vice on the S PI bu s ( see Figure
7., page 6).
The M41T94 can be driven by a microcontroller with its SPI peripheral runnin g in either of the two following modes:
(CPOL, CPHA) = ('0', '0') or (CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock SCL, and out­put data (SDO) is shifted out on the high-to-low transitio n of SC L (se e T abl e 2. , page 7 and Figure
8., page 7).
There is one clock for each bit transferred. Ad­dress and data bits are transferred in groups of eight bits. Due to memory si ze the second most significant address bit is a Don’t Care (address bit
6).
reaches
CC
8/32

Figure 9. Input Timing Requirements

E
tELCH
SCL
tDVCH
tCHDX
tCHEH
tCLCH
M41T94
tEHEL
tEHCH
tCHCL
SDI
SDO
MSB IN
HIGH IMPEDANCE

Figure 10. Output Timing Requirements

E
SCL
tCLQV
tCLQX
SDO
ADDR. LSB IN
SDI
MSB OUT
tDLDH tDHDL
tCH
LSB IN
tCL
tQLQH tQHQL
AI04633
tEHQZ
LSB OUT
AI04634
9/32
M41T94

Table 3. AC Characteristics

Symbol
f
SCL
(2)
t
CH
(3)
t
CHCL
t
CHDX
t
CHEH
(2)
t
CL
(3)
t
CLCH
t
CLQV
t
CLQX
(3)
t
DHDL
(3)
t
DLDH
t
DVCH
t
EHCH
t
EHEL
(3)
t
EHQZ
t
ELCH
(3)
t
QHQL
(3)
t
QLQH
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where not ed).
2. t
CH
3. Value guaranteed by design, not 100% tested in production.
Serial Clock Input Frequency DC 2 MHz Clock High 200 ns
Clock Transition (Fall Time) 1 µs Serial Clock Input High to Input Data Transition 50 ns
Serial Clock Input High to Chip Enable High 200 ns Clock Low 200 ns
Clock Transition (Rise Time) 1 µs Serial Clock Input Low to Ou tpu t Valid 150 ns
Serial Clock Input Low to Output Data Transition 0 ns Input Data Transition (Fall Time) 1 µs
Input Data Transition (Rise Time) 1 µs Input Data to Serial Clock Input High 40 ns
Chip Enable High to Serial Clock Input High 200 ns Chip Enable High to Chip Enable Low 200 ns
Chip Enable High to Output High-Z 250 ns Chip Enable Low to Serial Clock Input High 200 ns Output Data Transition (Fall Time) 100 ns
Output Data Transition (Rise Time) 100 ns
+ tCL 1/f
SCL
Parameter
(1)
Min Max Unit
10/32

READ and WRITE Cycles

Address and data are shifted MSB first into the Se­rial Data Input (SDI) and out of the Serial Data Output (SDO). Any data transfer considers the first bit to define whether a READ or WRITE will occur. This is followed by seven bits defining the address to be read or written. Data is transferred out of the SDO for a READ operation and into th e SDI for a WRITE operation. The address is always the sec­ond through the eighth b it w ritten afte r the E nab le (E
) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a '0,' one or more READ cycles will occur (see Figure 11 and Figure 12., page 12).
Data transfers can occ ur one byte at a time or in multiple byte burst mode, during which the ad­dress pointer will be automatically incremented. For a single byte transfer, one byte is read or writ­ten and then E transfer all that is required is that E
is driven high. For a multip le byte
continue to re­main low. Under this condition, the address pointer will continue to increment as stated previously. In­crementing will con tinue until the devi ce is dese­lected by taking E
high. The address will wrap to
00h after incrementing to 3Fh. The system-to-user trans fer of clock data will be
halted whenever the address being read is a clock address (00h to 07h). A lthough the clock contin­ues to maintain the corre ct time, this will prevent updates of time and date dur ing either a READ or WRITE of these address locations by the user.
M41T94
The update will res ume either due to a deselect condition or when the pointer increments to an non-clock or RAM address (08h to 3Fh).

Note: This is true both in READ and WRITE mode. Data Retention Mode

With valid V cessed as described ab ov e wi th RE AD or WR ITE cycles. Should the supply voltage decay, the M41T94 will automati cally de select, write prot ect­ing itself when V V
(min) (see Figure 19., page 25). At this time,
PFD
the Reset pin (RST main active until V When V
), power input is switched from the VCC pin to
(V
SO
the SNAPHAT battery (or external battery for SO16) at this time, and the clock registers are maintained from the attache d battery supply. All outputs become high impedance. On power up, when V
CC
tion continues for t The RST time (see Figure 19., page 25). Before the next ac­tive cycle, Chip Enable should be taken high for at least t
EHEL
For a further more detailed rev iew of battery life­time calculations, please see Application Note AN1012.
applied, the M41T94 can be ac-
CC
falls between V
CC
(max) and
PFD
) is driven active and will re-
returns to nominal levels.
falls below the switch-over voltage
CC
CC
returns to a nominal value, write protec-
by internally inhibiting E.
REC
signal also remains active during this
, then low.

Figure 11. READ Mode Sequence

E
3
4
2
0
1
SCL
7 BIT ADDRESS
3
4
6
5
HIGH IMPEDANCE
SDI
SDO
W/R BIT
7
MSB
5
201
7
9
8
6
7
6
MSB
DATA OUT
(BYTE 1)
4
5
12 13
3
201
14
15 16
17 22
6
7
MSB
DATA OUT
(BYTE 2)
4
5
3
201
AI04635
11/32
M41T94

Figure 12. WRITE Mode Sequence

E
SCL
SDI
SDO
W/R BIT
7
MSB
9
1
2
0
7 BIT ADDR
443321
665
7
5
0
7
MSB
10
8
DATA BYTE
4321
65
HIGH IMPEDANCE
15
0
7
AI04636
12/32

CLOCK OPERATIONS

The eight byte clock register (see Table
4., page 14) is used to both set the c lock and to
read the date and time from the cl ock, in a binar y coded decimal format. Tenths/Hundredths of Sec­onds, Seconds, Minutes, and Hours are contained within the first four registers. Bits D6 and D7 of Clock Register 03h (Century/Hours Register) con­tain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (dep ending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06 h, and 07h con­tain the Date (day of month), Month and Years. The ninth clock register is the Control Register (this is described in the Clock Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will ca use the oscillator to stop. If the device is expected to spe nd a signifi­cant amou nt of ti me on th e shelf, the oscil lator m ay
TIMEKEEPER
The M41T94 offers 20 internal registers which contain Clock, Alarm, Watchdog, Flag, Square Wave and Control data (see Table 4., page 14). These registers are m emory lo cations which con ­tain external (user accessible) and internal copies of the data (usually referred to as BiPORT KEEPER cells). The external copies are inde pen ­dent of internal functions except that they are updated periodicall y by the s imultaneous tr ansfer of the incremented i nternal copy. Th e internal di-
®
Registers
TIME-
M41T94
be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second.
The eight Clock Registers may be read one byte at a time, or in a sequential block. The Control Reg­ister (Address l ocation 08h) may be accessed in ­dependently. Provisi on has been ma de to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock ad­dress is being read, an u pdate of the cl ock regis­ters will be halted. This will pr event a transiti on of data during the READ.

Power-down Time-Stamp

When a power failure occurs, the Halt Update Bit (HT) will automatically be set to a '1.' This will pre­vent the clock from updati ng the clock registers, and will allow the user to read the exact time of the power-dow n event. Resetting t he HT Bit to a '0' will allow the clock to upda te the clock registers with the current time. F or more i nform ation, see A ppli ­cation Note AN1572.
vider (or clock) chain will be reset upon t he com­pletion of a WRITE to any clock address.
The system-to-user trans fer of clock data will be halted whenever the clock addresses (00h to 07h) are being written. The upd ate will resume either due to a deselect condition or when the pointer in­crements to a non-clock or RAM address.
TIMEKEEPER and Ala rm Registers store data in BCD. Control, Watchdo g and Sq uare Wave Reg ­isters store data in Binary format.
13/32
M41T94

Table 4. TIMEKEEPER® Register Map

Addr
D7 D6 D5 D4 D3 D2 D1 D0
Function/Range
BCD Format
00h 0.1 Seconds 0.01 Seconds Seconds 00-99 01h ST 10 Seconds Seconds Seconds 00-59 02h 0 10 Minutes Minutes Minutes 00-59 03h CEB CB 10 Hours Hours (24 Hour Format) Century/Hours 0-1/00-23 04h TR 0 0 0 0 Day of Week Day 01-7 05h 0 0 10 Date Date: Day of Mo nth D at e 01-31 06h 0 0 0 10M Month Month 01-12 07h 10 Years Year Year 00-99 08h OUT FT S Calibration Control 09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 0Ah AFE SQWE ABE Al 10M Alarm Month Al Month 01-12
0Bh RPT4 RPT5 AI 10 Date Alarm Date Al Date 01-31 0Ch RPT3 HT AI 10 Hour Alarm Hour Al Hour 00-23 0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59 0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59 0FhWDFAF0BL0 0 0 0 Flags
10h00000000Reserved
11h00000000Reserved
12h00000000Reserved
13h RS3 RS2 RS1 RS0 0 0 0 0 SQW
Keys: S = Sign Bit
FT = Frequency Test Bit ST = Stop Bit 0 = Must be set to zero BL = Battery Low Flag (Read only) BMB0-BMB4 = Watchdog Multiplier Bits CEB = Century Enable Bit CB = Century Bit OUT = Output level AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bi ts WDS = Watchdog Steering Bit ABE = Alarm in Battery Back-Up Mode Enable Bit RPT1-RPT5 = Alarm Repeat Mode Bits WDF = Watchdog flag (Read only) AF = Alarm flag (Read only) SQWE = Square Wave Enable RS0-RS3 = SQW Frequency HT = Halt Update Bit TR = t
REC
Bit
14/32

Setting Alarm Clock Registers

Address locations 0Ah- 0E h con tai n the al arm set ­tings. The alarm c an be configured t o go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or sec ond. It can also be pro­grammed to go off while the M41T94 is in the bat­tery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 5., page 15 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickl y alert the user of an incorrect alarm setting.
When the clock information matches the alarm clock settings bas ed on th e m atc h c riter i a de fin ed by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condi­tion activates the IRQ
/FT/OUT pin.
Note: If the address pointer is allowed to incre­ment to the Flag Register addre ss, an alarm con­dition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different ad-
dress. It should al so be noted that if the last ad ­dress written is the “Ala rm Se conds,” the addr ess pointer will increment to the Flag address, causing this situation to occur.
To disable the alarm, write '0' to the Alarm Date Register and to RPT1–5. The IRQ is cleared by a READ to the Flags Register . This READ of the Flags Register will also reset the Alarm Flag (D6; Register 0Fh). See Figure
13., page 15.
The IRQ
/FT/OUT pin can also be activat ed in the battery back-up mode. The IRQ low if an alarm occurs and both ABE (Alarm in Bat­tery Back-up Mode Enab le ) a nd A F E a re se t. T he ABE and AFE Bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Fl ag Register at system boot-up to determine if an alarm was generated while th e M41T94 was in the deselect mode during power-up. Fig ure 14., page 16 illus­trates the back-up mode alarm timing.

Table 5. Alarm Repeat Mode

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting
1 1 1 1 1 Once per Second 1 1 1 1 0 Once pe r Minu te 1 1 1 0 0 Once per Hour 11000Once per Day 10000Once per Month 00000Once per Year
M41T94
/FT/OUT output
/FT/OUT will go

Figure 13. Alarm Interrupt Reset Waveforms

ACTIVE FLAG
IRQ/FT/OUT
0Fh0Eh 10h
HIGH-Z
AI03664
15/32
M41T94

Figure 14. Back-up Mode Alarm Waveforms

V
CC
V
PFD
V
SO
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
tREC
HIGH-Z

Watchdog Timer

The watchdog timer can be used to detect an out­of-control microprocessor. The user programs the watchdog timer by sett ing the desired amount of time-out into the Watchdog Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB 0 select the resolu­tion, where 00 =
1
/16 second, 01 =1/4 second, 10 = 1 second, and 11 = 4 seconds. T he amount of time-out is then determined to be the multiplica­tion of the five-bit multi plier value with th e resolu­tion. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M41T94 sets the WDF (Watchdog Flag) and generates a watchdog inter­rupt or a microprocess or reset. WDF is reset by reading the Flags Register (0Fh).
The most significan t bit of the Watc hdog Re gister is the Watchdog Steer ing B it (WDS ). When se t to a '0,' the watchdog w ill activate the IRQ
/FT/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a nega tiv e p uls e o n the RST pin for t
. The Watchdog regi ster and the AF E,
REC
ABE, SQWE, and FT Bits will reset to a '0' at the end of a Watchdog time-o ut when the WD S Bit is set to a '1.'
HIGH-Z
AI03920
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI), or
2. the microprocessor can perform a WRITE of the Watchdog Register.
The time-out period then starts over. The W DI pin should be tied to V
if not used. In o rder to per-
SS
form a software reset of the watchdog tim er, the original time-out period can be written into the Watchdog Register, effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS Bit is programmed to output an interrupt, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ
/FT/OUT pin. This will also disable the watchdog functio n until it is again pro­grammed correctly. A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0Fh).
The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ
/FT/OUT pin and the Freque ncy T est (FT ) function is activated, the watchdog function pre­vails and the Frequency Test function is denied.
16/32

Square Wave Output

The M41T94 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies
SQW frequency has been completed, the SQW pin can be turned on an d off under so ftware con­trol with the Square Wave Enab le Bit ( SQWE) lo­cated in Register 0Ah.
are listed in Table 6. Once the selection of the

Table 6. Square Wave Output Frequency

Square Wave Bits Square Wave
RS3 RS2 RS1 RS0 Frequency Units
0000None–
000132.768kHz
00108.192kHz
00114.096kHz
01002.048kHz
01011.024kHz 0110512Hz 0111256Hz 1000128Hz 100164Hz 101032Hz 101116Hz 11008Hz 11014Hz 11102Hz 11111Hz
M41T94
17/32
M41T94

Power-on Reset

The M41T94 continuously monitors V
falls to the power fail detect trip point, the RST
V
CC
. When
CC
pulls low (open dra in) and re mains low on power ­up for t
after VCC passes V
REC
(max). The RST
PFD
pin is an open drain output and an appropriate pull-up resistor should be chosen to control rise time.
Figure 15. RSTIN1
RSTIN1
RSTIN2
RST
and RSTIN2 Timing Waveforms
tRLRH1
(1)
tR1HRH tR2HRH
Reset Inputs (RSTIN1
& RSTIN2)
The M41T94 provides two independent inputs which can generate an output rese t. The duration and function of these res ets is ident ical to a res et generated by a power cycle. Table 7., page 18 and Figure 15., page 18 illustrate the AC reset characteristics of this function. Pulses shorter than t
RLRH1
tion. RSTIN1 pulled up to V
tRLRH2
and t
will not generate a rese t co ndi -
RLRH2
and RSTIN2 are each internally
through a 100k resistor.
CC
AI03665

Table 7. Reset AC Characteristics

Symbol
(2)
t
RLRH1
(3)
t
RLRH2
(4)
t
R1HRH
(4)
t
R2HRH
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where not ed).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. Programmable (see Table 8., page 21).
RSTIN1 Low to RSTIN1 High 200 ns RSTIN2 Low to RSTIN2 High 100 ms RSTIN1 High to RST High 40 200 ms RSTIN2 High to RST High 40 200 ms
Parameter
(1)
Min Max Unit
18/32

Calibrating the Clock

The M41T94 is driven by a quartz-controlled oscil­lator with a nominal frequency of 32,768Hz. Uncal­ibrated clock accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. When the Calibration circuit is properly em­ployed, accuracy improves to better than ±2 ppm at 25°C.
The oscillation rate of crystals ch anges with tem­perature (see Figure 16., page 20). Therefore, the M41T94 design emplo ys periodic c ounter correc­tion. The calibration circuit adds or subtracts counts from the osc illator divider circui t at the di­vide by 256 stage, as shown in Figure
17., page 20. The number of times pulses are
blanked (subtracted, ne gative calibration) or split (added, positive calibration) depends upon the value loaded into the fiv e Ca li br ation B it s fo und in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order bits (D4-D0) in the Control Register (8h). These bits can be set to represent a ny value betw een 0 and 31 in binary form. Bit D5 is a Sign B it; '1' in di ­cates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minute s in the cyc le may, once per minute, have one s econd eith er shorten ed by 128 or lengthened by 256 oscillator cycles. If a bi­nary '1' is loaded into t he register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the firs t 12 will be affected, and so on.
Therefore, each c alibration step ha s the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 act ual oscillator cy cles, that is +4.068 or –2.034 ppm of adjustment per cal ibra­tion step in the calibrati on reg ister. A ssum ing that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Ca li br ati on b yte wou ld
M41T94
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month.
Two methods are avail able for ascertaining how much calibration a given M41T94 may require.
The first involves setting the clock, letting it run for a month and comparing it to a known accurate ref­erence and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Applicatio n Note AN934: TIMEKEEPER CALIBRATION. This al lows the designer to give the end user the ability to calibrate the clock as the environment requires, ev en if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that ac­cesses the Calibration Byte.
The second approach is better suited to a m anu­facturing environment, and involves the use of the IRQ
/FT/OUT pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 o f 1h) is '0,' the Fre­quency Test Bit (FT, D6 of 8h) is '1,' the Alarm Flag Enable Bit (AFE, D7 of Ah) is '0,' and the Watch ­dog Steering Bit (WDS, D7 of 9h) is '1' or the Watchdog Register (9h = 0) is reset.
Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (XX001010) to be loaded into the Calibration Byte for correction.
Note: Setting or changing the Calibration Byte does not affect the Frequency Test output fre­quency.
The IRQ which requires a pu ll -up r es istor for proper opera ­tion. A 500 to 10k resistor is recommended in or­der to control the rise time. The FT Bit is cleared on power-down.
/FT/OUT pin is an open drain output
19/32
M41T94

Figure 16. Crystal Accuracy Across Temperature

Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0 10203040506070
F
F
K = –0.036 ppm/°C2 ± 0.006 ppm/°C
TO = 25°C ± 5°C
Temperature °C
= K x (T –T
2
)
O
2
80–10–20–30–40
AI00999b

Figure 17. Calibration Waveform

NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
20/32

Century Bit

Bits D7 and D6 of Clock Register 03h contai n the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to tog­gle, either from a '0' to '1' or from '1' to '0' at the turn of the century (de pending u pon its in itial state). If CEB is set to a '0,' CB will not toggle.

Output Driver Pin

When the FT Bit, AFE B it and W atc hd og Re gi ste r are not set, the IRQ
/FT/OUT pin becomes an out­put driver that reflec ts the contents of D7 of the Control Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location 0 8h are a '0,' then the IRQ
Note: The IRQ
/FT/OUT pin will be driven low.
/FT/OUT pin is an open drain which
requires an external pull-up resistor.

Battery Low Warning

The M41T94 automatic ally performs battery volt ­age monitoring upon power-up and at factory-pro­grammed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bi t D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of bat­tery replacement and subsequent battery low monitoring tests, eith er during the next power -up sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se­quence, this indicates that the battery is below ap­proximately 2.5 volts and may not be able to maintain data integrit y in the SRAM. Dat a should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indicat ion is generated du ring the 24-hour interval c heck, this indi cates th at the bat -
M41T94
tery is near end of life. Howev er, data is not com ­promised due to the fact that a nominal V supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The SNAPHAT top may be replaced while V
is applied to the de-
CC
vice. Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is disconnected.
The M41T94 only monitors the battery when a nominal V
is applied to the device. Thus appli-
CC
cations which require extensive durations in the battery back-up mode should be powered-up peri­odically (at least onc e every few mon ths) in orde r for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power- up via a checksum or other technique.
t
Bit
REC
Bit D7 of Clock Register 04h con tai ns th e t (TR). t the deselect time after V
refers to the automatic con tinuation of
REC
reaches V
CC
PFD
lows for a voltage setting time before WRITEs may again be performed to the devi ce after a power­down condition. The t
Bit will allow the user to
REC
set the length of this des elect time as defined b y Table 8.

Initial Power-on Defaults

Upon initial application of power to the device, the following register bits are set to a '0' state: Watch­dog Register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state: ST, OUT, and HT (see Table 9., page 22).
is
CC
Bit
REC
. This al-
Table 8. t
t
REC
Note: 1. Default Setting
Definitions
REC
Bit (TR)
0 0 96 98 ms 0140 1 X 50 2000 µs
STOP Bit (ST)
Time
t
REC
Min Max
200
(1)
Units
ms
21/32
M41T94

Table 9. Default Values

Condition TR ST HT Out FT AFE ABE SQWE
Initial Power-up (Battery Attach for SNAPH AT)
Subsequent Powe r-u p (wit h battery back-up)
Note: 1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
(3)
0111000 0 0
(2)
UC UC 1 UC 0 0 0 0 0
WATCHDOG
Register
(1)

MAXIMUM RATING

Stressing the device above the ra ting l isted in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of th e device at these or any other conditions above those indicat­ed in the Operating sections of this specification is

Table 10. Absolute Maximum Ratings

Symbol Parameter Value Unit
T
STG
V
CC
T
SLD
V
IO
I
O
P
D
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
Storage Temperature (VCC Off, Oscillator Off)
Supply Voltage –0.3 to 7 V
(1)
Lead Solder Temperature for 10 seconds 260 °C Input or Output Voltage
Output Current 20 mA Power Dissipation 1 W
between 90 to 150 seconds). for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while i n the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
not implied. Exposure to Absolute Maximum Rat­ing conditions for extended periods may affect de­vice reliability. Refer also to the STMicroelectronic s SURE P ro gram and other rel­evant quality documents.
SNAPHAT –40 to 85 °C
SOIC –55 to 125 °C
–0.3 to V
CC
+0.3
V
22/32

DC AND AC PARAMETERS

This section summ arizes the operati ng and mea­surement conditions , as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests perfo rmed under the Measure-

Table 11. DC and AC Measurement Conditions

Parameter M41T94
V
Supply Voltage
CC
Ambient Operating Temperature –40 to 85°C Load Capacitance (C
)
L
Input Rise and Fall Times 50ns Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.

Figure 18. AC Testing Input/Output Waveforms

ment Conditions liste d in the relevant table s. De­signers should check that the operating conditions in their projects match the measurement condi­tions when using the quoted parameters.
2.7 to 5.5V
100pF
0.2 to 0.8V
0.3 to 0.7V
M41T94
CC
CC
0.8V
0.2V
CC
CC
0.7V
0.3V
AI02568
CC
CC

Table 12. Capacitance

Symbol
C
IN
C
OUT
t
LP
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs are deselected.
Input Capacitance 7 pF
(3)
Output Capacitance 10 pF Low-pass filter input time constant (SDA and SCL) 50 ns
Parameter
(1,2)
Min Max Unit
23/32
M41T94

Table 13. DC Characteristics

= 3V
CC
V
V
(1)
– 0.3V
CC
CC
Min Typ Max Unit
400 500 nA
0.7V
CC
2.4 V
4.20 4.40 4.50
2.55 2.60 2.70
Symb. Parameter
Battery Current OSC ON
I
BAT
Battery Current OSC OFF 50 nA I I
I
I
LO
V V
V
V
V
Supply Current f = 2 MHz 2 mA
CC1
Supply Current (Standby)
CC2
(2)
Input Leakage Curren t
LI
(3)
Output Leakage Current
Input High Voltage
IH
Input Low Voltage –0.3
IL
Battery Voltage 2.5
BAT
OH
Output High Voltage
Output Low Voltage
OL
(4)
(4)
Output Low Voltage (Open Drain)
(5)
Test Condition
= 25°C, VCC = 0V,
T
A
V
BAT
SCL, SDI = V
0V V
IN
0V V
OUT
IOH = –1.0mA
IOL = 3.0mA
IOL = 10mA
Pull-up Supply Voltage (Open Drain) RST, IRQ/FT/OUT 5.5 V
Power Fail Deselect (THS = VCC)
V
PFD
Power Fail Deselect (THS = V
V
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where not ed).
Battery Back-up Switchover 2.5 V
SO
2. RSTI N1
3. Outputs Deselected.
4. For SQW pin (CMOS).
5. For IRQ
6. For rechargeable back-up, V
and RSTIN2 internally pull ed-up to VCC through 100K resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
/FT/OUT, RST pins (Open Drain): if pulled-up to s upply other tha n VCC, this supply must be equa l to, or less than 3.0V when
V
= 0V (during battery back-up mode).
CC
(max) may be considered VCC.
BAT
SS
)
1.4 mA ±1 µA ±1 µA
VCC + 0.3
0.3V
CC
(6)
3.5
0.4
0.4
V V V
V
V

Table 14. Crystal Electrical Characteristics (Externally Supplied)

Symbol
f
0
R
S
C
L
Note: 1. Load capacitors are integrated wi thin the M41T94. Circuit board layout considerations for the 32.768 k H z crystal of minimum trace
lengths and isolation from RF gen erating signals should be taken into account. These characteristics are externally supplied.
2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contac ted at kouhou@kdsj.co.jp or ht­tp://www.kdsj.co.jp for furt her information on this crystal type.
Resonant Frequency 32.768 kHz Series Resistance 50 k Load Capacitance 12.5 pF
Parameter
(1,2)
24/32
Typ Min Max Unit

Figure 19. Power Down/Up Mode AC Waveforms

V
CC
V
(max)
PFD
V
(min)
PFD
VSO
M41T94
INPUTS
RST
OUTPUTS
tF
VALID VALID
(PER CONTROL INPUT)
tFB
tDR
tRB
DON'T CARE
HIGH-Z
tR

Table 15. Power Down/Up AC Characteristics

Symbol
(2)
t
F
(3)
t
FB
t
R
t
RB
t
REC
t
DR
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where not ed).
2. V
3. V
4. At 25°C, V
5. Programmable (see Table 8., page 21)
V
(max) to V
PFD
V
(min) to VSS VCC Fall Time
PFD
V
(min) to V
PFD
VSS to V
(5)
Power up Deselect Time 40 200 ms
(min) VCC Rise Time
PFD
Expected Data Retention Time
(max) to V
PFD
200µs after V
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
CC
(min) fall time of less than tF may result in deselection/wr i te protection not occurring until
PFD
passes V
CC
= 0V (when using SOH28 + M4T28-BR12SH SNAPHAT top).
Parameter
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(min).
PFD
(1)
Min Typ Max Unit
300 µs
10 µs 10 µs
s
(4)
10
tREC
RECOGNIZEDRECOGNIZED
(PER CONTROL INPUT)
AI03687
YEARS
25/32
M41T94

PACKAGE MECHANICAL INFORMATION

Figure 20. SO16 – 16-lead Plastic Small Outline Package Outline

A2
A
B
e
CP
D
N
E
H
1
SO-b
Note: Drawing is not to scale.

Table 16. SO16 – 16-lead Plastic Small Outline Package Mechanical Data

Symbol
Typ. Min. Max. Typ. Min. Max.
A – –1.75– –0.069 A1 0.10 0.25 0.004 0.010 A2 1.60 0.063
B 0.35 0.46 0.014 0.018
C 0.19 0.25 0.007 0.010
D 9.80 10.00 0.386 0.394
E 3.80 4.00 0.150 0.158
e 1.27 0.050
H 5.80 6.20 0.228 0.244
L 0.40 1.27 0.016 0.050 a–0°8°–0°8°
N16 16
CP 0.10 0.004
millimeters inches
C
LA1 α
26/32

Figure 21. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline

M41T94
A2
A
C
Be
eB
CP
D
N
E
H
LA1 α
1
SOH-A
Note: Drawing is not to scale.

Table 17. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data

Symbol
Typ Min Max Typ Min Max
A – –3.05– –0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 0.050 – eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α –0°8°–0°8°
N28 28
CP 0.10 0.004
millimeters inches
27/32
M41T94

Figure 22. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Cr yst a l, Package Outline

A2
A3
L
eA
D
A1
A
B
eB
E
SHTK-A
Note: Drawing is not to scale.

Table 18. SH – 4-pin SN A P H AT Housing f o r 4 8 mA h Ba tter y & C rysta l, Package Mechanical Data

Symbol
Typ Min Max Typ Min Max
A – –9.78– –0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.8560
E 14.22 14.99 0.556 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
millimeters inches
28/32

Figure 23. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

M41T94
eA
D
A1
A
B
eB
A3
L
E
SHTK-A
Note: Drawing is not to scale.

Table 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data

Symbol
Typ Min Max Typ Min Max
A 10.54 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
millimeters inches
A2
29/32
M41T94

PART NUMBERING

Table 20. Ordering Information Scheme

Example: M41T 94 MH 6 E
Device Type
M41T
Supply Voltage and Write Protect Voltage
94 = V
Package
MQ = SO16 MH
Temperature Range
6 = –40 to 85°C
= 2.7 to 5.5V
CC
THS = V THS = V
(1)
= SOH28
; 4.20V ≤ V
CC
; 2.55V ≤ V
SS
PFD
PFD
4.50V
2.70V
Shipping Method For SO16:
blank = Tubes (Not for New Design - Use E) E = Lead-free Package (ECO PACK F = Lead-free Package (ECO PACK
®
), Tubes
®
), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
For SOH28:
blank = Tubes (Not for New Design - Use E) E = Lead-free Package (ECO PACK
®
), Tubes
F = Lead-free Package (ECO PACK®), Tape & Reel TR = Tape & Reel (Not for New Design - Use F)
Note: 1. The 28-pin SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4T X X-BR12SHXTR” in Tape & Reel form (see Table 21).
Caution: Do not place the S NAPHAT bat te ry pack age “M4TXX -BR12SH” in co nduct ive f oam as it will dra in the lit hium b utton -cell b at­tery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.

Table 21. SNAPHAT Battery Table

Part Number Description Package
M4T28-BR12SH Lithium Battery (48mAh) and Crystal SNAPHAT SH M4T32-BR12SH Lithium Battery (120mAh) and Crystal SNAPHAT SH
30/32

REVISION HISTORY

Table 22. Document Revision History

Date Version Revision Details
April 2002 1.0 First edition
25-Apr-02 1.1
03-Jul-02 1.2
06-Nov-02 1.3 Correct dimensions (Table 19) 26-Mar-03 1.4 Update test condition (Table 15)
28-Apr-03 2.0 New Si changes (Figure 6;Table 15, 7, 8, 9)
15-Jun-04 3.0
Adjust graphic (Figure 6); fix table text (Table 10, 20); adjust characteristics (Table 13,
14)
Modify DC, Crystal Electrical Characteristics footnotes, Default Value table (Tables 13,
14, 9)
Reformatted; added Lead-free information; update characteristics (Figure 16; Table 10,
13, 20)
M41T94
31/32
M41T94
Information furnished is be lieved to be a ccur ate and reli able. Howe ver, STMicroele ctronic s assu mes no r esponsib ilit y for th e consequences of use of such information nor for any infrin gement of patent s or other rights of third parties which ma y result from it s use. No license is granted
by implication or otherwi se under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without not ice. This pub licat ion su persed es and repl aces all in format ion previou sly su pplie d. STMicroele c tronic s prod ucts ar e no t
authorized for use as critical compone nts in life support devices or systems witho ut express written approval of STMicroelectronics.
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All other names are the property of their respective owners.
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32/32
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