ST STTS424E02 User Manual

STTS424E02

Memory module temperature sensor with a 2 Kb SPD EEPROM

Features

■STTS424E02 includes a JEDEC JC 42.4 compatible temperature sensor, integrated with industry standard 2 Kb serial presence detect (SPD) EEPROM (STTS2002 is recommended for new designs)

Temperature sensor

■Temperature sensor resolution:

0.25°C (typ)/LSB

■Temperature sensor accuracy:

– ± 1 °C from +75 °C to +95 °C

– ± 2 °C from +40 °C to +125 °C

– ± 3 °C from –40 °C to +125 °C

■ADC conversion time: 125 ms (max)

■Supply voltage: 2.7 V to 3.6 V

■Maximum operating supply current: 210 µA (EEPROM standby)

■Hysteresis selectable set points from: 0, 1.5, 3,

6.0°C

■Ambient temperature sensing range: –40 °C to +125 °C

2 Kb SPD EEPROM

■Functionality identical to ST’s M34E02 SPD EEPROM

■Permanent and reversible software data protection for the lower 128 bytes

Not recommended for new design

TDFN8

2 mm x 3 mm (max height 0.80 mm)

DFN8

2 mm x 3 mm (max height 0.90 mm)

Two-wire bus

■2-wire SMBus/I2C - compatible serial interface

■Temperature sensor supports SMBus timeout

■Supports up to 400 kHz transfer rate

Packages

■DN: 2 mm x 3 mm TDFN8, height: 0.80 mm (max). Compliant to JEDEC MO-229, WCED-3.

■DA: 2 mm x 3 mm DFN8, height: 0.90 mm (max). Contact local ST sales office for availability.

■ RoHS compliant, halogen-free

■ Single supply voltage: 2.7 V to 3.6 V

■ Byte and page write (up to 16 bytes)

■ Self-time WRITE cycle (5 ms, max)

■ Automatic address incrementing

■ Operating temperature range:

– –40 °C to +85 °C (DA package only)

– –40 °C to +125 °C (DN package only)

October 2010	Doc ID 13448 Rev 8	1/50
This is information on a product still in production but not recommended for new designs.		www.st.com

Contents	STTS424E02

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 7
	2.1	Device type identifier (DTI) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.2	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10

2.2.1 A0, A1, A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.3 SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.5 EVENT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.6 VDD (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3	Temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	3.1	SMBus/I2C communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	3.2	SMBus/I2C slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.3	SMBus/I2C AC timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

4	Temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	4.1	Capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17

4.1.1 Alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 Critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.1 Event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.4 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.5 Event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3	Temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .				24
	4.3.1	Temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			24
4.4					25
	Temperature trip point registers (R/W)			. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5	Manufacturer ID register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . .				26
4.6	Device ID and device revision ID register (read-only) . . . . . . . . . . . . . . .				26

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STTS424E02 Contents

5	SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	5.1	2 Kb SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.2	Internal device reset - SPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.3	Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	5.4	Setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29

5.4.1 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4.2 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.5 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.5.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5.2 Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5.3 Write cycle polling using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.6 Read operations - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.6.1 Random address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6.2 Current address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6.3 Sequential read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6.4 Acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.7 Initial delivery state - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6	Use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	6.1 Programming the SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36

6.1.1 DIMM isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 DIMM inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 36

7	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
8	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
10	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
11	Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
12	Landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
13	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49

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List of tables	STTS424E02

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. AC SMBus and I2C compatibility timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10. Hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 11. Legend for Figure 9: Event output boundary timings.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12. Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13. Temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14. Temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 15. Alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 16. Alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17. Critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 18. Manufacturer ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 19. Device ID and device revision ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 20. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 21. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 22. Acknowledge when writing data or defining the write-protection (instructions with

R/W bit=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. Acknowledge when reading the write protection (instructions with R/W bit=1). . . . . . . . . . 35 Table 24. DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 25. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 26. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 27. DC/AC characteristics - temperature sensor component with EEPROM . . . . . . . . . . . . . . 38 Table 28. DFN8 – 8-lead dual flat, no-lead (2 mm x 3 mm) mechanical data (DA) . . . . . . . . . . . . . . 41 Table 29. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN) . . . . . . . . . . 42 Table 30. Carrier tape dimensions for DFN8 and TDFN8 packages . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 31. Reel dimensions for 8 mm carrier tape - TDFN8 and DFN8 packages . . . . . . . . . . . . . . . 44 Table 32. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 33. Parameters for landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 34. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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STTS424E02	List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. DFN8 and TDFN8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SMBus/I2C write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. SMBus/I2C write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 12

Figure 6. SMBus/I2C write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 13 Figure 7. SMBus/I2C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10. Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11. Setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12. Write mode sequences in a non write-protected area of SPD . . . . . . . . . . . . . . . . . . . . . . 31 Figure 13. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 14. Read mode sequences - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 15. DFN8 – 8-lead dual flat, no-lead (2 mm x 3 mm) package outline (DA) . . . . . . . . . . . . . . . 41 Figure 16. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN) . . . . . . . . . . 42 Figure 17. Carrier tape for DFN8 and TDFN8 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 18. Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 19. DA package topside marking information (DFN-8L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 20. DN package topside marking information (TDFN-8L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 21. Landing pattern - TDFN package (DN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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Description	STTS424E02

1 Description

The STTS424E02 is targeted for DIMM modules in mobile personal computing platforms (laptops), server memory modules and other industrial applications. The thermal sensor (TS) in the STTS424E02 is compliant with the JEDEC specification JC 42.4, which defines memory module thermal sensors requirements for mobile platforms. The 2 Kb serial presence detect (SPD) I2C-compatible electrically erasable programmable memory (EEPROM) in the STTS424E02 is organized as 256 x 8 bits and is functionally identical to the industry standard M34E02.

The TS-SPD EEPROM combination provides space as well as cost savings for mobile and server platform dual inline memory modules (DIMM) manufacturers, as it is packaged in the compact 2 mm x 3 mm 8-lead DFN package which is available in two variations. The DA package has a maximum height of 0.90 mm. The DN package has an identical footprint as the DA package with a thinner maximum height of 0.80 mm. The DN package is compliant to JEDEC MO-229, variation WCED-3.

The temperature sensor includes a band gap-based temperature sensor and 10-bit analog- to-digital converter (ADC) which monitor and digitize the temperature to a resolution of up to 0.25 °C. The typical accuracies over these temperature ranges are:

±3 °C over the full temperature measurement range of –40 °C to 125 °C,

±2 °C in the +40 °C to +125 °C temperature range, and

±1 °C in the +75 °C to +95 °C temperature range.

The temperature sensor in the STTS424E02 is specified for operating at supply voltages from 2.7 V to 3.6 V. Operating at 3.3 V, the supply current is 100 µA (typ) with EEPROM in standby mode.

The on-board sigma delta ADC converts the measured temperature to a digital value that is calibrated in °C. For Fahrenheit applications, a lookup table or conversion routine is required. The STTS424E02 is factory-calibrated and requires no external components to measure temperature.

The digital temperature sensor component has user-programmable registers that provide the capabilities for DIMM temperature-sensing applications. The open drain event output pin is active when the monitoring temperature exceeds a programmable limit, or it falls above or below an alarm window. The user has the option to set the event output as a critical temperature output. This pin can be configured to operate in either a comparator mode for thermostat operation or in interrupt mode.

The 2 Kb serial EEPROM memory in the STTS424E02 has the ability to permanently lock the data in its first half (upper) 128 bytes (locations 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs with SPD. All of the information concerning the DRAM module configuration (e.g. access speed, size, and organization) can be kept write protected in the first half of the memory. The second half (lower) 128 bytes of the memory can be write protected using two different software write protection mechanisms.

By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. In the STTS424E02 the EEPROM write control (WC) is always held low. Thus, the write protection of the memory array is dependent on whether the software protection has been set.

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STTS424E02	Serial communications

2 Serial communications

The STTS424E02 has a simple 2-wire SMBus™/I2C-compatible digital serial interface which allows the user to access both the 2 Kb serial EEPROM and the data in the temperature register at any time. It communicates via the serial interface with a master controller which operates at speeds of up to 400 kHz. It also gives the user easy access to all of the STTS424E02 registers in order to customize device operation.

2.1Device type identifier (DTI) code

	The JEDEC temperature sensor and EEPROM each have their own unique I2C address,
	which ensures that there are no compatibility or data translation issues. This is due to the
	fact that each of the devices have their own 4-bit DTI code, while the remaining three bits
	are configurable. This enables the EEPROM and thermal sensors to provide their own
	individual data via their unique addresses and still not interfere with each others’ operation
	in any way. The DTI codes are:
	● '0011' for the TS, and
	● '1010' for addressing the EEPROM memory array, and
	● ‘0110’ to access the software write protection settings of the EEPROM.
Note:	The EEPROM in the STTS424E02 package has its		pin internally tied to the VSS
		WC
	(Ground) pad inside the package while the A0, A1, and A2 pins in the logic diagram (see
	Figure 1 on page 8) correspond to the chip enable pins E0, E1 and E2 of EEPROM.

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Serial communications

STTS424E02

Figure 1.

Logic diagram

VDD

SDA(1)

(1)

EVENT

SCL

A2

STTS424E02

A1

A0

VSS

AI12261

1. SDA and

are open drain.

EVENT

Table 1.

Signal names

Pin

Symbol

Description

Direction

1

A0

Serial bus address selection pin. Can be tied to VSS or VDD.

Input

2

A1

Serial bus address selection pin. Can be tied to VSS or VDD.

Input

3

A2

Serial bus address selection pin. Can be tied to VSS or VDD.

Input

4

VSS

Supply ground.

5

SDA(1)

Serial data.

Input/output

6

SCL

Serial clock.

Input

7

(1)

Event output pin. Open drain and active-low.

Output

EVENT

8

VDD

Supply power (2.7 V to 3.6 V).

1. SDA and

are open drain.

EVENT

Note:

See Section 2.2: Pin descriptions on page 10 for details.

Figure 2.

DFN8 and TDFN8 connections (top view)

A0

VDD

1

8

A1

2

7

(1)

EVENT

A2

3

6

SCL

GND

4

5

SDA(1)

AI12262

1. SDA and EVENT are open drain.

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STTS424E02	Serial communications

Figure 3. Block diagram

			8
			VDD
		Temperature
		Sensor
			Logic Control	EVENT
			Comparator	7
			Timing
		ADC
		Capability
		Register	Upper
		Configuration	Register
		Register	Lower
		Temperature	Register
		Register	Critical
			Register
2Kb SPD EEPROM		Address Pointer	Manufacturer
			ID
Software Write Protect		Register
WC	E0 E1 E2		Device ID/
			Revision
	VSS
A0				SCL
1			SMBus/I2C	6
A1
2			Interface	SDA
A2
				5
3
			VSS
			4
				AI12278a

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Serial communications	STTS424E02

2.2Pin descriptions

2.2.1A0, A1, A2

A2, A1, and A0 are selectable address pins for the 3 LSBs of the I2C interface address. They can be set to VDD or GND to provide 8 unique address selections. These pins are internally connected to the E2, E1, E0 (chip selects) of EEPROM.

2.2.2VSS (ground)

This is the reference for the power supply. It must be connected to system ground.

2.2.3SDA (open drain)

This is the serial data input/output pin.

2.2.4SCL

This is the serial clock input pin.

2.2.5EVENT (open drain)

This output pin is open drain and active-low, and functions as an alert interrupt.

2.2.6VDD (power)

This is the supply voltage pin, and ranges from +2.7 V to +3.6 V.

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STTS424E02	Temperature sensor operation

3 Temperature sensor operation

The temperature sensor continuously monitors the ambient temperature and updates the temperature data register at least eight times per second. Temperature data is latched internally by the device and may be read by software from the bus host at any time.

The SMBus/I2C slave address selection pins allow up to 8 such devices to co-exist on the same bus. This means that up to 8 memory modules can be supported, given that each module has one such slave device address slot.

After initial power-on, the configuration registers are set to the default values. The software can write to the configuration register to set bits per the bit definitions in Section 3.1: SMBus/I2C communications.

For details of operation and usage of 2 Kb SPD EEPROM, refer to Section 5: SPD EEPROM operation.

3.1SMBus/I2C communications

The registers in this device are selected by the pointer register. At power-up, the pointer register is set to “00”, which is the capability register location. The pointer register latches the last location it was set to. Each data register falls into one of three types of user accessibility:

1.Read-only

2.Write-only, and

3.WRITE/READ same address

A WRITE to this device will always include the address byte and the pointer byte. A WRITE to any register other than the pointer register, requires two data bytes.

Reading this device is achieved in one of two ways:

●If the location latched in the pointer register is correct (most of the time it is expected that the pointer register will point to one of the read temperature registers because that will be the data most frequently read), then the READ can simply consist of an address byte, followed by retrieval of the two data bytes.

●If the pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a READ.

	The data byte transfers the MSB first. At the end of a READ, this device can accept either an
	acknowledge (ACK) or no acknowledge (NoACK) status from the master. The NoACK status
	is typically used as a signal for the slave that the master has read its last byte. This device
	subsequently takes up to 125 ms to measure the temperature.
Note:	STTS424E02 does not initiate clock stretching which is an optional I2C bus feature.

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Temperature sensor operation	STTS424E02

Figure 4. SMBus/I2C write to pointer register

1

9

1

9

SCL

SDA

0
		0 1 1 A2 A1 A0 R/W					0 0	0 0 0 D2 D1 D0
Start		Address		Byte				Pointer		Byte
by					ACK					ACK
Master						by					by
				STTS424E02						STTS424E02

AI12264

Figure 5. SMBus/I2C write to pointer register, followed by a read data word

SCL

1

9

1

9

SDA

0

0

1

1

A2 A1

A0

R/W

0

0

0

0

0

D2

D1

D0

Start

Address Byte

Pointer Byte

ACK

by

ACK

Master

by

by

STTS424E02

STTS424E02

SCL

1

9

1

9

1

9

(continued)

SDA

(continued)

0

0

1

1

A2

A1

A0 R/W

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Repeat

Address Byte

Stop

MSB Data Byte

LSB Data Byte

Cond.

Start

ACK

ACK

No ACK

by

by

by

by

by

Master

Master

STTS424E02

Master

Master

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Doc ID 13448 Rev 8

STTS424E02	Temperature sensor operation

Figure 6. SMBus/I2C write to pointer register, followed by a write data word

SCL

1

9

1

9

SDA

0

0

1

1 A2

A1

A0

R/W

0

0

0

0

0

D2

D1

D0

Start

Address Byte

Pointer Byte

ACK

by

ACK

Master

by

by

STTS424E02

STTS424E02

SCL

1

9

1

9

(continued)

SDA

(continued)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Stop

MSB Data Byte

LSB Data Byte

ACK

Cond.

ACK

by

by

by

Master

STTS424E02

STTS424E02

AI14012

3.2SMBus/I2C slave sub-address decoding

The physical address for the TS is different than that used by the EEPROM. The TS physical address is binary 0 0 1 1 A2 A1 A0 RW, where A2, A1, and A0 are the three slave subaddress pins, and the LSB “RW” is the READ/WRITE flag.

The EEPROM physical address is binary 1 0 1 0 A2 A1 A0 RW for the memory array and is 0 1 1 0 A2 A1 A0 RW for permanently set write protection mode.

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Temperature sensor operation	STTS424E02

3.3SMBus/I2C AC timing consideration

In order for this device to be both SMBusand I2C-compatible, it complies to a subset of each specification. The requirements which enable this device to co-exist with devices on either an SMBus or an I2C bus include:

●The SMBus minimum clock frequency is required.

●The 300 ns SMBus data hold time (THD:DAT) is required (see Figure 7 and Table 2 on page 15.

●The SMBus timeout is maximum 50 ms (temperature sensor only).

Note:

Since the voltage levels are specified only within 3.3 V ±10%, there are no compatibility

concerns with the SMBus/I2C DC specifications.

Figure 7. SMBus/I2C timing diagram

tR

tLOW

tF

SCL

VIH

VIL

tSU:STA

tHD:STA

tBUF

tHIGH

tSU:DAT

tSU:STO

SDA

VIH

tHD:DAT

VIL

P

S

S

P

A12266

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STTS424E02			Temperature sensor operation
Table 2.	AC SMBus and I2C compatibility timings
Symbol		Parameter	DA package		DN package		Units
			Min	Max	Min	Max
tBUF		Bus free time between stop (P) and start (S) conditions	4.7	–	1.3	–	µs
tHD:STA		Hold time after (repeated) start condition. After this	4.0	–	0.6	–	µs
		period, the first clock cycle is generated.
(1)		Repeated start condition setup time	4.7	–	0.6	–	µs
tSU:STA
tHIGH		Clock high period	4.0	–	0.6	–	µs
(2)		Clock low period	4.7	–	1.3	–	µs
tLOW
tF		Clock/data fall time	–	300	–	300	ns
tR		Clock/data rise time	–	1000	–	300	ns
tSU:DAT		Data setup time	250	–	100	–	ns
tHD:DAT		Data hold time	300	–	300	–	ns
tSU:STO		Stop condition setup time	4.0	–	0.6	–	µs
t (3)		WRITE time for EEPROM	–	10	–	10	ms
W
fSCL		SMBUS/I2C clock frequency	10	100	10	400	KHz
ttimeout		Bus timeout (temperature sensor only)	25	50	25	50	ms

1.For a restart condition, or following a WRITE cycle.

2.STTS424E02 will not initiate clock stretching which is an I2C bus optional feature.

3.This parameter reflects maximum WRITE time for EEPROM.

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