ST STM32F412xE, STM32F412xG Errata sheet

STM32F412xE/xG

Errata sheet

STM32F412xE/xG device limitations

Applicability

This document applies to the part numbers of STM32F412xx devices listed in Table 1 and their variants shown in Table 2.

Section 1 gives a summary and Section 2 a description of / workaround for device

limitations, with respect to the device datasheet and reference manual [RM0402.

Table 1. Device summary

Reference Part numbers

STM32F412xx

Reference

STM32F412xx Z 0x1001

STM32F412xx C 0x3000

STM32F412xx 1 0x3000

1. Refer to the device data sheet for how to identify this code on different types of package.

2. REV_ID[15:0] bit field of DBGMCU_IDCODE register. Refer to the reference manual.

STM32F412CE, STM32F412RE, STM32F412VE, STM32F412ZE,

STM32F412CG, STM32F412RG, STM32F412VG, STM32F412ZG

Table 2. Device variants

Silicon revision codes

Device marking

(1)

REV_ID

(2)

October 2020 ES0305 Rev 9 1/25

www.st.com

Contents STM32F412xE/xG

Contents

1 Arm® 32-bit Cortex®-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . 5

1.1 Cortex-M4 interrupted loads to stack pointer can cause

erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 VDIV or VSQRT instructions might not complete correctly

when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 STM32F412xx silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Debugging Sleep/Stop mode with WFE/WFI entry . . . . . . . . . . . . . . . . . 9

2.1.2 Wakeup sequence from Standby mode when using more than

one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.3 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 10

2.1.4 MPU attribute to RTC and IWDG registers could be managed

incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.5 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 10

2.1.6 Internal noise impacting the ADC accuracy . . . . . . . . . . . . . . . . . . . . . . 10

2.1.7 Flash sector erase issue for sectors 5 to 11 . . . . . . . . . . . . . . . . . . . . . 11

2.1.8 In some specific cases, DMA2 data corruption occurs when managing

AHB and APB2 peripherals in a concurrent way . . . . . . . . . . . . . . . . . . 11

2.2 IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1 RVU and PVU flags are not reset in STOP mode . . . . . . . . . . . . . . . . . 12

2.3 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.1 SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.2 Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . 12

2.3.3 Mismatch on the “Setup time for a repeated Start condition” timing

parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.4 Data valid time (t

2.3.5 Both SDA and SCL maximum rise time (t

higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.6 Last received byte can be lost when using Reload mode

with NBYTES > 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

) violated without the OVR flag being set . . . . . 13

VD;DAT

) violated when VDD_I2C bus

2.4 FMPI2C peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.1 Wrong data sampling when data set-up time (tSU;DAT) is smaller than

one FMPI2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 SPI/I2S peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.1 Wrong CRC calculation when the polynomial is even. . . . . . . . . . . . . . 15

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STM32F412xE/xG Contents

2.5.2 BSY bit may stay high at the end of a data transfer in slave mode . . . . 15

2.5.3 Corrupted last bit of data and/or CRC, received in Master mode with

delayed SCK feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.1 Idle frame is not detected if receiver clock speed is deviated . . . . . . . . 17

2.6.2 In full duplex mode, the Parity Error (PE) flag can be cleared by

writing to the data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.3 Parity Error (PE) flag is not set when receiving in Mute mode

using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.4 Break frame is transmitted regardless of nCTS input line status . . . . . . 18

2.6.5 nRTS signal abnormally driven low after a protocol violation . . . . . . . . 18

2.6.6 Start bit detected too soon when sampling for NACK signal

from the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6.7 Break request can prevent the Transmission Complete flag (TC)

from being set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6.8 Guard time is not respected when data are sent on TXE events . . . . . . 19

2.6.9 nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7 bxCAN limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7.1 bxCAN time triggered communication mode not supported . . . . . . . . . 20

2.8 FSMC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.8.1 Dummy read cycles inserted when reading synchronous memories . . . 20

2.9 SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.9.1 Wrong CCRCFAIL status after a response without CRC is received . . . 20

2.9.2 No underrun detection with wrong data transmission . . . . . . . . . . . . . . 21

2.10 ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.10.1 ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 21

2.11 QuadSPI limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.11.1 First nibble of data is not written after dummy phase . . . . . . . . . . . . . . 21

2.11.2 Wrong data can be read in memory-mapped after an indirect mode

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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List of tables STM32F412xE/xG

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 3. Cortex-M4 core limitations and impact on microcontroller behavior . . . . . . . . . . . . . . . . . . . 5

Table 4. Summary of silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. Maximum allowable APB frequency at 30 pF load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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STM32F412xE/xG Arm® 32-bit Cortex®-M4 with FPU limitations

1 Arm® 32-bit Cortex®-M4 with FPU limitations

An errata notice of the STM32F412xx core is available from http://infocenter.arm.com.

All the described limitations are minor and related to the revision r0p1-v1 of the Cortex-M4 core. Table 3 summarizes these limitations and their implications on the behavior of STM32F412xx devices.

Table 3. Cortex-M4 core limitations and impact on microcontroller behavior

Arm ID

752770 Cat B

776924 Cat B

Arm

1.1 Cortex-M4 interrupted loads to stack pointer can cause erroneous behavior

Description

An interrupt occurring during the data-phase of a single word load to the stack pointer (SP/R13) can cause an erroneous behavior of the device. In addition, returning from the interrupt results in the load instruction being executed an additional time.

For all the instructions performing an update of the base register, the base register is erroneously updated on each execution, resulting in the stack pointer being loaded from an incorrect memory location.

The instructions affected by this limitation are the following:

• LDR SP, [Rn],#imm

• LDR SP, [Rn,#imm]!

• LDR SP, [Rn,#imm]

• LDR SP, [Rn]

• LDR SP, [Rn,Rm]

Workaround

As of today, no compiler generates these particular instructions. This limitation can only occur with hand-written assembly code.

Both limitations can be solved by replacing the direct load to the stack pointer by an intermediate load to a general-purpose register followed by a move to the stack pointer.

Example:

Replace LDR SP, [R0] by

LDR R2,[R0]

MOV SP,R2

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Arm® 32-bit Cortex®-M4 with FPU limitations STM32F412xE/xG

1.2 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used

Description

On Cortex-M4 with FPU core, 14 cycles are required to execute a VDIV or VSQRT instruction.

This limitation is present when the following conditions are met:

• A VDIV or VSQRT is executed

• The destination register for VDIV or VSQRT is one of s0 - s15

• An interrupt occurs and is taken

• The ISR being executed does not contain a floating point instruction

• 14 cycles after the VDIV or VSQRT is executed, an interrupt return is executed

In this case, if there are only one or two instructions inside the interrupt service routine, then the VDIV or VQSRT instruction does not complete correctly and the register bank and FPSCR are not updated, meaning that these registers hold incorrect out-of-date data.

Workaround

Two workarounds are applicable:

• Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the

FPCCR at address 0xE000EF34).

• Ensure that every ISR contains more than 2 instructions in addition to the exception

return instruction.

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STM32F412xE/xG STM32F412xx silicon limitations

2 STM32F412xx silicon limitations

Table 4 gives quick references to all documented limitations.

Legend for Table 4: A = workaround available; N = no workaround available; P = partial workaround available, ‘-’ and grayed = fixed.

Section 2.1.1: Debugging Sleep/Stop mode with WFE/WFI entry AA

Section 2.1.2: Wakeup sequence from Standby mode when using more than one wakeup source

Table 4. Summary of silicon limitations

Links to silicon limitations Revision Z

Revision C

and

Revision 1

Section 2.1: System limitations

Section 2.2: IWDG peripheral limitation

Section 2.3: I2C peripheral limitations

Section 2.1.3: Full JTAG configuration without NJTRST pin cannot be used

Section 2.1.4: MPU attribute to RTC and IWDG registers could be managed incorrectly

Section 2.1.5: Delay after an RCC peripheral clock enabling AA

Section 2.1.6: Internal noise impacting the ADC accuracy AA

Section 2.1.7: Flash sector erase issue for sectors 5 to 11 A

Section 2.1.8: In some specific cases, DMA2 data corruption occurs when managing AHB and APB2 peripherals in a concurrent

way

Section 2.2.1: RVU and PVU flags are not reset in STOP mode AA

Section 2.3.1: SMBus standard not fully supported AA

Section 2.3.2: Start cannot be generated after a misplaced Stop AA

Section 2.3.3: Mismatch on the “Setup time for a repeated Start condition” timing parameter

Section 2.3.4: Data valid time (t

) violated without the OVR

VD;DAT

flag being set

Section 2.3.5: Both SDA and SCL maximum rise time (t

) violated

when VDD_I2C bus higher than ((VDD+0.3) / 0.7) V

Section 2.3.6: Last received byte can be lost when using Reload mode with NBYTES > 1

Section 2.4: FMPI2C peripheral limitation

Section 2.4.1: Wrong data sampling when data set-up time (tSU;DAT) is smaller than one FMPI2CCLK period

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STM32F412xx silicon limitations STM32F412xE/xG

Table 4. Summary of silicon limitations (continued)

Revision C

Links to silicon limitations Revision Z

and

Revision 1

Section 2.5: SPI/I2S peripheral limitation

Section 2.6: USART peripheral limitations

Section 2.5.1: Wrong CRC calculation when the polynomial is even.

Section 2.5.2: BSY bit may stay high at the end of a data transfer in slave mode

Section 2.5.3: Corrupted last bit of data and/or CRC, received in Master mode with delayed SCK feedback

Section 2.6.1: Idle frame is not detected if receiver clock speed is deviated

Section 2.6.2: In full duplex mode, the Parity Error (PE) flag can be cleared by writing to the data register

Section 2.6.3: Parity Error (PE) flag is not set when receiving in Mute mode using address mark detection

Section 2.6.4: Break frame is transmitted regardless of nCTS input line status

Section 2.6.5: nRTS signal abnormally driven low after a protocol violation

Section 2.6.6: Start bit detected too soon when sampling for NACK signal from the smartcard

Section 2.6.7: Break request can prevent the Transmission Complete flag (TC) from being set

Section 2.6.8: Guard time is not respected when data are sent on TXE events

Section 2.6.9: nRTS is active while RE or UE = 0 AA

Section 2.7: bxCAN limitation

Section 2.8: FSMC peripheral limitation

Section 2.9: SDIO peripheral limitations

Section 2.10: ADC peripheral limitations

Section 2.11: QuadSPI limitations

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Section 2.7.1: bxCAN time triggered communication mode not supported

Section 2.8.1: Dummy read cycles inserted when reading synchronous memories

Section 2.9.1: Wrong CCRCFAIL status after a response without CRC is received

Section 2.9.2: No underrun detection with wrong data transmission AA

Section 2.10.1: ADC sequencer modification during conversion AA

Section 2.11.1: First nibble of data is not written after dummy phase AA

Section 2.11.2: Wrong data can be read in memory-mapped after an indirect mode operation

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