ST STBB2 User Manual

800 mA 2.5 MHz, high efficiency dual mode

Features

■ Operating input voltage range from 2.3 V to

5.5 V

■ ± 2% output voltage tolerance over process

and temperature variations

■ Bypass power save function

■ Selectable output voltage with dedicated VSEL

■ Very fast line and load transients

■ 2.5 MHz switching frequency

■ Power save mode (PS) at light load

■ Typical efficiency higher than 90%

■ 50 µA max. quiescent current

■ Flip Chip 20 bumps 0.4 mm pitch 2.1 x 1.8 mm

Applications

■ Memory card supply

■ Cellular phones

Description

STBB2

buck-boost DC-DC converter

Datasheet − production data

Flip Chip 20 (2.1x1.8 mm)

selection between auto mode and forced PWM mode, therefore benefiting from either lower power consumption or best dynamic performance. The bypass function allows battery power saving. In this operating mode the highside switches are turned on so that the output voltage is equal to the input voltage; in this condition the current consumption is reduced to a maximum of 5 µA. The device includes also softstart control, thermal shutdown, and current limit. The STBB2 is packaged in Flip Chip 20 bumps with 0.4 mm pitch.

The STBB2 is a fixed frequency, high efficiency, buck-boost DC-DC converter able to provide output voltages from 1.2 V to 4.5 V starting from input voltage of 2.3 V to 5.5 V. The device can operate with input voltages higher than, equal to, or lower than the output voltage making the product suitable for single Li-Ion, multi-cell alkaline or NiMH applications where the output voltage is within the battery voltage range. The low-R

N-channel and P-channel MOSFET

DSon

switches are integrated and contribute to achieving high efficiency. The MODE pin allows

Table 1. Device summary

Order codes Markings Packaging Output voltages

STBB2JAD-R BB2 Tape and reel Adjustable

STBB2J29-R B229 Tape and reel 2.9 V / 3.4 V

July 2012 Doc ID 022745 Rev 4 1/24

This is information on a product in full production.

www.st.com

24

Contents STBB2

Contents

1 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1 Dual mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.2 Enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.3 Bypass operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.4 VSEL pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.5 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5.1 Soft-start and short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5.2 Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.5.3 Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.1 Programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.3 Input and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.4 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.5 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.6 Thermal consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/24 Doc ID 022745 Rev 4

STBB2 Application schematic

1 Application schematic

Figure 1. Application schematic for fixed version

L1

SW2SW1

PGND GND

L1

SW2SW1

PGND GND

VOUT

FB

C3 C4

FB

C4

C3

R1

R2

VBAT

C1

C2

VIN

VINA

VINA1

MODE

EN

BP

VSEL

Figure 2. Application schematic for adjustable version

VBAT

C1

C2

VIN

VINA

VINA1

MODE

EN

BP

VSEL

Table 2. Typical external components

Component Manufacturer Part number Value Size

Murata GRM188R60J106M

C1

10 µF 0603

TDK-EPC C1608X5R0J106M

C2 Murata GRM188R61C105K 1 µF 0603

Murata GRM188R60J106M

C3, C4

10 µF 0603

TDK-EPC C1608X5R0J106M

Murata LQH3NPN1R0NM0

(1)

L

Coilcraft LPS3015-102ML 3.0 x 3.0 x 1.5 mm

1.0 µH

3 x 3 x 1.4 mm

TDK-EPC VLS252010ET1R0N 2.5 x 2 x 1 mm

R1 Depending on the output voltage, 0 Ω for fixed output version

R2

1. Inductor used for the maximum power capability. Optimized choice can be done according to the application conditions (see

Depending on the output voltage, not used for fixed output

version

Section 8

).

Note: All the above components refer to a typical application. Operation of the device is not limited

to the choice of these external components.

Doc ID 022745 Rev 4 3/24

Block diagram STBB2

2 Block diagram

Figure 3. Block diagram adjustable

SW1

SW2

VIN

VINA1

+

-

Σ

FB

-

EA

+

VREF and

Soft start

GND

Figure 4. Block diagram fixed

VIN

OSC

VSUM

Burst

Control 1

Level shift

Burst

Control 2

+

COMP 1

-

SW1

Driv er

LOGIC

CONTROL

+

COMP 2

VSUM

Gate

DMD

VSEL

VOUT

+

-

DMD

UVLO

SHUT

DOWN

OSC

DEVICE

CONTROL

BP

SW2

OTP

OSC

VINA

EN

MODE

BP

VSEL

AM10455v1

VOUT

VINA1

+

VREF and

Soft start

-

Σ

OSC

VSUM

-

EA

+

Burst

Contr ol 1

Level shift

Burst

Control 2

+

COMP 1

-

FB

VSEL

BP

GND

4/24 Doc ID 022745 Rev 4

Gate Driver

LOGIC

CONTROL

+

COMP 2

VSUM

DMD

VSEL

+

-

DMD

UVLO

SHUT

DOWN

OSC

DEVICE

CONTROL

BP

OTP

OSC

VINA

EN

MODE

BP

VSEL

AM10456v1

STBB2 Absolute maximum ratings

3 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VIN, VINA, VINA1 Supply voltage -0.3 to 7.0 V

SW1,SW2 Switching nodes -0.3 to 7.0 V

VOUT Output voltage -0.3 to 7.0 V

MODE, EN, BP, VSEL Logic pins -0.3 to 7.0 V

FB Feedback pin -0.3 to 6.0 V

ESD

T

AMB

T

STG

J

Human body model ± 2000

V

Charged device model ± 500

Operating ambient temperature -40 to 85 °C

Maximum operating junction temperature 150 °C

Storage temperature -65 to 150 °C

Note: Absolute maximum ratings are those values beyond which damage to the device may occur.

Functional operation under these conditions is not implied.

Table 4. Thermal data

Symbol Parameter Value Unit

R

thJA

1. PCB condition: JEDEC standard 2s2P(4-layer).

Thermal resistance junction-ambient 80

(1)

°C/W

Doc ID 022745 Rev 4 5/24

Pin configuration STBB2

4 Pin configuration

Figure 5. Pin connections (top view)

A4

[EN]

A3

[VINA]

A2

[VIN]

A1

[VIN]

B4

[BP]

B3

[VINA1]

B2

[SW1]

B1

[SW1]

C4

[MODE]

C3

[GND]

C2

[PGND]

C1

[PGND]

D4

[VSEL]

D3

[GND]

D2

[SW2]

D1

[SW2]

E4

[GND]

E3

[FB]

E2

[VO]

E1

[VO]

A1

[VIN]

A2

[VIN]

A3

[VINA]

A4

[EN]

TOP VIEW

Table 5. Pin description

Pin name Pin n° Description

VOUT E1, E2 Output voltage

SW2 D1, D2

Switch pin - internal switches C and D are connected to this pin. Connect inductor between SW1 to SW2

PGND C1, C2 Power ground

SW1 B1, B2

Switch Pin - internal switches A and B are connected to this pin. Connect inductor between SW1 and SW2

B1

[SW1]

B2

[SW1]

B3

[VINA1]

B4

[BP]

[MODE]

BOTTOM VIEW

C1

[PGND]

C2

[PGND]

C3

[GND]

C4

D1

[SW2]

D2

[SW2]

D3

[GND]

D4

[VSEL]

E1

[VO]

E2

[VO]

E3

[FB]

E4

[GND]

EN A4

Enable pin. Connect this pin to GND or a voltage lower than 0.4 V to shut down the IC. A voltage higher than 1.2 V is required to enable the IC. Do not leave this pin floating.

When in normal operation, the MODE pin selects between auto mode and forced PWM

MODE C4

mode. If the MODE pin is low, the STBB2 automatically switches between pulse-skipping and standard PWM according to the load level. If the MODE pin is pulled high, the STBB2 works always in PWM mode. Do not leave this pin floating.

VINA A3 Supply voltage for control stage.

A 100 Ω resistor is internally connected between VIN and VINA1. Connecting a 1 µF

VINA1 B3

capacitor between VINA1 and GND, an input filter is realized suitable to provide a clean supply to VINA.

VIN A1, A2

Power input voltage. Connect a ceramic bypass capacitor (10 µF min.) between this pin and PGND

GND C3, D3, E4 Signal ground

FB E3 Feedback voltage. For the fixed version this pin must be connected to VOUT.

Bypass mode selection.

BP B4

When EN is high, connecting this pin to a voltage higher than 1.2 V, the device works in bypass mode. A voltage lower than 0.4 V is required to disable bypass mode. In bypass mode VIN is shorted to VOUT through the internal switches. Do not leave this pin floating.

VSEL D4

Selection of output voltage for fixed versions (0 V

= 2.9 V / 1 V

OUT

This feature is not present in the adjustable version where the VSEL pin must be

OUT

= 3.4 V).

connected to VINA. Do not leave this pin floating.

6/24 Doc ID 022745 Rev 4

STBB2 Electrical characteristics

5 Electrical characteristics

- 40 °C < TA < 85 °C, VIN = 3.6 V; V

= 25 °C, unless otherwise specified.

T

A

Table 6. Electrical characteristics

= 3.4 V, VEN = VIN, VBP = 0 V; typical values are at

OUT

Symbol Parameter Test conditions Min. Typ. Max. Unit

General section

V

UVLO

f

I

OUT

I

PS-PWM

Operating power input voltage

IN

range

Shutdown mode V

Pulse-skipping I

Iq

PWM mode I

Bypass mode

Undervoltage lockout threshold

Switching frequency 2 2.5 3 MHz

SW

Continuous output current

Switch current limitation 2.3 2.5 2.7 A

PK

(1)

PS to PWM transition V

= 0 V 0.5 2 µA

EN

= 0 A, V

OUT

= 0 A, V

OUT

V

= VIN; I

BP

V

= 0, V

MODE

rising; V

V

IN

I

= 100 mA

OUT

VIN falling; V I

= 100 mA

OUT

2.5 V ≤ V

IN

= 3.6 V 100

= 0 35 50 µA

MODE

= V

MODE

OUT

IN

MODE

IN

= 0 A;

= 2.3 to 5.5 V

= V

IN;

= V

IN;

≤ 5.5 V 800 mA

2.3 5.5 V

810mA

510µA

1.6 2.2

1.5 2

PWM to PS transition 80

V

mA

Efficiency

η

(V

IN

ON

Tu r n- on t im e

T

Thermal shutdown 150 °C

T

SHDN

Hysteresis 20 °C

Output voltage

V

Output voltage range 1.2 4.5 V

OUT

Output voltage accuracy in PWM mode

%V

OUT

Output voltage accuracy in power save mode

= 3.6 V; V

(2)

OUT

= 3.4 V)

I

=1 0 mA (PS mode) 85

OUT

I

= 50 mA (PS mode) 90

OUT

= 150 mA (PWM) 90

I

OUT

I

= 250 mA (PWM) 91

OUT

I

= 500 mA (PWM) 92

OUT

= 800 mA (PWM) 92

I

OUT

VEN from low to high;

= 10 mA

I

OUT

V

= 2.5 to 5.5 V,

IN

= VIN V

V

MODE

V

= 2.5 to 5.5 V, V

IN

V

= GND/VIN suitable output

SEL

= GND/V

SEL

MODE

IN

= GND

-1.5 +1.5 %

260 300 µs

-3 +3 %

%

current to keep PS operation

Doc ID 022745 Rev 4 7/24

Electrical characteristics STBB2

Table 6. Electrical characteristics (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

%V

V

OPP-PS

I

LKFB

Feedback voltage accuracy Adj version 493 500 507 mV

FB

Maximum load regulation I

OUT

Peak-to-peak ripple in PS mode I

FB pin leakage current V

= from 10 mA to 800 mA ±0.5 %

LOAD

= 100 mA 100 mV

OUT

= 5.5 V 9 µA

FB

Logic inputs

V

I

LK-I

Low-level input voltage (EN,

IL

MODE, BP, VSEL pins)

High-level input voltage (EN,

IH

MODE, BP, VSEL pins)

Input leakage current (EN, MODE, BP, VSEL pins)

V

EN=VMODE=VBP=VSEL

1.2 V

= 5.5 V 0.01 1 µA

0.4 V

Power switches

P-channel on-resistance 130 350 mΩ

R

DSON

I

LKG-P

I

LKG-N

1. Not tested in production. This value is guaranteed by correlation with rds_on, peak current limit and operating input voltage.

2. Not tested in production.

N-channel on-resistance 130 350 mΩ

P-channel leakage current V

N-channel leakage current V

= V

IN

SW1

OUT

= V

= 5.5 V; V

SW2

= 0 1 µA

EN

= 0 1 µA

EN

8/24 Doc ID 022745 Rev 4