ROM with read-out protection capability. InApplication Programming and In-Circuit Pro
gramming for HDFlash devices
– 1.5 to 2K RAM
– HDFlash endurance: 100 cycles, data reten-
tion 40 years at 85°C
■ Clock, Reset and Supply Management
– Low power crystal/ceramic resonator oscilla-
tors and bypass for external clock
– PLL for 2x frequency multiplication
– 5 power saving modes: Halt, Auto Wake Up
From Halt, Active Halt, Wait and Slow
■ Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– TLI top level interrupt (on 64-pin devices)
– Up to 21 external interrupt lines (on 4 vectors)
■ Up to 48 I/O Ports
– Up to 48 multifunctional bidirectional I/O lines
– Up to 36 alternate function lines
– Up to 6 high sink outputs
■ 5 Timers
– 16-bit timer with 2 input captures, 2 output
compares, external clock input, PWM and
pulse generator modes
– 8-bit timer with 1 or 2 input captures, 1 or 2
output compares, PWM and pulse generator
modes
– 8-bit PWM auto-reload timer with 1 or 2 input
captures, 2 or 4 independent PWM output
channels, output compare and time base in
terrupt, external clock with event detector
ST72361
8-bit MCU with Flash or ROM,
™
-
– Main clock controller with real-time base and
clock output
– Window watchdog timer
■ Up to 3 Communications Interfaces
– SPI synchronous serial interface
– Master/slave LINSCI™ asynchronous serial
interface
– Master-only LINSCI™ asynchronous serial in-
terface
■ Analog Peripheral (Low Current Coupling)
– 10-bit A/D converter with up to 16 inputs
– Up to 9 robust ports (low current coupling)
■ Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
-
– 8 x 8 unsigned multiply instruction
■ Development Tools
– Full hardware/software development package
Table 1. Device Summary
Features
Program memory - bytes60K 48K 32K
RAM (stack) - bytes2K (256)2K (256)1.5K (256)
Operating Supply4.5V to 5.5 V
CPU FrequencyExternal Resonator Osc. w/ PLLx2/8 MHz
Max. Temp. Range-40°C to +125°C
PackagesLQFP64 10x10mm (AR), LQFP44 10x10mm (J), LQFP32 7x7mm (K)
On some devices only (see Device Summary on page 1)
TLI
1
WATCHDOG
WINDOW
(1.5 - 2 Kbytes)
1 DESCRIPTION
The ST72361 devices are members of the ST7 microcontroller family designed for mid-range applications with LIN (Local Interconnect Network) interface.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc
tion set and are available with Flash or ROM program memory. The ST7 family architecture offers
both power and flexibility to software developers,
enabling the design of highly efficient and compact
application code.
Figure 1. Device Block Diagram
The on-chip peripherals include an A/D converter,
a PWM Autoreload timer, 2 general purpose tim
ers, 2 asynchronous serial interfaces, and an SPI
interface.
For power economy, microcontroller can switch
-
dynamically into WAIT, SLOW, Active-Halt, Auto
Wake-up from HALT (AWU) or HALT mode when
the application is in idle or stand-by state.
Typical applications are consumer, home, office
and industrial products.
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
T16_ICAP1 can be moved to PD4
Figure 4. LQFP 32-Pin Package Pinout
ST72361
For external pin connection guidelines, refer to “ELECTRICAL CHARACTERISTICS” on page 178.
7/225
ST72361
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to “ELECTRICAL CHARACTERISTICS” on page 178.
Legend / Abbreviations for Table 2:
Type: I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger
TT= TTL 0.8V / 2V with Schmitt trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:float = floating, wpu = weak pull-up, int = interrupt1), ana = analog, RB = robust
– Output: OD = open drain, PP = push-pull
Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 2. Device Pin Description
Pin n°
Pin Name
LQFP64
LQFP44
LQFP32
111OSC1
222OSC2
3)
3)
3--PA0 / ARTIC1I/O C
433PA1 / PWM0I/O C
LevelPort
Type
Input
Output
float
I
InputOutput
wpu
int
ana
OD
Main
function
(after
reset)
PP
Alternate function
External clock input or Resonator oscillator inverter input
Flash programming voltage. Must be
tied low in user mode.
SPI Slave
Select
ADC Analog
Input 6
LINSCI1 Receive Data input
LINSCI1 Transmit Data
output
LINSCI2 Serial Clock Output
9/225
ST72361
Pin n°
Pin Name
LQFP64
LQFP44
LQFP32
54 36 26 PD4 / SCI2_RDII/O C
55 37 27 V
56 38 28 V
57 39 29 V
58 40 30 V
SSA
SS_0
DDA
DD_0
59 41 31 PD5 / SCI2_TDOI/O C
60 42 32 RESETI/O C
61 43-PD6 / AIN10I/O C
62 44-PD7 / AIN11I/O C
63--PF6I/O T
64--PF7I/O T
LevelPort
InputOutput
Type
Input
Output
float
T
Xei3XXPort D4
wpu
int
ana
OD
Main
function
(after
reset)
PP
Alternate function
LINSCI2 Receive Data input
SAnalog Ground Voltage
SDigital Ground Voltage
IAnalog Reference Voltage for ADC
SDigital Main Supply Voltage
T
T
T
T
T
T
XXXXPort D5
Top priority non maskable interrupt.
Xei3XXXPort D6 ADC Analog Input 10
Xei3 XXXPort D7 ADC Analog Input 11
XXXXPort F6
XXXXPort F7
LINSCI2 Transmit Data
output
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is
merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating
interrupt input.
2. Input mode can be used for general purpose I/O, output mode cannot be used.
3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section
6 and Section 12.5 "CLOCK AND TIMING CHARACTERISTICS" for more details.
4. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration
after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
10/225
3 REGISTER AND MEMORY MAP
0000h
RAM
Program Memory
(60K, 48K, 32K, 16K)
Interrupt & Reset Vectors
HW Registers
0080h
007Fh
0FFFh
(see Table 3)
1000h
FFDFh
FFE0h
FFFFh
(see Table 9)
0880h
Reserved
087Fh
Short Addressing
RAM (zero page)
256 bytes Stack
16-bit Addressing
RAM
0100h
01FFh
0080h
0200h
00FFh
1000h
32 Kbytes
60 Kbytes
FFDFh
8000h
or 087Fh
16 Kbytes
C000h
48 Kbytes
4000h
(2048/1536 bytes)
067Fh
ST72361
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.
The available memory locations consist of 128
bytes of register locations, up to 2 Kbytes of RAM
and up to 60 Kbytes of user program memory.
Figure 5. Memory Map
The RAM space includes up to 256 bytes for the
stack from 0100h to 01FFh.The highest address
bytes contain the user reset and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the
device.
Table 3. Hardware Register Map
AddressBlock
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
Port A
Port B
Port C
Port D
Port E
Register
Label
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Reset
Status
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
1)
00h
00h
00h
Remarks
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
2)
R/W
11/225
ST72361
AddressBlock
000Fh
0010h
Port F
0011h
Register
Label
PFDR
PFDDR
PFOR
Register Name
Port F Data Register
Port F Data Direction Register
Port F Option Register
Reset
Status
1)
00h
00h
00h
0012h
to
Reserved Area (15 bytes)
0020h
0021h
0022h
0023h
SPI
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
SCI2 Status Register
SCI2 Data Register
SCI2 Baud Rate Register
SCI2 Control Register 1
SCI2 Control Register 2
SCI2 Control Register 3
SCI2 Extended Receive Prescaler Register
SCI2 Extended Transmit Prescaler Register
Reserved area (24 bytes)
C0h
xxh
00h
xxh
00h
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Legend: x = undefined, R/W = read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values
of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
13/225
ST72361
4 Kbytes
4 Kbytes
2Kbytes
SECTOR 1
SECTOR 0
16 Kbytes
SECTOR 2
8K16K32K60K
FLASH
FFFFh
EFFFh
DFFFh
3FFFh
7FFFh
1000h
24 Kbytes
MEMORY SIZE
8 Kbytes40 Kbytes
52 Kbytes
9FFFh
BFFFh
D7FFh
4K10K24K48K
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu
al sectors and programmed on a Byte-by-Byte basis using an external VPP supply.
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 MAIN FEATURES
■ 3 Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be pro
-
grammed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro
-
grammed or erased without removing the device from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be pro
-
grammed or erased without removing the device from the application board and while the
application is running.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection
■ Register Access Security System (RASS) to
prevent accidental programming or erasing
4.3 STRUCTURE
The Flash memory is organised in sectors and can
be used for both code and data storage.
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and in
terrupt vectors are located in Sector 0 (F000hFFFFh).
Table 4. Sectors available in Flash devices
Flash Size (bytes)Available Sectors
4KSector 0
8KSectors 0,1
> 8KSectors 0,1, 2
4.3.1 Read-out Protection
Read-out protection, when selected, provides a
protection against Program Memory content ex
traction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcon
troller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
Read-out protection selection depends on the device type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
Figure 6. Memory Map and Sector Address
14/225
FLASH PROGRAM MEMORY (Cont’d)
ICC CONNECTOR
ICCDATA
ICCCLK
RESET
V
DD
HE10 CONNECTOR TYPE
APPLICATION
POWER SUPPLY
1
246810
975 3
PROGRAMMING TOOL
ICC CONNECTOR
APPLICATION BOARD
ICC Cable
(See Note 3)
10kΩ
V
SS
ICCSEL/VPP
ST7
C
L2
C
L1
OSC1
OSC2
OPTIONAL
See Note 1
See Note 2
APPLICATION
RESET SOURCE
APPLICATION
I/O
(See Note 4)
ST72361
4.4 ICC INTERFACE
ICC (In-Circuit Communication) needs a minimum
of four and up to six pins to be connected to the
programming tool (see Figure 7). These pins are:
– RESET: device reset
–VSS: device power supply ground
Figure 7. Typical ICC Interface
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/VPP: programming voltage
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
–VDD: application board power supply (see Fig-
ure 7, Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de
vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val
ues.
2. During the ICC session, the programming tool
must control the
flicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli
cation RESET circuit in this case. When using a
classical RC network with R
RESET pin. This can lead to con-
> 1K or a reset man-
agement IC with open drain output and pull-up
resistor
> 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program
ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2
grounded in this case.
-
15/225
ST72361
FLASH PROGRAM MEMORY (Cont’d)
4.5 ICP (IN-CIRCUIT PROGRAMMING)
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom
-
ized (number of bytes to program, program locations, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe
-
cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap
-
plication board (see Figure 7). For more details on
the pin locations, refer to the device pinout de
-
scription.
4.6 IAP (IN-APPLICATION PROGRAMMING)
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us
-
er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI or
other type of serial interface and program it in the
Flash. IAP mode can be used to program any of
the Flash sectors except Sector 0, which is write/
erase protected to allow recovery in case errors
occur during the programming operation.
4.7 RELATED DOCUMENTATION
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Refer-
ence Manual and to the ST7 ICC Protocol Reference Manual.
4.8 REGISTER DESCRIPTION
FLASH CONTROL/STATUS REGISTER (FCSR)
Read / Write
Reset Value: 0000 0000 (00h)
70
00000000
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
Table 5. Flash Control/Status Register Address and Reset Value
Address
(Hex.)
0024h
16/225
Register
Label
FCSR
Reset Value00000000
76543210
5 CENTRAL PROCESSING UNIT
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER
70
1C1I1HI0NZ
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
70
70
0
7
158
PCH
PCL
15
8
70
RESET VALUE = STACK HIGHER ADDRESS
RESET VALUE =
1X11X1XX
RESET VALUE = XXh
RESET VALUE = XXh
RESET VALUE = XXh
X = Undefined Value
ST72361
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
addressing mode)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
Figure 8. CPU Registers
5.3 CPU REGISTERS
The six CPU registers shown in Figure 8 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol
lowing instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
-
17/225
ST72361
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
70
11I1HI0NZ
The 8-bit Condition Code register contains the interrupt masksand four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in
structions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re
sult 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
C
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruc
-
tion (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack
higher address.
Figure 9. Stack Manipulation Example
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in
-
struction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with
out indicating the stack overflow. The previously
stored information is then overwritten and there
fore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 9.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
19/225
ST72361
0
1
PLL OPTION BIT
PLL x 2
f
OSC2
/ 2
f
OSC
LOW VOLTAGE
DETECTOR
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
MULTI-
OSCILLATOR
(MO)
OSC1
RESET
V
SS
V
DD
RESET SEQUENCE
MANAGER
(RSM)
OSC2
MAIN CLOCK
AVD Interrupt Request
CONTROLLER
PLL
SYSTEM INTEGRITY MANAGEMENT
WATCHDOG
SICSR
TIMER (WDG)
WITH REALTIME
CLOCK (MCC/RTC)
AVD AVD
LVD
RF
IE
WDG
RF
f
OSC
f
OSC2
(option)
0
0
F
f
CPU
00
8-BIT TIMER
/ 8000
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example, in case of a power brown-out), and re
ducing the number of external components. An
overview is shown in
Figure 11.
For more details, refer to dedicated parametric
section.
Main features
■ Optional PLL for multiplying the frequency by 2
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
– 4 Crystal/Ceramic resonator oscillators
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
Figure 11. Clock, Reset and Supply Block Diagram
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
OSC2
of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
OSC2
= f
OSC
/2.
Caution: The PLL is not recommended for applications where timing accuracy is required. See
“PLL Characteristics” on page 187.
Figure 10. PLL Block Diagram
20/225
6.2 MULTI-OSCILLATOR (MO)
OSC1OSC2
EXTERNAL
ST7
SOURCE
OSC1OSC2
LOAD
CAPACITORS
ST7
C
L2
C
L1
ST72361
The main clock of the ST7 can be generated by
two different source types coming from the multioscillator block:
■ an external source
■ a crystal or ceramic resonator oscillator
Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in
Table 6. Refer to the
electrical characteristics section for more details.
Caution: The OSC1 and/or OSC2 pins must not
be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if
the OSC1 and/or OSC2 pins are left unconnected,
the ST7 main oscillator may start and, in this con
figuration, could generate an f
in excess of the allowed maximum (>
clock frequency
OSC
16 MHz),
-
putting the ST7 in an unsafe/undefined state. The
product behavior must therefore be considered
undefined when the OSC pins are left unconnect
-
ed.
External Clock Source
In external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of
the ST7. The selection within a list of five oscilla
tors with different frequency ranges must be done
by option byte in order to reduce consumption (re
fer to Section 14.1 on page 210 for more details on
the frequency ranges). The resonator and the load
capacitors must be placed as close as possible to
the oscillator pins in order to minimize output dis
tortion and start-up stabilization time. The loading
capacitance values must be adjusted according to
the selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.
Table 6. ST7 Clock Sources
Hardware Configuration
External ClockCrystal/Ceramic Resonators
21/225
ST72361
RESET
Active Phase
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
RESET
R
ON
V
DD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
Filter
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 2:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of three
phases as shown in Figure 1:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (selected by
option byte)
■ RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilize and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application.
The RESET vector fetch phase duration is two
clock cycles.
Figure 12. RESET Sequence Phases
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac
weak pull-up resistor.
ON
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
order to be recognized (see Figure 3). This detec
in
tion is asynchronous and therefore the MCU can
enter reset state even in HALT mode.
Figure 13. Reset Block Diagram
22/225
RESET SEQUENCE MANAGER (Cont’d)
V
DD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
V
IT+(LVD)
V
IT-(LVD)
t
h(RSTL)in
RUN
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUNRUN
RESET
RESET
SOURCE
EXTERNAL
RESET
LVD
RESET
WATCHDOG
RESET
INTERNAL RESET (256 or 4096 T
CPU
)
VECTOR FETCH
ACTIVE
PHASE
ACTIVE
PHASE
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris
-
tics section.
6.3.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
is over the minimum
DD
frequency.
OSC
A proper reset signal for a slow rising VDD supply
can generally be provided by an external RC net
-
work connected to the RESET pin.
Figure 14. RESET Sequences
ST72361
6.3.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET pin acts as an output that is
< V
pulled low when V
< V
V
DD
(falling edge) as shown in Figure 3.
IT-
DD
The LVD filters spikes on V
avoid parasitic resets.
6.3.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 3.
Starting from the Watchdog counter underflow, the
device
low during at least t
RESET pin acts as an output that is pulled
w(RSTL)out
(rising edge) or
IT+
larger than t
DD
g(VDD)
.
to
23/225
ST72361
V
DD
V
IT+
(LVD)
RESET
V
IT-
(LVD)
V
hys
6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
the Low Voltage Detector (LVD) and Auxiliary Volt
age Detector (AVD) functions. It is managed by
the SICSR register.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is
below a V
IT-(LVD)
reference value. This means that
it secures the power-up as well as the power-down
keeping the ST7 in reset.
The V
IT-(LVD)
lower than the V
reference value for a voltage drop is
IT+(LVD)
reference value for poweron in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup
-
ply (hysteresis).
The LVD Reset circuitry generates a reset when
is below:
V
DD
–V
–V
IT+(LVD)
IT-(LVD)
when VDD is rising
when VDD is falling
The LVD function is illustrated in Figure 15.
Figure 15. Low Voltage Detector vs Reset
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above V
IT-(LVD)
, the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be se-
lected by option byte.
It is recommended to make sure that the V
DD
supply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func
tions properly.
-
24/225
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
V
DD
V
IT+(AVD)
V
IT-(AVD)
AVDF bit00RESET VALUE
IF AVDIE bit = 1
V
hyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS
INTERRUPT PROCESS
V
IT+(LVD)
V
IT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
1
1
t
rv
VOLTAGE RISE TIME
6.4.2 AuxiliaryVoltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a V
V
IT+(AVD)
ply. The V
age is lower than the V
reference value and the VDD main sup-
IT-(AVD)
reference value for falling volt-
IT+(AVD)
reference value for
IT-(AVD)
and
rising voltage in order to avoid parasitic detection
(hysteresis).
The output of the AVD comparator is directly readable by the application software through a real
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte.
6.4.2.1 Monitoring the VDD Main Supply
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V
V
IT-(AVD)
threshold (AVDF bit toggles).
IT+(AVD)
or
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
ST72361
down safely before the LVD resets the microcon
troller. See Figure 16.
The interrupt on the rising edge is used to inform
the application that the V
warning state is over.
DD
If the voltage rise time trv is less than 256 or 4096
CPU cycles (depending on the reset delay select
ed by option byte), no AVD interrupt will be generated when V
IT+(AVD)
is reached.
If trv is greater than 256 or 4096 cycles then:
– If the AVD interrupt is enabled before the
V
IT+(AVD)
threshold is reached, then two AVD interrupts will be received: The first when the
AVDIE bit is set and the second when the thresh
old is reached.
– If the AVD interrupt is enabled after the V
IT+(AVD)
threshold is reached, then only one AVD interrupt occurs.
-
-
-
Figure 16. Using the AVD to Monitor V
DD
25/225
ST72361
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
Mode Description
WAIT
HALTThe SICSR register is frozen.
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the AVDIE bit is set and the interrupt mask in the
CC register is reset (RIM instruction).
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
Flag
Enable
Control
Bit
Interrupt Event
AVD event AVDF AVDIEYesNo
Event
Exit
from
Wait
Exit
from
Halt
26/225
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.4 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)
Read / Write
Reset Value: 000x 000x (00h)
Bits 3:1 = Reserved, must be kept cleared.
ST72361
70
AVD
IE
AVDFLVD
RF
000
0
WDG
RF
Bit 7 = Reserved, must be kept cleared.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables
an interrupt to be generated when the AVDF flag
changes (toggles). The pending interrupt informa
tion is automatically cleared when software enters
the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware.
If the AVDIE bit is set, an interrupt request is gen
erated when the AVDF bit changes value. Refer to
Figure 16 and to Section 6.4.2.1 for additional de-
tails.
0: VDD over V
IT+(AVD)
1: VDD under V
Bit 4 = LVDRF LVD reset flag
IT-(AVD)
threshold
threshold
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
-
RESET SourcesLVDRFWDGRF
External RESET pin00
Watchdog01
LVD1X
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
CAUTION: When the LVD is not activated with the
associated option byte, the WDGRF flag can not
be used in the application.
-
27/225
ST72361
“IRET”
RESTORE PC, X, A, CC
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
FETCH NEXT
RESET
TLI
PENDING
INSTRUCTION
I1:0
FROM STACK
LOAD PC FROM INTERRUPT VECTOR
Y
N
Y
N
Y
N
Interrupt has the same or a
lower software priority
THE INTERRUPT
STAYS PENDING
than current one
Interrupt has a higher
software priority
than current one
EXECUTE
INSTRUCTION
INTERRUPT
7 INTERRUPTS
7.1 INTRODUCTION
The ST7 enhanced interrupt management provides the following features:
■ Hardware interrupts
■ Software interrupt (TRAP)
■ Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level Event: TLI
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest
-
ed) ST7 interrupt controller.
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 6). The process
ing flow is shown in Figure 17.
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter
-
mined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
ority then the interrupt with the highest hardware
priority is serviced first.
Figure 18 describes this decision process.
Figure 18. Priority Decision Process
When an interrupt request is not serviced immediately, it is latched and then processed when its
software priority combined with the hardware pri
-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci
-
sion process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 17). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
■ TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord
-
ing to the flowchart in Figure 17 as a TLI.
Caution: TRAP can be interrupted by a TLI.
■ RESET
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high
-
est hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi
tions is false, the interrupt is latched and thus remains pending.
■ TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.
■ External Interrupts
External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
■ Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (that is, waiting for being
serviced) will therefore be lost if the clear se
quence is executed.
29/225
ST72361
MAIN
IT4
IT2
IT1
TLI
IT1
MAIN
IT0
I1
HARDWARE PRIORITY
SOFTWARE
3
3
3
3
3
3/0
3
11
11
11
11
11
11 / 10
11
RIM
IT2
IT1
IT4
TLI
IT3
IT0
IT3
I0
10
PRIORITY
LEVEL
USED STACK = 10 BYTES
MAIN
IT2
TLI
MAIN
IT0
IT2
IT1
IT4
TLI
IT3
IT0
HARDWARE PRIORITY
3
2
1
3
3
3/0
3
11
00
01
11
11
11
RIM
IT1
IT4
IT4
IT1
IT2
IT3
I1I0
11 / 10
10
SOFTWARE
PRIORITY
LEVEL
USED STACK = 20 BYTES
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc
ess shown in Figure 18.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 19. Concurrent Interrupt Management
7.4 CONCURRENT & NESTED MANAGEMENT
The following Figure 19 and Figure 20 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in
terrupt to be interrupted, unlike the nested mode in
Figure 20. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without notifying the software of the failure.
-
Figure 20. Nested Interrupt Management
30/225
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