ST ST72361 User Manual

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10-bit ADC, 5 timers, SPI, 2x LINSCI

LQFP32

7x7mm

LQFP44

10x10mm

LQFP64

10x10mm

Features

■ Memories

– 16K to 60K High Density Flash (HDFlash) or

ROM with read-out protection capability. InApplication Programming and In-Circuit Pro

gramming for HDFlash devices – 1.5 to 2K RAM – HDFlash endurance: 100 cycles, data reten-

tion 40 years at 85°C

■ Clock, Reset and Supply Management

– Low power crystal/ceramic resonator oscilla-

tors and bypass for external clock – PLL for 2x frequency multiplication – 5 power saving modes: Halt, Auto Wake Up

From Halt, Active Halt, Wait and Slow

■ Interrupt Management

– Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – TLI top level interrupt (on 64-pin devices) – Up to 21 external interrupt lines (on 4 vectors)

■ Up to 48 I/O Ports

– Up to 48 multifunctional bidirectional I/O lines – Up to 36 alternate function lines – Up to 6 high sink outputs

■ 5 Timers

– 16-bit timer with 2 input captures, 2 output

compares, external clock input, PWM and

pulse generator modes – 8-bit timer with 1 or 2 input captures, 1 or 2

output compares, PWM and pulse generator

modes – 8-bit PWM auto-reload timer with 1 or 2 input

captures, 2 or 4 independent PWM output

channels, output compare and time base in

terrupt, external clock with event detector

ST72361

8-bit MCU with Flash or ROM,

™

– Main clock controller with real-time base and

clock output

– Window watchdog timer

■ Up to 3 Communications Interfaces

– SPI synchronous serial interface – Master/slave LINSCI™ asynchronous serial

interface

– Master-only LINSCI™ asynchronous serial in-

terface

■ Analog Peripheral (Low Current Coupling)

– 10-bit A/D converter with up to 16 inputs – Up to 9 robust ports (low current coupling)

■ Instruction Set

– 8-bit data manipulation – 63 basic instructions – 17 main addressing modes

– 8 x 8 unsigned multiply instruction

■ Development Tools

– Full hardware/software development package

Table 1. Device Summary

Features

Program memory - bytes 60K 48K 32K RAM (stack) - bytes 2K (256) 2K (256) 1.5K (256) Operating Supply 4.5V to 5.5 V CPU Frequency External Resonator Osc. w/ PLLx2/8 MHz Max. Temp. Range -40°C to +125°C Packages LQFP64 10x10mm (AR), LQFP44 10x10mm (J), LQFP32 7x7mm (K)

October 2008 1/225

ST72361AR9/ST72361J9/

ST72361K9

ST72361AR7/ST72361J7/

ST72361K7

ST72361AR6/ST72361J6/

ST72361K6

Rev. 4

Table of Contents

1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.5 ACTIVE HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.6 AUTO WAKE-UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.6 I/O PORT REGISTER CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

225

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Table of Contents

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC . . . . . . . . . . . . . . . 58

10.3 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

10.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.5 8-BIT TIMER (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . . . 120

10.8 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER ONLY) . . . . . . . . . . . . 151

10.9 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

12.6 AUTO WAKEUP FROM HALT OSCILLATOR (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

12.10CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

12.11TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

12.12COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 202

12.1310-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 210

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

14.2 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

15 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

16.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

16.2 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

16.3 ROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

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ST72361

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1 OSC2

RESET

PORT A

CONTROL

RAM

PA7:0

(8 bits)

PROGRAM

(16 - 60 Kbytes)

MEMORY

PLL x 2

PWM

8-Bit

PORT B

PORT C

SPI

LINSCI2

PB7:0

(8 bits)

PC7:0

(8 bits)

OSC

PORT D

PD7:0

(8 bits)

option

LINSCI1

16-Bit

TIMER

(LIN master)

(LIN master/slave)

POWER SUPPLY

PORT E

PE7:0

(8 bits)

PORT F

PF7:0

(8 bits)

TIMER

ART

MCC

(Clock Control)

On some devices only (see Device Summary on page 1)

TLI

WATCHDOG

WINDOW

(1.5 - 2 Kbytes)

1 DESCRIPTION

The ST72361 devices are members of the ST7 microcontroller family designed for mid-range applications with LIN (Local Interconnect Network) interface.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc tion set and are available with Flash or ROM program memory. The ST7 family architecture offers both power and flexibility to software developers, enabling the design of highly efficient and compact application code.

Figure 1. Device Block Diagram

The on-chip peripherals include an A/D converter, a PWM Autoreload timer, 2 general purpose tim ers, 2 asynchronous serial interfaces, and an SPI interface.

For power economy, microcontroller can switch

dynamically into WAIT, SLOW, Active-Halt, Auto Wake-up from HALT (AWU) or HALT mode when the application is in idle or stand-by state.

Typical applications are consumer, home, office and industrial products.

4/225

2 PIN DESCRIPTION

AIN15 / PE3

ICCDATA / AIN1 / PB5

(*)T16_OCMP1 / AIN2 / PB6

SS_2

DD_2

(*)T16_OCMP2 / AIN3 / PB7

(*)T16_ICAP1 / AIN4 / PC0

(*)T16_ICAP2 / (HS) PC1

T16_EXTCLK / (HS) PC2

PE4

ICCSEL/V

AIN12 / PE0

AIN13 / PE1

ICCCLK / AIN0 / PB4

AIN14 / PE2

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

47 46 45 44 43

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PWM1 / (HS) PA2

PWM2 / PA3 PWM3 / PA4

SS_3

DD_3

ARTCLK / (HS) PA5

ARTIC2 / (HS) PA6

T8_OCMP2 / PA7

T8_ICAP2 / PB0

T8_OCMP1 / PB1

T8_ICAP1 / PB2

MCO / PB3

OSC1 OSC2

ARTIC1 / PA0

PWM0 / PA1

PF0 PE7 PD0 / SPI_SS / AIN6 VDD_1 VSS_1 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PE6 / AIN5 PE5

PC4 PC3

PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PF2 / AIN8 PF1 / AIN7

RESET

PD5 / LINSCI2_TDO

DD_0VDDAVSS_0VSSA

PD4 / LINSCI2_RDI

PD3 (HS)/ LINSCI2_SCK

PF5

TLI

PF4

PF3 / AIN9

PF7

PF6

PD7 / AIN11

PD6 / AIN10

ei0

(HS) 20mA high sink capability

eix associated external interrupt vector

ei3

ei1

ei3

ei2

ei3

ei0

ei1

(*) : by option bit:

T16_ICAP2 can be moved to PD1 T16_OCMP1 can be moved to PD3 T16_OCMP2 can be moved to PD5

T16_ICAP1 can be moved to PD4

Figure 2. LQFP 64-Pin Package Pinout

ST72361

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ST72361

SS_2

DD_2

(*)T16_OCMP2 / AIN3 / PB7

(*)T16_ICAP1 / AIN4 / PC0

(*)T16_ICAP2 / (HS) PC1

T16_EXTCLK / (HS) PC2

PE4

ICCSEL/V

ICCCLK / AIN0 / PB4

ICCDATA / AIN1 / PB5

(*)T16_OCMP1 / AIN2 / PB6

44 43 42 41 40 39 38 37 36 35 34

33 32 31 30 29 28 27 26 25 24 23

12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

PWM2 / PA3 PWM3 / PA4

ARTCLK / (HS) PA5

ARTIC2 / (HS) PA6

T8_OCMP1 / PB1

T8_ICAP1 / PB2

MCO / PB3

OSC1 OSC2

PWM0 / PA1

PWM1 / (HS) PA2

PD0 / SPI_SS / AIN6 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PE6 / AIN5 PC4 PC3

PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PF2 / AIN8 PF1 / AIN7

DD_0VDDAVSS_0VSSA

PD4 / LINSCI2_RDI

PD3 (HS) / LINSCI2_SCK

PF5

PD7 / AIN11

PD6 / AIN10

RESET

PD5 / LINSCI2_TDO

(HS) 20mA high sink capability

eix associated external interrupt vector

ei0

ei3

ei1

ei3

ei1

ei2

ei3

(*) : by option bit:

T16_ICAP2 can be moved to PD1 T16_OCMP1 can be moved to PD3 T16_OCMP2 can be moved to PD5

T16_ICAP1 can be moved to PD4

PIN DESCRIPTION (Cont’d)

Figure 3. LQFP 44-Pin Package Pinout

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PIN DESCRIPTION (Cont’d)

T16_OCMP2 / AIN3 / PB7

T16_ICAP1 / AIN4 / PC0

T16_ICAP2 / (HS) PC1

T16_EXTCLK / (HS) PC2

ICCSEL/V

ICCCLK / AIN0 / PB4

ICCDATA / AIN1 / PB5

T16_OCMP1 / AIN2 / PB6

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

9 10111213141516

1 2 3 4 5 6 7 8

ARTCLK / (HS) PA5

T8_OCMP1 / PB1

T8_ICAP1 / PB2

MCO / PB3

OSC1 OSC2

PWM0 / PA1

PWM1 / (HS) PA2

PC6 / SPI_MOSI PC5 / SPI_MISO PC4 PC3

PD2 /

LINSCI1_TDO

PD1 / LINSCI1_RDI PD0 / SPI_SS / AIN6 PC7 / SPI_SCK

SS_0VSSA

PD4 / LINSCI2_RDI

PD3 (HS) / LINSCI2_SCK

RESET

PD5 / LINSCI2_TDO

DD_0VDDA

(HS) 20mA high sink capability

eix associated external interrupt vector

ei0

ei1

ei3

ei1

ei2

(*) : by option bit:

T16_ICAP2 can be moved to PD1 T16_OCMP1 can be moved to PD3 T16_OCMP2 can be moved to PD5

T16_ICAP1 can be moved to PD4

Figure 4. LQFP 32-Pin Package Pinout

ST72361

For external pin connection guidelines, refer to “ELECTRICAL CHARACTERISTICS” on page 178.

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ST72361

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to “ELECTRICAL CHARACTERISTICS” on page 178.

Legend / Abbreviations for Table 2:

Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger

TT= TTL 0.8V / 2V with Schmitt trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt1), ana = analog, RB = robust

– Output: OD = open drain, PP = push-pull Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 2. Device Pin Description

Pin n°

Pin Name

LQFP64

LQFP44

LQFP32

1 1 1 OSC1

2 2 2 OSC2

3 - - PA0 / ARTIC1 I/O C

4 3 3 PA1 / PWM0 I/O C

Level Port

Type

Input

Output

float

Input Output

wpu

int

ana

Main

function

(after

reset)

Alternate function

External clock input or Resonator oscillator inverter input

I/O Resonator oscillator inverter output

X ei0 X X Port A0 ART Input Capture 1

X ei0 X X Port A1 ART PWM Output 0

5 4 4 PA2 (HS) / PWM1 I/O CTHS X ei0 X X Port A2 ART PWM Output 1

6 5 - PA3 / PWM2 I/O C

7 6 - PA4 / PWM3 I/O C

8 - - V

9 - - V

SS_3

DD_3

S Digital Ground Voltage

S Digital Main Supply Voltage

X ei0 X X Port A3 ART PWM Output 2

X ei0 X X Port A4 ART PWM Output 3

10 7 5 PA5 (HS) / ARTCLK I/O CTHS X ei0 X X Port A5 ART External Clock

11 8 - PA6 (HS) / ARTIC2 I/O CTHS X ei0 X X Port A6 ART Input Capture 2

12 - - PA7 / T8_OCMP2 I/O C

13 - - PB0 /T8_ICAP2 I/O C

14 9 6 PB1 /T8_OCMP1 I/O C

15 10 7 PB2 / T8_ICAP1 I/O C

16 11 8 PB3 / MCO I/O C

17 - - PE0 / AIN12 I/O T

18 - - PE1 / AIN13 I/O T

19 12 9 PB4 / AIN0 / ICCCLK I/O C

20 - - PE2 / AIN14 I/O T

21 - - PE3 / AIN15 I/O T

22 13 10 PB5 / AIN1 / ICCDATA I/O C

X ei0 X X Port A7 TIM8 Output Compare 2

X ei1 X X Port B0 TIM8 Input Capture 2

X ei1 X X Port B1 TIM8 Output Compare 1

X ei1 X X Port B2 TIM8 Input Capture 1

X ei1 X X Port B3 Main clock out (f

OSC2

X X RB X X Port E0 ADC Analog Input 12

X X RB X X Port E1 ADC Analog Input 13

X ei1 RB X X Port B4

ICC Clock input

ADC Analog Input 0

X X RB X X Port E2 ADC Analog Input 14

X X RB X X Port E3 ADC Analog Input 15

X ei1 RB X X Port B5

ICC Data input

ADC Analog Input 1

)

8/225

ST72361

Pin n°

LQFP64

LQFP44

LQFP32

23 14 11

24 15 - V

25 16 - V

26 17 12

27 18 13

Pin Name

PB6 / AIN2 / T16_OCMP1

SS_2

DD_2

PB7 /AIN3 / T16_OCMP2

PC0 / AIN4 / T16_ICAP1

Level Port

Input Output

Type

Input

Output

float

wpu

int

ana

Main

function

(after

reset)

Alternate function

TIM16 Out-

I/O C

X X RB X X Port B6

put Compare 1

S Digital Ground Voltage

S Digital Main Supply Voltage

TIM16 Out-

I/O C

X X RB X X Port B7

put Compare 2

I/O C

X X RB X X Port C0

TIM16 Input Capture 1

ADC Analog Input 2

ADC Analog Input 3

ADC Analog Input 4

28 19 14 PC1 (HS) / T16_ICAP2 I/O CTHS X ei2 X X Port C1 TIM16 Input Capture 2

29 20 15

30 21 - PE4 I/O T

PC2 (HS) / T16_EXTCLK

I/O CTHS X ei2 X X Port C2 TIM16 External Clock input

X X X X Port E4

31 - - NC Not Connected

32 22 16 V

33 23 17 PC3 I/O C

34 24 18 PC4 I/O C

35 - - PE5 I/O T

36 25 - PE6 / AIN5 I/O T

37 26 19 PC5 /MISO I/O C

38 27 20 PC6 / MOSI I/O C

39 28 21 PC7 /SCK I/O C

40 - - V

41 - - V

SS_1

DD_1

42 29 22 PD0 / SS/ AIN6 I/O C

43 - - PE7 I/O T

44 - - PF0 I/O T

45 30 - PF1 / AIN7 I/O T

46 31 - PF2 / AIN8 I/O T

47 32 23 PD1 / SCI1_RDI I/O C

48 33 24 PD2 / SCI1_TDO I/O C

49 - - PF3 / AIN9 I/O T

50 - - PF4 I/O T

51 - - TLI I C

52 34 - PF5 I/O T

X X X X Port C3

X X2)Port C4

X X X X Port E5

X X X X X Port E6 ADC Analog Input 5

X X X X Port C5 SPI Master In/Slave Out

X X X X Port C6 SPI Master Out/Slave In

X X X X Port C7 SPI Serial Clock

S Digital Ground Voltage

S Digital Main Supply Voltage

X ei3 X X X Port D0

X X X X Port E7

X X X X Port F0

X X X X X Port F1 ADC Analog Input 7

X X X X X Port F2 ADC Analog Input 8

X ei3 X X Port D1

X X X X Port D2

X X X X X Port F3 ADC Analog Input 9

X X X X Port F4

X X Top level interrupt input pin

X X X X Port F5

53 35 25 PD3 (HS) / SCI2_SCK I/O CTHS X X X X Port D3

Flash programming voltage. Must be tied low in user mode.

SPI Slave Select

ADC Analog Input 6

LINSCI1 Receive Data input

LINSCI1 Transmit Data output

LINSCI2 Serial Clock Output

9/225

ST72361

Pin n°

Pin Name

LQFP64

LQFP44

LQFP32

54 36 26 PD4 / SCI2_RDI I/O C

55 37 27 V

56 38 28 V

57 39 29 V

58 40 30 V

SSA

SS_0

DDA

DD_0

59 41 31 PD5 / SCI2_TDO I/O C

60 42 32 RESET I/O C

61 43 - PD6 / AIN10 I/O C

62 44 - PD7 / AIN11 I/O C

63 - - PF6 I/O T

64 - - PF7 I/O T

Level Port

Input Output

Type

Input

Output

float

X ei3 X X Port D4

wpu

int

ana

Main

function

(after

reset)

Alternate function

LINSCI2 Receive Data input

S Analog Ground Voltage

S Digital Ground Voltage

I Analog Reference Voltage for ADC

S Digital Main Supply Voltage

X X X X Port D5

Top priority non maskable interrupt.

X ei3 X X X Port D6 ADC Analog Input 10

X ei3 X X X Port D7 ADC Analog Input 11

X X X X Port F6

X X X X Port F7

LINSCI2 Transmit Data output

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. Input mode can be used for general purpose I/O, output mode cannot be used.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Section

6 and Section 12.5 "CLOCK AND TIMING CHARACTERISTICS" for more details.

4. On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

10/225

3 REGISTER AND MEMORY MAP

0000h

RAM

Program Memory

(60K, 48K, 32K, 16K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 3)

1000h

FFDFh FFE0h

FFFFh

(see Table 9)

0880h

Reserved

087Fh

Short Addressing RAM (zero page)

256 bytes Stack

16-bit Addressing

RAM

0100h

01FFh

0080h

0200h

00FFh

1000h

32 Kbytes

60 Kbytes

FFDFh

8000h

or 087Fh

16 Kbytes

C000h

48 Kbytes

4000h

(2048/1536 bytes)

067Fh

ST72361

As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory.

Figure 5. Memory Map

The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device.

Table 3. Hardware Register Map

Address Block

0000h 0001h 0002h

0003h 0004h 0005h

0006h 0007h 0008h

0009h 000Ah 000Bh

000Ch 000Dh 000Eh

Port A

Port B

Port C

Port D

Port E

Label

PADR PADDR PAOR

PBDR PBDDR PBOR

PCDR PCDDR PCOR

PDDR PDDDR PDOR

PEDR PEDDR PEOR

Port A Data Register Port A Data Direction Register Port A Option Register

Port B Data Register Port B Data Direction Register Port B Option Register

Port C Data Register Port C Data Direction Register Port C Option Register

Port D Data Register Port D Data Direction Register Port D Option Register

Port E Data Register Port E Data Direction Register Port E Option Register

Reset

Status

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

00h

00h 00h

Remarks

R/W

11/225

ST72361

Address Block

000Fh 0010h

Port F

0011h

Label

PFDR PFDDR PFOR

Port F Data Register Port F Data Direction Register Port F Option Register

Reset

Status

00h

00h 00h

0012h

Reserved Area (15 bytes)

0020h

0021h 0022h 0023h

SPI

SPIDR SPICR SPICSR

SPI Data I/O Register SPI Control Register SPI Control/Status Register

xxh 0xh 00h

0024h FLASH FCSR Flash Control/Status Register 00h R/W

0025h 0026h 0027h 0028h 0029h 002Ah

002Bh 002Ch

002Dh 002Eh

ITC

AWU

CKCTRL

ISPR0 ISPR1 ISPR2 ISPR3 EICR0 EICR1

AWUCSR AWUPR

SICSR MCCSR

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 External Interrupt Control Register 0 External Interrupt Control Register 1

Auto Wake up f. Halt Control/Status Register Auto Wake Up From Halt Prescaler

System Integrity Control / Status Register Main Clock Control / Status Register

FFh FFh FFh FFh 00h 00h

00h FFh

0xh 00h

Remarks

R/W

R/W R/W R/W

R/W R/W R/W R/W R/W R/W

R/W R/W

002Fh 0030h

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh

003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h

0045h 0046h 0047h

WWDG

PWM

ART

8-BIT

TIMER

ADC

WDGCR WDGWR

PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2

T8CR2 T8CR1 T8CSR T8IC1R T8OC1R T8CTR T8ACTR T8IC2R T8OC2R

ADCCSR ADCDRH ADCDRL

Watchdog Control Register Watchdog Window Register

Pulse Width Modulator Duty Cycle Register 3 PWM Duty Cycle Register 2 PWM Duty Cycle Register 1 PWM Duty Cycle Register 0 PWM Control register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register ART Input Capture Control/Status Register ART Input Capture Register 1 ART Input Capture register 2

Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture 1 Register Timer Output Compare 1 Register Timer Counter Register Timer Alternate Counter Register Timer Input Capture 2 Register Timer Output Compare 2 Register

Control/Status Register Data High Register Data Low Register

7Fh 7Fh

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

00h 00h 00h xxh

00h FCh FCh

xxh

00h

R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only

R/W R/W Read Only Read Only R/W Read Only Read Only Read Only R/W

R/W Read Only Read Only

12/225

ST72361

Address Block

0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

0050h Reserved Area (1 byte)

0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh

LINSCI1

(LIN Master/

Slave)

16-BIT TIMER

Label

SCI1ISR SCI1DR SCI1BRR SCI1CR1 SCI1CR2 SCI1CR3 SCI1ERPR SCI1ETPR

T16CR2 T16CR1 T16CSR T16IC1HR T16IC1LR T16OC1HR T16OC1LR T16CHR T16CLR T16ACHR T16ACLR T16IC2HR T16IC2LR T16OC2HR T16OC2LR

SCI1 Status Register SCI1 Data Register SCI1 Baud Rate Register SCI1 Control Register 1 SCI1 Control Register 2 SCI1Control Register 3 SCI1 Extended Receive Prescaler Register SCI1 Extended Transmit Prescaler Register

Timer Control Register 2 Timer Control Register 1 Timer Control/Status Register Timer Input Capture 1 High Register Timer Input Capture 1 Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Input Capture 2 High Register Timer Input Capture 2 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register

Reset

Status

C0h

xxh

00h

xxh

00h

xxh

80h

00h FFh FCh FFh FCh

xxh

80h

00h

Remarks

Read Only R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h

0068h

007Fh

LINSCI2

(LIN Master)

SCI2SR SCI2DR SCI2BRR SCI2CR1 SCI2CR2 SCI2CR3 SCI2ERPR SCI2ETPR

SCI2 Status Register SCI2 Data Register SCI2 Baud Rate Register SCI2 Control Register 1 SCI2 Control Register 2 SCI2 Control Register 3 SCI2 Extended Receive Prescaler Register SCI2 Extended Transmit Prescaler Register

Reserved area (24 bytes)

C0h

xxh

00h

xxh

00h

Read Only R/W R/W R/W R/W R/W R/W R/W

Legend: x = undefined, R/W = read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

13/225

ST72361

4 Kbytes

2Kbytes

SECTOR 1 SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K

FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8 Kbytes 40 Kbytes

52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individu

al sectors and programmed on a Byte-by-Byte basis using an external VPP supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 MAIN FEATURES

■ 3 Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro

grammed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro

grammed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro

grammed or erased without removing the device from the application board and while the application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 STRUCTURE

The Flash memory is organised in sectors and can be used for both code and data storage.

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 3). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 6). They are mapped in the upper part of the ST7 addressing space so the reset and in

terrupt vectors are located in Sector 0 (F000hFFFFh).

Table 4. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0

8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content ex

traction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcon

troller.

In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 6. Memory Map and Sector Address

14/225

FLASH PROGRAM MEMORY (Cont’d)

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10kΩ

ICCSEL/VPP

ST7

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See Note 4)

ST72361

4.4 ICC INTERFACE

ICC (In-Circuit Communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure 7). These pins are:

– RESET: device reset –VSS: device power supply ground

Figure 7. Typical ICC Interface

– ICCCLK: ICC output serial clock pin – ICCDATA: ICC input/output serial data pin – ICCSEL/VPP: programming voltage – OSC1(or OSCIN): main clock input for exter-

nal source (optional)

–VDD: application board power supply (see Fig-

ure 7, Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another de vice forces the signal. Refer to the Programming Tool documentation for recommended resistor val ues.

2. During the ICC session, the programming tool must control the flicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the appli cation RESET circuit in this case. When using a classical RC network with R

RESET pin. This can lead to con-

> 1K or a reset man-

agement IC with open drain output and pull-up resistor

> 1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin

must be connected when using most ST Program

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2

grounded in this case.

15/225

ST72361

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (IN-CIRCUIT PROGRAMMING)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully custom

ized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the spe

cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap

plication board (see Figure 7). For more details on the pin locations, refer to the device pinout de

scription.

4.6 IAP (IN-APPLICATION PROGRAMMING)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us

er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI or other type of serial interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/ erase protected to allow recovery in case errors occur during the programming operation.

4.7 RELATED DOCUMENTATION

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Reference Manual.

4.8 REGISTER DESCRIPTION

FLASH CONTROL/STATUS REGISTER (FCSR)

Read / Write Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 0 0

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

Table 5. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

0024h

16/225

Label

FCSR

Reset Value 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

5 CENTRAL PROCESSING UNIT

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

ST72361

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 8. CPU Registers

5.3 CPU REGISTERS

The six CPU registers shown in Figure 8 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the fol lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

17/225

ST72361

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write Reset Value: 111x1xxx

7 0

1 1 I1 H I0 N Z

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in structions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re sult 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri ority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

18/225

CENTRAL PROCESSING UNIT (Cont’d)

PCH

PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCH PCL

PCL

PCH

PCH PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh Stack Lower Address =

0100h

ST72361

Stack Pointer (SP)

Read/Write Reset Value: 01 FFh

15 8

0 0 0 0 0 0 0 1

7 0

SP7 SP6 SP5 SP4 SP3 SP2 SP1

SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruc

tion (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 9. Stack Manipulation Example

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD in

struction. Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with

out indicating the stack overflow. The previously stored information is then overwritten and there

fore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc

tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

19/225

ST72361

PLL OPTION BIT

PLL x 2

OSC2

/ 2

OSC

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

RESET SEQUENCE

MANAGER

(RSM)

OSC2

MAIN CLOCK

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD AVD

LVD

WDG

OSC

OSC2

(option)

CPU

8-BIT TIMER

/ 8000

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and re

ducing the number of external components. An overview is shown in

Figure 11.

For more details, refer to dedicated parametric section.

Main features

■ Optional PLL for multiplying the frequency by 2

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator Clock Management (MO)

– 4 Crystal/Ceramic resonator oscillators

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) – Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply

Figure 11. Clock, Reset and Supply Block Diagram

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an f

OSC2

of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2

= f

OSC

/2.

Caution: The PLL is not recommended for applications where timing accuracy is required. See

“PLL Characteristics” on page 187.

Figure 10. PLL Block Diagram

20/225

6.2 MULTI-OSCILLATOR (MO)

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

ST72361

The main clock of the ST7 can be generated by two different source types coming from the multioscillator block:

■ an external source

■ a crystal or ceramic resonator oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in

Table 6. Refer to the

electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not

be left unconnected. For the purposes of Failure Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this con figuration, could generate an f in excess of the allowed maximum (>

clock frequency

OSC

16 MHz),

putting the ST7 in an unsafe/undefined state. The product behavior must therefore be considered undefined when the OSC pins are left unconnect

ed.

External Clock Source

In external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of five oscilla

tors with different frequency ranges must be done by option byte in order to reduce consumption (re

fer to Section 14.1 on page 210 for more details on

the frequency ranges). The resonator and the load capacitors must be placed as close as possible to the oscillator pins in order to minimize output dis

tortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Table 6. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic Resonators

21/225

ST72361

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

WATCHDOG RESET

LVD RESET

INTERNAL RESET

PULSE

GENERATOR

Filter

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 2:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of three phases as shown in Figure 1:

■ Active Phase depending on the RESET source

■ 256 or 4096 CPU clock cycle delay (selected by

option byte)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application.

The RESET vector fetch phase duration is two clock cycles.

Figure 12. RESET Sequence Phases

Caution: When the ST7 is unprogrammed or fully

erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recom

mended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated R This pull-up has no fixed value but varies in ac

weak pull-up resistor.

cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

order to be recognized (see Figure 3). This detec

tion is asynchronous and therefore the MCU can enter reset state even in HALT mode.

Figure 13. Reset Block Diagram

22/225

RESET SEQUENCE MANAGER (Cont’d)

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

RUN

WATCHDOG UNDERFLOW

w(RSTL)out

RUN RUN

RESET

RESET SOURCE

EXTERNAL

RESET

LVD

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 T

CPU

)

VECTOR FETCH

ACTIVE PHASE

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris

tics section.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V level specified for the selected f

is over the minimum

frequency.

OSC

A proper reset signal for a slow rising VDD supply can generally be provided by an external RC net

work connected to the RESET pin.

Figure 14. RESET Sequences

ST72361

6.3.4 Internal Low Voltage Detector (LVD) RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pin acts as an output that is

< V

pulled low when V

< V

(falling edge) as shown in Figure 3.

IT-

The LVD filters spikes on V avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 3.

Starting from the Watchdog counter underflow, the device low during at least t

RESET pin acts as an output that is pulled

w(RSTL)out

(rising edge) or

IT+

larger than t

g(VDD)

23/225

ST72361

IT+

(LVD)

RESET

IT-

(LVD)

hys

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Volt

age Detector (AVD) functions. It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a V

IT-(LVD)

reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The V

IT-(LVD)

lower than the V

reference value for a voltage drop is

IT+(LVD)

reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the sup

ply (hysteresis). The LVD Reset circuitry generates a reset when

is below:

–V –V

IT+(LVD)

IT-(LVD)

when VDD is rising

when VDD is falling

The LVD function is illustrated in Figure 15.

Figure 15. Low Voltage Detector vs Reset

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above V

IT-(LVD)

, the

MCU can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. The LVD is an optional function which can be se-

lected by option byte. It is recommended to make sure that the V

supply voltage rises monotonously when the device is exiting from Reset, to ensure the application func tions properly.

24/225

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

IT+(AVD)

IT-(AVD)

AVDF bit 0 0RESET VALUE

IF AVDIE bit = 1

hyst

AVD INTERRUPT REQUEST

INTERRUPT PROCESS

IT+(LVD)

IT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

VOLTAGE RISE TIME

6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on

an analog comparison between a V V

IT+(AVD)

ply. The V age is lower than the V

reference value and the VDD main sup-

IT-(AVD)

reference value for falling volt-

IT+(AVD)

reference value for

IT-(AVD)

and

rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD function is active only if the LVD is enabled through the option byte.

6.4.2.1 Monitoring the VDD Main Supply

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V V

IT-(AVD)

threshold (AVDF bit toggles).

IT+(AVD)

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut

ST72361

down safely before the LVD resets the microcon troller. See Figure 16.

The interrupt on the rising edge is used to inform the application that the V

warning state is over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay select ed by option byte), no AVD interrupt will be generated when V

IT+(AVD)

is reached. If trv is greater than 256 or 4096 cycles then: – If the AVD interrupt is enabled before the

IT+(AVD)

threshold is reached, then two AVD interrupts will be received: The first when the AVDIE bit is set and the second when the thresh old is reached.

– If the AVD interrupt is enabled after the V

IT+(AVD)

threshold is reached, then only one AVD interrupt occurs.

Figure 16. Using the AVD to Monitor V

25/225

ST72361

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Low Power Modes

Mode Description

WAIT

HALT The SICSR register is frozen.

6.4.3.1 Interrupts

The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask in the CC register is reset (RIM instruction).

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

Flag

Enable

Control

Bit

Interrupt Event

AVD event AVDF AVDIE Yes No

Event

Exit

from

Wait

Exit

from

Halt

26/225

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read / Write Reset Value: 000x 000x (00h)

Bits 3:1 = Reserved, must be kept cleared.

ST72361

7 0

AVD

AVDFLVD

0 0 0

WDG

Bit 7 = Reserved, must be kept cleared.

Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt informa tion is automatically cleared when software enters the AVD interrupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is gen erated when the AVDF bit changes value. Refer to

Figure 16 and to Section 6.4.2.1 for additional de-

tails. 0: VDD over V

IT+(AVD)

1: VDD under V

Bit 4 = LVDRF LVD reset flag

IT-(AVD)

threshold

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET pin 0 0

Watchdog 0 1

LVD 1 X

Application notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi

nal failure. In this case, a watchdog reset can be detected by software while an external reset can not.

CAUTION: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application.

27/225

ST72361

“IRET”

RESTORE PC, X, A, CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

TLI

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Interrupt has the same or a

lower software priority

THE INTERRUPT STAYS PENDING

than current one

Interrupt has a higher

software priority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels – Up to 16 interrupt vectors fixed by hardware – 2 non maskable events: RESET, TRAP – 1 maskable Top Level Event: TLI

This interrupt management is based on: – Bit 5 and bit 3 of the CPU CC register (I1:0), – Interrupt software priority registers (ISPRx), – Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nest

ed) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of

each interrupt vector (see Table 6). The process ing flow is shown in Figure 17.

When an interrupt request has to be serviced: – Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to “Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 7. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main) Level 1 Level 2 0 Level 3 (= interrupt disable) 1 1

Low

High

1 0

Figure 17. Interrupt Processing Flowchart

28/225

INTERRUPTS (Cont’d)

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

ST72361

Servicing Pending Interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account is deter

mined by the following two-step process: – the highest software priority interrupt is serviced, – if several interrupts have the same software pri-

ority then the interrupt with the highest hardware priority is serviced first.

Figure 18 describes this decision process.

Figure 18. Priority Decision Process

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware pri

ority becomes the highest one. Note 1: The hardware priority is exclusive while

the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the deci

sion process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 17). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced accord

ing to the flowchart in Figure 17 as a TLI. Caution: TRAP can be interrupted by a TLI.

■ RESET

The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the high

est hardware priority. See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two condi

tions is false, the interrupt is latched and thus remains pending.

■ TLI (Top Level Hardware Interrupt)

This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine.

■ External Interrupts

External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being serviced) will therefore be lost if the clear se

quence is executed.

29/225

ST72361

MAIN

IT4

IT2

IT1

TLI

IT1

MAIN

IT0

HARDWARE PRIORITY

SOFTWARE

3/0

11 / 10

RIM

IT2

IT1

IT4

TLI

IT3

IT0

IT3

PRIORITY LEVEL

USED STACK = 10 BYTES

MAIN

IT2

TLI

MAIN

IT0

IT2

IT1

IT4

TLI

IT3

IT0

HARDWARE PRIORITY

3/0

RIM

IT1

IT4

IT1

IT2

IT3

I1 I0

11 / 10

SOFTWARE PRIORITY LEVEL

USED STACK = 20 BYTES

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exit

ing HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision proc

ess shown in Figure 18.

Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 19. Concurrent Interrupt Management

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 19 and Figure 20 show two different interrupt management modes. The first is called concurrent mode and does not allow an in terrupt to be interrupted, unlike the nested mode in

Figure 20. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

Figure 20. Nested Interrupt Management

30/225

INTERRUPTS (Cont’d)

ST72361

7.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

Read / Write Reset Value: 111x 1010 (xAh)

7 0

1 1 I1 H I0 N Z C

Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft-

ware priority.

Interrupt Software Priority Level I1 I0

Level 0 (main) Level 1 Level 2 0 Level 3 (= interrupt disable*) 1 1

Low

High

1 0

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri

ority registers (ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP in

structions (see “Interrupt Dedicated Instruction Set” table).

*Note: TLI, TRAP and RESET events can interrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)

7 0

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where its own software priority is stored. This corre

spondence is shown in the following table.

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 cannot be written (I1_x = 1, I0_x = 0). In

this case, the previously stored value is kept (Ex

ample: previous = CFh, write = 64h,

= 44h)

result

The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

*Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process man

agement. Caution: If the I1_x and I0_x bits are modified

while the interrupt x is executed the following be

havior has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

31/225

ST72361

INTERRUPTS (Cont’d)

Table 8. Dedicated Interrupt Instruction Set

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0

IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C

JRM Jump if I1:0 = 11 (level 3) I1:0 = 11 ?

JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?

POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C

RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0

SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1

TRAP Software trap Software NMI 1 1

WFI Wait for interrupt 1 0

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

32/225

INTERRUPTS (Cont’d)

Table 9. Interrupt Mapping

ST72361

N°

Source

Block

Description

RESET Reset

TRAP Software interrupt no FFFCh-FFFDh

0 TLI External top level interrupt EICR yes FFFAh-FFFBh

1 MCC/RTC Main clock controller time base interrupt MCCSR yes FFF8h-FFF9h

2 ei0/AWUFH External interrupt ei0/ Auto wake-up from Halt

3 ei1/AVD External interrupt ei1/Auxiliary Voltage Detector

Label

N/A

EICR/

AWUCSR

EICR/

SICSR

Priority

Order

Highest

Priority

Exit from

HALT

Address

Vector

yes FFFEh-FFFFh

FFF6h-FFF7h

yes

FFF4h-FFF5h

4 ei2 External interrupt ei2 EICR FFF2h-FFF3h

5 ei3 External interrupt ei3 EICR FFF0h-FFF1h

6 not used FFEEh-FFEFh

7 not used FFECh-FFEDh

8 SPI SPI peripheral interrupts SPICSR yes FFEAh-FFEBh

9 TIMER8 8-bit TIMER peripheral interrupts T8_TCR1 no FFE8h-FFE9h

10 TIMER16 16-bit TIMER peripheral interrupts TCR1 no FFE6h-FFE7h

11 LINSCI2 LINSCI2 Peripheral interrupts SCI2CR1 no FFE4h-FFE5h

12 LINSCI1

13 PWM ART 8-bit PWM ART interrupts PWMCR yes FFE0h-FFE1h

LINSCI1 Peripheral interrupts (LIN Master/ Slave)

SCI1CR1 no

Lowest Priority

FFE2h-FFE3h

Notes:

1. Valid for HALT and ACTIVE HALT modes except for the MCC/RTC interrupt source which exits from ACTIVE HALT mode only.

2. Except AVD interrupt

3. It is possible to exit from Halt using the external interrupt which is mapped on the RDI pin.

33/225

ST72361

IS10 IS11

EICR

SENSITIVITY

CONTROL

PBOR.0

PBDDR.0

PB0

ei1 INTERRUPT SOURCE

PORT B [5:0] INTERRUPTS

PB0 PB1

PB2 PB3

IS20 IS21

EICR

SENSITIVITY

CONTROL

PCOR.7

PCDDR.7

PC1

ei2 INTERRUPT SOURCE

PORT C [2:1] INTERRUPTS

PC1 PC2

IS00 IS01

EICR

SENSITIVITY

CONTROL

PAOR.0

PADDR.0

PA0

ei0 INTERRUPT SOURCE

PORT A [7:0] INTERRUPTS

PA0 PA1

PA2 PA3

PA4 PA5 PA6 PA7

/ AWUPR

AWUFH

Oscillator

To Timer Input Capture 1

PB4 PB5

IS30 IS31

EICR

SENSITIVITY

CONTROL

PDOR.0

PDDDR.0

PD0

ei3 INTERRUPT SOURCE

PORT D [7:6, 4, 1:0] INTERRUPTS

PD0 PD1

PD4 PD6

PD7

INTERRUPTS (Cont’d)

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by the ISxx bits in the EICR register ( control allows up to four fully independent external interrupt source sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

■ Falling edge

■ Rising edge

Figure 21. External Interrupt Control Bits

Figure 21). This

■ Falling and rising edge

■ Falling edge and low level

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0] of the EICR.

34/225

INTERRUPTS (Cont’d)

7.6.2 Register Description EXTERNAL INTERRUPT CONTROL

Read / Write Reset Value: 0000 0000 (00h)

7 0

IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00

Bits 7:6 = IS3[1:0] ei3 sensitivity The interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei3 external interrupts:

ST72361

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bits 1:0 = IS0[1:0] ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts:

IS01 IS00 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

IS31 IS30 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bits 5:4 = IS2[1:0] ei2 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the ei2 external interrupts:

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bits 3:2 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei1 external interrupts:

IS11 IS10 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

EXTERNAL INTERUPT CONTROL REGISTER 1 (EICR1)

Read / Write Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 TLIS TLIE

BIts 7:2 = Reserved

Bit 1 = TLIS Top Level Interrupt sensitivity This bit configures the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared. 0: Falling edge 1: Rising edge

Bit 0 = TLIE Top Level Interrupt enable This bit allows to enable or disable the TLI capability on the dedicated pin. It is set and cleared by software. 0: TLI disabled 1: TLI enabled

Notes: – A parasitic interrupt can be generated when

clearing the TLIE bit.

– In some packages, the TLI pin is not available. In

this case, the TLIE bit must be kept low to avoid parasitic TLI interrupts.

35/225

ST72361

INTERRUPTS (Cont’d)

Table 10. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

0025h

0026h

0027h

0028h

0029h

002Ah

Label

ISPR0

Reset Value

ISPR1

Reset Value

ISPR2

Reset Value

ISPR3

Reset Value 1 1 1 1

EICR0

Reset Value

EICR1

Reset Value 0 0 0 0 0 0

7 6 5 4 3 2 1 0

ei1 ei0 CLKM TLI

I1_3

I1_7

LINSCI 2 TIMER 16 TIMER 8 SPI

I1_11

IS31

I0_3

I0_7

I0_11

IS30

I1_2

I1_6

I1_10

IS21

I0_2

I0_6

I0_10

IS20

I1_1

I1_5

I1_9

I1_13

IS11

I0_1

ei3 ei2

I0_5

I0_9

ART LINSCI 1

I0_13

IS10

1 1

I1_4

I1_8

I1_12

IS01

TLIS

I0_4

I0_8

I0_12

IS00

TLIE

36/225

8 POWER SAVING MODES

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

AUTO WAKE-UP FROM HALT

HALT

00 01

SMS

CP1:0

CPU

NEW SLOW

NORMAL RUN MODE

MCCSR

FREQUENCY

REQUEST

OSC2

/2 f

OSC2

/4 f

OSC2

ST72361

8.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see

Figure 22):

■ Slow

■ Wait (and Slow-Wait)

■ Active Halt

■ Auto Wake-up From Halt (AWUFH)

■ Halt

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2

OSC2

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 22. Power Saving Mode Transitions

8.2 SLOW MODE

This mode has two targets: – To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f

In this mode, the master clock frequency (f can be divided by 2, 4, 8 or 16. The CPU and pe

CPU

)

OSC2

ripherals are clocked at this lower frequency

CPU

Note: SLOW-WAIT mode is activated by entering WAIT mode while the device is in SLOW mode.

Figure 23. SLOW Mode Clock Transitions

37/225

ST72361

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

256 OR 4096 CPU CLOCK

CYCLE DELAY

POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 24

Figure 24. WAIT Mode Flow-chart

38/225

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits of the CC reg ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

POWER SAVING MODES (Cont’d)

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[MCCSR.OIE=0]

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF OFF

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

WATCHDOG

RESET

CYCLE

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=0)

ST72361

8.4 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see tails on the MCCSR register) and when the AWUEN bit in the AWUCSR register is cleared.

The MCU can exit HALT mode on reception of either a specific interrupt (see Table 9, “Interrupt

Mapping,” on page 33) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see

ure 26).

When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, in cluding the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla tor).

The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” op tion bit of the option byte. The HALT instruction when executed while the Watchdog system is en abled, can generate a Watchdog RESET (see

Section 10.1 on page 52 for more details).

Figure 25. HALT Timing Overview

Section 10.2 on page 58 for more de-

Fig-

Figure 26. HALT Mode Flow-chart

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Re fer to Table 9, “Interrupt Mapping,” on page 33 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC reg ister are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

39/225

ST72361

POWER SAVING MODES (Cont’d)

Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to ex ternal interference or by an unforeseen logical condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precautionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memo ry. For example, avoid defining a constant in ROM with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits be fore executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corre sponding to the wake-up event (reset or external interrupt).

8.5 ACTIVE HALT MODE

ACTIVE HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ in struction when MCC/RTC interrupt enable flag (OIE bit in MCCSR register) is set and when the AWUEN bit in the AWUCSR register is cleared

See “Register Description” on page 44.)

(

MCCSR

OIE

Power Saving Mode entered when HALT

bit

0 HALT mode

1 ACTIVE HALT mode

instruction is executed

The MCU can exit ACTIVE HALT mode on reception of the RTC interrupt and some specific inter-

rupts (see Table 9, “Interrupt Mapping,” on page

33) or a RESET. When exiting ACTIVE HALT

mode by means of a RESET a 4096 or 256 CPU cycle delay occurs (depending on the option byte). After the start up delay, the CPU resumes opera

tion by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 28).

When entering ACTIVE HALT mode, the I[1:0] bits in the CC register are are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In ACTIVE HALT mode, only the main oscillator and its associated counter (MCC/RTC) are run ning to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE HALT mode is provided by the oscillator interrupt.

Note: As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

40/225

POWER SAVING MODES (Cont’d)

HALTRUN RUN

256 OR 4096 CYCLE

DELAY (AFTER RESET)

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

(Active Halt enabled)

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR PERIPHERALS

I[1:0] BITS

ON ON

256 OR 4096 CPU CLOCK

CYCLE DELAY

(MCCSR.OIE=1)

(AWUCSR.AWUEN=0)

ST72361

Figure 27. ACTIVE HALT Timing Overview

Figure 28. ACTIVE HALT Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits ACTIVE

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock

source can still be active.

3. Only the RTC interrupt and some specific inter-

rupts can exit the MCU from ACTIVE HALT mode (such as external interrupt). Refer to

Table 9, “Interrupt Mapping,” on page 33 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I[1:0] bits in the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

41/225

ST72361

AWU RC

AWUFH

AWU_RC

AWUFH

(ei0 source)

oscillator

prescaler

interrupt

/64

divider

to Timer input capture

/1 .. 255

AWUFH interrupt

CPU

RUN MODE HALT MODE 256 or 4096 t

CPU

RUN MODE

AWU_RC

Clear by software

AWU

POWER SAVING MODES (Cont’d)

8.6 AUTO WAKE-UP FROM HALT MODE

Auto Wake-Up From Halt (AWUFH) mode is similar to Halt mode with the addition of an internal RC oscillator for wake-up. Compared to ACTIVE HALT mode, AWUFH has lower power consump

tion because the main clock is not kept running, but there is no accurate realtime clock available.

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set and the OIE bit in the MCCSR register is cleared (see

Section 10.2 on page 58 for more de-

tails).

Figure 29. AWUFH Mode Block Diagram

As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (f

AWU_RC

). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler pro

vides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes up the MCU from Halt mode. At the same time the main oscillator is immediately turned on

and a 256 or 4096 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes oper

ation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register.

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f

AWU_RC

and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects f

AWU_RC

lowing the f

to the ICAP1 input of the 16-bit timer, al-

AWU_RC

to be measured using the main

oscillator clock as a reference timebase.

Similarities with Halt mode

The following AWUFH mode behavior is the same as normal Halt mode:

– The MCU can exit AWUFH mode by means of

any interrupt with exit from Halt capability or a re

set (see Section 8.4 "HALT MODE").

– When entering AWUFH mode, the I[1:0] bits in

the CC register are forced to 10b to enable inter

rupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

– In AWUFH mode, the main oscillator is turned off

causing all internal processing to be stopped, in

cluding the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscil

lator like the AWU oscillator).

– The compatibility of Watchdog operation with

AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can gen

erate a Watchdog RESET.

Figure 30. AWUF Halt Timing Diagram

42/225

POWER SAVING MODES (Cont’d)

RESET

INTERRUPT

CPU

MAIN OSC PERIPHERALS

I[1:0] BITS

OFF OFF

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

MAIN OSC PERIPHERALS

I[1:0] BITS

OFF

CPU

MAIN OSC PERIPHERALS

I[1:0] BITS

ON ON

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

WATCHDOG

RESET

CYCLE

AWU RC OSC ON

AWU RC OSC OFF

HALT INSTRUCTION

(MCCSR.OIE=0)

(AWUCSR.AWUEN=1)

Figure 31. AWUFH Mode Flow-chart Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 9, “Interrupt

Mapping,” on page 33 for more details.

ST72361

43/225

ST72361

AWU

64 A W UPR×

AWURC

--------------------------t RCSTRT

+×=

POWER SAVING MODES (Cont’d)

8.6.1 Register Description AWUFH CONTROL/STATUS REGISTER

(AWUCSR)

Read / Write (except bit 2 read only) Reset Value: 0000 0000 (00h)

7 0

0: AWUFH (Auto Wake-Up From Halt) mode disa-

bled

1: AWUFH (Auto Wake-Up From Halt) mode ena-

bled

AWUFH PRESCALER REGISTER (AWUPR)

Read / Write Reset Value: 1111 1111 (FFh)

0 0 0 0 0

AWUFAWUMAWU

Bits 7:3 = Reserved.

Bit 2 = AWUF Auto Wake-Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. 0: No AWU interrupt occurred 1: AWU interrupt occurred

Bit 1 = AWUM Auto Wake-Up Measurement This bit enables the AWU RC oscillator and connects its output to the ICAP1 input of the 16-bit timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compen

sate this dispersion by providing the right value in the AWUPR register. 0: Measurement disabled 1: Measurement enabled

Bit 0 = AWUEN Auto Wake-Up From Halt Enabled This bit enables the Auto Wake-Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay de

fined by the AWU prescaler value. It is set and cleared by software.

7 0

AWU

PR7

PR6

PR5

PR4

PR3

PR2

PR1

Bits 7:0 = AWUPR[7:0] Auto Wake-Up Prescaler These 8 bits define the AWUPR Dividing factor (as explained below:

AWUPR[7:0] Dividing factor

00h Forbidden (See note)

01h 1

... ...

FEh 254

FFh 255

In AWU mode, the period that the MCU stays in Halt Mode (t

in Figure 30) is defined by

AWU

This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically.

Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction or the AWUPR remains unchanged.

AWU

PR0

Table 11. AWU Register Map and Reset Values

Address

(Hex.)

002Bh

002Ch

44/225

Label

AWUCSR

Reset Value

AWUPR

Reset Value

7 6 5 4 3 2 1 0

0 0 0 0 0

AWUPR71AWUPR61AWUPR51AWUPR41AWUPR31AWUPR21AWUPR11AWUPR0

AWUF0AWUM0AWUEN

9 I/O PORTS

ST72361

9.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs

and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has two main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR registers: Bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, (for specific ports which do not pro

vide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 32

9.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies the latch value but does not affect the pin status.

2. When switching from input to output mode, the DR register has to be written first to drive the cor

rect level on the pin as soon as the port is configured as an output.

3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this might corrupt the DR content for I/Os configured as input.

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter

rupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are se

lected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified.

9.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writ

ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg

ister returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

DR Push-pull Open-drain

0 V 1 V

Vss

Floating

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically select

ed. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

45/225

ST72361

DDR

DATA BUS

PAD

ALTERNATE ENABLE

ALTERNATE OUTPUT

OR SEL

DDR SEL

DR SEL

PULL-UP CONDITION

P-BUFFER (see table below)

N-BUFFER

PULL-UP (see table below)

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

DIODES (see table below)

EXTERNAL

SOURCE (eix)

INTERRUPT

CMOS SCHMITT TRIGGER

I/O PORTS (Cont’d)

Figure 32. I/O Port General Block Diagram

Table 12. I/O Port Mode Options

Input

Output

Configuration Mode Pull-Up P-Buffer

Floating with/without Interrupt Off Pull-up with/without Interrupt On Push-pull Open Drain (logic level) Off True Open Drain NI NI NI (see note)

Legend: NI - not implemented

Off - implemented not activated On - implemented and activated

46/225

Off

Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and V vice against positive stress.

Diodes

to V

Off

is implemented to protect the de-

to V

I/O PORTS (Cont’d)

CONDITION

PAD

EXTERNAL INTERRUPT

DATA B U S

PULL-UP

INTERRUPT

DR REGISTER ACCESS

SOURCE (eix)

CONDITION

ALTERNATE INPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

ANALOG INPUT

PAD

DATA B U S

DR REGISTER ACCESS

R/W

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

PAD

DATA B U S

DR REGISTER ACCESS

R/W

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS

Table 13. I/O Port Configurations

INPUT

ST72361

Hardware Configuration

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

OPEN-DRAIN OUTPUT

PUSH-PULL OUTPUT

reading the DR register will read the alternate function output status.

the alternate function reads the pin status given by the DR register content.

47/225

ST72361

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the select ed pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected an alog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maxi mum ratings.

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC In put or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33 on page 49. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 33. Interrupt I/O Port State Transitions

9.4 LOW POWER MODES

Mode Description

WAIT

HALT

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

9.5 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

External interrupt on selected external event

Event

Flag

Enable

Control

Bit

DDRx

ORx

Exit from Wait

Exit

from

Halt

Yes

48/225

I/O PORTS (Cont’d)

9.6 I/O PORT REGISTER CONFIGURATIONS

The I/O port register configurations are summarized as follows.

9.6.1 Standard Ports

PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0

MODE DDR OR

floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1

9.6.2 Interrupt Ports PA0,2,4,6; PB0,2,4; PC1; PD0,6 (with pull-up)

MODE DDR OR

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

ST72361

PA1,3,5,7; PB1,3,5; PC2; PD1,4,7

(without pull-up)

MODE DDR OR

floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1

9.6.3 Pull-up Input Port PC4

MODE

pull-up input

The PC4 port cannot operate as a general purpose output. If DDR = 1 it is still possible to read the port through the DR register.

49/225

ST72361

I/O PORTS (Cont’d)

Table 14. Port Configuration

Port Pin name

PA0 PA1 floating interrupt (ei0) PA2 pull-up interrupt (ei0)

Port A

Port B

Port C

Port D

Port E Port F

PA3 floating interrupt (ei0) PA4 pull-up interrupt (ei0) PA5 floating interrupt (ei0) PA6 pull-up interrupt (ei0) PA7 floating interrupt (ei0) PB0 PB1 floating interrupt (ei1) PB2 pull-up interrupt (ei1) PB3 floating interrupt (ei1) PB4 pull-up interrupt (ei1) PB5 floating interrupt (ei1) PC0 PC1 pull-up interrupt (ei2) PC2 floating interrupt (ei2) PC3 pull-up PC4 pull-up N/A PC7:5 floating pull-up open drain push-pull PD0 PD1 floating interrupt (ei3) PD3:2 pull-up PD4 floating interrupt (ei3) PD5 pull-up PD6 pull-up interrupt (ei3) PD7 floating interrupt (ei3) PE7:0 floating (TTL) pull-up (TTL) open drain push-pull PF7:0 floating (TTL) pull-up (TTL) open drain push-pull

Input Output

OR = 0 OR = 1 OR = 0 OR = 1

pull-up interrupt (ei0)

floating

pull-up interrupt (ei1)

floating

pull-up

floating

pull-up interrupt (ei3)

floating

open drain push-pull

50/225

I/O PORTS (Cont’d)

Table 15. I/O Port Register Map and Reset Values

ST72361

Address

(Hex.)

Reset Value

of all IO port registers

0000h PADR

0002h PAOR 0003h PBDR

0005h PBOR 0006h PCDR

0008h PCOR 0009h PDDR

000Bh PDOR

000Ch PEDR

000Eh PEOR 000Fh PFDR

0011h PFOR

Label

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

MSB LSB0001h PADDR

MSB LSB0004h PBDDR

MSB LSB0007h PCDDR

MSB LSB000Ah PDDDR

MSB LSB000Dh PEDDR

MSB LSB0010h PFDDR

51/225

ST72361

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

WATCHDOG CONTROL REGISTER (WDGCR)

WATCHDOG WINDOW REGISTER (WDGWR)

comparator

T6:0 > W6:0

CMP

= 1 when

Write WDGCR

WDG PRESCALER

DIV 4

OSC2

12-BIT MCC

RTC COUNTER

MSB

LSB

DIV 64

MCC/RTC

TB[1:0] bits (MCCSR Register)

10 ON-CHIP PERIPHERALS

10.1 WINDOW WATCHDOG (WWDG)

10.1.1 Introduction

The Window Watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical con ditions, which causes the application program to abandon its normal sequence. The Watchdog cir cuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also gener ated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited win dow.

10.1.2 Main Features

■ Programmable free-running downcounter

■ Conditional reset

– Reset (if watchdog activated) when the down-

counter value becomes less than 40h

– Reset (if watchdog activated) if the down-

Figure 34. Watchdog Block Diagram

counter is reloaded outside the window (see

Figure 4)

■ Hardware/Software Watchdog activation

(selectable by option byte)

■ Optional reset on HALT instruction

(configurable by option byte)

10.1.3 Functional Description

The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 16384 f

cycles (approx.), and the length of the timeout pe-

riod can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit downcounter (T[6:0] bits) rolls over from 40h to 3Fh (T6 becomes cleared), it ini tiates a reset cycle pulling low the reset pin for typically 30μs. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated.

OSC2

52/225

WINDOW WATCHDOG (Cont’d) The application program must write in the

WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WDGCR register must be between FFh and C0h (see Figure 2):

– Enabling the watchdog:

When Software Watchdog is selected (by option byte), the watchdog is disabled after a reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be disabled again except by a reset.

When Hardware Watchdog is selected (by option byte), the watchdog is always active and the WDGA bit is not used.

– Controlling the downcounter:

This downcounter is free-running: It counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see Figure 2. Ap

proximate Timeout Duration). The timing varies

ST72361

between a minimum and a maximum value due to the unknown status of the prescaler when writ ing to the WDGCR register (see Figure 3).

The window register (WDGWR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 3Fh. Figure 4 describes the window watch dog process.

Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).

– Watchdog Reset on Halt option

If the watchdog is activated and the watchdog reset on halt option is selected, then the HALT instruction will generate a Reset.

10.1.4 Using Halt Mode with the WDG

If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT instruction), it is recommended before executing the HALT instruc tion to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

53/225

ST72361

CNT Value (hex.)

Watchdog timeout (ms) @ 8 MHz f

OSC2

128

1.5 65

503418 82 98 114

WINDOW WATCHDOG (Cont’d)

10.1.5 How to Program the Watchdog Timeout

Figure 2 shows the linear relationship between the

6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milli seconds. This can be used for a quick calculation without taking the timing variations into account. If

Figure 35. Approximate Timeout Duration

more precision is needed, use the formulae in Fig

ure 3.

Caution: When writing to the WDGCR register, al-

ways write 1 in the T6 bit to avoid generating an immediate reset.

54/225

WINDOW WATCHDOG (Cont’d)

WHERE:

min0

= (LSB + 128) x 64 x t

OSC2

max0

= 16384 x t

OSC2

= 125ns if f

OSC2

= 8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

To calculate the minimum Watchdog Timeout (t

min

IF THEN

ELSE

To calculate the maximum Watchdog Timeout (t

max

IF THEN

ELSE

Note: In the above formulae, division results must be rounded down to the next integer value. Example:

With 2ms timeout selected in MCCSR register

TB1 Bit

(MCCSR Reg.)

TB0 Bit

(MCCSR Reg.)

Selected MCCSR

Timebase

MSB LSB

0 0 2ms 4 59 0 1 4ms 8 53 1 0 10ms 20 35 1 1 25ms 49 54

Value of T[5:0] Bits in

WDGCR Register (Hex.)

Min. Watchdog

Timeout (ms)

min

Max. Watchdog

Timeout (ms)

max

00 1.496 2.048 3F 128 128.552

CNT

MSB

-------------

mintmin0

16384 CNT t

osc2

××+

mintmin0

16384 CNT

4CNT

MSB

-----------------

–

⎝⎠

⎛⎞

× 192 LS B+()64

4CNT

MSB

-----------------

××

+ t

osc2

×+=

CNT

MSB

-------------

≤

maxtmax0

16384 CNT t

osc2

××+=

maxtmax0

16384 CNT

4CNT

MSB

-----------------

–

⎝⎠

⎛⎞

× 192 LS B+()64

4CNT

MSB

-----------------

××

+ t

osc2

×+=

ST72361

Figure 36. Exact Timeout Duration (t

min

and t

max

)

55/225

ST72361

T6 bit

Reset

WDGWR

T[5:0] CNT downcounter

time

Refresh WindowRefresh not allowed

(step = 16384/f

OSC2

)

3Fh

WINDOW WATCHDOG (Cont’d)

Figure 37. Window Watchdog Timing Diagram

10.1.6 Low Power Modes

Mode Description

SLOW No effect on Watchdog: The downcounter continues to decrement at normal speed.

WAIT No effect on Watchdog: The downcounter continues to decrement.

OIE bit in

MCCSR register

HALT

0 0

0 1 A reset is generated instead of entering halt mode.

ACTIVE HALT

10.1.7 Hardware Watchdog Option

1 x

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description.

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external inter rupt or a reset.

If an interrupt is received (refer to interrupt table mapping to see interrupts which can occur in halt mode), the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For applica tion recommendations see Section 0.1.8 below.

No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting im mediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.

10.1.8 Using Halt Mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcon troller.

56/225

WINDOW WATCHDOG (Cont’d)

10.1.9 Interrupts

None.

10.1.10 Register Description CONTROL REGISTER (WDGCR)

Read / Write Reset Value: 0111 1111 (7F h)

7 0

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by

hardware after a reset. When WDGA

= 1, the

watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watch-

dog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog counter. It is decremented every 16384 f

OSC2

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

ST72361

WINDOW REGISTER (WDGWR)

Read/Write Reset Value: 0111 1111 (7Fh)

7 0

- W6 W5 W4 W3 W2 W1 W0

Bit 7 = Reserved Bits 6:0 = W[6:0] 7-bit window value

These bits contain the window value to be compared to the downcounter.

Figure 38. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

Label

WDGCR

Reset Value

WDGWR

Reset Value

7 6 5 4 3 2 1 0

WDGA

57/225

ST72361

DIV 2, 4, 8, 16

MCC/RTC INTERRUPT

SMSCP1 CP0 TB1 TB0 OIE OIF

CPU CLOCK

MCCSR

RTC

COUNTER

TO CPU AND

PERIPHERALS

OSC2

CPU

MCO

WATCHDOG

TIMER

ON-CHIP PERIPHERALS (Cont’d)

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC

The Main Clock Controller consists of three different functions:

■

a programmable CPU clock prescaler

■

a clock-out signal to supply external devices

■

a real time clock timer with interrupt capability

Each function can be used independently and simultaneously.

10.2.1

Programmable CPU Clock Prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal periph erals. It manages SLOW power saving mode (See

Section 8.2 "SLOW MODE" for more details).

The prescaler selects the f

main clock frequen-

CPU

cy and is controlled by three bits in the MCCSR register: CP[1:0] and SMS.

10.2.2

The clock-out capability is an alternate function of an I/O port pin that outputs a f external devices. It is controlled by the MCO bit in the MCCSR register.

10.2.3

The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depend ing directly on f

functionality is controlled by 4 bits of the MCCSR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE HALT mode when the HALT instruction is executed. See

"ACTIVE HALT MODE" for more details.

Clock-out Capability

Real Time Clock Timer (RTC)

Figure 39. Main Clock Controller (MCC/RTC) Block Diagram

clock to drive

OSC2

are available. The whole

OSC2

Section 8.5

58/225

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.4

Low Power Modes

Mode Description

No effect on MCC/RTC peripheral.

WAIT

ACTIVE HALT

HALT and AWUF HALT

MCC/RTC interrupt cause the device to exit from WAIT mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE HALT mode.

MCC/RTC counter and registers are frozen. MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from HALT” capability.

Bits 6:5 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software

in SLOW mode CP1 CP0

CPU

OSC2

Bit 4 = SMS Slow mode select

10.2.5

Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

Time base overflow event

Event

Enable

Control

Flag

OIF OIE Yes No

Bit

Exit from Wait

Exit

from

Halt

Note: The MCC/RTC interrupt wakes up the MCU from

ACTIVE HALT mode, not from HALT or AWUF HALT mode.

10.2.6

Register Description

MCC CONTROL/STATUS REGISTER (MCCSR)

This bit is set and cleared by software. 0: Normal mode. f 1: Slow mode. f See Section 8.2 "SLOW MODE" and Section 10.2

"MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC" for more details.

Bits 3:2 = TB[1:0] Time base control These bits select the programmable divider time

base. They are set and cleared by software.

Counter

Prescaler

16000 4ms 2ms 0 0

32000 8ms 4ms 0 1

80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

Read / Write Reset Value: 0000 0000 (00h)

A modification of the time base is taken into account at the end of the current period (previously

7 0

set) to avoid an unwanted time shift. This allows to use this time base as a real time clock.

/ 2 0 0

OSC2

/ 4 0 1

OSC2

/ 8 1 0

OSC2

/ 16 1 1

= f

OSC2

is given by CP1, CP0

Time Base

=8 MHz

OSC2

CPU

=4 MHz f

ST72361

TB1 TB0

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

Bit 7 = MCO Main clock out selection This bit enables the MCO alternate function on the corresponding I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

OSC2

on I/O

port)

Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from ACTIVE HALT mode. When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE HALT power saving

mode

59/225

ST72361

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached

Table 16. Main Clock Controller Register Map and Reset Values

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.

Address

(Hex.)

002Dh

002Eh

Label

SICSR

Reset Value

MCCSR

Reset Value

7 6 5 4 3 2 1 0

0 AVDIE AVDF LVDRF 0

MCO

CP1

CP0

SMS

TB1

0 0

TB0

OIE

WDGRF

OIF

60/225

ON-CHIP PERIPHERALS (Cont’d)

OVF INTERRUPT

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

ARTCSR

INPUT

PWMx

PORT

FUNCTION

ALTERNATE

OCRx

COMPARE

PROGRAMMABLE

PRESCALER

8-BIT COUNTER

(CAR REGISTER)

ARR

ICRx

LOAD

OPx

POLARITY

CONTROL

OEx

PWMCR

MUX

CPU

DCRx

LOAD

COUNTER

ARTCLK

EXT

ARTICx

ICFxICSx

ICCSR

LOAD

ICx INTERRUPT

ICIEx

INPUT CAPTURE

CONTROL

10.3 PWM AUTO-RELOAD TIMER (ART)

10.3.1 Introduction

The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source.

These resources allow five possible operating modes:

– Generation of up to four independent PWM sig-

nals

Figure 40. PWM Auto-Reload Timer Block Diagram

ST72361

– Output compare and Time base interrupt – Up to two input capture functions – External event detector – Up to two external interrupt sources The three first modes can be used together with a

single counter frequency. The timer can be used to wake up the MCU from

WAIT and HALT modes.

61/225

ST72361

COUNTER

FDh FEh FFh FDh FEh FFh FDh FEh

ARTARR=FDh

COUNTER

OCRx

PWMDCRx

FDh

FEh

FDh

FEh

FFh

PWMx

PWM AUTO-RELOAD TIMER (Cont’d)

10.3.2 Functional Description

Counter

The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris

ing edge of the clock signal. It is possible to read or write the contents of the

counter on the fly by reading or writing the Counter Access register (ARTCAR).

When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected).

Counter clock and prescaler

The counter clock frequency is given by: f

COUNTER

= f

INPUT

The timer counter’s input clock (f

/ 2

CC[2:0]

INPUT

) feeds the 7-bit programmable prescaler, which selects one of the eight available taps of the prescaler, as de

fined by CC[2:0] bits in the Control/Status Register (ARTCSR). Thus the division factor of the prescal

er can be set to 2n (where n = 0, 1,..7).

This f

frequency source is selected through

INPUT

the EXCL bit of the ARTCSR register and can be either the f

or an external input frequency f

CPU

EXT

The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter contents are frozen. When TCE is set, the counter runs at the rate of the selected clock source.

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are cleared and f

INPUT

= f

CPU

. The counter can be initialized by: – Writing to the ARTARR register and then setting

the FCRL (Force Counter Re-Load) and the TCE (Timer Counter Enable) bits in the ARTCSR reg

ister. – Writing to the ARTCAR counter access register, In both cases the 7-bit prescaler is also cleared,

whereupon counting will start from a known value. Direct access to the prescaler is not possible.

Output compare control

The timer compare function is based on four different comparisons with the counter (one for each PWMx output). Each comparison is made be tween the counter value and an output compare register (OCRx) value. This OCRx register can not be accessed directly, it is loaded from the duty cy cle register (PWMDCRx) at each overflow of the counter.

This double buffering method avoids glitch generation when changing the duty cycle on the fly.

Figure 41. Output Compare Control

62/225

PWM AUTO-RELOAD TIMER (Cont’d)

DUTY CYCLE

AUTO-RELOAD

PWMx OUTPUT

255

000

WITH OEx=1 AND OPx=0

(ARTARR)

(PWMDCRx)

WITH OEx=1 AND OPx=1

COUNTER

PWMx OUTPUT

WITH OEx=1

AND OPx=0

FDh FEh FFh FDh FEh FFh FDh FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

ARTARR=FDh

COUNTER

ST72361

Independent PWM signal generation

This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode.

Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as out

put push-pull alternate function. The PWM signals all have the same frequency

which is controlled by the counter period and the ARTARR register value.

PWM

= f

COUNTER

/ (256 - ARTARR)

When a counter overflow occurs, the PWMx pin level is changed depending on the corresponding OPx (output polarity) bit in the PWMCR register.

Figure 42. PWM Auto-reload Timer Function

When the counter reaches the value contained in one of the output compare register (OCRx) the corresponding PWMx pin level is restored.

It should be noted that the reload values will also affect the value and the resolution of the duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the OCRx register must be greater than the contents of the ARTARR reg

ister. The maximum available resolution for the PWMx

duty cycle is: Resolution = 1 / (256 - ARTARR) Note: To get the maximum resolution (1/256), the

ARTARR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.

Figure 43. PWM Signal from 0% to 100% Duty Cycle

63/225

ST72361

COUNTER

FDh FEh FFh FDh

OVF

ARTCSR READ

INTERRUPT

ARTARR=FDh

EXT=fCOUNTER

FEh FFh FDh

IF OIE=1

INTERRUPT

IF OIE=1

ARTCSR READ

PWM AUTO-RELOAD TIMER (Cont’d)

Output compare and Time base interrupt

On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generat ed if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be re set by the user software. This interrupt can be used as a time base in the application.

External clock and event detector mode

Using the f

auto-reload timer can be used as an external clock event detector. In this mode, the ARTARR register

is used to select the n be counted before setting the OVF flag.

EVENT

Caution: The external clock function is not available in HALT mode. If HALT mode is used in the application, prior to executing the HALT instruction, the counter must be disabled by clearing the TCE bit in the ARTCSR register to avoid spurious coun ter increments.

Figure 44. External Event Detector Example (3 counts)

external prescaler input clock, the

EXT

EVENT

= 256 - ARTARR

number of events to

64/225

PWM AUTO-RELOAD TIMER (Cont’d)

04h

COUNTER

01h

COUNTER

xxh

02h 03h 05h 06h 07h

05h

ARTICx PIN

CFx FLAG

ICAP SAMPLED

INTERRUPT

CPU

ICAP SAMPLED

ST72361

Input Capture Function

Input Capture mode allows the measurement of external signal pulse widths through ARTICRx registers.

Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status regis

ter (ARTICCSR). These input capture interrupts are enabled

through the CIEx bits of the ARTICCSR register. The active transition (falling or rising edge) is soft-

ware programmable through the CSx bits of the ARTICCSR register.

The read only input capture registers (ARTICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register). After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.

Note: After a capture detection, data transfer in the ARTICRx register is inhibited until the next read (clearing the CFx bit). The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled (CIEx bit

set). This means, the ARTICRx register has to be read at each capture event to clear the CFx flag.

The timing resolution is given by auto-reload counter cycle time (1/f

COUNTER

Note: During HALT mode, input capture is inhibited (the ARTICRx is never reloaded) and only the external interrupt capability can be used.

Note: The ARTICx signal is synchronized on CPU clock. It takes two rising edges until ARTICRx is latched with the counter value. Depending on the prescaler value and the time when the ICAP event occurs, the value loaded in the ARTICRx register may be different.

If the counter is clocked with the CPU clock, the value latched in ARTICRx is always the next coun ter value after the event on ARTICx occurred (Fig-

ure 45).

If the counter clock is prescaled, it depends on the position of the ARTICx event within the counter cy cle (Figure 46).

Figure 45. Input Capture Timing Diagram, f

COUNTER

= f

CPU

65/225

ST72361

04h

COUNTER

xxh

03h

04h

ARTICx PIN

CFx FLAG

ICRx REGISTER

INTERRUPT

CPU

ICAP SAMPLED

05h

04h

COUNTER

xxh

03h

05h

ARTICx PIN

CFx FLAG

ICRx REGISTER

INTERRUPT

CPU

ICAP SAMPLED

05h

ARTICx PIN

CFx FLAG

INTERRUPT

PWM AUTO-RELOAD TIMER (Cont’d)

Figure 46. input Capture Timing Diagram, f

COUNTER

= f

CPU

/ 4

External Interrupt Capability

This mode allows the Input capture capabilities to be used as external interrupt sources. The inter rupts are generated on the edge of the ARTICx signal.

The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR register) and they are independently enabled through CIEx bits of the ARTICCSR register. After fetching the interrupt vector, the CFx flags can be read to iden tify the interrupt source.

During HALT mode, the external interrupts can be used to wake up the micro (if the CIEx bit is set). In

66/225

this case, the interrupt synchronization is done di rectly on the ARTICx pin edge (Figure 47).

Figure 47. ART External Interrupt in Halt Mode

ON-CHIP PERIPHERALS (Cont’d)

10.3.3 Register Description

ST72361

CONTROL / STATUS REGISTER (ARTCSR)

Read / Write Reset Value: 0000 0000 (00h)

7 0

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock.

Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from f

COUNTER

INPUT

/ 2 / 4

/ 8 / 16 / 32 / 64

/ 128

With f

=8 MHz CC2 CC1 CC0

INPUT

8 MHz 4 MHz 2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

62.5 kHz

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

INPUT

0 1 0 1 0 1 0 1

0: New transition not yet reached 1: Transition reached

COUNTER ACCESS REGISTER (ARTCAR)

Read / Write Reset Value: 0000 0000 (00h)

7 0

CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hard-

ware or by software. The ARTCAR register is used to read or write the auto-reload counter “on the fly” (while it is counting).

AUTO-RELOAD REGISTER (ARTARR)

Read / Write Reset Value: 0000 0000 (00h)

7 0

AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

Bit 3 = TCE Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running.

Bit 2 = FCRL Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logical zero. When set, it causes the contents of ARTARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count.

Bit 1 = OIE Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable.

Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the tran

sition of the counter from FFh to the ARTARR value.

Bit 7:0 =

AR[7:0]

Counter Auto-Reload Data

These bits are set and cleared by software. They are used to hold the auto-reload value which is au tomatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register.

This register has two PWM management functions:

– Adjusting the PWM frequency – Setting the PWM duty cycle resolution

PWM Frequency vs Resolution:

ARTARR

value

0 8-bit ~0.244 kHz 31.25 kHz

[ 0..127 ] > 7-bit ~0.244 kHz 62.5 kHz [ 128..191 ] > 6-bit ~0.488 kHz 125 kHz [ 192..223 ] > 5-bit ~0.977 kHz 250 kHz [ 224..239 ] > 4-bit ~1.953 kHz 500 kHz

Resolution

PWM

Min Max

67/225

ST72361

ON-CHIP PERIPHERALS (Cont’d)

PWM CONTROL REGISTER (PWMCR)

Read / Write Reset Value: 0000 0000 (00h)

7 0

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels inde pendently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled.

Bit 3:0 = OP[3:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the four PWM output signals.

PWMx output level

Counter <= OCRx Counter > OCRx

1 0 0 0 1 1

OPx

Note: When an OPx bit is modified, the PWMx out-

put signal polarity is immediately reversed.

DUTY CYCLE REGISTERS (PWMDCRx)

Read / Write Reset Value: 0000 0000 (00h)

7 0

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

Bit 7:0 = DC[7:0] Duty Cycle Data These bits are set and cleared by software.

A PWMDCRx register is associated with the OCRx

register of each PWM channel to determine the second edge location of the PWM signal (the first edge location is common to all channels and given by the ARTARR register). These PWMDCR regis ters allow the duty cycle to be set independently for each PWM channel.

68/225

ON-CHIP PERIPHERALS (Cont’d)

ST72361

INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR)

Read / Write Reset Value: 0000 0000 (00h)

7 0

0 0 CS2 CS1 CIE2 CIE1 CF2 CF1

Bit 7:6 = Reserved, always read as 0.

Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corre sponding input capture channel. 0: Falling edge triggers capture on channel x. 1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable These bits are set and cleared by software. They enable or disable the Input capture channel inter rupts independently. 0: Input capture channel x interrupt disabled. 1: Input capture channel x interrupt enabled.

INPUT CAPTURE REGISTERS (ARTICRx)

Read only Reset Value: 0000 0000 (00h)

7 0

IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

Bit 7:0 = IC[7:0] Input Capture Data These read only bits are set and cleared by hard-

ware. An ARTICRx register contains the 8-bit auto-reload counter value transferred by the input capture channel x event.

Bit 1:0 = CF[2:1] Capture Flag These bits are set by hardware and cleared by software reading the corresponding ARTICRx reg

ister. Each CFx bit indicates that an input capture x has occurred. 0: No input capture on channel x. 1: An input capture has occurred on channel x.

69/225

ST72361

PWM AUTO-RELOAD TIMER (Cont’d)

Table 17. PWM Auto-Reload Timer Register Map and Reset Values

Address

(Hex.)

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

Label

PWMDCR3

Reset Value

PWMDCR2

Reset Value

PWMDCR1

Reset Value

PWMDCR0

Reset Value

PWMCR

Reset Value

ARTCSR

Reset Value

ARTCAR

Reset Value

ARTARR

Reset Value

ARTICCSR

Reset Value

ARTICR1

Reset Value

ARTICR2

Reset Value

7 6 5 4 3 2 1 0

DC7

OE3

EXCL

CA7

AR7

0 0

IC7

DC6

OE2

CC2

CA6

AR6

IC6

DC5

OE1

CC1

CA5

AR5

CE2

IC5

DC4

OE0

CC0

CA4

AR4

CE1

IC4

DC3

OP3

TCE

CA3

AR3

CS2

IC3

DC2

OP2

FCRL

CA2

AR2

CS1

IC2

DC1

OP1

RIE

CA1

AR1

CF2

IC1

DC0

OP0

OVF

CA0

AR0

CF1

IC0

70/225

10.4 16-BIT TIMER

ST72361

10.4.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input sig

nals (input capture) or generation of up to two output waveforms (output compare and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequen

cies are not modified. This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

10.4.2 Main Features

■ Programmable prescaler: f

■ Overflow status flag and maskable interrupt

■ External clock input (must be at least four times

slower than the CPU

clock speed) with the choice

divided by 2, 4 or 8

CPU

of active edge

■ 1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ 1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One Pulse mode

■ Reduced Power Mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

10.4.3 Functional Description

10.4.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS

Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit tim

er). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 17 Clock

Control Bits. The value in the counter register re

peats every 131072, 262144 or 524288 CPU clock

/2, f

CPU

/4, f

CPU

cycles depending on the CC[1:0] bits. The timer frequency can be f

CPU

or an external frequency.

The Block Diagram is shown in Figure 48. *Note: Some timer pins may not be available (not

bonded) in some ST7 devices. Refer to the device pin out description.

71/225

ST72361

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE

OUTPUT COMPARE

EDGE DETECT

OVERFLOW

DETECT

CIRCUIT

1/2 1/4

1/8

8-bit

buffer

ST7 INTERNAL BUS

LATCH1

OCMP1

ICAP1

EXTCLK

CPU

TIMER INTERRUPT

ICF2ICF1

TIMD

OCF2OCF1 TOF

PWMOC1E

EXEDG

IEDG2CC0CC1

OC2E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOI E

ICAP2

LATCH2

OCMP2

8 low

8 high

16 16

(Control Register 1) CR1

(Control Register 2) CR2

(Control/Status Register)

8 8 8

88 8

high

low

high

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

OUTPUT

COMPARE

INPUT

CAPTURE

INPUT

CAPTURE

CC[1:0]

COUNTER

Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)

(See note)

CSR

16-BIT TIMER (Cont’d)

Figure 48. Timer Block Diagram

72/225

16-BIT TIMER (Cont’d)

is buffered

Read

At t0

Read

Returns the buffered

LS Byte value at t0

At t0 +Δt

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS Byte

16-bit read sequence: (from either the Counter Register or the Alternate Counter Register).

The user must read the MS Byte first, then the LS Byte value is buffered automatically.

This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they re

turn the LS Byte of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.

ST72361

Clearing the overflow interrupt request is done in two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with out the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

10.4.3.2 External Clock

The external clock (where available) is selected if

= 1 and CC1 = 1 in the CR2 register.

CC0 The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter nal clock pin EXTCLK that will trigger the free running counter.

The counter is synchronized with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre quency must be less than a quarter of the CPU clock frequency.

73/225

ST72361

CPU CLOCK

FFFD

FFFE FFFF 0000 0001 0002 0003

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD

0000

16-BIT TIMER (Cont’d)

Figure 49. Counter Timing Diagram, Internal Clock Divided by 2

Figure 50. Counter Timing Diagram, Internal Clock Divided by 4

Figure 51. Counter Timing Diagram, Internal Clock Divided By 8

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

74/225

16-BIT TIMER (Cont’d)

10.4.3.3 Input Capture

In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer.

The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free run

ning counter after a transition is detected on the ICAPi pin (see Figure 52).

MS Byte LS Byte

ICiR ICiHR ICiLR

ICiR register is a read-only register. The active transition is software programmable

through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running

counter: (

CPU

/CC[1:0]).

Procedure:

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 17

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is

available). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin – Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input or input with pull-

up without interrupt if this configuration is availa

ble).

ST72361

When an input capture occurs: – ICFi bit is set. – The ICiR register contains the value of the free

running counter on the active transition on the ICAPi pin (see Figure 53).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other wise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Notes:

1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read.

2. The ICiR register contains the free running counter value which corresponds to the most recent input capture.

3. The two input capture functions can be used together even if the timer also uses the two out put compare functions.

4. In One Pulse mode and PWM mode only Input Capture 2 can be used.

5. The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user tog gles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).

75/225

ST72361

ICIE

CC0

CC1

16-BIT FREE RUNNING

COUNTER

IEDG1

(Control Register 1) CR1

(Control Register 2) CR2

ICF2ICF1 000

(Status Register) SR

IEDG2

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

16-BIT

IC1R Register

IC2R Register

EDGE DETECT

CIRCUIT1

FF01 FF02 FF03

FF03

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: The rising edge is the active edge.

16-BIT TIMER (Cont’d)

Figure 52. Input Capture Block Diagram

Figure 53. Input Capture Timing Diagram

76/225

16-BIT TIMER (Cont’d)

Δ OCiR =

Δt * f

CPU

PRESC

Δ OCiR = Δt

* fEXT

10.4.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16bit timer.

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.

MS Byte LS Byte

OCiR OCiHR OCiLR

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

iR value to 8000h.

Timing resolution is one count of the free running counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i signal.

– Select the timer clock (CC[1:0]) (see Table 17

Clock Control Bits).

And select the following in the CR1 register: – Select the OLVLi bit to applied to the OCMPi pins

after the match occurs. – Set the OCIE bit to generate an interrupt if it is

needed. When a match is found between OCiR register

and CR register: – OCFi bit is set.

ST72361

– The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in the CC register (CC).

The OCiR register value required for a specific timing application can be calculated using the following formula:

Where:

Δt = Output compare period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 17

Clock Control Bits)

If the timer clock is an external clock, the formula is:

Where:

Δt = Output compare period (in seconds)

= External timer clock frequency (in hertz)

EXT

Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OC

– Write to the OCiHR register (further compares

are inhibited).

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

– Write to the OCiLR register (enables the output

compare function and clears the OCFi bit).

iR register:

77/225

ST72361

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E CC0CC1

OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2

FOLV1

16-BIT TIMER (Cont’d) Notes:

1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3. In both internal and external clock modes, OCFi and OCMPi are set while the counter

CPU

value equals the OCiR register value (see Fig

ure 55 on page 80 for an example with f

and Figure 56 on page 80 for an example with

/4). This behavior is the same in OPM or

CPU

PWM mode.

4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used.

5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each suc cessful comparison in order to control an output waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit

= 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both One Pulse mode and PWM mode.

Figure 54. Output Compare Block Diagram

78/225

16-BIT TIMER (Cont’d)

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi =1)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

2ED3

2ED0 2ED1 2ED2

2ED3

2ED42ECF

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi =1)

ST72361

Figure 55. Output Compare Timing Diagram, f

Figure 56. Output Compare Timing Diagram, f

TIMER

= f

CPU

79/225

ST72361

event occurs

Counter = OC1R

OCMP1 = OLVL1

When

on ICAP1

One Pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

OCiR Value =

CPU

PRESC

- 5

OCiR = t

* fEXT

-5

16-BIT TIMER (Cont’d)

10.4.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The One Pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use One Pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 17

Clock Control Bits).

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific

timing application can be calculated using the fol lowing formula:

Where: t = Pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 17

Clock Control Bits)

If the timer clock is an external clock the formula is:

Where: t = Pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 57).

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the val ue FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

80/225

Notes:

1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an out put waveform because the level OLVL2 is dedicated to the One Pulse mode.

ST72361

COUNTER

FFFC FFFD FFFE 2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2

OLVL2OLVL1

ICAP1

OCMP1

compare1

Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1

01F8

2ED3

IC1R

COUNTER

34E2

34E2 FFFC

OLVL2

OLVL2OLVL1

OCMP1

compare2 compare1 compare2

Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

FFFC FFFD FFFE

2ED0

2ED1

2ED2

16-BIT TIMER (Cont’d)

Figure 57. One Pulse Mode Timing Example

Figure 58. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be generated

using the output compare and the counter overflow to define the pulse length.

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ST72361

Counter

OCMP1 = OLVL2

Counter = OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

OCiR Value =

CPU

PRESC

- 5

OCiR = t

* fEXT

-5

16-BIT TIMER (Cont’d)

10.4.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers.

Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R regis ter, and so this functionality can not be used when PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values writ ten in the OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).

Procedure

To use Pulse Width Modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1

= 0 and OLVL2 = 1) using the formula

in the opposite column.

3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with the OC2R register.

4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 17

Clock Control Bits).

If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers.

If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.

The OCiR register value required for a specific timing application can be calculated using the following formula:

Where: t = Signal or pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 17 Clock

Control Bits)

If the timer clock is an external clock the formula is:

Where: t = Signal or pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 58)

Notes:

1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written.

2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is discon

nected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.

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16-BIT TIMER (Cont’d)

10.4.4 Low Power Modes

Mode Description

WAIT

HALT

No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.

10.4.5 Interrupts

Interrupt Event

Input Capture 1 event/Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 Timer Overflow event TOF TOIE

Event

Flag

Enable

Control

Bit

ICIE

OCIE

ST72361

Exit from Wait

Yes No

Exit

from

Halt

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

10.4.6 Summary of Timer Modes

MODES

Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode PWM Mode Not Recommended

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

Yes Yes Yes Yes

Not Recommended

TIMER RESOURCES

Partially

1) See note 4 in Section 10.4.3.5 "One Pulse Mode"

2) See note 5 in Section 10.4.3.5 "One Pulse Mode"

3) See note 4 in Section 10.4.3.6 "Pulse Width Modulation Mode"

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16-BIT TIMER (Cont’d)

10.4.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al ternate counter.

Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison.

CONTROL REGISTER 1 (CR1)

Read/Write Reset Value: 0000 0000 (00h)

7 0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc cessful comparison.

Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg ister and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode.

Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.

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16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2)

Read/Write Reset Value: 0000 0000 (00h)

7 0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

ST72361

Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R regis ter.

Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Com pare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer re mains active. 0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Com pare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer re mains active. 0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM One Pulse Mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.

Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits:

Table 18. Clock Control Bits

Timer Clock CC1 CC0

External Clock (where available) 1

/ 4

CPU

/ 2 1

CPU

/ 8

CPU

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

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ST72361

16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR)

Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh)

7 0

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0

Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) reg ister.

Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg ister, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register.

Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has

matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) reg

ister.

Bit 2 = TIMD Timer disable. This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disa

bled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

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16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

ST72361

OUTPUT COMPARE 1 HIGH REGISTER (OC1HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

7 0

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the in put capture 1 event).

7 0

MSB LSB

7 0

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER (OC1LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

7 0

MSB LSB

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ST72361

16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

ALTERNATE COUNTER HIGH REGISTER (ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7 0

MSB LSB

OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

7 0

MSB LSB

COUNTER HIGH REGISTER (CHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7 0

MSB LSB

7 0

MSB LSB

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register.

7 0

MSB LSB

INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only

Reset Value: Undefined This is an 8-bit read only register that contains the

high part of the counter value (transferred by the Input Capture 2 event).

COUNTER LOW REGISTER (CLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.

7 0

MSB LSB

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7 0

MSB LSB

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the In put Capture 2 event).

7 0

MSB LSB

16-BIT TIMER (Cont’d)

Table 19. 16-Bit Timer Register Map

ST72361

Address

(Hex.)

51 CR2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

52 CR1 ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

53 CSR ICF1 OCF1 TOF ICF2 OCF2 TIMD

54 IC1HR MSB LSB

55 IC1LR MSB LSB

56 OC1HR MSB LSB

57 OC1LR MSB LSB

58 CHR MSB LSB

59 CLR MSB LSB

5A ACHR MSB LSB

5B ACLR MSB LSB

5C IC2HR MSB LSB

5D IC2LR MSB LSB

5E OC2HR MSB LSB

5F OC2LR MSB LSB

Name

7 6 5 4 3 2 1 0

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ST72361

10.5 8-BIT TIMER (TIM8)

10.5.1 Introduction

The timer consists of a 8-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input sig nals (input capture) or generation of up to two output waveforms (output compare and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the clock prescaler.

10.5.2 Main Features

■ Programmable prescaler: f

or f

■ Overflow status flag and maskable interrupt

■ Output compare functions with

divided by 8000.

OSC2

divided by 2, 4 , 8

CPU

– 2 dedicated 8-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Input capture functions with

– 2 dedicated 8-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Pulse width modulation mode (PWM)

■ One pulse mode

■ Reduced Power Mode

■ 4 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2)*

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

10.5.3 Functional Description

10.5.3.1 Counter

The main block of the Programmable Timer is a 8-

bit free running upcounter and its associated 8-bit registers.

These two read-only 8-bit registers contain the same value but with the difference that reading the ACTR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR).

Writing in the CTR register or ACTR register resets the free running counter to the FCh value. Both counters have a reset value of FCh (this is the only value which is reloaded in the 8-bit timer). The reset value of both counters is also FCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits of the CR2 register, as shown in Table 19 Clock

Control Bits. The value in the counter register re

peats every 512, 1024, 2048 or 20480000 f clock cycles depending on the CC[1:0] bits. The timer frequency can be f or f

For example, if f f

OSC2

/8000.

OSC2

/8000 is selected, and

OSC2

= 8 MHz, the timer frequency will be 1 ms.

CPU

/2, f

CPU

Refer to Table 19 on page 105.

/4, f

CPU

The Block Diagram is shown in Figure 59. *Note: Some timer pins may not be available (not

bonded) in some ST7 devices. Refer to the device pin out description.

90/225

8-BIT TIMER (Cont’d)

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE

OUTPUT COMPARE

EDGE DETECT

OVERFLOW

DETECT CIRCUIT

1/2 1/4 1/8

ST7 INTERNAL BUS

LATCH1

OCMP1

ICAP1

CPU

TIMER INTERRUPT

ICF2ICF1

TIMD

OCF2OCF1 TOF

PWMOC1E

IEDG2CC0CC1

OC2E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE

ICAP2

LATCH2

OCMP2

8 8

(Control Register 1) CR1

(Control Register 2) CR2

(Control/Status Register)

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

OUTPUT COMPARE REGISTER

INPUT CAPTURE REGISTER

INPUT

CAPTURE

CC[1:0]

COUNTER

Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)

(See note)

CSR

1/8000

OSC2

Figure 59. Timer Block Diagram

ST72361

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ST72361

8-BIT TIMER (Cont’d)

Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFh to 00h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.

Clearing the overflow interrupt request is done in two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CTR register.

Notes: The TOF bit is not cleared by accesses to ACTR register. The advantage of accessing the ACTR register rather than the CTR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with out the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

92/225

8-BIT TIMER (Cont’d)

CPU

CLOCK

FE FF 00 01 02 03

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FC FD 00 01

CPU

CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

CPU

CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FC FD

Figure 60. Counter Timing Diagram, Internal Clock Divided by 2

Figure 61. Counter Timing Diagram, Internal Clock Divided by 4

ST72361

Figure 62. Counter Timing Diagram, Internal Clock Divided by 8

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

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ST72361

8-BIT TIMER (Cont’d)

10.5.3.2 Input Capture

In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 8-bit timer.

The two 8-bit input capture registers (IC1R and IC2R) are used to latch the value of the free run ning counter after a transition is detected on the ICAPi pin (see Figure 63).

ICiR register is a read-only register. The active transition is software programmable

through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running

counter (see Table 19 Clock Control Bits).

When an input capture occurs: – ICFi bit is set. – The ICiR register contains the value of the free

running counter on the active transition on the ICAPi pin (see Figure 64).

– A timer interrupt is generated if the ICIE bit is set

and the interrrupt mask is cleared in the CC reg ister. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiR register.

Procedure:

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 19

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is

available). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin – Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input or input with

pull-up without interrupt if this configuration is

available).

Notes:

1. The ICiR register contains the free running counter value which corresponds to the most re cent input capture.

2. The two input capture functions can be used together even if the timer also uses the two output compare functions.

3. Once the ICIE bit is set both input capture features may trigger interrupt requests. If only one is needed in the application, the interrupt routine software needs to discard the unwanted capture interrupt. This can be done by checking the ICF1 and ICF2 flags and resetting them both.

4. In One pulse Mode and PWM mode only Input Capture 2 can be used.

5. The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function.

Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an inter rupt can be generated if the user toggles the output pin and if the ICIE bit is set.

6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFh).

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8-BIT TIMER (Cont’d)

ICIE

CC0

CC1

8-bit FREE RUNNING

COUNTER

IEDG1

(Control Register 1) CR1

(Control Register 2) CR2

ICF2ICF1 000

(Status Register) SR

IEDG2

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

8-bit

IC1R Register

IC2R Register

EDGE DETECT

CIRCUIT1

01 02 03

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: The rising edge is the active edge.

Figure 63. Input Capture Block Diagram

ST72361

Figure 64. Input Capture Timing Diagram

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ST72361

Δ OCiR =

Δt * f

CPU

PRESC

8-BIT TIMER (Cont’d)

10.5.3.3 Output Compare

In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 8-bit timer.

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCiE bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 8-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

Timing resolution is one count of the free running counter: (f

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i signal.

– Select the timer clock (CC[1:0]) (see Table 19

Clock Control Bits).

And select the following in the CR1 register:

iR value to 00h.

CPU/CC[1:0]

– Select the OLVLi bit to applied to the OCMPi pins

after the match occurs.

– Set the OCIE bit to generate an interrupt if it is

needed.

When a match is found between OCRi register and CR register:

– OCFi bit is set. – The OCMPi pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in the CC register (CC).

The OCiR register value required for a specific timing application can be calculated using the following formula:

Where:

Δt = Output compare period (in seconds)

= PLL output x2 clock frequency in hertz

CPU

(or f

PRESC

= Timer prescaler factor (2, 4, 8 or 8000

depending on CC[1:0] bits, see Table

19 Clock Control Bits)

Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiR register.

/2 if PLL is not enabled)

OSC

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8-BIT TIMER (Cont’d)

OUTPUT COMPARE

8-bit

CIRCUIT

OC1R Register

8 BIT FREE RUNNING

COUNTER

OC1E CC0CC1

OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status Register) SR

8-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

Notes:

1. Once the OCIE bit is set both output compare features may trigger interrupt requests. If only one is needed in the application, the interrupt routine software needs to discard the unwanted compare interrupt. This can be done by check

ing the OCF1 and OCF2 flags and resetting them both.

2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f

/2, OCFi and

CPU

OCMPi are set while the counter value equals the OCiR register value (see Figure 66 on page

99). This behaviour is the same in OPM or

PWM mode. When the timer clock is f 8000, OCFi and OCMPi are set while the coun

CPU

/4, f

CPU

/8 or f

CPU

ter value equals the OCiR register value plus 1 (see Figure 67 on page 99).

4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used.

5. The value in the 8-bit OCiR register and the OLVi bit should be changed after each suc

ST72361

cessful comparison in order to control an output waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit

= 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both one pulse mode and PWM mode.

Figure 65. Output Compare Block Diagram

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ST72361

CPU

CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi =1)

D0 D1 D2

D4CF

CPU

CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

D0 D1 D2

D4CF

OCMPi PIN (OLVLi =1)

OUTPUT COMPARE FLAG i (OCFi)

8-BIT TIMER (Cont’d)

Figure 66. Output Compare Timing Diagram, f

Figure 67. Output Compare Timing Diagram, f

TIMER

= f

CPU

98/225

8-BIT TIMER (Cont’d)

event occurs

Counter = OC1R

OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FCh

ICF1 bit is set

ICR1 = Counter

OCiR Value =

* fCPU

PRESC

- 5

10.5.3.4 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 19

Clock Control Bits).

Then, on a valid event on the ICAP1 pin, the counter is initialized to FCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

ST72361

Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific

timing application can be calculated using the fol lowing formula:

Where: t = Pulse period (in seconds)

= PLL output x2 clock frequency in hertz

CPU

PRESC

(or f

= Timer prescaler factor (2, 4, 8 or 8000

depending on the CC[1:0] bits, see Ta

/2 if PLL is not enabled)

OSC

ble 19 Clock Control Bits)

When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 68).

Notes:

1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an out put waveform because the level OLVL2 is dedicated to the one pulse mode.

99/225

ST72361

COUNTER

FD FE D0

FC FD

OLVL2

OLVL2OLVL1

ICAP1

OCMP1

compare1

Note: IEDG1 = 1, OC1R = D0h, OLVL1 = 0, OLVL2 = 1

IC1R

COUNTER

E2 FC

OLVL2

OLVL2OLVL1

OCMP1

compare2 compare1 compare2

Note: OC1R = D0h, OC2R = E2, OLVL1 = 0, OLVL2 = 1

FC FD FE

D0 D1 D2

8-BIT TIMER (Cont’d)

Figure 68. One Pulse Mode Timing Example

Figure 69. Pulse Width Modulation Mode Timing Example

100/225

ST ST72361 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 DESCRIPTION

2 PIN DESCRIPTION

3 REGISTER AND MEMORY MAP

4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

4.2 MAIN FEATURES

4.3 STRUCTURE

4.3.1 Read-out Protection

4.4 ICC INTERFACE

4.5 ICP (IN-CIRCUIT PROGRAMMING)

4.6 IAP (IN-APPLICATION PROGRAMMING)

4.7 RELATED DOCUMENTATION

4.8 REGISTER DESCRIPTION

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

5.2 MAIN FEATURES

5.3 CPU REGISTERS

6 SUPPLY, RESET AND CLOCK MANAGEMENT

6.1 PHASE LOCKED LOOP

6.2 MULTI-OSCILLATOR (MO)

6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

6.3.2 Asynchronous External RESET pin

6.3.3 External Power-On RESET

6.3.4 Internal Low Voltage Detector (LVD) RESET

6.3.5 Internal Watchdog RESET

6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

6.4.1 Low Voltage Detector (LVD)

6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on

6.4.2.1 Monitoring the VDD Main Supply

6.4.3 Low Power Modes

6.4.3.1 Interrupts

6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

7 INTERRUPTS

7.1 INTRODUCTION

7.2 MASKING AND PROCESSING FLOW

7.3 INTERRUPTS AND LOW POWER MODES

7.4 CONCURRENT & NESTED MANAGEMENT

7.5 INTERRUPT REGISTER DESCRIPTION

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

7.6.2 Register Description EXTERNAL INTERRUPT CONTROL

8 POWER SAVING MODES

8.1 INTRODUCTION

8.2 SLOW MODE

8.3 WAIT MODE

8.4 HALT MODE

8.5 ACTIVE HALT MODE

8.6 AUTO WAKE-UP FROM HALT MODE

8.6.1 Register Description AWUFH CONTROL/STATUS REGISTER

9 I/O PORTS

9.1 INTRODUCTION

9.2 FUNCTIONAL DESCRIPTION

9.2.1 Input Modes

9.2.2 Output Modes

9.2.3 Alternate Functions

9.3 I/O PORT IMPLEMENTATION

9.4 LOW POWER MODES

9.5 INTERRUPTS

9.6 I/O PORT REGISTER CONFIGURATIONS

9.6.1 Standard Ports

9.6.2 Interrupt Ports PA0,2,4,6; PB0,2,4; PC1; PD0,6 (with pull-up)

9.6.3 Pull-up Input Port PC4

10 ON-CHIP PERIPHERALS

10.1 WINDOW WATCHDOG (WWDG)

10.1.1 Introduction

10.1.2 Main Features

10.1.3 Functional Description

10.1.4 Using Halt Mode with the WDG

10.1.5 How to Program the Watchdog Timeout

10.1.6 Low Power Modes

10.1.7 Hardware Watchdog Option

10.1.8 Using Halt Mode with the WDG (WDGHALT option)

10.1.9 Interrupts

10.1.10 Register Description CONTROL REGISTER (WDGCR)

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK MCC/RTC