ST ST72344K2, ST72344K4, ST72344S2, ST72344S4, ST72345C4 User Manual

ST72344xx, ST72345xx

8-bit MCU with up to 16 Kbytes Flash memory, 10-bit ADC, two 16-bit timers, two I2C, SPI, SCI

Features

■Memories

–up to 16 Kbytes Program memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10,000 write/erase cycles guaranteed, data retention: 20 years at 55 °C.

–up to 1 Kbyte RAM

–256 bytes data EEPROM with readout protection. 300,000 write/erase cycles guaranteed, data retention: 20 years at 55 °C.

■Clock, reset and supply management

–Power on / power off safe reset with

3 programmable threshold levels (LVD)

–Auxiliary voltage detector (AVD)

–Clock sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock

–PLL for 4x or 8x frequency multiplication

–5 power-saving modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt

–Clock output capability (fCPU)

■Interrupt management

–Nested interrupt controller

–10 interrupt vectors plus TRAP and RESET

–9 external interrupt lines on 4 vectors

■Up to 34 I/O ports

–up to 34 multifunctional bidirectional I/O lines

Datasheet −production data

LQFP48	LQFP32	LQFP44
7 x 7 mm	7 × 7 mm	10 × 10 mm

–16-bit timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes

■3 communication interfaces

–I2C multimaster / slave

–I2C slave 3 addresses, no stretch, with DMA access and byte pair coherency on I²C read

–SCI asynchronous serial interface (LIN compatible)

–SPI synchronous serial interface

■1 analog peripheral

–10-bit ADC with 12 input channels (8 on 32pin devices)

■Instruction set

–8-bit data manipulation

–63 basic instructions with illegal opcode detection

–17 main addressing modes

–8 x 8 unsigned multiply instruction

■Development tools

–Full hardware/software development package

–On-chip debug module

–up to 12 high sink outputs (10 on 32-pin devices)

■4 timers

–Configurable window watchdog timer

–Real-time base

–16-bit timer A with: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes

Table 1. Device summary

References

Part numbers

ST72344xx

ST72344K2, ST72344K4,

ST72344S2, ST72344S4

ST72345xx ST72345C4

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Contents	ST72344xx, ST2345xx

Contents

1	Description .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			17
3	Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			23
4	Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			27
	4.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	4.2	Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	4.3	Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
		4.3.1	In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
		4.3.2	In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
	4.4	ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	4.5	Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
		4.5.1	Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
		4.5.2	Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	4.6	Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
		4.6.1	Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
5	Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			31

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.2 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.3 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.7.1 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 35

Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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	6.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	6.2	Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
	6.3	CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	36
		6.3.1 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
		6.3.2 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
7	Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . .		41

7.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 Multioscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4	Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		45
	7.4.1	RC control register (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
	7.4.2	RC control register (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46

7.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5.4 Internal low-voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 48 7.5.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6.1 Low-voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.6.2 Auxiliary-voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8	Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		53
	8.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	8.2	Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	8.3	Interrupts and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
	8.4	Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
	8.5	Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57

8.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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8.5.2 Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 58

8.6	External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		60
	8.6.1	I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60

8.7 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 61

9	Power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		64
	9.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64
	9.2	Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
	9.3	Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
	9.4	Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
	9.5	Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	68
	9.6	Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
	9.7	Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	72
		9.7.1 AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . .	72
		9.7.2 AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . .	73
10	I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		74

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.5.1 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11	On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82
	11.1 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	82

11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.1.4 Using Halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.1.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 84 11.1.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.1.7 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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11.1.8 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 87 11.1.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.1.10 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.2Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 88

11.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.3 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.2.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.3.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.4.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.4.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.5 SCI serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.5.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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11.6 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.6.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.6.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

11.7 I2C triple slave interface with DMA (I2C3S) . . . . . . . . . . . . . . . . . . . . . . 167

11.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.7.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.7.5 Address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11.7.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.7.7 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.8 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

185

11.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.8.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.8.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.8.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12	Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	190
	12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	190

12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 12.1.7 Relative Mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

12.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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13	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 199
	13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 199

13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 13.4 Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 13.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13.6.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 210

13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 13.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

13.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 213 13.8.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 13.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 214

	13.9	I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	215
	13.10	Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	222
		13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 222
	13.11	Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . .	224
		13.11.1 I2C and I²C3SNS interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 224
	13.12	10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	225
14	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		227

14.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

15 Device configuration and ordering information . . . . . . . . . . . . . . . . . 232

15.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

15.1.1 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 15.1.2 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 15.1.3 Option byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 15.1.4 Option byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

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15.2	Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		236
15.3	Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		236
	15.3.1	Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	236
	15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . .		237
	15.3.3	Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	237
	15.3.4 Order codes for ST72F34x development tools . . . . . . . . . . . . . . . . . .		238

16	Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		239
	16.1 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		239
	16.1.1	Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 239
	16.1.2	Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 241

16.2 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 241 16.3 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . 242

16.4.1 Impact on the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.4.2 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5.2 Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.5.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.6 Random read operations not supported with the standard I²C . . . . . . .

243

16.6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.6.2 Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.6.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7 Programming of EEPROM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.7.2 Impact on application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.7.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

245

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. ST72344xx and ST72345xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 4. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5. Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6. Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 7. PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 8. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 9. Calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 10. Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 11. Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 12. LVDRF and WDGRF description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 13. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 14. Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 15. Interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 16. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 17. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 18. External interrupt sensitivity (ei2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 19. External interrupt sensitivity (ei3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 20. External interrupt sensitivity (ei0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 21. External interrupt sensitivity (ei1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 22. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 23. Power saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 24. AWUPR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 25. AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 26. Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 27. I/O Port mode options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 28. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 29. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 30. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 31. I/O port register configurations (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 32. I/O port register configurations (interrupt ports with pull-up). . . . . . . . . . . . . . . . . . . . . . . . 79 Table 33. I/O port register configurations (interrupt ports without pull-up) . . . . . . . . . . . . . . . . . . . . . 79 Table 34. I/O port register configurations (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 35. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 36. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 37. Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 38. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 39. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 40. Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 41. CPU clock prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 42. Time base control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 43. Beep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 44. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 45. ICiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 46. OCiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 47. Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 48. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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List of tables	ST72344xx, ST2345xx

Table 49. Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 50. Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 51. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 52. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 53. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 54. SPI master mode SCK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 55. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 56. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 57. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 58. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 59. SCP[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 60. SCT[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 61. SCR[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 62. Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 63. SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 64. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 65. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 66. FR[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 67. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 68. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 69. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 70. PL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 71. I2C3S register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 72. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 73. Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 74. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 75. Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 76. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 77. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 78. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 79. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 194 Table 80. Short instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 81. Relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 82. Main instruction groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 83. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 84. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Table 85. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 86. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 87. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 88. LVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 89. AVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 90. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 91. Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 92. Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 93. Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 94. On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 95. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 96. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 97. Auto-wakeup from Halt oscillator (AWU) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 98. Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 99. Recommended load capacitance vs. equivalent serial resistance of ceramic

resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

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Table 100. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 101. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 102. EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 103. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 104. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 105. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 106. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 107. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 108. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 109. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 110. I2C and I²C3SNS interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 111. SCL frequency table (multimaster I2C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 112. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 113. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 114. 32-pin low profile quad flat package (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . 228 Table 115. 40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 229 Table 116. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Table 117. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 118. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 119. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Table 120. Size of sector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Table 121. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Table 122. List of valid option combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Table 123. Package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Table 124. Option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Table 125. Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 126. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

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List of figures	ST72344xx, ST2345xx

List of figures

Figure 1.	General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 2.	LQFP32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 3.	LQFP44 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
Figure 4.	LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 5.	Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
Figure 6.	Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
Figure 7.	EEPROM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 8.	Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
Figure 9.	Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 10.	Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 11.	CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	37
Figure 12.	Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 13.	Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	41
Figure 14.	PLL output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
Figure 15.	reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
Figure 16.	Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
Figure 17.	Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
Figure 18.	Low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
Figure 19.	Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
Figure 20.	Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
Figure 21.	Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
Figure 22.	Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
Figure 23.	Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	57
Figure 24.	External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
Figure 25.	Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64
Figure 26.	Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
Figure 27.	Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	66
Figure 28.	Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 29.	Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	67
Figure 30.	Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 31.	Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
Figure 32.	AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
Figure 33.	AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 34.	AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
Figure 35.	I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
Figure 36.	Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	78
Figure 37.	Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	83
Figure 38.	Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	84
Figure 39.	Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	85
Figure 40.	Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	86
Figure 41.	Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
Figure 42.	Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	95
Figure 43.	16-bit read sequence (from either the counter register or the alternate
	counter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	96
Figure 44.	Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 45.	Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 46.	Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	97
Figure 47.	Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	99

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Figure 48. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 49. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 50. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 51. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 52. One-pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 53. One-pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 54. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 55. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 56. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 57. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 58. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 59. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 60. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 61. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 123 Figure 62. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 63. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 64. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 65. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 66. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 67. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 68. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 69. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 70. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 71. I2C3S interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 72. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 73. 16-bit word write operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 74. 16-bit word read operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 75. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 76. Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 77. Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 78. Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 79. Random read (dummy write + restart + current address read). . . . . . . . . . . . . . . . . . . . . 175 Figure 80. Random read (dummy write + stop + start + current address read) . . . . . . . . . . . . . . . . . 176 Figure 81. Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 82. Combined format for read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 83. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Figure 84. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Figure 85. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Figure 86. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 87. fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . . 202 Figure 88. Typical RC frequency vs. RCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 89. Typical IDD in Run vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 90. Typical IDD in Run at fCPU = 8 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 91. Typical IDD in Slow vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 92. Typical IDD in Wait vs. fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 93. Typical IDD in Wait at fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 94. Typical IDD in Slow-wait vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 95. Typical IDD vs. temp. at VDD = 5 V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Figure 96. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 97. Typical application with a crystal or ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 98. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Figure 99. Typical VOL at VDD = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

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List of figures	ST72344xx, ST2345xx

Figure 100. Typical VOL at VDD = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 101. Typical VOL at VDD = 5 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 102. Typical VOL at VDD = 2.4 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 103. Typical VOL at VDD = 3 V (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 104. Typical VOL at VDD = 5 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 105. Typical VOL vs. VDD (std I/Os, 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 106. Typical VOL vs. VDD (std I/Os, 6 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 107. Typical VOL vs. VDD (HS I/Os, IIO = 8 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 108. Typical VOL vs. VDD (HS I/Os, IIO = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 109. Typical VOL vs. VDD (HS I/Os, IIO = 12 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 110. Typical VDD – vOH at VDD = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 111. Typical VDD – VOH at VDD = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 112. Typical VDD – VOH at VDD = 4 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 113. Typical VDD – VOH at VDD = 5 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 114. Typical VDD – VOH vs. VDD (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 115. RESET pin protection when LVD is enabled(1)(2)(3)(4). . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 116. RESET pin protection when LVD is disabled (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 117. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 118. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 119. 32-pin low profile quad flat package (7 x 7 mm) outline . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 120. 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 228 Figure 121. 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Figure 122. 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 123. ST7234x ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

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ST ST72344K2, ST72344K4, ST72344S2, ST72344S4, ST72345C4 User Manual

ST72344xx, ST2345xx	Description

1 Description

The ST7234x devices are members of the ST7 microcontroller family. Table 2 gives the available part numbers and details on the devices. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

They feature single-voltage Flash memory with byte-by-byte in-circuit programming (ICP) and in-application programming (IAP) capabilities.

Under software control, all devices can be placed in Wait, Slow, Auto-wakeup from Halt, Active-halt or Halt mode, reducing the power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Figure 1. General block diagram

	8-BIT CORE	PROGRAM
	ALU	MEMORY
		(16 K - 32 KBytes)
RESET	CONTROL
	CONTROL
		RAM
VSS		(5121024 Bytes)
VSS	LVD
VDD	LVD
	AVD	WATCHDOG
OSC1	CLOCK CONTROL
OSC2	CLOCK CONTROL	I2CMMS
OSC2		I2CMMS

ADDRESS

INTERNAL RC

PORT A

MCC/RTC/BEEP

AND

PORT B

DATA

PORT F

BUS

(6-bits)

TIMER A

PORT C

BEEP

TIMER B

I2C3SNS

SPI

(6-bits)

PORT D

PORT E

VAREF

10-BIT ADC

VSSA

SCI

PA (5-bits)

PB (5-bits)

PC (8-bits)

PE (2-bits)

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Description					ST72344xx, ST2345xx

	Table 2.	ST72344xx and ST72345xx features

	Features		ST72344K2, ST72344K4, ST72344S2,		ST72345C4
	Features		ST72344S4		ST72345C4
			ST72344S4

	Program memory - bytes		8,000	16,000	16,000

	RAM (stack) - bytes		512 bytes (256 bytes)	1 Kbyte (256 bytes)	1 Kbyte (256 bytes)

	EEPROM data - bytes		256	256	256

	Common peripherals		Window watchdog, 2 16-bit timers, SCI, SPI, I2CMMS

	Other peripherals		10-bit ADC		I2C3SNS, 10-bit ADC

	CPU frequency		8 MHz @ 3.3 V to 5.5 V, 4 MHz @ 2.7 V to 5.5 V

	Temperature range			-40 °C to +85 °C

	Package		LQFP32 7x7, LQFP44 10x10		LQFP48 7x7

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ST72344xx, ST2345xx	Pin description

2 Pin description

Figure 2. LQFP32 package pinout

		/ AIN1	/ AIN0 (HS)	/ RDI / TDO		_2
		PD1	PD0 PB4 PB3 PB0 PE1 PE0 V
						DD
VDDA		32 31 30		29 28 27 26		25
VDDA	1		ei3	ei2 ei0		24	OSC1
VSSA	2					23	OSC2
AIN8 / PF0	3					22	V	_2
(HS) PF1		ei1					SS
(HS) PF1	4	ei1				21	RESET
OCMP1_A / AIN10 / PF4	5					20	ICCSEL
ICAP1_A / (HS) PF6	6					19	PA7 (HS) / SCL
EXTCLK_A / (HS) PF7	7				ei0 18		PA6 (HS) / SDA
AIN12 / OCMP2_B / PC0	8					17	PA4 (HS)
		9	10 11	12 13 14 15 16
	AIN13 / OCMP1 B / PC1		ICAP2 B / (HS) PC2 ICAP1 B / (HS) PC3	ICCDATA / MISO / PC4 AIN14 / MOSI / PC5 ICCCLK / SCK / PC6	AIN15 / SS / PC7 (HS) PA3

(HS)	20mA high sink capability
eix	associated external interrupt vector

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Pin description	ST72344xx, ST2345xx

Figure 3. LQFP44 package pinout

		TDO/PE0 V			SCL SDA
			OSC1 OSC2 V		RESET ICCSEL (HS)PA7/ (HS)PA6/ (HS)PA5 (HS)PA4
			OSC1 OSC2 V		RESET ICCSEL (HS)PA7/ (HS)PA6/ (HS)PA5 (HS)PA4
		2	2
		DD	SS

RDI / PE1		44 43 42 41 40 39 38 37 36 35 34
RDI / PE1	1	ei0		33
PB0	2			32
PB1	3	ei2			ei0 31
PB2	4	ei2		30
PB2	4			30
PB3	5			29
(HS) PB4	6	ei3		28
AIN0 / PD0	7			27
AIN1 / PD1	8			26
AIN2 / PD2	9			25
AIN3 / PD3	10		ei1	24
AIN4 / PD4	11			23
		12 13 14 15 16 17 18 19 20 21 22

VSS_1

VDD_1

PA3 (HS)

PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12

V			SSA	DD0 SS0
PD5	DDA			MCO / AIN8PF0/ BEEP(HS)/ (HS)PF2 OCMP1 A / AIN10PF4/ ICAP1 A / (HS)PF6 EXTCLK A / (HS)PF7 V V
AIN5 /		V

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Figure 4. LQFP48 package pinout

		V	OSC1 OSC2 V		RESET ICCSEL (HS)/SCLPA7	(HS)/SDAPA6 (HS)PA5 (HS)PA4 PD6/SDA3SNS PD7/SCL3SNS
		V	OSC1 OSC2 V		RESET ICCSEL (HS)/SCLPA7	(HS)/SDAPA6 (HS)PA5 (HS)PA4 PD6/SDA3SNS PD7/SCL3SNS
		DD2	SS2

PE0/TD0		48 47 46 45			44 43 42 41 40 39 38 37
PE0/TD0	1					36
RDI / PE1	2	ei0				35
PB0	3					ei0 34
PB1	4	ei2				33
PB2	5	ei2				32
PB3	6					31
(HS) PB4	7	ei3				30
AIN0 / PD0	8					29
AIN1 / PD1	9					28
AIN2 / PD2	10					27
AIN2 / PD2	10					26
AIN3 / PD3	11			ei1		26
AIN3 / PD3	11			ei1		25
AIN4 / PD4	12					25
		13 14 15 16 17 18 19 20 21 22 23 24

VSS_1

VDD_1

PA3 (HS)

PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13 NC

AIN5 / PD5 V V	MCO/ AIN8 / PF0 BEEP/ (HS) PF1 (HS) PF2 /AOCMP1AIN10 / PF4 AICAP1/ (HS) PF6 AEXTCLK/ (HS) PF7 V V OCMP2/PC0B / AIN12
DDA SSA	DD0 SS0

Note:

For external pin connection guidelines, refer to Section 13: Electrical characteristics.

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Pin description	ST72344xx, ST2345xx

Legend / Abbreviations for Table 3:

Type:		I = input, O = output, S = supply
Input level:		A = Dedicated analog input
In/Output level:		CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:		HS = 20 mA high sink (on N-buffer only)
Port and control configuration:
●	Input:	float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
●	Output:	OD = open drain 2), PP = push-pull

The reset configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are set in input pull-up configuration after reset through the option byte Package selection. The configuration of these pads must be kept at reset state to avoid added current consumption.

Table 3.

Device pin description

Pin n°

Level

Port

Main

Type

LQFP32

LQFP44

LQFP48

Pin name

Input

Output

float

Input (1)

ana

Output

function

Alternate function

wpu

int

(after

reset)

(2)

Analog supply voltage

VDDA

(2)

Analog ground voltage

VSSA

Main clock

ADC

PF0/MCO/AIN8

I/O

ei1

Port F0

out

analog

(fOSC/2)

input 8

PF1 (HS)/BEEP

I/O

ei1

Port F1

Beep signal output

PF2 (HS) (3)

I/O

ei1

Port F2

Timer A

ADC

PF4/OCMP1_A/AIN10

I/O

Port F4

output

analog

compare 1

input 10

PF6 (HS)/ICAP1_A

I/O

Port F6

Timer A Input

Capture 1

PF7 (HS)/EXTCLK_A

I/O

Port F7

Timer A external

clock source

(2)

Digital main supply voltage

VDD_0

(2)

Digital ground voltage

VSS_0

Timer B

ADC

PC0/OCMP2_B/AIN12

I/O

Port C0

output

analog

compare 2

input 12

Timer B

ADC

PC1/OCMP1_B/AIN13

I/O

Port C1

output

analog

compare 1

input 13

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ST72344xx, ST2345xx

Pin description

Table 3.

Device pin description (continued)

Pin n°

Level

Port

Main

Type

LQFP32

LQFP44

LQFP48

Pin name

Input

Output

float

Input (1)

ana

Output

function

Alternate function

wpu

int

(after

reset)

PC2 (HS)/ICAP2_B

I/O

Port C2

Timer B input capture

PC3 (HS)/ICAP1_B

I/O

Port C3

Timer B input capture

PC4/MISO/ICCDATA

I/O

SPI Master

ICC data

Port C4

In / Slave

input

Out data

SPI Master

ADC

PC5/MOSI/AIN14

I/O

Port C5

Out / Slave

analog

In data

input 14

SPI serial

ICC

PC6/SCK/ICCCLK

I/O

Port C6

clock

output

SPI slave

ADC

select

PC7/SS/AIN15

I/O

Port C7

analog

(active

low)

input 15

PA3 (HS)

I/O

ei0

Port A3

(2)

Digital main supply voltage

VDD_1

(2)

Digital ground voltage

VSS_1

PD7 (3)/ SCL3SNS

I/O

Port D7

I2C3SNS serial clock

(4)

PD6 (3)/ SDA3SNS

I/O

Port D6

I2C3SNS serial data

PA4 (HS)

I/O

Port A4

PA5 (HS) (3)

I/O

Port A5

PA6 (HS)/SDA

I/O

Port A6

I2C serial data

PA7 (HS)/SCL

I/O

Port A7

I2C serial clock

ICCSEL (5)

ICC mode selection

Top priority non maskable

RESET

I/O

interrupt.

(2)

Digital ground voltage

VSS_2

OSC2

Resonator oscillator inverter

output

OSC1

External clock input or resonator

oscillator inverter input

(2)

Digital main supply voltage

VDD_2

PE0/TDO

I/O

Port E0

SCI transmit data out

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Pin description

ST72344xx, ST2345xx

Table 3.

Device pin description (continued)

Pin n°

Level

Port

Main

Type

LQFP32

LQFP44

LQFP48

Pin name

Input

Output

float

Input (1)

ana

Output

function

Alternate function

wpu

int

(after

reset)

PE1/RDI

I/O

ei0

Port E1

SCI receive data in

PB0

I/O

ei2

Port B0

PB1 (3)

I/O

ei2

Port B1

PB2 (3)

I/O

ei2

Port B2

PB3

I/O

ei2

Port B3

PB4 (HS)

I/O

ei3

Port B4

PD0/AIN0

I/O

Port D0

ADC analog input 0

PD1/AIN1

I/O

Port D1

ADC analog input 1

PD2/AIN2

I/O

Port D2

ADC analog input 2

PD3/AIN3

I/O

Port D3

ADC analog input 3

PD4/AIN4

I/O

Port D4

ADC analog input 4

PD5/AIN5

I/O

Port D5

ADC analog input 5

1.In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2.It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.

3.Pulled-up by hardware when not present on the package.

4.In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented).

5.Internal weak pull-down.

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ST72344xx, ST2345xx	Register and memory map

3 Register and memory map

As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 1 Kbyte of RAM, 256 bytes of Data EEPROM and up to 16 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 5. Memory map

0000h

0080h

HW registers

Short addressing

See Table 4

007Fh

RAM (zero page)

00FFh

0080h

RAM

0100h

(512 or 1K Bytes)

047Fh

256 Bytes stack

0480h

01FFh

Reserved

0BFFh

0200h

16-bit addressing

0C00h

Data EEPROM

047Fh

RAM

(256 Bytes)

0CFFh

0D00h

Reserved

C000h

SECTOR 2

BFFFh

C000h

Program memory

16 Kbytes

E000h

FFDFh

(8 or 16 KBytes)

SECTOR 1

F000h (4k)

8 Kbytes

FFE0h

Interrupt & Reset Vectors

or FB00h (2k)

or FC00h (1k)

See Table 17

or FE00h (0.5k)

SECTOR 0

FFFFh

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Table 4.	Hardware register map

Address	Block	Register	Register name	Reset status	Remarks
Address	Block	label	Register name	(1)	(2)
		label		(1)	(2)

0000h	Port A (3)	PADR	Port A Data Register	00h (4)	R/W
0001h	Port A (3)	PADDR	Port A Data Direction Register	00h	R/W
0002h		PAOR	Port A Option Register	00h	R/W

0003h	Port B (3)	PBDR	Port B Data Register	00h (4)	R/W
0004h	Port B (3)	PBDDR	Port B Data Direction Register	00h	R/W
0005h		PBOR	Port B Option Register	00h	R/W

0006h	Port C (3)	PCDR	Port C Data Register	00h (4)	R/W
0007h	Port C (3)	PCDDR	Port C Data Direction Register	00h	R/W
0008h		PCOR	Port C Option Register	00h	R/W

0009h	Port D (3)	PDADR	Port D Data Register	00h (4)	R/W
000Ah	Port D (3)	PDDDR	Port D Data Direction Register	00h	R/W
000Bh		PDOR	Port D Option Register	00h	R/W

000Ch	Port E (3)	PEDR	Port E Data Register	00h (4)	R/W
000Dh	Port E (3)	PEDDR	Port E Data Direction Register	00h	R/W
000Eh		PEOR	Port E Option Register	00h	R/W

000Fh	Port F (3)	PFDR	Port F Data Register	00h (4)	R/W
0010h	Port F (3)	PFDDR	Port F Data Direction Register	00h	R/W
0011h		PFOR	Port F Option Register	00h	R/W

0012h to			Reserved area (5 bytes)
0016h			Reserved area (5 bytes)
0016h

0017h	RC	RCCRH	RC oscillator Control Register High	FFh	R/W
0018h	RC	RCCRL	RC oscillator Control Register Low	03h	R/W
0018h		RCCRL	RC oscillator Control Register Low	03h	R/W

0019h			Reserved area (1 byte)

001Ah to	DM (5)		Reserved area (6 bytes)
001Fh	DM (5)		Reserved area (6 bytes)
001Fh

00020h	EEPROM	EECSR	Data EEPROM Control/Status Register	00h	R/W

0021h		SPIDR	SPI Data I/O Register	xxh	R/W
0022h	SPI	SPICR	SPI Control Register	0xh	R/W
0023h		SPICSR	SPI Control Status Register	00h	R/W

0024h		ISPR0	Interrupt Software Priority Register 0	FFh	R/W
0025h		ISPR1	Interrupt Software Priority Register 1	FFh	R/W
0026h	ITC	ISPR2	Interrupt Software Priority Register 2	FFh	R/W
0027h	ITC	ISPR3	Interrupt Software Priority Register 3	FFh	R/W
0027h		ISPR3	Interrupt Software Priority Register 3	FFh	R/W

0028h		EICR	External Interrupt Control Register	00h	R/W

00029h	Flash	FCSR	Flash Control/Status Register	00h	R/W

002Ah	WWDG	WDGCR	Watchdog Control Register	7Fh	R/W

002Bh	SI	SICSR	System Integrity Control/Status Register	000x 000xb	R/W

002Ch	MCC	MCCSR	Main Clock Control/Status Register	00h	R/W
002Dh	MCC	MCCBCR	MCC Beep Control Register	00h	R/W
002Dh		MCCBCR	MCC Beep Control Register	00h	R/W

002Eh	AWU	AWUCSR	AWU Control/Status Register	00h	R/W
002Fh	AWU	AWUPR	AWU Prescaler Register	FFh	R/W
002Fh		AWUPR	AWU Prescaler Register	FFh	R/W

0030h	WWDG	WDGWR	Window Watchdog Control Register	7Fh	R/W

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Table 4.	Hardware register map (continued)

Address	Block	Register	Register name		Reset status	Remarks
Address	Block	label	Register name		(1)	(2)
		label			(1)	(2)

0031h		TACR2	Timer A Control Register 2		00h	R/W
0032h		TACR1	Timer A Control Register 1		00h	R/W
0033h		TACSR	Timer A Control/Status Register		xxh	R/W
0034h		TAIC1HR	Timer A Input Capture 1 High Register		xxh	Read Only
0035h		TAIC1LR	Timer A Input Capture 1 Low Register		xxh	Read Only
0036h		TAOC1HR	Timer A Output Compare 1 High Register		80h	R/W
0037h		TAOC1LR	Timer A Output Compare 1 Low Register		00h	R/W
0038h	TIMER A	TACHR	Timer A Counter High Register		FFh	Read Only
0039h		TACLR	Timer A Counter Low Register		FCh	Read Only
003Ah		TAACHR	Timer A Alternate Counter High Register		FFh	Read Only
003Bh		TAACLR	Timer A Alternate Counter Low Register		FCh	Read Only
003Ch		TAIC2HR	Timer A Input Capture 2 High Register		xxh	Read Only
003Dh		TAIC2LR	Timer A Input Capture 2 Low Register		xxh	Read Only
003Eh		TAOC2HR	Timer A Output Compare 2 High Register		80h	R/W
003Fh		TAOC2LR	Timer A Output Compare 2 Low Register		00h	R/W

0040h			Reserved area (1 Byte)

0041h		TBCR2	Timer B Control Register 2		00h	R/W
0042h		TBCR1	Timer B Control Register 1		00h	R/W
0043h		TBCSR	Timer B Control/Status Register		xxh	R/W
0044h		TBIC1HR	Timer B Input Capture 1 High Register		xxh	Read Only
0045h		TBIC1LR	Timer B Input Capture 1 Low Register		xxh	Read Only
0046h		TBOC1HR	Timer B Output Compare 1 High Register		80h	R/W
0047h		TBOC1LR	Timer B Output Compare 1 Low Register		00h	R/W
0048h	TIMER B	TBCHR	Timer B Counter High Register		FFh	Read Only
0049h		TBCLR	Timer B Counter Low Register		FCh	Read Only
004Ah		TBACHR	Timer B Alternate Counter High Register		FFh	Read Only
004Bh		TBACLR	Timer B Alternate Counter Low Register		FCh	Read Only
004Ch		TBIC2HR	Timer B Input Capture 2 High Register		xxh	Read Only
004Dh		TBIC2LR	Timer B Input Capture 2 Low Register		xxh	Read Only
004Eh		TBOC2HR	Timer B Output Compare 2 High Register		80h	R/W
004Fh		TBOC2LR	Timer B Output Compare 2 Low Register		00h	R/W

0050h		SCISR	SCI Status Register		C0h	Read Only
0051h		SCIDR	SCI Data Register		xxh	R/W
0052h		SCIBRR	SCI Baud Rate Register		00h	R/W
0053h	SCI	SCICR1	SCI Control Register 1		x000 0000b	R/W
0054h	SCI	SCICR2	SCI Control Register 2		00h	R/W
0054h		SCICR2	SCI Control Register 2		00h	R/W
0055h			Reserved area		--
0056h		SCIERPR	SCI Extended Receive Prescaler Register		00h	R/W
0057h		SCIETPR	SCI Extended Transmit Prescaler Register		00h	R/W

0058h		I2CCR	I2C Control Register		00h	R/W
0059h		I2CSR1	I2C Status Register 1		00h	Read Only
005Ah		I2CSR2	I2C Status Register 2		00h	Read Only
005Bh	I2C	I2CCCR	I2C Clock Control Register		00h	R/W
005Ch		I2COAR1	I2C Own Address Register 1		00h	R/W
005Dh		I2COAR2	I2C Own Address Register2		40h	R/W
005Eh		I2CDR	I2C Data Register		00h	R/W
005Fh			Reserved area (1 byte)

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Table 4.	Hardware register map (continued)

Address	Block	Register	Register name	Reset status	Remarks
Address	Block	label	Register name	(1)	(2)
		label		(1)	(2)

0060h		I2C3SCR1	I2C3SNS Control Register 1	00h	R/W
0061h		I2C3SCR2	I2C3SNS Control Register 2	00h	R/W
0062h		I2C3SSR	I2C3SNS Status Register	00h	Read Only
0063h		I2C3SBCR	I2C3SNS Byte Count Register	00h	Read Only
0064h	I2C3SNS	I2C3SSAR1	I2C3SNS Slave Address 1 Register	00h	R/W
0065h	I2C3SNS	I2C3SCAR1	I2C3SNS Current Address 1 Register	00h	R/W
0066h		I2C3SSAR2	I2C3SNS Slave Address 2 Register	00h	R/W
0067h		I2C3SCAR2	I2C3SNS Current Address 2 Register	00h	R/W
0068h		I2C3SSAR3	I2C3SNS Slave Address 3 Register	00h	R/W
0069h		I2C3SCAR3	I2C3SNS Current Address 3 Register	00h	R/W
0070h		ADCCSR	A/D Control Status Register	00h	R/W
0071h	ADC	ADCDRH	A/D Data Register High	xxh	Read Only
0072h		ADCDRL	A/D Data Low Register	0000 00xxb	Read Only

0073h to			Reserved area (13 bytes)
007Fh			Reserved area (13 bytes)
007Fh

1.x = undefined.

2.R/W = read/write.

3.The bits associated with unavailable pins must always keep their reset value.

4.The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

5.For a description of the Debug Module registers, see ST7 ICC protocol reference manual.

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4 Flash program memory

4.1Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2Main features

●ICP (in-circuit programming)

●IAP (in-application programming)

●ICT (in-circuit testing) for downloading and executing user application test patterns in RAM

●Sector 0 size configurable by option byte

●Read-out and write protection

4.3Programming modes

The ST7 can be programmed in three different ways:

●Insertion in a programming tool

In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased.

●In-circuit programming

In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board.

●In-application programming

In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running.

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4.3.1In-circuit programming (ICP)

ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

●Download ICP Driver code in RAM from the ICCDATA pin

●Execute ICP Driver code in RAM to program the Flash memory

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2In-application programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.)

IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.4ICC interface

ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These pins are:

●RESET: device reset

●VSS: device power supply ground

●ICCCLK: ICC output serial clock pin

●ICCDATA: ICC input serial data pin

●ICCSEL: ICC selection

●OSC1: main clock input for external source (not required on devices without OSC1/OSC2 pins)

●VDD: application board power supply (optional, see Note 3)

Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push pull output or pull-up resistor<1,000). A schottky diode can be used

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to isolate the application reset circuit in this case. When using a classical RC network with R>1,000 or a reset management IC with open drain output and pull-up resistor>1,000, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

5In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte.

Caution: During normal operation, the ICCCLK pin must be internally or externally pulledup (external pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as an output, any reset will put it back in input pull-up.

Figure 6. Typical ICC interface

(See Note 3)

APPLICATION

CL2

POWER SUPPLY

VDD

OSC2

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

ICC CONNECTOR

HE10 CONNECTOR TYPE

OPTIONAL

APPLICATION BOARD

(See Note 4)

APPLICATION

RESET SOURCE

10kΩ

See Note 2

CL1

APPLICATION

See Note 1

I/O

OSC1

VSS

ICCSEL

RESET

ICCCLK

ICCDATA

ST7

4.5Memory protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1Readout protection

Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E2 memory are protected.

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In Flash devices, this protection is removed by reprogramming the option. In this case, both program and data E2 memory are automatically erased, and the device can be reprogrammed.

Read-out protection selection depends on the device type:

●In Flash devices, it is enabled and removed through the FMP_R bit in the option byte.

●In ROM devices, it is enabled by mask option specified in the Option List.

4.5.2Flash write/erase protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E2 data. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected Flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6Register description

4.6.1Flash control/status register (FCSR)

Reset value: 0000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)

	7								0
		0	0	0	0	0	OPT	LAT	PGM

					Read/Write

Note:	This register is reserved for programming using ICP, IAP or other programming methods. It
	controls the XFlash programming and erasing operations. For details on XFlash
	programming, refer to the ST7 Flash Programming Reference Manual.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

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