ST ST72344K2, ST72344K4, ST72344S2, ST72344S4, ST72345C4 User Manual

8-bit MCU with up to 16 Kbytes Flash memory, 10-bit ADC,

LQFP48

7 x 7 mm

LQFP44

LQFP32 7 × 7 mm

10 × 10 mm

Features

■ Memories

– up to 16 Kbytes Program memory: single

voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10,000 write/erase cycles guaranteed, data

retention: 20 years at 55 °C. – up to 1 Kbyte RAM – 256 bytes data EEPROM with readout

protection. 300,000 write/erase cycles

guaranteed, data retention: 20 years at

55 °C.

■ Clock, reset and supply management

– Power on / power off safe reset with

3 programmable threshold levels (LVD) – Auxiliary voltage detector (AVD) – Clock sources: crystal/ceramic resonator

oscillators, high-accuracy internal RC

oscillator or external clock – PLL for 4x or 8x frequency multiplication – 5 power-saving modes: Slow, Wait, Halt,

Auto-wakeup from Halt and Active-halt – Clock output capability (f

■ Interrupt management

– Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 9 external interrupt lines on 4 vectors

■ Up to 34 I/O ports

– up to 34 multifunctional bidirectional I/O

lines – up to 12 high sink outputs (10 on 32-pin

devices)

■ 4 timers

– Configurable window watchdog timer –Real-time base – 16-bit timer A with: 1 input capture, 1 output

compare, external clock input, PWM and

pulse generator modes

CPU

)

ST72344xx, ST72345xx

two 16-bit timers, two I2C, SPI, SCI

Datasheet − production data

– 16-bit timer B with: 2 input captures, 2

output compares, PWM and pulse generator modes

■ 3 communication interfaces

–I

C multimaster / slave

–I

C slave 3 addresses, no stretch, with DMA access and byte pair coherency on I²C read

– SCI asynchronous serial interface (LIN

compatible)

– SPI synchronous serial interface

■ 1 analog peripheral

– 10-bit ADC with 12 input channels (8 on 32-

pin devices)

■ Instruction set

– 8-bit data manipulation – 63 basic instructions with illegal opcode

detection

– 17 main addressing modes – 8 x 8 unsigned multiply instruction

■ Development tools

– Full hardware/software development

package

– On-chip debug module

Table 1. Device summary

References Part numbers

ST72344xx

ST72345xx ST72345C4

ST72344K2, ST72344K4, ST72344S2, ST72344S4

July 2012 Doc ID 12321 Rev 6 1/247

This is information on a product in full production.

www.st.com

Contents ST72344xx, ST2345xx

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.3.1 In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3.2 In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.5.2 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.6.1 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.2 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.3 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.5 Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.6 Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.7.1 EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 35

6 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.3.1 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3.2 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.3 Multioscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.1 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.2 Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4.1 RC control register (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4.2 RC control register (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.5.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.5.4 Internal low-voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 48

7.5.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.6.1 Low-voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.6.2 Auxiliary-voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7.6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.3 Interrupts and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.4 Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.5 Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Doc ID 12321 Rev 6 3/247

Contents ST72344xx, ST2345xx

8.5.2 Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 58

8.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.6.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.7 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 61

9 Power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

9.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.4 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.5 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

9.6 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

9.7.1 AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 72

9.7.2 AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.5.1 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

11.1.4 Using Halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.1.7 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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11.1.8 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 87

11.1.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.1.10 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.2 Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 88

11.2.1 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.2 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.3 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.2.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

11.3 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

11.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

11.3.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.3.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.3.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

11.4.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

11.4.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

11.4.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.4.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.5 SCI serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

11.5.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

11.5.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

11.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

11.5.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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11.6 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

11.6.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

11.6.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

11.6.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

11.7 I2C triple slave interface with DMA (I2C3S) . . . . . . . . . . . . . . . . . . . . . . 167

11.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

11.7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

11.7.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

11.7.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

11.7.5 Address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

11.7.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

11.7.7 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

11.7.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

11.8 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

11.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

11.8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

11.8.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

11.8.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

11.8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

11.8.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

12.1.7 Relative Mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

12.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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13 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

13.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

13.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

13.4 Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

13.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

13.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13.6.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 210

13.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

13.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

13.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 213

13.8.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

13.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 214

13.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

13.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 224

13.11.1 I2C and I²C3SNS interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

13.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

14 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

14.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

14.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

15 Device configuration and ordering information . . . . . . . . . . . . . . . . . 232

15.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

15.1.1 Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

15.1.2 Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

15.1.3 Option byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

15.1.4 Option byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

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Contents ST72344xx, ST2345xx

15.2 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

15.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

15.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

15.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

15.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

15.3.4 Order codes for ST72F34x development tools . . . . . . . . . . . . . . . . . . 238

16 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

16.1 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

16.1.1 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

16.1.2 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

16.2 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 241

16.3 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.4 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . 242

16.4.1 Impact on the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.4.2 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

16.5.2 Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.5.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.6 Random read operations not supported with the standard I²C . . . . . . . 243

16.6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.6.2 Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.6.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7 Programming of EEPROM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7.2 Impact on application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

16.7.3 Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

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ST72344xx, ST2345xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. ST72344xx and ST72345xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 6. Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 7. PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 8. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 9. Calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 10. Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 11. Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 12. LVDRF and WDGRF description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 13. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 14. Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 15. Interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 16. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 17. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 18. External interrupt sensitivity (ei2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 19. External interrupt sensitivity (ei3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 20. External interrupt sensitivity (ei0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 21. External interrupt sensitivity (ei1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 22. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 23. Power saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 24. AWUPR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 25. AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 26. Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 27. I/O Port mode options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 28. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 29. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 30. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 31. I/O port register configurations (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 32. I/O port register configurations (interrupt ports with pull-up). . . . . . . . . . . . . . . . . . . . . . . . 79

Table 33. I/O port register configurations (interrupt ports without pull-up) . . . . . . . . . . . . . . . . . . . . . 79

Table 34. I/O port register configurations (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 35. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 36. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 37. Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 38. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 39. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 40. Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 41. CPU clock prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 42. Time base control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 43. Beep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 44. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 45. ICiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 46. OCiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 47. Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 48. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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List of tables ST72344xx, ST2345xx

Table 49. Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 50. Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 51. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 52. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 53. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 54. SPI master mode SCK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 55. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 56. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 57. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 58. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 59. SCP[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 60. SCT[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 61. SCR[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 62. Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 63. SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 64. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 65. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 66. FR[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 67. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 68. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 69. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 70. PL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 71. I2C3S register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 72. Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 73. Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 74. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 75. Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 76. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 77. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 78. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 79. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 194

Table 80. Short instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 81. Relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 82. Main instruction groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 83. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 84. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 85. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 86. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 87. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 88. LVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 89. AVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 90. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 91. Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 92. Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 93. Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 94. On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 95. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 96. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 97. Auto-wakeup from Halt oscillator (AWU) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 98. Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 99. Recommended load capacitance vs. equivalent serial resistance of ceramic

resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

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Table 100. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 101. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 102. EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 103. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 104. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 105. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 106. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 107. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 108. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 109. Asynchronous RESET

Table 110. I2C and I²C3SNS interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 111. SCL frequency table (multimaster I

pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 112. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 113. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 114. 32-pin low profile quad flat package (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . 228

Table 115. 40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 229

Table 116. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 117. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 118. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 119. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 120. Size of sector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 121. Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Table 122. List of valid option combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Table 123. Package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 124. Option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 125. Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 126. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Doc ID 12321 Rev 6 11/247

List of figures ST72344xx, ST2345xx

List of figures

Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. LQFP32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. LQFP44 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4. LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 7. EEPROM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 8. Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 9. Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10. Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 13. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. PLL output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 15. reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 16. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 17. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 18. Low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 19. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 20. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 21. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 22. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 23. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 24. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 25. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 26. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 28. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 29. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 30. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 31. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 32. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 33. AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 34. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 35. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 36. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 37. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 38. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 39. Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 40. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 41. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 42. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 43. 16-bit read sequence (from either the counter register or the alternate

counter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 44. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 45. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 46. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 47. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

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Figure 48. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 49. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 50. Output compare timing diagram, f Figure 51. Output compare timing diagram, f

TIMER TIMER

= f = f

/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

CPU

/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

CPU

Figure 52. One-pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 53. One-pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 54. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 55. Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 56. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 57. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 58. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 59. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 60. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 61. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 123

Figure 62. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 63. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 64. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 65. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 66. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 67. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 68. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 69. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 70. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 71. I2C3S interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 72. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 73. 16-bit word write operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 74. 16-bit word read operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 75. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 76. Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 77. Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 78. Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 79. Random read (dummy write + restart + current address read). . . . . . . . . . . . . . . . . . . . . 175

Figure 80. Random read (dummy write + stop + start + current address read) . . . . . . . . . . . . . . . . . 176

Figure 81. Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 82. Combined format for read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 83. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 84. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 85. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 86. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 87. f

maximum operating frequency versus V

CPU

supply voltage . . . . . . . . . . . . . . . . . . . 202

Figure 88. Typical RC frequency vs. RCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 89. Typical I Figure 90. Typical I Figure 91. Typical I Figure 92. Typical I Figure 93. Typical I Figure 94. Typical I Figure 95. Typical I

in Run vs. f

in Run at f

in Slow vs. f

in Wait vs. f

in Wait at f

in Slow-wait vs. f

vs. temp. at V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

CPU

= 8 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

CPU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

CPU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

CPU

= 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

CPU

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

CPU

= 5 V and f

= 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

CPU

Figure 96. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 97. Typical application with a crystal or ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 98. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 99. Typical V

at VDD = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Doc ID 12321 Rev 6 13/247

List of figures ST72344xx, ST2345xx

Figure 100. Typical VOL at VDD = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 101. Typical V Figure 102. Typical V Figure 103. Typical V Figure 104. Typical V Figure 105. Typical V Figure 106. Typical V Figure 107. Typical V Figure 108. Typical V Figure 109. Typical V Figure 110. Typical V Figure 111. Typical V Figure 112. Typical V Figure 113. Typical V Figure 114. Typical V Figure 115. RESET Figure 116. RESET

at VDD = 5 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

at VDD = 2.4 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

at VDD = 3 V (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

at V

vs. VDD (std I/Os, 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

vs. VDD (std I/Os, 6 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

vs. VDD (HS I/Os, IIO = 8 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

vs. VDD (HS I/Os, IIO = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

vs. VDD (HS I/Os, IIO = 12 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

– vOH at V

– VOH at V

– VOH at VDD = 4 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

– VOH at V

– VOH vs. VDD (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

= 5 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

= 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

= 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

= 5 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

pin protection when LVD is enabled(1)(2)(3)(4). . . . . . . . . . . . . . . . . . . . . . . . . . 223

pin protection when LVD is disabled (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 117. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 118. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 119. 32-pin low profile quad flat package (7 x 7 mm) outline . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 120. 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 228

Figure 121. 44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 122. 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 123. ST7234x ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

14/247 Doc ID 12321 Rev 6

ST72344xx, ST2345xx Description

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

CONTROL

PROGRAM

(16 K - 32 KBytes)

RESET

PORT F

(6-bits)

TIMER A

BEEP

PORT A

RAM

(512- 1024 Bytes)

PORT C

10-BIT ADC

AREF

SSA

PORT B

(5-bits)

PWM ART

TIMER B

(5-bits)

PORT D

(6-bits)

SPI

(8-bits)

WATCHDOG

CLOCK CONTROL

LVD

OSC2

MEMORY

MCC/RTC/BEEP

AVD

I2CMMS

PORT E

(2-bits)

SCI

I2C3SNS

INTERNAL RC

1 Description

The ST7234x devices are members of the ST7 microcontroller family. Ta bl e 2 gives the available part numbers and details on the devices. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

They feature single-voltage Flash memory with byte-by-byte in-circuit programming (ICP) and in-application programming (IAP) capabilities.

Under software control, all devices can be placed in Wait, Slow, Auto-wakeup from Halt, Active-halt or Halt mode, reducing the power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Figure 1. General block diagram

Doc ID 12321 Rev 6 15/247

Description ST72344xx, ST2345xx

Table 2. ST72344xx and ST72345xx features

Features

ST72344K2, ST72344K4, ST72344S2,

ST72344S4

ST72345C4

Program memory - bytes 8,000 16,000 16,000

RAM (stack) - bytes 512 bytes (256 bytes) 1 Kbyte (256 bytes) 1 Kbyte (256 bytes)

EEPROM data - bytes 256 256 256

Common peripherals Window watchdog, 2 16-bit timers, SCI, SPI, I2CMMS

Other peripherals 10-bit ADC I2C3SNS, 10-bit ADC

CPU frequency 8 MHz @ 3.3 V to 5.5 V, 4 MHz @ 2.7 V to 5.5 V

Temperature range -40 °C to +85 °C

Package LQFP32 7x7, LQFP44 10x10 LQFP48 7x7

16/247 Doc ID 12321 Rev 6

ST72344xx, ST2345xx Pin description

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5

ICCCLK / SCK / PC6

AIN15 / SS / PC7

(HS) PA3

AIN13 / OCMP1_B / PC1

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

DDA

SSA

AIN8 / PF0

(HS) PF1

ICCSEL PA7 (HS) / SCL PA6 (HS) / SDA PA4 (H S)

OSC1 OSC2

RESET

PB0

PE1 / RDI

PE0 / TDO

PD1 / AIN1

PD0 / AIN0

PB4 (HS)

PB3

eix associated external interrupt vector

(HS) 20mA high sink capability

32 31 30 29 28 27 26 25

24 23

21 20 19 18 17

9 10111213141516

1 2 3 4

5 6 7 8

ei1

ei3

ei0

ei2 ei0

2 Pin description

Figure 2. LQFP32 package pinout

Doc ID 12321 Rev 6 17/247

Pin description ST72344xx, ST2345xx

MCO / AIN8 / PF0

BEEP / (HS)

(HS) PF2

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

DD_0

SS_0

AIN5 / PD5

DDA

SSA

44 43 42 41 40 39 38 37 36 35 34

33 32 31 30 29 28 27 26 25 24 23

12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

ei2

ei3

ei0

ei1

PB3

(HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4

RDI / PE1

PB0 PB1

PB2

PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12

SS_1

DD_1

PA3 (H S) PC7 / SS

/ AIN15

RESET

ICCSEL

PA7 (HS) / SCL

PA6 (HS) / SDA

PA5 (H S)

PA4 (H S)

PE0 / TDO

OSC1

OSC2

ei0

Figure 3. LQFP44 package pinout

18/247 Doc ID 12321 Rev 6

ST72344xx, ST2345xx Pin description

44 43 42 41 40 39 38 37

36 35 34

33 32 31 30 29 28 27 26 25

13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

48 47 46 45

RESET

ICCSEL

PA7 (H S) / SC L

PA6 (H S) / SDA

PA5 (H S)

PA4 (H S)

PD6/SDA3SNS

DD_2

OSC1

OSC2

SS_2

PB3

(HS) PB4 AIN0 / PD0 AIN1 / PD1

AIN3 / PD3

RDI / PE1

PB0 PB1

PB2

AIN2 / PD2

PE0/TD0

AIN4 / PD4

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

DD_0

SS_0

AIN5 / PD5

DDAVSSA

PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

SS_1

DD_1

PA3 ( HS ) PC7 / SS / AIN15

PD7/SCL3SNS

ei2

ei3

ei0

ei1

ei0

Figure 4. LQFP48 package pinout

Note: For external pin connection guidelines, refer to Section 13: Electrical characteristics.

Doc ID 12321 Rev 6 19/247

Pin description ST72344xx, ST2345xx

Legend / Abbreviations for Ta b le 3 :

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration:

● Input: float = floating, wpu = weak pull-up, int = interrupt

● Output: OD = open drain

The reset configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are set in input pull-up configuration after reset through the option byte Package selection. The configuration of these pads must be kept at reset state to avoid added current consumption.

LQFP44

LQFP48

DDA

SSA

Pin name

(2)

(3)

S Analog supply voltage

S Analog ground voltage

I/O CTHS X ei1 X X Port F2

Table 3. Device pin description

Pin n°

LQFP32

11314V

21415V

3 15 16 PF0/MCO/AIN8 I/O C

4 16 17 PF1 (HS)/BEEP I/O C

-1718PF2 (HS)

, ana = analog

, PP = push-pull

Level Port

Input

Type

Input

Output

float

(1)

wpu

Output

int

ana

Main

function

(after

reset)

Alternate function

Main clock

Xei1XXXPort F0

HS X ei1 X X Port F1 Beep signal output

out (f

OSC

/2)

ADC analog input 8

5 18 19 PF4/OCMP1_A/AIN10 I/O C

6 19 20 PF6 (HS)/ICAP1_A I/O C

7 20 21 PF7 (HS)/EXTCLK_A I/O C

-2122V

-2223V

DD_0

SS_0

(2)

S Digital main supply voltage

S Digital ground voltage

8 23 24 PC0/OCMP2_B/AIN12 I/O C

9 24 27 PC1/OCMP1_B/AIN13 I/O C

XX XXXPort F4

HS X X X X Port F6

HS X X X X Port F7

XX XXXPort C0

XX XXXPort C1

20/247 Doc ID 12321 Rev 6

Timer A output compare 1

ADC analog input 10

Timer A Input Capture 1

Timer A external clock source

Timer B output compare 2

Timer B output compare 1

ADC analog input 12

ADC analog input 13

ST72344xx, ST2345xx Pin description

Table 3. Device pin description (continued)

Pin n°

LQFP32

LQFP44

Pin name

LQFP48

Type

10 25 28 PC2 (HS)/ICAP2_B I/O C

11 26 29 PC3 (HS)/ICAP1_B I/O C

12 27 30 PC4/MISO/ICCDATA I/O C

13 28 31 PC5/MOSI/AIN14 I/O C

14 29 32 PC6/SCK/ICCCLK I/O C

15 30 33 PC7/SS

/AIN15 I/O C

16 31 34 PA3 (HS) I/O C

-3235V

-3336V

DD_1

SS_1

- - 37 PD7

(2)

(3)

/ SCL3SNS I/O CTHS X

S Digital main supply voltage

S Digital ground voltage

Level Port

(1)

Input

Output

HS X X X X Port C2

HS X X X X Port C3

HS X ei0 X X Port A3

wpu

float

XX XXPort C4

XX XXXPort C5

XX XXPort C6

XX XXXPort C7

Output

int

ana

(4)

Main

function

(after

Alternate function

reset)

Timer B input capture 2

Timer B input capture 1

SPI Master In / Slave Out data

SPI Master Out / Slave In data

SPI serial clock

SPI slave select (active low)

ICC data input

ADC analog input 14

ICC clock output

ADC analog input 15

Port D7 I2C3SNS serial clock

- - 38 PD6

(3)

/ SDA3SNS I/O CTHS X T Port D6 I2C3SNS serial data

17 34 39 PA4 (HS) I/O C

- 35 40 PA5 (HS)

(3)

I/O CTHS X X X X Port A5

18 36 41 PA6 (HS)/SDA I/O C

19 37 42 PA7 (HS)/SCL I/O C

20 38 43 ICCSEL

21 39 44 RESET

22 40 45 V

SS_2

(2)

(5)

I ICC mode selection

I/O C

S Digital ground voltage

23 41 46 OSC2 O

24 42 47 OSC1 I

25 43 48 V

DD_2

(2)

S Digital main supply voltage

26 44 1 PE0/TDO I/O C

HS X X X X Port A4

HS X T Port A6 I2C serial data

HS X T Port A7 I2C serial clock

Top priority non maskable interrupt.

Resonator oscillator inverter output

External clock input or resonator oscillator inverter input

X X X X Port E0 SCI transmit data out

Doc ID 12321 Rev 6 21/247

Pin description ST72344xx, ST2345xx

Table 3. Device pin description (continued)

Pin n°

Pin name

LQFP32

LQFP44

LQFP48

27 1 2 PE1/RDI I/O C

28 2 3 PB0 I/O C

- 3 4 PB1

- 4 5 PB2

(3)

29 5 6 PB3 I/O C

30 6 7 PB4 (HS) I/O C

31 7 8 PD0/AIN0 I/O C

32 8 9 PD1/AIN1 I/O C

- 9 10 PD2/AIN2 I/O C

- 10 11 PD3/AIN3 I/O C

- 11 12 PD4/AIN4 I/O C

- 12 13 PD5/AIN5 I/O C

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. It is mandatory to connect all available V

3. Pulled-up by hardware when not present on the package.

4. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V implemented).

5. Internal weak pull-down.

Level Port

Type

Input

Output

I/O C

HS X ei3 X X Port B4

and V

pins to the supply voltage and all VSS and V

DDA

Main

Input

float

(1)

wpu

Output

int

ana

function

(after

reset)

Alternate function

X ei0 X X Port E1 SCI receive data in

Xei2 XXPort B0

Xei2 XXPort B1

Xei2 XXPort B2

Xei2XXPort B3

X X X X X Port D0 ADC analog input 0

X X X X X Port D1 ADC analog input 1

X X X X X Port D2 ADC analog input 2

X X X X X Port D3 ADC analog input 3

X X X X X Port D4 ADC analog input 4

X X X X X Port D5 ADC analog input 5

pins to ground.

SSA

are not

22/247 Doc ID 12321 Rev 6

ST72344xx, ST2345xx Register and memory map

0000h

RAM

Program memory

Interrupt & Reset Vectors

HW registers

0080h

007Fh

BFFFh

See Table 4

C000h

FFDFh FFE0h

FFFFh

Short addressing RAM (zero page)

256 Bytes stack

16-bit addressing

RAM

0100h

01FFh

047Fh

0080h

0200h

00FFh

(512 or 1K Bytes)

0480h

047Fh

Data EEPROM

(256 Bytes)

Reserved

0C00h

0CFFh

0BFFh

0D00h

See Table 17

FFFFh

E000h

C000h

(8 or 16 KBytes)

16 Kbytes

8 Kbytes

SECTOR 2

SECTOR 1

FFFFh

E000h

C000h

SECTOR 0

F000h (4k)

FC00h (1k)

FE00h (0.5k)

FB00h (2k)

3 Register and memory map

As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 1 Kbyte of RAM, 256 bytes of Data EEPROM and up to 16 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

The highest address bytes contain the user reset and interrupt vectors.

Figure 5. Memory map

Doc ID 12321 Rev 6 23/247

Table 4. Hardware register map

Address Block

0000h 0001h 0002h

0003h 0004h 0005h

0006h 0007h 0008h

0009h 000Ah 000Bh

000Ch 000Dh 000Eh

000Fh 0010h 0011h

Por t A

Por t B

Por t C

Por t D

Por t E

Por t F

(3)

label

PA DR PADDR PA OR

PBDR PBDDR PBOR

PCDR PCDDR PCOR

PDADR PDDDR PDOR

PEDR PEDDR PEOR

PFDR PFDDR PFOR

0012h to

0016h

0017h 0018h

RCCRH RCCRL

Port A Data Register Port A Data Direction Register Port A Option Register

Port B Data Register Port B Data Direction Register Port B Option Register

Port C Data Register Port C Data Direction Register Port C Option Register

Port D Data Register Port D Data Direction Register Port D Option Register

Port E Data Register Port E Data Direction Register Port E Option Register

Port F Data Register Port F Data Direction Register Port F Option Register

Reserved area (5 bytes)

RC oscillator Control Register High RC oscillator Control Register Low

Reset status

(1)

(4)

00h

00h 00h

(4)

00h

00h 00h

(4)

00h

00h 00h

(4)

00h

00h 00h

(4)

00h

00h 00h

(4)

00h

00h 00h

FFh 03h

Remarks

(2)

R/W R/W R/W

R/W R/W

0019h Reserved area (1 byte)

001Ah to

001Fh

(5)

Reserved area (6 bytes)

00020h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

0021h 0022h 0023h

0024h 0025h 0026h 0027h

SPI

ITC

SPIDR SPICR SPICSR

ISPR0 ISPR1 ISPR2 ISPR3

SPI Data I/O Register SPI Control Register SPI Control Status Register

Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3

xxh 0xh 00h

FFh FFh FFh FFh

R/W R/W R/W

R/W R/W R/W R/W

0028h EICR External Interrupt Control Register 00h R/W

00029h Flash FCSR Flash Control/Status Register 00h R/W

002Ah WWDG WDGCR Watchdog Control Register 7Fh R/W

002Bh SI SICSR System Integrity Control/Status Register 000x 000xb R/W

002Ch 002Dh

002Eh 002Fh

MCC

AWU

MCCSR MCCBCR

AWUCSR AWUPR

Main Clock Control/Status Register MCC Beep Control Register

AWU Control/Status Register AWU Prescaler Register

00h 00h

00h FFh

R/W R/W

0030h WWDG WDGWR Window Watchdog Control Register 7Fh R/W

24/247 Doc ID 12321 Rev 6

ST72344xx, ST2345xx Register and memory map

Table 4. Hardware register map (continued)

Address Block

0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h

TIMER A 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh

label

TACR2 TACR1 TA CS R TA I C1 H R TAIC1LR TA OC 1 H R TA OC 1 L R TACHR TA CL R TAACHR TA AC L R TA I C2 H R TAIC2LR TA OC 2 H R TA OC 2 L R

Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

0040h Reserved area (1 Byte)

0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h

0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh

TIMER B

SCI

TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

SCISR SCIDR SCIBRR SCICR1 SCICR2

SCIERPR SCIETPR

I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR

Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 Reserved area SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register

C Control Register

I I2C Status Register 1

C Status Register 2

I I2C Clock Control Register I2C Own Address Register 1

C Own Address Register2

I I2C Data Register

005Fh Reserved area (1 byte)

Reset status

(1)

00h 00h xxh xxh xxh 80h 00h

FFh FCh FFh FCh

xxh

80h

00h

xxh

80h

00h FFh FCh FFh FCh

xxh

80h

00h

C0h

xxh

00h

x000 0000b

00h

-00h 00h

00h 00h 00h 00h 00h 40h 00h

Remarks

(2)

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

Read Only R/W R/W R/W R/W

R/W R/W

R/W Read Only Read Only R/W R/W R/W R/W

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Table 4. Hardware register map (continued)

Address Block

0060h 0061h 0062h 0063h 0064h 0065h

C3SNS

0066h 0067h 0068h 0069h

0070h 0071h

ADC

0072h

0073h to

007Fh

1. x = undefined.

2. R/W = read/write.

3. The bits associated with unavailable pins must always keep their reset value.

4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

5. For a description of the Debug Module registers, see ST7 ICC protocol reference manual.

label

I2C3SCR1 I2C3SCR2 I2C3SSR I2C3SBCR I2C3SSAR1 I2C3SCAR1 I2C3SSAR2 I2C3SCAR2 I2C3SSAR3 I2C3SCAR3

ADCCSR ADCDRH ADCDRL

C3SNS Control Register 1

I I2C3SNS Control Register 2 I2C3SNS Status Register

C3SNS Byte Count Register

I I2C3SNS Slave Address 1 Register I2C3SNS Current Address 1 Register

C3SNS Slave Address 2 Register

I I2C3SNS Current Address 2 Register I2C3SNS Slave Address 3 Register

C3SNS Current Address 3 Register

A/D Control Status Register A/D Data Register High A/D Data Low Register

Reserved area (13 bytes)

Reset status

(1)

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h

00h xxh

0000 00xxb

Remarks

(2)

R/W R/W Read Only Read Only R/W R/W R/W R/W R/W R/W

R/W Read Only Read Only

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ST72344xx, ST2345xx Flash program memory

4 Flash program memory

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main features

● ICP (in-circuit programming)

● IAP (in-application programming)

● ICT (in-circuit testing) for downloading and executing user application test patterns in

RAM

● Sector 0 size configurable by option byte

● Read-out and write protection

4.3 Programming modes

The ST7 can be programmed in three different ways:

● Insertion in a programming tool

In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased.

● In-circuit programming

In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board.

● In-application programming

In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running.

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Flash program memory ST72344xx, ST2345xx

4.3.1 In-circuit programming (ICP)

ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET

pin is pulled low. When the ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

● Download ICP Driver code in RAM from the ICCDATA pin

● Execute ICP Driver code in RAM to program the Flash memory

Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In-application programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.4 ICC interface

ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These pins are:

● RESET: device reset

● V

● ICCCLK: ICC output serial clock pin

● ICCDATA: ICC input serial data pin

● ICCSEL: ICC selection

● OSC1: main clock input for external source (not required on devices without

● V

Note: 1 If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal

isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2 During the ICP session, the programming tool must control the RESET

conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push pull output or pull-up resistor<1,000). A schottky diode can be used

: device power supply ground

OSC1/OSC2 pins)

: application board power supply (optional, see Note 3)

pin. This can lead to

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ST72344xx, ST2345xx Flash program memory

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

VDD

HE10 CONNECTOR TYPE

APPLICATION POWER SUPPLY

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10kΩ

VSS

ICCSEL

ST7

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See Note 4)

to isolate the application reset circuit in this case. When using a classical RC network with R>1,000 or a reset management IC with open drain output and pull-up resistor>1,000, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3 The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This

pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4 Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the

application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

5 In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a

clock source, regardless of the selection in the option byte.

Caution: During normal operation, the ICCCLK pin must be internally or externally pulled- up

(external pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as an output, any reset will put it back in input pull-up.

Figure 6. Typical ICC interface

4.5 Memory protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Readout protection

Readout protection, when selected, provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E

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memory are protected.

Flash program memory ST72344xx, ST2345xx

In Flash devices, this protection is removed by reprogramming the option. In this case, both program and data E

memory are automatically erased, and the device can be

reprogrammed. Read-out protection selection depends on the device type:

● In Flash devices, it is enabled and removed through the FMP_R bit in the option byte.

● In ROM devices, it is enabled by mask option specified in the Option List.

4.5.2 Flash write/erase protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A

write-protected Flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

data. Its purpose is to provide advanced security to

4.6 Register description

4.6.1 Flash control/status register (FCSR)

Reset value: 0000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)

7 0

00000OPTLATPGM

Read/Write

Note: This register is reserved for programming using ICP, IAP or other programming methods. It

controls the XFlash programming and erasing operations. For details on XFlash programming, refer to the ST7 Flash Programming Reference Manual.

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

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