ST ST72104G1, ST72104G2, ST72216G1, ST72215G2, ST72254G1 User Manual

...
ST72104Gx-Auto, ST72215Gx-Auto,
ST72216Gx-Auto, ST72254Gx-Auto
8-bit MCU for automotive with single voltage Flash/ROM memory,
SO28
2
C interfaces
ADC, 16-bit timers, SPI, I
– 4K or 8K bytes Program memory (ROM and
single voltage Flash) with readout protection and in-situ programming (remote ISP)
– 256 bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system – Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator os-
cillators or RC oscillators, external clock,
backup Clock Security System – Clock-out capability – 3 Power Saving Modes: Halt, Wait and Slow
Interrupt Management
– 7 interrupt vectors plus TRAP and RESET – 22 external interrupt lines (on 2 vectors)
22 I/O Ports
– 22 multifunctional bidirectional I/O lines – 14 alternate function lines – 8 high sink outputs
3 Timers
– Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and Pulse generator modes (one
only on ST72104Gx-Auto and ST72216G1-
Auto)
2 Communications Interfaces
– SPI synchronous serial interface – I2C multimaster interface
(only on ST72254Gx-Auto)
1 Analog Peripheral
– 8-bit ADC with 6 input channels
(except on ST72104Gx-Auto)
Instruction Set
– 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation
Development Tools
– Full hardware/software development package
Device Summary
Features
Program memory Flash/ROM 4 Kbytes 8 Kbytes 4 Kbytes 8 Kbytes 4 Kbytes 8 Kbytes RAM (stack) 256 (128) bytes
Peripherals
Operating Supply 3.2V to 5.5 V CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz) Operating Temperature -40°C to +85°C / -40°C to +105°C / -40°C to +125C° Packages SO28
ST72104G1-
Auto
ST72104G2-
Auto
One 16-bit timer Two 16-bit timers
- ADC
ST72216G1-
Auto
Watchdog timer
- I2C
ST72215G2-
Auto
SPI
ST72254G1-
Auto
ST72254G2-
Auto
Rev. 1
October 2007 1/135
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 STRUCTURAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 MEMORY READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2 Safe Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . . . . . . . . . 23
6.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 NON-MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
135
2/135
2
Table of Contents
9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.6 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.2.6 Summary of Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
11.3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
11.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
11.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.5.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3/135
3
Table of Contents
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.1 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.2 Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.3 Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.4 Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.1.5 Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
13.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 99
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.4.3 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.4.5 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
13.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.6.2 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
13.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
13.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
135
4/135
Table of Contents
13.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.9.2 ISPSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.10.1 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 123
13.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.2 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 129
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 130
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
15.3.1 Package/Socket Footprint Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

1 INTRODUCTION

The ST72104G-Auto, ST72215G-Auto, ST72216G-Auto and ST72254G-Auto devices are members of the ST7 microcontroller family. They can be grouped as follows:
– ST72254G-Auto devices are designed for mid-
range applications with ADC and I²C interface capabilities.
– ST72215/6G-Auto devices target the same
range of applications but without I²C interface.
– ST72104G-Auto devices are for applications that
do not need ADC and I²C peripherals.
All devices are based on a common industry­standard 8-bit core, featuring an enhanced instruc
-
tion set. The ST72C104G, ST72C215G, ST72C216G and
ST72C254G versions feature single-voltage Flash
Figure 1. General Block Diagram
INTERNAL
OSC1
OSC2
V
DD
V
RESET
SS
MULTI OSC
+
CLOCK FILTER
LVD
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
PROGRAM
MEMORY
(4 or 8K bytes)
CLOCK
ADDRESS AND DATA BUS
memory with byte-by-byte In-Situ Programming (ISP) capability.
Under software control, all devices can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 micro
­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing modes.
For easy reference, all parametric data are located
Section 13 on page 95.
in
I2C
PA7:0
PORT A
SPI
PORT B
16-BIT TIMER A
PORT C
8-BIT ADC
16-BIT TIMER B
(8 bits)
PB7:0
(8 bits)
PC5:0
(6 bits)
6/135
4
RAM
(256 bytes)
WATCHDOG
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

2 PIN DESCRIPTION

Figure 2. 28-Pin SO Package Pinout
RESET
OSC1 OSC2
SS
/PB7
ISPCLK/SCK/PB6
ISPDATA/MISO/PB5
MOSI/PB4
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
1
2
3
4
5
6
7
8
9
10
11
12
13 14
ei1 ei0
ei0 or ei1
V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DD
V
SS
ISPSEL
PA0 (HS)
PA1 (HS)
PA2 (HS)
PA3 (HS)
PA4 (HS)/SCLI
PA5 (HS) PA6 (HS)/SDAI PA7 (HS)
PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1
PC2/MCO/AIN2
(HS) 20mA high sink capability eiX associated external interrupt vector
7/135
5
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page
95.
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD,
CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt – Output: OD = open drain
2)
, PP = push-pull Refer to Section 9 "I/O PORTS" on page 30 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.
Table 1. SO28 Device Pin Description
Pin
No. Name
1 RESET I/O C
2 OSC1
3 OSC2
3)
3)
4 PB7/SS I/O C
5 PB6/SCK/ISPCLK I/O C
6 PB5/MISO/ISPDATA I/O C
7 PB4/MOSI I/O C
8 PB3/OCMP2_A I/O C
9 PB2/ICAP2_A I/O C
10 PB1 /OCMP1_A I/O C
11 PB0 /ICAP1_A I/O C
12 PC5/EXTCLK_A/AIN5 I/O C
13 PC4/OCMP2_B/AIN4 I/O C
14 PC3/ ICAP2_B/AIN3 I/O C
15 PC2/MCO/AIN2 I/O C
16 PC1/OCMP1_B/AIN1 I/O C
17 PC0/ICAP1_B/AIN0 I/O C
Level Port / Control
Input Output
Type
Input
Output
T
wpu
float
X X Top priority non maskable interrupt (active low)
I
O
X ei1 X X Port B7 SPI Slave Select (active low)
T
X ei1 X X Port B6 SPI Serial Clock or ISP Clock
T
X ei1 X X Port B5
T
X ei1 X X Port B4 SPI Master Out / Slave In Data
T
X ei1 X X Port B3 Timer A Output Compare 2
T
X ei1 X X Port B2 Timer A Input Capture 2
T
X ei1 X X Port B1 Timer A Output Compare 1
T
X ei1 X X Port B0 Timer A Input Capture 1
T
X ei0/ei1 X X Port C5
T
X ei0/ei1 X X Port C4
T
X ei0/ei1 X X X Port C3
T
X ei0/ei1 X X X Port C2
T
X ei0/ei1 X X X Port C1
T
X ei0/ei1 X X X Port C0
T
int
ana
OD
PP
1)
, ana = analog
Main
Function
Alternate Function
(after reset)
External clock input or Resonator oscillator inverter input or resistor input for RC oscillator
Resonator oscillator inverter output or capacitor in­put for RC oscillator
SPI Master In/ Slave Out Data or ISP Data
Timer A Input Clock or ADC Analog Input 5
Timer B Output Compare 2 or ADC Analog Input 4
Timer B Input Capture 2 or ADC An­alog Input 3
Main clock output (f
CPU
) or ADC
Analog Input 2 Timer B Output Compare 1 or ADC
Analog Input 1 Timer B Input Capture 1 or ADC An-
alog Input 0
8/135
6
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
Pin
No. Name
Level Port / Control
Input Output
Type
Input
Output
float
int
wpu
ana
OD
Main
Function
(after reset)
PP
Alternate Function
18 PA7 I/O CTHS X ei0 X X Port A7
19 PA6 /SDAI I/O CTHS X ei0 T Port A6 I2C Data
20 PA5 I/O CTHS X ei0 X X Port A5
21 PA4 /SCLI I/O CTHS X ei0 T Port A4 I2C Clock
22 PA3 I/O CTHS X ei0 X X Port A3
23 PA2 I/O CTHS X ei0 X X Port A2
24 PA1 I/O CTHS X ei0 X X Port A1
25 PA0 I/O CTHS X ei0 X X Port A0
26 ISPSEL I C X
27 V
28 V
SS
DD
S Ground
S Main power supply
In-situ programming selection (should be tied low in standard user mode).
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not imple­mented). See Section 9 "I/O PORTS" on page 30 and Section 13.8 "I/O PORT PIN CHARACTERISTICS" on page 116 for more details.
3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see
Section 2 "PIN DESCRIPTION" on page 7 and Section 13.5 "CLOCK AND TIMING CHARACTERISTICS"
on page 104 for more details.
9/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

3 REGISTER AND MEMORY MAP

As shown in the Figure 3, the MCU is capable of addressing 64 Kbytes of memories and I/O regis­ters.
The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh.
The highest address bytes contain the user reset and interrupt vectors.
Figure 3. Memory Map
0000h
007Fh 0080h
017Fh 0180h
DFFFh E000h
FFDFh FFE0h
FFFFh
HW Registers
(see Table 2)
256 bytes RAM
Reserved
Program Memory
(4K, 8K bytes)
Interrupt & Reset Vectors (see Table 5 on page 26)
IMPORTANT: Memory locations marked as “Re­served” must never be accessed. Accessing a re­served area can have unpredictable effects on the device.
0080h
00FFh 0100h
017Fh
E000h
F000h
FFFFh
Short Addressing RAM
Zero page
(128 bytes)
Stack or
16-bit Addressing RAM
(128 bytes)
8 Kbytes
4 Kbytes
10/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
Table 2. Hardware Register Map
Address Block
0000h 0001h
Port C
0002h
Register
Label
PCDR PCDDR PCOR
Register Name
Port C Data Register Port C Data Direction Register Port C Option Register
Reset
Status
1)
00h
00h 00h
0003h Reserved (1 byte)
0004h 0005h 0006h
Port B
PBDR PBDDR PBOR
Port B Data Register Port B Data Direction Register Port B Option Register
00h
00h 00h
1)
0007h Reserved (1 byte)
0008h 0009h 000Ah
Port A
PADR PADDR PAOR
Port A Data Register Port A Data Direction Register Port A Option Register
00h
00h 00h
1)
000Bh
to
Reserved (21 bytes)
001Fh
0020h MISCR1 Miscellaneous Register 1 00h R/W
0021h 0022h 0023h
SPI
SPIDR SPICR SPISR
SPI Data I/O Register SPI Control Register SPI Status Register
xxh 0xh 00h
0024h WATCHDOG WDGCR Watchdog Control Register 7Fh R/W
Remarks
2)
R/W
2)
R/W
2)
R/W
R/W R/W R/W
R/W R/W R/W
R/W R/W Read Only
0025h CRSR Clock, Reset, Supply Control / Status Register 000x 000x R/W
0026h 0027h
0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh
I2C
I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR
Control Register Status Register 1 Status Register 2 Clock Control Register Own Address Register 1 Own Address Register 2 Data Register
Reserved (2 bytes)
00h 00h 00h 00h 00h 00h 00h
R/W Read Only Read Only R/W R/W R/W R/W
002Fh
to
Reserved (2 bytes)
0030h
11/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
Address Block
0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh
0040h MISCR2 Miscellaneous Register 2 00h R/W
0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh
TIMER A
TIMER B
Register
Label
TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR
TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR
Register Name
Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register
Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register
Reset
Status
00h 00h xxh xxh xxh 80h 00h
FFh FCh FFh FCh
xxh
xxh
80h
00h
00h
00h
xxh
xxh
xxh
80h
00h FFh FCh FFh FCh
xxh
xxh
80h
00h
Remarks
R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
0050h
to
006Fh
0070h 0071h
0072h
to
007Fh
ADC
ADCDR ADCCSR
Data Register Control/Status Register
Reserved (32 bytes)
Reserved (14 bytes)
00h
00h
Read Only R/W
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
12/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

Flash devices have a single voltage non-volatile Flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by-byte basis.

4.2 MAIN FEATURES

Remote In-Situ Programming (ISP) mode
Up to 16 bytes programmed in the same cycle
MTP memory (Multiple Time Programmable)
Readout memory protection against piracy

4.3 STRUCTURAL ORGANIZATION

The Flash program memory is organized in a sin­gle 8-bit wide memory block which can be used for storing both code and data constants.
The Flash program memory is mapped in the up­per part of the ST7 addressing space and includes the reset and interrupt user vector area.

4.4 IN-SITU PROGRAMMING (ISP) MODE

The Flash program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be up dated using a standard ST7 programming tools af­ter the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area im pact.
An example Remote ISP hardware interface to the standard ST7 programming tool is described be low. For more details on ISP programming, refer to the ST7 Programming Specification.
This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are:
– RESET: device reset –VSS: device ground power supply – ISPCLK: ISP output serial clock pin – ISPDATA: ISP input serial data pin – ISPSEL: Remote ISP mode selection. This pin
must be connected to V board through a pull-down resistor.
on the application
SS
If any of these pins are used for other purposes on the application, a serial resistor has to be imple mented to avoid a conflict if the other device forces the signal level.
Figure 4 shows a typical hardware interface to a
standard ST7 programming tool. For more details on the pin locations, refer to the device pinout de scription.
Figure 4. Typical Remote ISP Interface
HE10 CONNECTOR TYPE
XTAL
C
L0
C
L1
-
OSC1
OSC2
-
-
ST7
TO PROGRAMMING TOOL
ISPSEL
DD
V
V
RESET
ISPCLK
ISPDATA
10K
SS
-
-
1
47K
Remote ISP Overview
The Remote ISP mode is initiated by a specific se­quence on the dedicated ISPSEL pin.
The Remote ISP is performed in three steps:
– Selection of the RAM execution mode – Download of Remote ISP code in RAM – Execution of Remote ISP code in RAM to pro-
gram the user program into the Flash
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied with power (V
and VSS) and a clock signal (os-
DD
cillator and application crystal circuit for example).
APPLICATION

4.5 MEMORY READOUT PROTECTION

The readout protection is enabled through an op­tion bit.
For Flash devices, when this option is selected, the program and data stored in the Flash memory are protected against readout piracy (including a re-write protection). When this protection option is removed the entire Flash program memory is first automatically erased. However, the E
2
PROM data memory (when available) can be protected only with ROM devices.
13/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt

5.3 CPU REGISTERS

The six CPU registers shown in Figure 5 are not present in the memory mapping and are accessed by specific instructions.
Figure 5. CPU Registers
70
RESET VALUE = XXh
70
RESET VALUE = XXh
70
RESET VALUE = XXh
Accumulator (A)
The Accumulator is an 8-bit general purpose reg­ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede in
­struction (PRE) to indicate that the following in­struction refers to the Y register.)
The Y register is not affected by the interrupt auto­matic procedures (not pushed to and popped from the stack).
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
15 8
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
15
RESET VALUE = STACK HIGHER ADDRESS
14/135
PCH
RESET VALUE =
7
70
1C11HI NZ
1X11X1XX
70
8
PCL
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC)
Read/Write Reset Value: 111x1xxx
7 0
1 1 1 H I N Z C
The 8-bit Condition Code register contains the in­terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in structions.
These bits can be individually tested and/or con­trolled by specific instructions.
Bit 4 = H Half carry This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines.
Bit 3 = I Interrupt mask
This bit is set by hardware when entering in inter­rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET in­structions and is tested by the JRM and JRNM in­structions.
Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible
-
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur
­rent interrupt routine.
Bit 2 = N Negative This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7
th
bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc­tions.
Bit 1 = Z Zero
This bit is set and cleared by hardware. This bit in­dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
15/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
CPU REGISTERS (cont’d) Stack Pointer (SP)
Read/Write Reset Value: 01 7Fh
15 8
0 0 0 0 0 0 0 1
7 0
0 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is al­ways pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see
Figure 6).
Since the stack is 128 bytes deep, the 9 most sig­nificant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruc tion (RSP), the Stack Pointer contains its reset val­ue (the SP6 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD in struction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, with out indicating the stack overflow. The previously stored information is then overwritten and there fore lost. The stack also wraps in case of an under­flow.
The stack is used to save the return address dur­ing a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instruc tions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 6.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
­and the context is popped from the stack.
A subroutine call occupies two locations and an in­terrupt five locations in the stack area.
-
-
-
-
Figure 6. Stack Manipulation Example
@ 0100h
SP
@ 017Fh
CALL
Subroutine
SP
PCH PCL
Stack Higher Address = 017Fh Stack Lower Address =
Interrupt
Event
SP
CC
A
X PCH PCL PCH PCL
0100h
PUSH Y POP Y IRET
SP
Y
CC
A X
PCH
PCL
PCH
PCL
CC
A
X PCH PCL PCH PCL
SP
PCH PCL
RET
or RSP
SP
16/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

6 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72104G-Auto, ST72215G-Auto, ST72216G-Auto and ST72254G-Auto microcon trollers include a range of utility features for secur­ing the application in critical situations (for exam­ple, in case of a power brown-out), and reducing the number of external components. An overview is shown in
Figure 7.
See Section 13 "ELECTRICAL CHARACTERIS-
TICS" on page 95 for more details.
Main Features
Supply Manager with main supply low voltage
detection (LVD)
Reset Sequence Manager (RSM)
Multi-Oscillator (MO)
– 4 Crystal/Ceramic resonator oscillators – 1 External RC oscillator – 1 Internal RC oscillator
Clock Security System (CSS) – Clock Filter
– Backup Safe Oscillator
-
Figure 7. Clock, Reset and Supply Block Diagram
MCO
OSC2
OSC1
RESET
V
DD
V
SS
MULTI-
OSCILLATOR
(MO)
RESET SEQUENCE
MANAGER
(RSM)
LOW VOLTAGE
DETECTOR
(LVD)
CLOCK SECURITY SYSTEM
CLOCK
FILTER
(CSS)
SAFE
OSC
CRSR
f
OSC
FROM
WATCHDOG
PERIPHERAL
MAIN CLOCK
CONTROLLER
(MCC)
LVD
f
CPU
CSS WDG
IE D00 0 0 RF RF
CSS INTERRUPT
17/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

6.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detec
­tor function (LVD) generates a static reset when the V
supply voltage is below a V
DD
reference
IT-
value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
The V than the V to avoid a parasitic reset when the MCU starts run
reference value for a voltage drop is lower
IT-
reference value for power-on in order
IT+
­ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
is below:
V
DD
–V
when VDD is rising
IT+
–V
when VDD is falling
IT-
The LVD function is illustrated in the Figure 8. Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above V
, the MCU
IT-
can only be in two modes:
– under full software control – in static safe reset
Figure 8. Low Voltage Detector vs Reset
V
DD
In these conditions, secure operation is always en­sured for the application without the need for ex­ternal reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
Notes:
1. The LVD allows the device to be used without any external RESET circuitry.
2. Three different reference levels are selectable through the option byte according to the applica­tion requirement.
LVD application note
Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register.
This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).
V
IT+
V
IT-
RESET
V
hyst
18/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introduction
The reset sequence manager includes three RE­SET sources as shown in Figure 10:
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
These sources act on the RESET pin and it is al­ways kept low during the delay phase.
The RESET service routine vector is fixed at ad­dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of three phases as shown in
Delay depending on the RESET source
4096 CPU clock cycle delay
RESET vector fetch
Figure 9:
Figure 10. Reset Block Diagram
V
RESET
DD
R
ON
f
CPU
The 4096 CPU clock cycle delay allows the oscil­lator to stabilise and ensures that recovery has taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock cycles.
Figure 9. RESET Sequence Phases
RESET
DELAY
INTERNAL RESET
4096 CLOCK CYCLES
COUNTER
FETCH
VECTOR
INTERNAL RESET
WATCHDOG RESET
LVD RESET
19/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain output with integrated R This pull-up has no fixed value but varies in ac
weak pull-up resistor.
ON
­cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.
A RESET signal originating from an external source must have a duration of at least t
h(RSTL)in
order to be recognized. This detection is asynchro
in
­nous and therefore the MCU can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris
­tics section.
Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see
Figure 11).
Starting from the external RESET pulse recogni­tion, the device RESET pin acts as an output that is pulled low during at least t
w(RSTL)out
.
Figure 11. RESET Sequences
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in­ternal LVD circuitry can be distinguished:
Power-On RESET
Voltage Drop RESET
The device RESET pin acts as an output that is pulled low when V V
DD<VIT-
(falling edge) as shown in Figure 11.
DD<VIT+
The LVD filters spikes on V
(rising edge) or
larger than t
DD
g(VDD)
to
avoid parasitic resets.
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal Watchdog counter overflow is shown in
Figure 11.
Starting from the Watchdog counter underflow, the device low during at least t
RESET pin acts as an output that is pulled
w(RSTL)out
.
V V
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
IT+
IT-
V
DD
RUN
LVD
RESET
DELAY
RUN
t
w(RSTL)out
t
h(RSTL)in
SHORT EXT.
RESET
DELAY
LONG EXT.
RESET
RUN RUN
DELAY
t
h(RSTL)in
WATCHDOG UNDERFLOW
WATCHDOG
RESET
RUN
DELAY
t
w(RSTL)out
INTERNAL RESET (4096 T FETCH VECTOR
CPU
)
20/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

6.3 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by four different source types coming from the multi­oscillator block:
an external source
4 crystal or ceramic resonator oscillators
an external RC oscillator
an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in
Table 3. Refer to the
electrical characteristics section for more details.
External Clock Source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of pro­ducing a very accurate rate on the main clock of the ST7. The selection within a list of four oscilla
­tors with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RE­SET phase to avoid losing time in the oscillator start-up phase.
tion should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied to ground.
Table 3. ST7 Clock Sources
Hardware Configuration
ST7
ST7
LOAD
CAPACITORS
ST7
C
L2
External ClockCrystal/Ceramic ResonatorsExternal RC OscillatorInternal RC Oscillator
OSC1 OSC2
EXTERNAL
SOURCE
OSC1 OSC2
C
L1
OSC1 OSC2
External RC Oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an external resis tor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is dependent on V
, TA, process varia-
DD
tions and the accuracy of the discrete components used. This option should not be used in applica tions that require accurate timing.
Internal RC Oscillator
The internal RC oscillator mode is based on the same principle as the external RC oscillator includ ing the resistance and the capacitance of the de­vice. This mode is the most cost effective one with the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz. This op
R
EX
C
EX
-
ST7
OSC1 OSC2
-
-
-
21/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

6.4 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in
­tegration of the security features in the applica­tions, it is based on a clock filter control and an In­ternal safe oscillator. The CSS can be enabled or disabled by option byte.
6.4.1 Clock Filter Control
The clock filter is based on a clock frequency limi­tation function.
This filter function is able to detect and filter high frequency spikes on the ST7 main clock.
If the oscillator is not working properly (e.g. work­ing at a harmonic frequency of the resonator), the current active oscillator clock can be totally fil
­tered, and then no clock signal is available for the ST7 from this oscillator anymore. If the original clock source recovers, the filtering is stopped au
­tomatically and the oscillator supplies the ST7 clock.
6.4.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low fre­quency back-up clock source (see Figure 12).
If the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations.
Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers.
Limitation detection
The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generated if the CS SIE bit has been previously set.
These two bits are described in the CRSR register description.
6.4.3 Low Power Modes
Mode Description
WAIT
HALT
No effect on CSS. CSS interrupt cause the device to exit from Wait mode.
The CRSR register is frozen. The CSS (in­cluding the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.
6.4.4 Interrupts
The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is re set (RIM instruction).
Interrupt Event
CSS event detection (safe oscillator acti vated as main clock)
Flag
Enable
Control
Bit
Event
-
CSSD CSSIE Yes No
Exit from Wait
Exit
from
Halt
1)
-
-
Notes:
1. This interrupt allows to exit from Active Halt mode if this mode is available in the MCU.
Figure 12. Clock Filter Function and Safe Oscillator Function
f
/2
OSC
f
FUNCTION
CPU
CLOCK FILTER
f
/2
OSC
f
SFOSC
FUNCTION
f
CPU
SAFE OSCILLATOR
22/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)

Read / Write Reset Value: 000x 000x (XXh)
7 0
0 0 0
LVD
RF
CSSIECSSDWDG
0
RF
Bit 7:5 = Reserved, always read as 0.
Bit 4 = LVDRF LVD reset flag This bit indicates that the last RESET was gener­ated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined.
Bit 3 = Reserved, always read as 0.
Bit 2 = CSSIE Clock security syst. interrupt enable This bit enables the interrupt when a disturbance is detected by the clock security system (CSSD bit set). It is set and cleared by software. 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled Refer to Table 5, “Interrupt Mapping,” on page 26 for more details on the CSS interrupt vector. When the CSS is disabled by option byte, the CSSIE bit has no effect.
Bit 1 = CSSD Clock security system detection This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (f
). It is set by hardware and cleared by
OSC
reading the CRSR register when the original oscil lator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the CSS is disabled by option byte, the CSSD bit value is forced to 0.
Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last RESET was gener­ated by the watchdog peripheral. It is set by hard­ware (Watchdog RESET) and cleared by software (writing zero) or an LVD RESET (to ensure a sta ble cleared state of the WDGRF flag when the CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources LVDRF WDGRF
External RESET pin 0 0 Watchdog 0 1 LVD 1 X
Application notes
The LVDRF flag is not cleared when another RE­SET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the origi nal failure. In this case, a watchdog reset can be detected by software while an external reset cannot.
-
-
-
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
0025h
Register
Label
CRSR Reset Value 0 0 0
7 6 5 4 3 2 1 0
LVDRF
x
0
CSSIE0CSSD0WDGRF
x
23/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

6.6 MAIN CLOCK CONTROLLER (MCC)

The Main Clock Controller (MCC) supplies the clock for the ST7 CPU and its internal peripherals. It allows SLOW power saving mode to be man aged by the application.
All functions are managed by the Miscellaneous register 1 (MISCR1).
The MCC block consists of:
A programmable CPU clock prescaler
A clock-out signal to supply external devices
The prescaler allows the selection of the main clock frequency and is controlled by three bits of
-
the MISCR1: CP1, CP0 and SMS. The clock-out capability consists of a dedicated
I/O port pin configurable as an f drive external devices. It is controlled by the MCO bit in the MISCR1 register.
See Section 10 "MISCELLANEOUS REGIS-
TERS" on page 36 for more details.
Figure 13. Main Clock Controller (MCC) Block Diagram
PORT
ALTERNATE
f
OSC
/2
MISCR1
FUNCTION
MCO ----
CP1 CP0
SMS
clock output to
CPU
CLOCK TO CAN
PERIPHERAL
MCO
f
OSC
DIV 2
DIV 2, 4, 8, 16
f
CPU
CPU CLOCK
TO CPU AND
PERIPHERALS
24/135

7 INTERRUPTS

ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
The ST7 core may be interrupted by one of two dif­ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non­maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in
The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).
Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector address es).
The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume.
Priority Management
By default, a servicing interrupt cannot be inter­rupted because the I bit is set by hardware enter­ing in interrupt routine.
In the case when several interrupts are simultane­ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map ping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT” column in the Interrupt Mapping Ta ble).

7.1 NON-MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc­tion is executed regardless of the state of the I bit.
Figure 14.
-
-
-
-
It will be serviced according to the flowchart on
Figure 14.

7.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).
An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.
If several input pins, connected to the same inter­rupt vector, are configured as interrupts, their sig­nals are logically NANDed before entering the edge/level detection block.
Caution: The type of sensitivity defined in the Mis­cellaneous or Interrupt register (if available) ap­plies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of rising­edge sensitivity.

7.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:
– The I bit of the CC register is cleared. – The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the flag is set
followed by a read or write of an associated reg ister.
Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be en abled) will therefore be lost if the clear sequence is executed.
-
-
25/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
INTERRUPTS (Cont’d)
Figure 14. Interrupt Processing Flowchart
FROM RESET
N
N
INTERRUPT
PENDING?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
I BIT SET?
Y
FETCH NEXT INSTRUCTION
N
THIS CLEARS I BIT BY DEFAULT
IRET?
Y
Table 5. Interrupt Mapping
No.
Source
Block
Description
RESET Reset
TRAP Software Interrupt no FFFCh-FFFDh
0 ei0 External Interrupt Port A7..0 (C5..01)
Register
Label
N/A
Priority
Order
Highest
Priority
1 ei1 External Interrupt Port B7..0 (C5..01) FFF8h-FFF9h
2 CSS Clock Security System Interrupt CRSR
3 SPI SPI Peripheral Interrupts SPISR FFF4h-FFF5h
4 TIMER A TIMER A Peripheral Interrupts TASR FFF2h-FFF3h
5 Not used FFF0h-FFF1h
6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh-FFEFh
7 Not used FFECh-FFEDh
8 Not used FFEAh-FFEBh
9 Not used FFE8h-FFE9h
10 Not used FFE6h-FFE7h
11 I²C I²C Peripheral Interrupt I2CSRx no FFE4h-FFE5h
12 Not Used FFE2h-FFE3h
13 Not Used FFE0h-FFE1h
Lowest Priority
Notes:
1. Configurable by option byte.
Exit from
HALT
Address
Vector
yes FFFEh-FFFFh
yes
FFFAh-FFFBh
FFF6h-FFF7h
no
26/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the applica­tion in terms of power consumption, three main power saving modes are implemented in the ST7
Figure 15).
(see After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f
CPU
).
From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.
Figure 15. Power Saving Mode Transitions
High
RUN
SLOW
WAIT

8.2 SLOW MODE

This mode has two targets: – To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
CPU
) to
the available supply voltage.
SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f
CPU
).
In this mode, the oscillator frequency can be divid­ed by 4, 8, 16 or 32 instead of 2 in normal operat­ing mode. The CPU and peripherals are clocked at this lower frequency.
Note: SLOW-WAIT mode is activated when enter­ing WAIT mode while the device is already in SLOW mode.
Figure 16. SLOW Mode Clock Transitions
f
f
CPU
f
OSC
CP1:0
/2
/4 f
OSC
00 01
/8 f
OSC
OSC
/2
SLOW WAIT
HALT
Low
POWER CONSUMPTION
SMS
MISCR1
NEW SLOW
FREQUENCY
REQUEST
NORMAL RUN MODE
REQUEST
27/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

WAIT mode places the MCU in a low power con­sumption mode by stopping the CPU.
This power saving mode is selected by calling the “WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and memory re
­main unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereup
­on the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up.
Refer to Figure 17.
Figure 17. WAIT Mode Flowchart
OSCILLATOR
WFI INSTRUCTION
N
INTERRUPT
Y
PERIPHERALS CPU I BIT
N
RESET
Y
OSCILLATOR PERIPHERALS CPU I BIT
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR PERIPHERALS CPU IBIT
ON ON
OFF
0
ON
OFF
ON
1
ON ON ON
1)
X
FETCH RESET VECTOR OR SERVICE INTERRUPT
Notes:
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
28/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto
POWER SAVING MODES (Cont’d)

8.4 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see
Figure 19).
The MCU can exit HALT mode on reception of ei­ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the os
­cillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure 18).
When entering HALT mode, the I bit in the CC reg­ister is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immedi
­ately.
In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, in
­cluding the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla
­tor).
The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” op
­tion bit of the option byte. The HALT instruction when executed while the Watchdog system is en
­abled, can generate a Watchdog RESET (see
Section 15.1 "OPTION BYTES" on page 129 for
more details).
Figure 18. HALT Mode Timing Overview
HALTRUN RUN
4096 CPU CYCLE
DELAY
Figure 19. HALT Mode Flow-chart
HALT INSTRUCTION
WDGHALT
1
WATCHDOG
RESET
N
INTERRUPT
Y
1)
ENABLE
0
OSCILLATOR PERIPHERALS CPU I BIT
N
3)
OSCILLATOR PERIPHERALS CPU I BIT
4096 CPU CLOCK CYCLE
OSCILLATOR PERIPHERALS CPU I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
WATCHDOG
RESET
Y
DELAY
DISABLE
OFF
2)
OFF OFF
0
ON
OFF
ON
1
ON ON ON
4)
X
HALT
INSTRUCTION
INTERRUPT
RESET
OR
FETCH
VECTOR
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 5,
“Interrupt Mapping,” on page 26 for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
29/135
ST72104Gx-Auto, ST72215Gx-Auto, ST72216Gx-Auto, ST72254Gx-Auto

9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs
and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has two main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis­ters: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.
The following description takes into account the OR register, (for specific ports which do not pro
­vide this register refer to the I/O Port Implementa­tion section). The generic I/O block diagram is shown in
Figure 20.
9.2.1 Input Modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Notes:
1. Writing the DR register modifies the latch value but does not affect the pin status.
2. When switching from input to output mode, the DR register has to be written first to drive the cor
­rect level on the pin as soon as the port is config­ured as an output.
3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter
­rupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the Mis
-
cellaneous register. Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description and interrupt section). If several input pins are se
­lected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones.
In case of a floating input with interrupt configura­tion, special care must be taken when changing the configuration (see
Figure 21).
The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellane
­ous register must be modified.
9.2.2 Output Modes
The output configuration is selected by setting the corresponding DDR register bit. In this case, writ
­ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg
­ister returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.
DR register value and output pin status:
DR Push-pull Open-drain
0 V 1 V
SS
DD
V
SS
Floating
9.2.3 Alternate Functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically select
­ed. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip periph­eral, the I/O pin is automatically configured in out­put mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note: Input pull-up configuration can cause unex­pected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as in
­put and output, this pin has to be configured in in­put floating mode.
30/135
Loading...
+ 105 hidden pages