ST M48T212A User Manual

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■ CONVERTS LOW POWER SRAM int o

NVRAMs

■ YEAR 2000 COMPLIANT (4-Digit Year)

■ USES SUPER CAPACITOR or LITHIUM

BATTERY (User Supplied)

■ BATTERY LOW FLAG

■ INTEGRATED REAL TIME CLOCK,

POWER-FAIL CONTROL CIRCUIT

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WATCHDOG T IM E R

■ WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48T212A: 2.7V ≤ V

■ MICROPRO CESSOR POWER-ON RESET

■ PROG R AMMA BLE ALA R M O U TPUT ACTIVE

in the BATTERY BACKED-UP MODE

PFD

≤ 3.0V

M48T212A

3.3V TIMEKEEPER® CONTROLLER

PRELIMINARY DATA

44

1

SOH44 (MH)

Figure 1. Logic Diagram

CC

V

CAP

V

DESCRIPTION

The M48T212A is a se lf-contained device that includes a real time clock (RTC), programmable alarms, a watchdog timer, and two external chip enable outputs which provide control of up to four (two in parallel) external low-power static RAMs.

A built-in 32.768 kHz oscillator (external crystal controlled) is used for the clock/calendar function.

Access to all TIMEKEEPER functions and the external RAM is the same as conventional byte-wide SRAM. The 16 TIMEKEEPER Registers offer Century, Year, Month, Date, Day, Hour, Minute, Second, Control, Calibration, Alarm, Watchdog, and Flags. Externally attached static RAMs are controlled by the M48T212A via the E1

signals (see Table 4).

E2

CON

and

Automatic backup and write protection for an external SRAM is provided through V and E2

pins. (Users are urged to insure that

CON

OUT

, E1

CON

voltage specifications, for both the controll er chip and external SRAM chosen, are similar).

A0-A3

EX

W

WDI RSTIN1 RSTIN2

X0

XI

4

A E

G

M48T212A

V

SS

V

BAT–

8

DQ0-DQ7

IRQ/FT RST E1

CON

E2

CON

V

CCSW

V

OUT

AI03047

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/20

M48T212A

Figure 2. SOIC Connections

XI

1 2 3 4 5 6 7 8 9

A

10 11

M48T212A

12 13 14 15 16 17 18 19 20 21 22

RSTIN1 RSTIN2

RST

NC XO EX

NC NC

NC NC NC

A3 A2 A1 A0

WDI

E2

CON

DQ1 DQ2

V

SS

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

AI03048

V

CC

V

OUT

V

CCSW

IRQ/FT

NC NC NC NC NC G W V

BAT–

NC E E1

CON

DQ7 DQ6 DQ5DQ0 DQ4 DQ3 V

CAP

Table 1. Signal Names

A0-A3 Address Inputs DQ0-DQ7 Data Inputs/Outputs XO Oscillator Output XI Oscillator Input RSTIN1 RSTIN2 RST WDI Watchdog Input A Bank Select Input E EX G W E1

CON

E2

CON

IRQ

/FT Int/Freq Test Output (Open Drain) Vccsw V

OUT

V

CAP

V

BAT–

V

CC

V

SS

NC Not Connected internally

Reset 1 Input Reset 2 Input Reset Output (Open Drain)

Chip Enable Input External Chip Enable Input Output Enable Input Write Enable Input RAM Chip Enable 1 Output RAM Chip Enable 2 Output

VCC Switch Output Supply Voltage Output Super Capacitor Input Battery Ground Pin (optional) Supply Voltage Ground

The lithium energy source (or super capacitor) used to permanently power the real time clock is also used to retain RAM data in the absence of

power through the V

V

CC

The chip enable outputs to RAM (E1

) are controlled during power transie nts to

E2

CON

OUT

pin.

CON

and

prevent data corruption. The dat e is aut om atically adjusted for months with less than 31 days and corrects for leap years. The internal watchdog timer provides programmable alarm windows.

The nine clock bytes (Fh - 9h and 1h) are not the actual clock counters, they are memory locations consisting of BiPORT

TM

read/write memory cells within the static RAM array. Clock circuitry updates the clock bytes with current information once per second. The information ca n be accessed by the user in the same manner as any other location in the static memory array.

Byte 8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibra tion setting. Byte 7h con-

2/20

tains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the W atchdog Stee ring bit (WDS). Bytes 6h-2h include bits that, when programmed, provide for clock alarm functionality.

Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 1h contains century information. Byte 0h contains additional flag information pertaining to the watchdog timer, alarm and battery status.

The M48T212A also has its o wn Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When V

is out of tolerance, the circuit

CC

write pro tect s the TI MEKEEPER regist er data and external SRAM, providing data security in the midst of unpredictable system operat ion. As V

CC

falls, the control circuitry automatically switches to the battery, maintaining data and clock o peration until valid power is restored.

M48T212A

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

STG

(2)

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional opera tion of the devi ce at these or any other conditions above those i ndi cated in th e operational section of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowe d on any pin while i n the Batter y Back-up mod e.

Table 3. Operating Modes

Mode

Deselect

Write Read Read

Deselect Deselect

Note: 1. X = VIH or VIL.

2. V

SO

Ambient Operating Temperature 0 to 70 °C

Storage Temperature (VCC Off, Oscillator Off)

–55 to 125 °C Lead Solder Temperature for 10 sec 260 °C Input or Output Voltages –0.3 to 4.6 V

Supply Voltage –0.3 to 4.6 V Output Current 20 mA Power Dissipation 1 W

(1)

V

CC

3.0V to 3.6V

V

to V

SO

PFD

≤ V

SO

= Battery Back-up Swit chover Voltage. (See Ta bl e 7 for details).

(min)

(2)

E G W DQ7-DQ0 Power

V

IH

V

IL

V

IL

V

IL

X X High-Z Standby X

V

IL

V

IH

V

IL

V

IH

V

IH

D

IN

D

OUT

High-Z Active X X X High-Z CMOS Standby X X X High-Z Battery Back-Up

Active Active

Table 4. Truth Table for SRAM Bank Select

Mode

V

CC

(1)

EX A

E1

CON

E2

CON

Low Low Low High Active

Select

3.0V to 3.6V

Low High High Low Active

Deselect High X High High Standby Deselect

Deselect

Note: 1. X = VIH or VIL.

= Battery Back-up Swit chover Voltage. (See Ta bl e 7 for details).

2. V

SO

to V

V

SO

PFD

≤ V

SO

(min)

(2)

X X High High CMOS Standby X X High High Battery Back-Up

Power

3/20

M48T212A

Figure 3. Hardware Hookup

A0-A18

3.3V

0.1µF

SuperCap Supply

1N5817

0.1µF

32 kHz Crystal

MOTOROLA MTD20P06HDL

V

CC

E

V

CC

E

A0-Axx

CMOS SRAM

A0-Axx

CMOS SRAM

A0-A3

V

CC

(1)

A

E

M48T212A

EX

W

G

WDI

RSTIN1

RSTIN2

DQ0-DQ7

V

CAP

V

SS

CCSW

V

OUT

E1

CON

E2

CON

RST

IRQ/FT

Note 2

X0

XI

Note: 1. See descri ption in Power Suppl y Decouplin g and Undershoot Protection.

2. Trac es connecting E1

Figure 4. AC Testing Load Circuit

CON

and E2

to external SRAM should be as short as possible.

CON

(3,4)

Table 5. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns

DEVICE UNDER

TEST

645Ω

Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no longer driven.

(1)

(2)

1.75V

AI03239

CL includes JIG capacitance

Note: 1. DQ0-DQ7

2. E1

3. Exc l udi ng open-drain output pins

CON

and E2

CON

CL = 100pF or 5pF CL = 30 pF

4/20

AI03049

M48T212A

Table 6. Capacitance

(T

= 25 °C, f = 1 MHz)

A

(1)

Symbol Parameter Test Condition Min Max Unit

C

OUT

Note: 1. Sampled only, not 100% tested.

2. Outputs desele ct ed.

Input Capacitance

IN

(2)

Input/Output Capacitance

V

OUT

IN

= 0V

10 pF 10 pF

Table 7. DC Characteristics

= 0 to 70°C; VCC = 3V to 3.6V)

(T

A

Symbol Parameter Test Condition Min Typ Max Unit

(1,2)

I

LI

I

LO

I

CC

I

CC1

I

CC2

I

BAT

V V

Input Leakage Current

(1)

Output Leakage Curren t Supply Current Outputs Open 4 10 mA Supply Current (Standby) TTL

Supply Current (Standby) CMOS Battery Current OSC ON 575 800 nA Battery Current OSC OFF 100 nA Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.0

IH

Output Low Voltage

V

OL

Output Low Voltage (open drain)

V

OHB

I

OUT1

I

OUT2

V

PFD

V

CAP

Note: 1. Outputs deselected.

Output High Voltage

OH

(4)

VOH Battery Back-up I

(5)

V

Current (Active) V

OUT

V

Current (Battery Back-up) V

OUT

Power-fail Deselect Voltage 2.7 2.9 3.0 V Battery Back-up Switchover Voltage

SO

Battery Voltage 3.0 V

BAT

CON

(6)

- E2

CON

Capacitor Voltage

2. RST IN1

3. For I RQ

4. Con di t i oned output s (E1

5. External SRAM must match TIMEKEEPER Controller chip V

6. Whe n fu l l y charged.

and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor. /FT & RST pins (Open Drain).

rents will reduce battery life.

(3)

) can onl y sustain CMOS leakage currents in the battery back-up mode. Hi gher leaka ge cur-

0V ≤ V

OUT

E

= V

E

= V

I

= 2.1mA

OL

IOL = 10mA

I

= –1.0mA

OH

= –1.0µA

OUT2

> VCC –0.3

OUT1

> V

OUT2

≤ V

IN

CC

≤ V

IH

–0.2

CC

–0.3

BA T

specification.

CC

±1 µA ±1 µA

3mA 2mA

V

+ 0.3

CC

0.4 V

2.4 V

2.0 3.6 V 70 mA

100 µA

V

–100mV

PFD

V

CC

V

5/20

M48T212A

Figure 5. Power Down/Up AC Waveform

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

INPUTS

OUTPUTS

RST

V

CCSW

tF

tFB

VALID VALID

DON'T CARE

HIGH-Z

tR

tRECtRB

AI02638

Table 8. Power Down/Up AC Characteristics

(T

= 0 to 70°C)

A

Symbol Parameter Min Max Unit

V

t

F

(max) to V

PFD

(min) VCC Fall Time

PFD

300 µs

6/20

t

FB

t

REC

t

RB

V

(min) to VSS VCC Fall Time

PFD

V

R

(min) to V

PFD

V

(max) to RST High

PFD

VSS to V

PFD

(max) VCC Rise Time

PFD

(min) VCC Rise Time

150 µs

10 µs 40 20 0 ms

5µs