Datasheet M48T212A Datasheet (ST)

查询M48T212A供应商

■ CONVERTS LOW POWER SRAM int o

NVRAMs

■ YEAR 2000 COMPLIANT (4-Digit Year)

■ USES SUPER CAPACITOR or LITHIUM

BATTERY (User Supplied)

■ BATTERY LOW FLAG

■ INTEGRATED REAL TIME CLOCK,

POWER-FAIL CONTROL CIRCUIT

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WATCHDOG T IM E R

■ WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48T212A: 2.7V ≤ V

■ MICROPRO CESSOR POWER-ON RESET

■ PROG R AMMA BLE ALA R M O U TPUT ACTIVE

in the BATTERY BACKED-UP MODE

PFD

≤ 3.0V

M48T212A

3.3V TIMEKEEPER® CONTROLLER

PRELIMINARY DATA

44

1

SOH44 (MH)

Figure 1. Logic Diagram

CC

V

CAP

V

DESCRIPTION

The M48T212A is a se lf-contained device that in­cludes a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.

A built-in 32.768 kHz oscillator (external crystal
controlled) is used for the clock/calendar function.

Access to all TIMEKEEPER functions and the ex­ternal RAM is the same as conventional byte-wide
SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Control, Calibration, Alarm, Watchdog,
and Flags. Externally attached static RAMs are
controlled by the M48T212A via the E1

signals (see Table 4).

E2

CON

CON

and

Automatic backup and write protection for an ex­ternal SRAM is provided through V
and E2

pins. (Users are urged to insure that

CON

OUT

, E1

CON

voltage specifications, for both the controll er chip
and external SRAM chosen, are similar).

A0-A3

EX

W

WDI
RSTIN1
RSTIN2

X0

XI

4

A
E

G

M48T212A

V

SS

V

BAT–

8

DQ0-DQ7

IRQ/FT
RST
E1

CON

E2

CON

V

CCSW

V

OUT

AI03047

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/20

M48T212A

Figure 2. SOIC Connections

XI

1
2
3
4
5
6
7
8
9

A

10
11

M48T212A

12
13
14
15
16
17
18
19
20
21
22

RSTIN1
RSTIN2

RST

NC
XO EX

NC
NC

NC
NC
NC

A3
A2
A1
A0

WDI

E2

CON

DQ1
DQ2

V

SS

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

AI03048

V

CC

V

OUT

V

CCSW

IRQ/FT

NC
NC
NC
NC
NC
G
W
V

BAT–

NC
E
E1

CON

DQ7
DQ6
DQ5DQ0
DQ4
DQ3
V

CAP

Table 1. Signal Names

A0-A3 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
XO Oscillator Output
XI Oscillator Input
RSTIN1
RSTIN2
RST
WDI Watchdog Input
A Bank Select Input
E
EX
G
W
E1

CON

E2

CON

IRQ

/FT Int/Freq Test Output (Open Drain)
Vccsw
V

OUT

V

CAP

V

BAT–

V

CC

V

SS

NC Not Connected internally

Reset 1 Input
Reset 2 Input
Reset Output (Open Drain)

Chip Enable Input
External Chip Enable Input
Output Enable Input
Write Enable Input
RAM Chip Enable 1 Output
RAM Chip Enable 2 Output

VCC Switch Output
Supply Voltage Output
Super Capacitor Input
Battery Ground Pin (optional)
Supply Voltage
Ground

The lithium energy source (or super capacitor)
used to permanently power the real time clock is
also used to retain RAM data in the absence of

power through the V

V

CC

The chip enable outputs to RAM (E1

) are controlled during power transie nts to

E2

CON

OUT

pin.

CON

and

prevent data corruption. The dat e is aut om atically
adjusted for months with less than 31 days and
corrects for leap years. The internal watchdog tim­er provides programmable alarm windows.

The nine clock bytes (Fh - 9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT

TM

read/write memory cells
within the static RAM array. Clock circuitry up­dates the clock bytes with current information once
per second. The information ca n be accessed by
the user in the same manner as any other location
in the static memory array.

Byte 8h is the clock control register. This byte con­trols user access to the clock information and also
stores the clock calibra tion setting. Byte 7h con-

2/20

tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the W atchdog Stee ring
bit (WDS). Bytes 6h-2h include bits that, when pro­grammed, provide for clock alarm functionality.

Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.

The M48T212A also has its o wn Power-Fail De­tect circuit. This control circuitry constantly moni­tors the supply voltage for an out of tolerance
condition. When V

is out of tolerance, the circuit

CC

write pro tect s the TI MEKEEPER regist er data and
external SRAM, providing data security in the
midst of unpredictable system operat ion. As V

CC

falls, the control circuitry automatically switches to
the battery, maintaining data and clock o peration
until valid power is restored.

M48T212A

Table 2. Absolute Maximum Ratings

(1)

Symbol Parameter Value Unit

T

A

T

STG

(2)

T

SLD

V

IO

V

CC

I

O

P

D

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional opera tion of the devi ce at these or any other conditions above those i ndi cated in th e operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowe d on any pin while i n the Batter y Back-up mod e.

Table 3. Operating Modes

Mode

Deselect

Write
Read
Read

Deselect
Deselect

Note: 1. X = VIH or VIL.

2. V

SO

Ambient Operating Temperature 0 to 70 °C

Storage Temperature (VCC Off, Oscillator Off)

–55 to 125 °C
Lead Solder Temperature for 10 sec 260 °C
Input or Output Voltages –0.3 to 4.6 V

Supply Voltage –0.3 to 4.6 V
Output Current 20 mA
Power Dissipation 1 W

(1)

V

CC

3.0V to 3.6V

V

to V

SO

PFD

≤ V

SO

= Battery Back-up Swit chover Voltage. (See Ta bl e 7 for details).

(min)

(2)

(2)

E G W DQ7-DQ0 Power

V

IH

V

IL

V

IL

V

IL

X X High-Z Standby
X

V

IL

V

IH

V

IL

V

IH

V

IH

D

IN

D

OUT

High-Z Active
X X X High-Z CMOS Standby
X X X High-Z Battery Back-Up

Active
Active

Table 4. Truth Table for SRAM Bank Select

Mode

V

CC

(1)

EX A

E1

CON

E2

CON

Low Low Low High Active

Select

3.0V to 3.6V

Low High High Low Active

Deselect High X High High Standby
Deselect

Deselect

Note: 1. X = VIH or VIL.

= Battery Back-up Swit chover Voltage. (See Ta bl e 7 for details).

2. V

SO

to V

V

SO

PFD

≤ V

SO

(min)

(2)

(2)

X X High High CMOS Standby
X X High High Battery Back-Up

Power

3/20

M48T212A

Figure 3. Hardware Hookup

A0-A18

3.3V

0.1µF

SuperCap Supply

1N5817

0.1µF

32 kHz
Crystal

MOTOROLA
MTD20P06HDL

V

CC

E

V

CC

E

A0-Axx

CMOS
SRAM

A0-Axx

CMOS
SRAM

A0-A3

V

V

CC

(1)

A

E

M48T212A

EX

W

G

WDI

RSTIN1

RSTIN2

DQ0-DQ7

V

CAP

V

SS

CCSW

V

OUT

E1

CON

E2

CON

RST

IRQ/FT

Note 2

X0

XI

Note: 1. See descri ption in Power Suppl y Decouplin g and Undershoot Protection.

2. Trac es connecting E1

Figure 4. AC Testing Load Circuit

CON

and E2

to external SRAM should be as short as possible.

CON

(3,4)

Table 5. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns

DEVICE
UNDER

TEST

645Ω

Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data
is no longer driven.

(1)

(2)

1.75V

AI03239

CL includes JIG capacitance

Note: 1. DQ0-DQ7

2. E1

3. Exc l udi ng open-drain output pins

CON

and E2

CON

CL = 100pF or 5pF
CL = 30 pF

4/20

AI03049

M48T212A

Table 6. Capacitance

(T

= 25 °C, f = 1 MHz)

A

(1)

Symbol Parameter Test Condition Min Max Unit

C

C

OUT

Note: 1. Sampled only, not 100% tested.

2. Outputs desele ct ed.

Input Capacitance

IN

(2)

Input/Output Capacitance

V

V

OUT

IN

= 0V

= 0V

10 pF
10 pF

Table 7. DC Characteristics

= 0 to 70°C; VCC = 3V to 3.6V)

(T

A

Symbol Parameter Test Condition Min Typ Max Unit

(1,2)

I

LI

I

LO

I

CC

I

CC1

I

CC2

I

BAT

V
V

Input Leakage Current

(1)

Output Leakage Curren t
Supply Current Outputs Open 4 10 mA
Supply Current (Standby) TTL

Supply Current (Standby) CMOS
Battery Current OSC ON 575 800 nA
Battery Current OSC OFF 100 nA
Input Low Voltage –0.3 0.8 V

IL

Input High Voltage 2.0

IH

Output Low Voltage

V

OL

Output Low Voltage (open drain)

V

V

OHB

I

OUT1

I

OUT2

V

PFD

V

V

V

CAP

Note: 1. Outputs deselected.

Output High Voltage

OH

(4)

VOH Battery Back-up I

(5)

V

Current (Active) V

OUT

V

Current (Battery Back-up) V

OUT

Power-fail Deselect Voltage 2.7 2.9 3.0 V
Battery Back-up Switchover Voltage

SO

Battery Voltage 3.0 V

BAT

CON

(6)

- E2

CON

Capacitor Voltage

2. RST IN1

3. For I RQ

4. Con di t i oned output s (E1

5. External SRAM must match TIMEKEEPER Controller chip V

6. Whe n fu l l y charged.

and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
/FT & RST pins (Open Drain).

rents will reduce battery life.

(3)

) can onl y sustain CMOS leakage currents in the battery back-up mode. Hi gher leaka ge cur-

0V ≤ V

0V ≤ V

OUT

E

= V

E

= V

I

= 2.1mA

OL

IOL = 10mA

I

= –1.0mA

OH

= –1.0µA

OUT2

> VCC –0.3

OUT1

> V

OUT2

≤ V

IN

CC

≤ V

IH

–0.2

CC

–0.3

BA T

specification.

CC

CC

±1 µA
±1 µA

3mA
2mA

V

+ 0.3

CC

0.4 V

0.4 V

2.4 V

2.0 3.6 V
70 mA

100 µA

V

–100mV

PFD

V

CC

V

V

V

5/20

M48T212A

Figure 5. Power Down/Up AC Waveform

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

INPUTS

OUTPUTS

RST

V

CCSW

tF

tFB

VALID VALID

VALID VALID

DON'T CARE

HIGH-Z

tR

tRECtRB

AI02638

Table 8. Power Down/Up AC Characteristics

(T

= 0 to 70°C)

A

Symbol Parameter Min Max Unit

V

t

F

(max) to V

PFD

(min) VCC Fall Time

PFD

300 µs

6/20

t

FB

t

t

REC

t

RB

V

(min) to VSS VCC Fall Time

PFD

V

R

(min) to V

PFD

V

(max) to RST High

PFD

VSS to V

PFD

(max) VCC Rise Time

PFD

(min) VCC Rise Time

150 µs

10 µs
40 20 0 ms

5µs

Table 9. Chip Enable Control and Bank Select Characteristics

(T

= 0 to 70°C)

A

M48T212A

M48T212A

Symbol Parameter

t

EXPD

t

APD

EX to E1
A to E1

CON

CON

or E2

or E2

(Low or High)

CON

(Low or High)

CON

Figure 6. Chi p E nable Contro l and Bank Selec t Tim i ng

EX

tEXPD tAPD

A

E1

CON

E2

CON

Unit-85

Min Max

15 ns
15 ns

tEXPD

AI02639

Table 10. Read Mode Characteristics

(T

= 0 to 70°C)

A

Symbol Parameter

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. CL = 5pF

(1)

(1)

(1)

Read Cycle Time 85 ns
Address Valid to Output Valid 85 ns
Chip Enable Low to Output Valid 85 ns
Output Enable Low to Output Valid 35 ns

Chip Enable Low to Output Transition 5 ns
Output Enable Low to Output Transition 0 ns
Chip Enable High to Output Hi-Z 25 ns

(1)

Output Enable High to Output Hi-Z 25 ns
Address Transition to Output Transition 5 ns

M48T212A

Unit-85

Min M ax

7/20

M48T212A

Address Decoding

The M48T212A accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registe rs. All TIMEKEEP­ER registers reside in the controller chip itself. All
TIMEKEEPER re giste rs are access ed by enabling
E

(Chip Enable).

READ MODE

The M48T212A executes a read cycle whenever

(Write Enable) is high and E (Chip Enable) is

W
low. The unique address specified by the address
inputs (A3-A0) defines which o ne of the on-chip
TIMEKEEPER registers is to be accessed. When

Table 11. Write Mode AC Characteristics

(T

= 0 to 70°C)

A

Symbol Parameter

t

AVAV

t

AVWL

t

AVEL

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVWH

t

DVEH

t

WHDX

t

EHDX

(1,2)

t

WLQZ

t

AVWH

t

AVEH

(1,2)

t

WHQX

Note: 1. CL = 5pF.

2. If E

Write Cycle Time 85 ns
Address Valid to Write Enable Low 0 ns
Address Valid to Chip Enable Low 0 ns
Write Enable Pulse Width 55 ns
Chip Enable Low to Chip Enable High 60 ns
Write Enable High to Address Transition 0 ns
Chip Enable High to Address Transition 0 ns
Input Valid to Write Enable High 30 ns
Input Valid to Chip Enable High 30 ns
Write Enable High to Input Transition 0 ns
Chip Enable High to Input Transition 0 ns

Write Enable Low to Output High-Z 25 ns
Address Valid to Write Enable High 65 ns

Address Valid to Chip Enable High 65 ns
Write Enable High to Output Transition 5 ns

goes low simultaneously with W going l ow, the output s remain in the h i gh i m pedance state.

the address presented t o the M48T212A is in the
range of 0h-Fh, one of the on-board TIMEKEEP­ER registers is accessed and valid data will be
available to the eight data output drivers within
t

after the address input signal is sta ble, pro-

AVQV

viding that the E

and G access times are also sat­isfied. If they are not, then data access must be
measured from the latter occurring signal (E
and the limiting parameter is either t
t

for G rather than the a ddress access time.

GLQV

When EX

input is low, an e xternal S RA M location

ELQV

or G)

for E or

will be selec t ed .
Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten­tion.

M48T212A

Unit-85

Min Max

8/20

Figure 7. Read Cycle Timi ng: R TC C ontrol Sign al s

READ READ WRITE

tAVAV

ADDRESS

M48T212A

tAVAV tAVAV

tELQV

tAVQV tWHAXtAVWL

E

tELQX

G

tGLQV

W

DQ7-DQ0

DATA OUT

VALID

Figure 8. Write Cycle Timing: RTC Control Signals

WRITE WRITE READ

tAVAV

ADDRESS

tWLWH

tAXQXtGLQX

DATA OUT

VALID

tAVAV tAVAV

tGHQZ

DATA IN

VALID

AI02640

E

G

W

DQ0-DQ7

tAVEL

tAVWL

DATA OUT

VALID

tAVEH

tELEH tEHAX

tWLWH

tEHQZ

DATA IN

tEHDX

tDVEH

VALID

tAVWH

tDVWH

tWHAX

tWHQX tWLQZ

tWHDX

DATA IN

VALID

tAVQV

tGLQV

DATA OUT

VALID

AI02641

9/20

M48T212A

Table 12. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

11111 Once per Second
11110 Once per Minute
11100 Once per Hour
11000 Once per Day
10000 Once per Month
00000 Once per Year

Figure 9. Alarm Interrupt Reset Waveforms

A0-A3

ACTIVE FLAG BIT

IRQ/FT

1h Fh

ADDRESS 0h

WRITE MODE

The M48T212A is in th e Write M ode whenever W
(Write Enable) and E (Chip Enable) are in a low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W
earlier rising edge of W
be held valid throughout the cycle. E
turn high for a minimum of t
or t

from Write Enable prior to the initiation of

WHAX

or E. A write is terminated by the

or E. The addresses must

or W must r e-

from Chip Enable

EHAX

another read or write cycle. Data-in must be valid
t

prior to the end of write and remain valid for

DVWH

afterward.

t

WHDX

should be kept high during write cycles to avoid

G
bus contention; although, if the output bus has
been activated by a low on E
disable the outputs t

When E

is low during the write, one of the on-

WLQZ

and G a low on W will

after W falls.

board TIMEKEEPER registe rs will be sele cted and
data will be written into the device. When EX
(and E

is high) an external SRAM location is se-

is low

lected.
Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten­tion.

HIGH-Z

AI03021

DATA RETENTION MODE

With valid V

applied, the M48T212A can be ac-

CC

cessed as described a bove with read or write cy­cles. Should the supply voltage decay, the
M48T212A will automatically deselect, write pro­tecting itself (and any external SRAM ) when V
falls between V

(max) and V

PFD

(min). This is

PFD

CC

accomplished by internally inhibiting access to the
clock registers via the E
Reset pin (RST
active until V

) is driven active and will remain

returns to nominal levels.

CC

signal. At this time, the

External RAM access is inhibited in a similar man­ner by forcing E1
This level is wit hin 0.2V of the V
E2

will remain at this level as long as VCC re-

CON

CON

and E2

to a high level.

CON

BAT

. E1

CON

and

mains at an out-of tolerance condition.
When V

(V

BAT

falls below the level of the battery

CC

), power input is sw itched from the VCC pin
to the battery and the clock registers and ex ternal
SRAM are maintained from the attached battery
supply. All outputs become high impedance. The
V

pin is capable of supplying 100µA of current

OUT

to the attached memory with less than 0.3V drop
under this condition. On power up, when V

CC

re­turns to a nominal value, write protection contin­ues for 200ms (max) by inhibiting E1
E2

.

CON

CON

or

10/20

Table 13. TIMEKEEPER Register Map

M48T212A

Address

D7 D6 D5 D4 D3 D2 D1 D0

Fh 10 Years Year Year 00-99
Eh 0 0 0 10M Month Month 01-12
Dh 0 0 10 Date Date: Day of Month Date 01-31
Ch 0 FT 0 0 0 Day of Week Day 01-7
Bh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23
Ah 0 10 Minutes Minutes Min 00-59

9h ST 10 Seconds Seconds Sec 00-59

8h W R S Calibration Control

7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

6h AFE 0 ABE Al 10M Alarm Month A Month 01-12

5h RPT4 RPT5 AI 10 Date Alarm Date A Date 01-31

4h RPT3 0 AI 10 Hour Alarm Hour A Hour 00-23

3h RPT2 Alarm 10 Minutes Alarm Minutes A Min 00-59

2h RPT1 Alarm 10 Seconds Alarm Seconds A Sec 00-59

1h 1000 Year 100 Year Century 00-99

0h WDF AF Y BL Y Y Y Y Flag

Function/Ran ge

BCD Format

Keys: S = Sign Bit

FT = Frequency Test Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to ze ro
BL = Battery Low Flag
BMB0-BMB4 = Watchdog M ultiplie r B i ts

The RST signal also remains active during this
time (see Figure 5).

Note: Most low power SRAMs on the market to­day can be used with the M48T212A TIMEKEEP­ER Controller. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth­er inputs to the SRAM. This allows inputs to t he
M48T212A and SRAMs to be Don’t Care once
V

falls below V

CC

guarantee data retention down to V

(min). The SRAM should also

PFD

=2.0V. The

CC

chip enable access time must be sufficient to meet
the system needs with the chip enable output
propagation delays included.

If the SRAM includes a second chip enable pin

), this pin should be tied to V

(E2

OUT

.

AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watch dog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1- R PT5 = Alarm Repe at Mode Bits
WDF = Watchdog flag
AF = Alarm flag

Y = ’1’ or ’0’

If data retention lifetime is a critical parameter f or
the system, it is importa nt to re view the dat a reten­tion current specifications for the particular
SRAMs being evaluated. M ost SRAMs specify a
data retention current at 3.0V. Manufacturers gen­erally specify a typical condition for room temper­ature along with a worst case condition (generally
at elevated temperatures). The system level re­quirements will determine the choice of which val­ue to use.

The data retention current value of the SRAMs can
then be added to the I

value of the M48T212A

BAT

to determine the total current requirements for
data retention. The available battery capa city can
then be divided b y this current to determine the
amount of data retention available.

For a further more detailed review of lifetime calcu­lations, please see Application Note AN1012.

11/20

M48T212A

TIMEKEEPER REGISTERS

The M48T212A of fers 16 internal registers which
contain TIMEKEEPER, Alarm, Watchdog, Flag,
and Control data. These regi s ters a re m em ory lo­cations which contain external (user accessible)
and internal copies of the data (usually referred to
as BiPORT

TM

TIMEKEEPER cells).

The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous t ransfer of the incremented
interna l copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Flags
Registers store data in Binary Format.

CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME­KEEPER cel ls in the RAM array are only data reg­isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.

Updating is halted when a ’1' is written to the
READ bit, D6 in the Control Register (8h). As long
as a `1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and time that were
current at the moment the halt command was is­sued.

All of the TIMEKEEPER registers are updated si­multaneously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ bit is reset to a ’0'.

Setting the Clock

Bit D7 of the Control Register (8h) is the WRITE
bit. Setting the WRITE bit to a `1', like the READ
bit, halts updates to the T IMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD f ormat (see
Table 13).

Resetting the WRITE bit to a `0' then transfers the
values of all time registers (Fh-9h, 1h) to the actual
TIMEKEEPER counters and allows normal opera­tion to resume. After the WRIT E bit is reset, the
next clock update will occur one second later.

Note: Upon power-up following a power failure,
the READ bit will automatically be set to a `1'. This
will prevent the clock from updating the TIME-

KEEPER registers, and will allow the user to read
the exact time of the power-down event.

Resetting the RE A D B it t o a `0' wi ll allow the clock
to update these registers with the current time. The
WRITE Bit will be reset to a `0' upon powerup.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the de­vice is going to spend a significant amount of time
on the shelf, the oscillator can be turned off to min­imize current drain on the battery. The STOP bit is
located at Bit D7 within the Seconds Register (9h).
Setting it to a ’1' stops the oscillator. When reset to
a ’0', the M48T212A oscillator starts within one sec­ond.

Note: It is not necessary to set the WRITE bit when
setting or resetting the FREQUENCY TEST bit (FT)
or the STOP bit (ST).

SETTING ALARM CLOCK REGISTERS

Address locations 6h-2h contain the alarm settings.
The alarm can be configured to go off at a pre­scribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro­grammed to go off while the M48T212A is in the
battery back-up to serve as a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 12 shows the poss ibl e configu­rations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.

When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set.

If AFE (Alarm Flag Enable) is also set, the alarm
condition activates the IRQ

/FT pin. The IRQ/FT
output is cleared by a read to the Flags regist er as
shown in Figure 9. A subsequent read of the Flags
register will reset the Alarm Flag (D6; Register 0h).

The IRQ
back-up mode. The IRQ

/FT pin can also be activated in the battery

/FT wi ll g o low if an ala rm
occurs and both ABE (Alarm in Battery Back-up
Mode Enable) and AFE are set. The ABE and AFE
bits are reset during power-up, therefore an alarm
generated during power-up will only set AF. The
user can read the Flag Register at system boot-up
to determine if an alarm was generated while the
M48T212A was in the deselect mode durin g pow­er-up. Figure 10 illustrates the back-up mode alarm
timing.

12/20

Figure 10. Back-Up Mode Alarm Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

AFE bit/ABE bit

AF bit in Flags Register

IRQ/FT

M48T212A

tREC

HIGH-Z

WATCHD OG TI M E R

The watchdog timer can be used to detect an out­of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 7h.

Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu­tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time­out is then determ ined to be the multiplic ation of
the five bit multiplier value with the resolution. (For
example: writing 00001110 in the Wa tchdo g Reg­ister = 3*1 or 3 seconds). If the processor does not
reset the timer within the specified period, the
M48T212A sets the WDF (Watchdog Flag) and
generates a watchdog interrupt or a m icroproc es­sor reset.

The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ‘0’, the watchdog will activate the IRQ

/FT pin
when timed-out. When WDS is set to a ‘ 1’, the
watchdog will output a negative pulse on the RS T
pin for 40 to 200 ms. The Watchdo g register and
the FT bit will reset to a ‘0 ’ at the end of a Wa tch­dog time-out when the WDS bit is set to a ‘ 1’.

HIGH-Z

AI03622

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or

2. the microprocessor can perform a write of the
Watchdog Register.

The time-out period then starts over. The WDI pin
should be tied to V

if not used. The watchdog

SS

will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effec­tively restarting the count-down cycle.

Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis­able the watchdog function until it is again pro­grammed correctly. A rea d of the Flags Register
will reset the Watchdog Flag (Bit D7; Register 0h).

The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IR Q

/FT pin and the frequency tes t function is
activated, the watchdog function prevai ls and the
frequency test function is denied.

13/20

M48T212A

VCC SWITCH OUTPUT

output goes low when V

Vccsw
V

turning on a customer supplied P-Channel

CC

switches to

OUT

MOSFET (see Figure 3). The Motorola
MTD20P06HDL is recomm ended. This MOSFET
in turn connects V
the current requirement is greater than I

to a separate supply when

OUT

OUT1

(see
Table 7). This output may also be used simply to
indicate the status of the internal battery switcho­ver comparator, which controls the source (V
battery) of the V

OUT

output.

CC

or

POWER-ON RESET

The M48T212A continuously monitors V

falls to the power f ail detect t rip point, t he RST

V

CC

. When

CC

pulls low (open drain) and remains low on power­up for 40 to 200ms after V
RST

pin is an open drain output and an a ppropri-

ate pull-up resistor to V

passes V

CC

should be chosen to

CC

PFD

. The

control rise time.
Note: If th e RST

the R STI N

output is fed back into either of

inputs (for a microprocessor with a bi­directional reset) then a 1kΩ (max) pull-up resistor
is recommended.

Reset Inputs (RSTIN1

& RSTIN2)

The M48T212A provides two independent inputs
which can generate an output reset. The duration
and function of these resets is identical to a reset
generated by a power cycle. Table 14 and Figure
12 illustrate the AC reset characteristics of this
function. During the time RST
& t

Note: RSTIN1
pulled up to V

), the Reset Inputs are ignored.

R2HRH

and RSTIN2 are each internally

through a 100KΩ resistor.

CC

is enabled (t

R1HRH

Calibrating the Clock

The M48T212A is driven by a quartz controlled os­cillator with a nominal frequency of 32,768 Hz. The

devices are tested not to exceed ±35 ppm (parts
per million) oscillator frequency error at 25°C,
which equates to about ±1.53 minutes per mo nth.
When the Calibration circuit is properly employed,
accuracy improves to better than +1/–2 ppm at
25°C.

The oscillation rate of crystals changes with tem­perature. The M48T212A design employs periodic
counter correction. The calibration c ircuit adds or
subtracts counts from the o scillator divider circuit
at the divide by 256 stage, as shown in Figure 11.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load­ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub­tracting counts slows the clock down.

The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register 8h. These bits
can be set to represent a ny value betw een 0 and

31 in binary form. Bit D5 is a Sign bit; ’1’ indicates
positive calibration, ’0’ indicates negative calibra­tion. Calibration occurs within a 64 minute cycle.
The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128
or lengthened by 256 oscillator cycles.

If a binary ’1' is loaded into the register, only t he
first 2 minutes in the 64 minute cycle will be modi­fied; if a binary 6 is loaded, the first 12 will be af­fected, and so on.

Therefore, each cal ibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra­tion step in the cal ibration registe r. Ass um ing that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.

Two methods are available for ascertaining how
much calibration a given M48T212 A may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref­erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
Calibratio n.

This allows the designer to give the end user the
ability to calibrate the clock as the environment re­quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibrati on byte .

The second approach is better suit ed to a manu­facturing environment, and involves the use of the

/FT pin. The pin will toggle at 512Hz, when the

IRQ
Stop bit (ST, D7 of 9h) is ’0’, the Frequency Test
bit (FT, D6 of Ch) is ’1’, the A larm Flag E nabl e bit
(AFE, D7 of 6h) is ’0’, and the Watchdog Steering
bit (WDS, D7 of 7h) is ’1’ or the Watchdog Register
(7h = 0) is reset.

Any deviation from 512 Hz i ndicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm oscilla­tor frequency error, requiring a –10 (WR001010)
to be loaded into the Calibration Byte for correc­tion. Note that setting or cha nging the Calibrat ion
Byte does not affect the Frequency test output fre­quency.

The IRQ
quires a pull-up resist or to V

/FT pin is an open drain out put which re-

for proper opera-

CC

tion. A 500-10kΩ resistor is recommended in order
to control the rise time. The FT bit is cleared on
power-up.

14/20

M48T212A

Table 14. Reset AC Characteristics

(T

= 0 to 70°C; VCC = 3V to 3.6V)

A

Symbol Parameter Min Max Unit

(1)

t

R1

(2)

t

R2

t

R1HRH

t

R2HRH

Note: 1. Pulse width less than 50ns will result in no RESET (for noise immunity).

2. Pulse width less than 20ms will result in no RESET

3. C

L

Table 15. Crystal Electrical Characteristics (Externally Suppl ied)

Symbol Description Min Typ Max Unit

Note: L oad capacito rs are integra ted within the M 48T212A. Circu it board layout consideration s for the 32kHz crystal of minim um trace

lengths a nd is olati on f ro m R F gen era tin g sig nals s houl d be tak en in to a ccou nt. ST rec omme nds the KD S D T-3 8 Tunin g F ork Typ e
quartz crystal for all temperature operations. KDS can be contacted at 913-491-6825 or at
on this crystal type.

RSTIN1 Low to RSTIN1 High 200 ns
RSTIN2 Low to RSTIN2 High 100 ms

(3)

RSTIN1 High to RST High 40 200 ms

(3)

RSTIN2 High to RST High 40 200 ms

= 5pF (see Figure 4).

f

O

R

S

C

L

Resonant Frequency 32,768 kHz
Series Resistance 50 70
Load Capacitance 12.5 pF

(for nois e i m m unity).

http://www.kdsj.co.jp

Ω

k

for forther i nformatio n

BATTERY LOW WARNING

The M48T212A automatically performs battery
voltage monitoring upon power-up and at factory­programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 0h, will be asserted if the bat t ery voltage
is found to b e less than approximately 2.5V. T he
BL bit will remain asserted until completion of bat­tery replacement and subsequent battery low
monitoring tests, either during the nex t power-up
sequence or the next scheduled 24-hour interval.

If a battery low is generated during a power-up se­quence, this indicates that the battery is below ap­proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data shou ld
be considered suspect an d verified as correct. A
fresh battery should be installed.

If a battery low indication is generated during the
24-hour interval check, this indicates that the bat­tery is near end of life. However, data is not com­promised due to the fact that a nominal Vcc is
supplied. In order to insure data integrity during

subsequent periods of bat tery back-up m ode, the
battery should be replaced. The battery should be
replaced with V

powering the device to avoid

CC

data loss.
The M48T212A only monitors the battery when a

nominal Vcc is applied to the device. Thus applica­tions which require extensive durations in the bat­tery back-up mode should be powered-up
periodically (at least once every few months) in or­der for this technique to be beneficial.

Additionally, if a battery low is indicated, data in­tegrity should be verified upon power-up via a
checksum or other technique.

Note: Battery Low w arning is on ly valid whe n us­ing a 3V button cell battery. Use a super capacitor
for back-up supply causes the BL flag to be invalid.

INITIAL POWER-ON DEFAULTS

Upon application of power to the de vice, the fol-

lowing register bits are set to a ’0' state: WDS,
BMB0-BMB4, RB0-RB1, AFE, ABE, W and FT
(See Table 16).

15/20

M48T212A

Figure 11. Cal ib rat i on Waveform

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

Figure 12. RSTIN1 & RSTIN2 Timing Wa v ef orm s

RSTIN1

tR1

RSTIN2

(1)

RST

AI00594B

tR2

tR1HRH

Note: 1 . With pul l -up resistor.

tR2HRH

AI02642

Table 16. Default Values

Condition W R FT AFE ABE

Initial Power-up
(Battery Attach for SNAPHAT)

RESET
Power-down

(3)

(4)

(2)

00000 0

00000 0
01011 0

Subsequent Power-up 01000 0

Note: 1. WDS, BM B0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. State of other control bits rem ains unchanged.

4. Assuming these bits set to ‘1’ prior to power-down.

WATCHDOG

Register

(1)

16/20

M48T212A

POWER SUPPLY DECOUPLING
AND UNDERSHOOT PROTECTION

Note : I

transients, including those produ ced by

CC

output switching, can produce voltage fluctua­tions, resulting in spikes on the V

bus. These

CC

transients can be reduced if capacitors are used to
store energy, which stabilizes the V

bus. The

CC

energy stored in the bypass c apacitors will be re­leased as low going spikes are generated or ener­gy will be absorbed when overshoots occur.

A ceramic bypass capac itor val ue of 0. 1µF is rec­ommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg­ative voltage spikes on V
below V

by as much as one volt. These negative

SS

that drive it to values

CC

spikes can cause data corruption in the SRAM
while in battery backup mode.

To protect from these voltage spikes, ST recom­mends connecting a schottky diode from V

(cathode connected to VCC, anode to VSS).

V

SS

CC

to

(Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount).

Figure 13. Supply Voltage Protection

V

CC

V

CC

0.1µF DEVICE

V

SS

AI02169

17/20

M48T212A

Table 17. Ordering Information Scheme

Example: M48T212A -85 MH 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

212A = V

Speed

-85 = 85ns

Package

MH = SOH44

Temperature Range

1 = 0 to 70 °C
6 = –40 to 85 °C

Shipping Method for SOIC

blank = Tubes
TR = Tape & Reel

= 3.0V to 3.6V; V

CC

= 2.7V to 3.0V

PFD

For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 18. Revision History

Date Revision Details

October 1999 First Issue

SNAPHAT Battery & Crystal removed

03/01/00

Hardware Hookup scheme changed (Figure 3)
Back-Up Mode Alarm Waveforms changed (Figure 10)
Default Values Table added (Table 16)
SOH44 package silhouette, mechanical drawings and mechanical data changed (Figure 14)

18/20

M48T212A

Table 19. SOH44 - 44 lead Plastic Small Outline SNAPHAT, Package Mechanical Data

Symb

Typ Min Max Typ Min Max

A 3.0 5 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0 .012

D 17.71 18.4 9 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

H 11.51 12.7 0 0.453 0.500

L 0.41 1.27 0. 016 0.050

α 0° 8° 0° 8°

N44 44

CP 0.10 0.004

mm inches

Figure 14. SOH44 - 44 lead Plastic Small Outline SNAPHAT, Package Outline

A2

A

Be

CP

D

N

E

H

1

SOH-C

Drawing is not to scale.

C

LA1 α

19/20

M48T212A

Information furnished is believed to be ac curate and reli able. Howev er, STMicroel ectronics assumes no responsibilit y for the consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ro nics.

The ST log o i s registered trademark of STMicroelectronics

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20/20