ST M41T82, M41T83 User Manual
M41T82
M41T83
Serial I2C bus real-time clock (RTC) with battery switchover
Datasheet − production data
Features
■ Ultra-low battery supply current of 365 nA
■ Factory calibrated accuracy ±5 ppm
guaranteed after 2 reflows (SOX18)
– Much better accuracies achievable using
built-in programmable analog and digital
calibration circuits
■ 2.0 V to 5.5 V clock operating voltage
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ Automatic switchover and reset output circuitry
(fixed reference)
–M41T83S
V
= 3.00 V to 5.50 V
CC
(2.85 V ≤ V
–M41T83R
V
= 2.70 V to 5.50 V
CC
(2.55 V ≤ V
–M41T83Z
V
= 2.38 V to 5.50 V
CC
(2.25 V ≤ V
■ Serial interface supports I
protocol)
■ Programmable alarm with interrupt function
(valid even during battery backup mode)
■ Optional 2
■ Square wave output defaults to 32 KHz on
nd
power-up (M41T83 only)
■ RESET (RST) output
■ Watchdog timer
■ Programmable 8-bit counter/timer
■ 7 bytes of battery-backed user SRAM
■ Battery low flag
■ Low operating current of 80 µA
≤ 3.00 V)
RST
≤ 2.70 V)
RST
≤ 2.38 V)
RST
2
C bus (400 kHz
programmable alarm available
QFN16, 4 mm x 4 mm
(VFQFPN16)
18
1
SOX18 (18-pin, 300 mil SOIC
with embedded crystal)
SO8
■ Oscillator stop detection
■ Battery or SuperCap™ backup
■ Operating temperature of –40 °C to 85 °C
■ Package options
– a 16-lead QFN (M41T83),
– an 18-lead embedded crystal SOIC
(M41T83), or
– an 8-lead SOIC (M41T82)
■ RoHS compliance: lead-free components are
compliant with the RoHS directive
May 2012 Doc ID 12578 Rev 14 1/63
This is information on a product in full production.
www.st.com
1
Contents M41T82-M41T83
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Data retention and battery switchover (V
2.5 Power-on reset (t
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
rec
SO
= V
) . . . . . . . . . . . . . . . . 18
RST
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.1 Example of incoherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.2 Accessing the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Halt bit (HT) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1 Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 28
3.4.2 Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 31
3.5 Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6 Optional second programmable alarm and user SRAM . . . . . . . . . . . . . . 36
3.7 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.8 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8.1 M41T83 timer interrupt/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8.2 Timer flag (TF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.3 Timer interrupt enable (TIE, M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 39
3.8.4 Timer enable (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.5 TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/63 Doc ID 12578 Rev 14
M41T82-M41T83 Contents
3.9 Square wave output (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.11 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.12 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.13 Oscillator fail interrupt enable (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 43
3.14 IRQ1
/FT/OUT pin, frequency test, interrupts and the OUT bit
(M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.14.1 Active mode operation on V
3.14.2 Backup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.15 FT/RST pin, frequency test and reset output pin (M41T82 only) . . . . . . . 46
3.16 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.17 OTP bit operation (M41T83 in SOX18 package only) . . . . . . . . . . . . . . . 47
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Doc ID 12578 Rev 14 3/63
List of tables M41T82-M41T83
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. M41T82 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3. Key to Table 2: M41T82 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 24
Table 4. M41T83 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Key to Table 4: M41T83 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Watchdog register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. Timer interrupt operation in free-running mode (with TI
Table 12. Timer source clock frequency selection (244.1 µs to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 39
Table 13. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 14. Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 15. Priority for IRQ1
Table 16. Priority for IRQ1/FT/OUT pin when operating in backup mode . . . . . . . . . . . . . . . . . . . . . 45
Table 17. Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 18. Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 19. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 20. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 22. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 23. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 24. Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 25. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 27. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm pack. mech. data . . . . . . . . . . . 55
Table 28. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, package mech. data 57
Table 29. SO8 – 8-lead plastic small outline (150 mils body width), package mech. data . . . . . . . . . 58
Table 30. Carrier tape dimensions for QFN16, SOX18, and SO8 packages . . . . . . . . . . . . . . . . . . . 59
Table 31. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 32. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
/FT/OUT pin when operating on V
/TP = 1). . . . . . . . . . . . . . . . . . . . . 38
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4/63 Doc ID 12578 Rev 14
M41T82-M41T83 List of figures
List of figures
Figure 1. M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. M41T83 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SO8 (M) connections (M41T82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. QFN16 (QA) connections (M41T83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. SOX18 (MY) connections (M41T83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. M41T82 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. M41T82 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. M41T83 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. M41T83 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Clock accuracy vs. on-chip load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21. Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. Timer output waveform in free-running mode (with TI
Figure 23. Battery check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. IRQ1
Figure 25. Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 26. I
Figure 27. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 28. Bus timing requirement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline . . . . . . . . . . . 55
Figure 30. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint . . . . . . 56
Figure 31. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 32. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline . . . . . . . . . . . 57
Figure 33. SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 34. Carrier tape for QFN16, SOX18, and SO8 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
/FT/OUT output pin circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CC2
/TP = 1) . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 12578 Rev 14 5/63
Description M41T82-M41T83
1 Description
The M41T8x are low-power serial I2C real-time clocks (RTCs) with a built-in 32.768 kHz
oscillator (external crystal-controlled for the QFN16 and SO8 packages, embedded crystal
for the SOX18 package). Eight bytes of the register map (see Table 2 on page 23) are used
for the clock/calendar function and are configured in binary-coded decimal (BCD) format. An
additional 17 bytes of the register map provide status/control of the two alarms, watchdog,
8-bit counter, and square wave functions. An additional seven bytes are made available as
user SRAM.
Addresses and data are transferred serially via a two-line, bidirectional I
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T8x has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button battery
when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, two alarm
interrupts, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight
clock address locations contain the century, year, month, date, day, hour, minute, second,
and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap
year), 30, and 31 day months are made automatically. The M41T83 is supplied in either a
QFN16 or an SOX18, 300 mil SOIC which includes an embedded 32 KHz crystal. The
SOX18 package requires only a user-supplied battery to provide non-volatile operation. The
M41T82 is available only in an SO8 package.
2
C interface. The
6/63 Doc ID 12578 Rev 14
M41T82-M41T83 Description
Figure 1. M41T82 logic diagram
XI
XO
SDA
SCL
1. Open drain
Figure 2. M41T83 logic diagram
(1)
XI
(1)
XO
SDA
SCL
V
BAT
V
BAT
V
CC
(1)
FT/RST
V
SS
V
CC
(2)
SQW
IRQ1/OUT/FT
(3)
RST
IRQ2
(3)
(3)
AI11196
1. For QFN16 package only
2. Defaults to 32 KHz on power-up
3. Open drain
V
SS
AI11195
Doc ID 12578 Rev 14 7/63
Description M41T82-M41T83
Table 1. Signal names
Symbol Description
(1)
XI
(1)
XO
/OUT/FT
IRQ1
(3)
SQW
RST
FT/RST
(2)
IRQ2
SDA Serial data address input/output
SCL Serial clock input
32 KHz oscillator input
32 KHz oscillator output
(2)
Interrupt 1/output driver/frequency test output (open drain)
32 KHz programmable square wave output
Power-on reset output (open drain)
Frequency test output/power-on reset (open drain - M41T82 only)
Interrupt for alarm 2 (open drain)
V
BAT
(4)
DU
V
CC
V
SS
1. For SO8 and QFN16 packages only.
2. For SOX18 and QFN16 packages only.
3. Defaults to 32 KHz on power-up.
4. DU pin must be tied to VCC.
Battery supply voltage (tie V
Do not use
Supply voltage
Ground
to VSS if no battery is connected.)
BAT
8/63 Doc ID 12578 Rev 14
M41T82-M41T83 Description
Figure 3. SO8 (M) connections (M41T82)
1
XI
2
XO
V
BAT
V
SS
M41T82
3
45
1. Open drain output
Figure 4. QFN16 (QA) connections (M41T83)
XI
15
M41T83
6
SS
V
V
14
7
NC
RST
SQW
1. Open drain output.
2. Defaults to 32 KHz on power-up.
(1)
NC
NC
(2)
XO
16
1
2
3
4
5
BAT
V
CC
8
V
CC
FT/RST
SCL
(1)
7
6
SDA
AI11199
NC
13
(1)
IRQ2
12
11
IRQ1/FT/OUT
SCL
10
9
SDA
(1)
8
NC
AI11197
Figure 5. SOX18 (MY) connections (M41T83)
1
NC
(1)
NC
SS
2
(1)
3
4
(2)
5
6
7
M41T83
(3)
(4)
8
9
NF
NF
RST
DU
SQW
V
V
BAT
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together.
2. Open drain output.
3. Do not use (must be tied to V
CC
).
4. Defaults to 32 KHz on power-up.
18
17
16
15
14
13
12
11
10
NC
(1)
NF
(1)
NF
V
CC
(2)
IRQ2
NC
IRQ1/FT/OUT
SCL
SDA
(2)
AI11198
Doc ID 12578 Rev 14 9/63
Description M41T82-M41T83
Figure 6. M41T82 block diagram
REAL TIME CLOCK
CALENDAR
CRYSTAL
SDA
SCL
V
CC
V
BAT
V
RST/VSO
XI
OSCILLATOR
XO
INTERFACE
COMPARE
(1)
32KHz
I2C
WRITE
PROTECT
VCC < V
RST
OSCILLATOR FAIL
CIRCUIT
ALARM1
ALARM2
WATCHDOG
FREQUENCY TEST
OUTPUT DRIVER
8-BIT COUNTER
USER SRAM (7 Bytes)
FT
INTERNAL
POWER
t
rec
TIMER
RST
(2)
AI11812
1. V
= VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z).
RST
2. Open drain output.
Figure 7. M41T82 hardware hookup
V
CC
M41T82
V
CC
XI
XO
V
BAT
V
SS
1. Open drain output.
10/63 Doc ID 12578 Rev 14
FT/RST
(1)
SCL
SDA
MCU
V
CC
Reset Input
Serial Clock Line
Serial Data Line
AI11813
M41T82-M41T83 Description
Figure 8. M41T83 block diagram
REAL TIME CLOCK
CALENDAR
CRYSTAL
SDA
SCL
V
CC
V
BAT
V
RST/VSO
XI
OSCILLATOR
XO
INTERFACE
COMPARE
(2)
32KHz
I2C
WRITE
PROTECT
VCC < V
RST
OSCILLATOR FAIL
CIRCUIT
ALARM1
ALARM2
WATCHDOG
FREQUENCY TEST
OUTPUT DRIVER
8-BIT COUNTER
SQUARE WAVE
8 BITS OF OTP
USER SRAM (7 Bytes)
OFIE
A1IE
A2IE
FT
OUT
TIE
SQWE
INTERNAL
POWER
t
rec
TIMER
(1)
IRQ2
IRQ1/FT/OUT
SQW
(1)
RST
AI11800
(1)
1. Open drain output.
2. V
= VSO = 2.93 V (S), 2.63 V (R), and 2.32 V (Z).
RST
Figure 9. M41T83 hardware hookup
V
CC
M41T83
V
CC
RST
IRQ2
(1)
(1)
(1)
SCL
SDA
SQW
1. Open drain output.
IRQ1/FT/OUT
XI
XO
V
BAT
V
SS
MCU
V
CC
INT
Reset Input
Por t
Serial Clock Line
Serial Data Line
32KHz CLKIN
AI11801
Doc ID 12578 Rev 14 11/63
Operation M41T82-M41T83
2 Operation
The M41T8x clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 32 bytes
contained in the device can then be accessed sequentially in the following order:
st
● 1
● 2
● 3
● 4
● 5
● 6
● 7
● 8
● 9
● 10
● 11
● 16
● 17
● 18
● 19
● 20
● 21
● 26
byte: tenths/hundredths of a second register
nd
byte: seconds register
rd
byte: minutes register
th
byte: century/hours register
th
byte: day register
th
byte: date register
th
byte: month register
th
byte: year register
th
byte: digital calibration register
th
byte: watchdog register
th
- 15th bytes: alarm 1 registers
th
byte: flags register
th
byte: timer value register
th
byte: timer control register
th
byte: analog calibration register
th
byte: square wave register
st
- 25th bytes: alarm 2 registers
th
- 32nd bytes: user RAM
The M41T8x clock continually monitors V
fall below V
, the device terminates an access in progress and resets the device address
RST
for an out-of-tolerance condition. Should V
CC
CC
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out-of-tolerance system. The power input will also
be switched from the V
switchover voltage (V
attached battery supply. As system power returns and V
disconnected, and the power supply is switched to external V
pin to the battery when V
CC
=
V
SO
). At this time the clock registers will be maintained by the
RST
falls below the battery back-up
CC
rises above VSO, the battery is
CC
CC
.
12/63 Doc ID 12578 Rev 14
M41T82-M41T83 Operation
2.1 2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.1.4 Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Doc ID 12578 Rev 14 13/63
Operation M41T82-M41T83
2.1.5 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 10. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
STA RT
CONDITION
CHANGE OF
DATA ALLOWED
Figure 11. Acknowledgement sequence
STA RT
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
12 8 9
MSBLSB
STOP
CONDITION
AI00587
CLOCK PULSE FOR
ACKNOWLEDGEMENT
AI00601
14/63 Doc ID 12578 Rev 14
M41T82-M41T83 Operation
2.2 Read mode
In this mode the master reads the M41T8x slave after setting the slave address (see
Figure 13 on page 16). Following the WRITE mode control bit (R/W = 0) and the
acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ mode control bit
(R/W = 1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the master receiver will send an acknowledge
bit to the slave transmitter. The address pointer is only incremented on reception of an
acknowledge clock. The M41T8x slave transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and acknowledges the new byte and the
address pointer is incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter. Most of the registers and memory locations are
accessed directly, but the RTC counters are accessed via a set of buffer/transfer registers at
addresses 00h to 07h. The counters are not directly read nor written. Instead, at the start of
a read or write cycle, the counters are copied into the eight buffer/transfer registers so that
the user can read them out sequentially, receiving a coherent set of data, copied from the
same instant in time.
An alternate READ mode may also be implemented whereby the master reads the M41T8x
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 14 on page 16).
Figure 12. Slave address location
STA RT A
SLAVE ADDRESS
MSB
0100 011
R/W
LSB
AI00602
Doc ID 12578 Rev 14 15/63
Operation M41T82-M41T83
Figure 13. Read mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
STA RT
S
SLAVE
ADDRESS
R/W
ADDRESS (An)
ACK
DATA n+X
WORD
STOP
P
NO ACK
Figure 14. Alternative read mode sequence
BUS ACTIVITY:
MASTER
STA RT
R/W
STA RT
S
ACK
ADDRESS
SLAVE
R/W
DATA n DATA n+ 1
ACK
ACK
ACK
AI00899
STOP
BUS ACTIVITY:
S
SLAVE
ADDRESS
DATA n DATA n+ 1 DATA n+ X
ACK
ACK
ACK
ACK
PSDA LINE
NO ACK
AI00895
16/63 Doc ID 12578 Rev 14
M41T82-M41T83 Operation
2.3 Write mode
In this mode the master transmitter transmits to the M41T8x slave receiver. Bus protocol is
shown in Figure 15. Following the START condition and slave address, a logic 0 (R/W = 0) is
placed on the bus and indicates to the addressed device that word address “An” will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T8x slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see Figure 12 on page 15 and again after it has received the word address and each data
byte.
Figure 15. Write mode sequence
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
As in the case of reading, some registers and memory locations are written directly, but the
RTC counters are written via a set of eight buffer/transfer registers at addresses 00h to 07h.
The user will write the date and time information sequentially, and then, at the end of the I
write cycle or when the address pointer increments beyond 07h, the buffer/transfer registers
will be copied into the RTC counters. All the time parameters - fractions, seconds, minutes,
hours, day, date, month, year, and century bits - are copied simultaneously.
Whatever value is in the buffer/transfer registers will be copied to the counters, so if the user
only changes one of the eight bytes, the remaining seven bytes will receive the unchanged
contents of the buffer/transfer registers, which will contain whatever was in the counters at
the start of the write access.
For example, if the user starts a write cycle on Monday, November 16, 2009, at 17:52:27.03,
and writes a 22 to the minutes registers, the value Monday, November 16, 2009,
17:52:22.03 will be written back into the counters. At the start of the write cycle, the eight
bytes of counters were copied into the buffer/transfer registers. Then, the seconds register
was overwritten. Finally, the eight bytes were copied back into the counters with the result
that the seconds value was changed.
STA RT
S
ADDRESS
SLAVE
R/W
WORD
ADDRESS (An)
ACK
DATA n DATA n+1 DATA n+X
ACK
ACK
ACK
PSDA LINE
ACK
STOP
AI00591
2
C
Doc ID 12578 Rev 14 17/63
Operation M41T82-M41T83
2.4 Data retention and battery switchover (VSO = V
Once VCC falls below the switchover voltage (VSO = V
switches over to the battery and powers down into an ultra low current mode of operation to
preserve battery life. If V
from V
CC
to V
when VCC drops below V
BAT
clock registers and user RAM will be maintained by the attached battery supply.
When it is powered back up, the device switches back from battery to V
hysteresis. When V
rises above V
CC
on battery storage life refer to Application Note AN1012.
2.5 Power-on reset (t
The M41T8x continuously monitors VCC. When VCC falls to the power fail detect trip point,
the RST
typical) after V
Note: The t
below V
RST
The RST
chosen to control the rise time.
output pulls low (open drain) and remains low after power-up for t
rises above V
CC
period does not affect the RTC operation. Write protect only occurs when VCC is
rec
. When VCC rises above V
RST
output is affected by the t
pin is an open drain output and an appropriate pull-up resistor to VCC should be
is less than, or greater than V
BAT
rec
)
RST
rec
RST
(max).
RST
period.
(see Figure 27 on page 52). At this time the
RST
, it will recognize the inputs. For more information
, the RTC will be selectable immediately. Only the
), the device automatically
RST
, the device power is switched
RST
RST
at VSO +
CC
rec
)
(210 ms
18/63 Doc ID 12578 Rev 14
M41T82-M41T83 Clock operation
3 Clock operation
The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The 8-byte clock register (see Table 2 on page 23 and Table 4 on page 25) is used to both
set the clock and to read the date and time from the clock, in binary coded decimal format.
Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first
four registers.
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. When reset to a 0 the oscillator restarts within one second (typical).
Note: Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to 0. This provides an additional “kick-start” to the oscillator circuit.
Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The
ninth clock register is the digital calibration register, while the analog calibration register is
found at address 12h (these are both described in Section 3.4: Clock calibration). The RTC
includes an oscillator fail detect circuit which sets the OF bit in the flags register (bit 2,
register 0fh). For the M41T83, bit D7 of register 09h (watchdog register) contains the
oscillator fail interrupt enable bit (OFIE) which can be used to enable an interrupt when the
OF bit is set (see Section 3.12: Oscillator fail detection on page 42) will also generate an
interrupt output.
Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the ST bit and CB0-CB1 bits will result in an update of the RTC counters and a
reset of the divider chain. This could result in an inadvertent change of the current time. For
example, the ST bit is in the seconds register (address 01h) and the century bits (CB0-CB1)
are in the hours register (address 03h), so the user should take care to not alter these other
parameters when changing the ST bit or the century bits.
The eight clock registers may be read one byte at a time or in a sequential block. At the start
of a read cycle, a copy of the time/date counters is placed in the buffer/transfer registers and
can then be transferred out sequentially without concern that the time/date increments
during the transfer and thus yields a corrupt value. For example, if the user were to read the
seconds register, then start another bus cycle to read the minutes register, the minutes
counter could have incremented during the time between the two read cycles. The seconds
and minutes values would not be from the same instant in time; they would not be coherent.
By using the sequential read feature, the values shifted out are from the same instant in time
and are thus coherent.
Similarly, when writing to the RTC registers, during one write cycle, the user can
sequentially transfer all eight bytes of time/date into the buffer/transfer registers whereupon
they will be loaded simultaneously into the RTC counters thus ensuring a coherent update
of the time/date.
Doc ID 12578 Rev 14 19/63
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