Serial access real-time clock (RTC) with alarms
Features
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ 32 KHz crystal oscillator with integrated load
capacitance (12.5 pf) which provides
exceptional oscillator stability and high crystal
series resistance operation)
■ Oscillator stop detection (monitors clock
operation)
■ Serial interface supports I
protocol)
■ Ultra-low battery supply current of 0.6 µA (typ)
■ 2.0 to 5.5 V clock operating voltage
■ Automatic switchover and deselect circuitry
(fixed reference) which provides full operation
in 3.0 V applications)
■ V
■ 2.5 V ≤ V
■ Power-down time-stamp (HT bit) which allows
= 2.7 to 5.5 V
CC
PFD
≤ 2.7 V
determination of time elapsed in battery
backup
■ Battery low flag
■ Programmable alarm and interrupt function
(valid even during battery backup mode)
■ Accurate programmable watchdog timer (from
62.5 ms to 128 s)
■ Software clock calibration (to compensate for
crystal deviation due to temperature)
■ Operating temperature of –40 to 85 °C
■ Package options include an 8-lead SOIC or
18-lead embedded crystal SOIC
2
C bus (400 kHz
M41T81S
Datasheet − production data
8
1
SO8
8-pin SOIC
18
1
SOX18
18-pin (300 mil) SOIC
with embedded crystal
May 2012 Doc ID 10773 Rev 7 1/32
This is information on a product in full production.
www.st.com
1
Contents M41T81S
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting alarm clock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Century bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/32 Doc ID 10773 Rev 7
M41T81S Contents
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 10773 Rev 7 3/32
List of tables M41T81S
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 28
Table 15. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/32 Doc ID 10773 Rev 7
M41T81S List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. 18-pin, 300 mil SOIC (MY) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline . . . . . . . . . . . 29
Doc ID 10773 Rev 7 5/32
Description M41T81S
1 Description
The M41T81S is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight bytes of the SRAM are used for the
clock/calendar function and are configured in binary-coded decimal (BCD) format. An
additional 12 bytes of SRAM provide status/control of alarm, watchdog and square wave
functions. Addresses and data are transferred serially via a two line, bidirectional I
interface. The built-in address register is incremented automatically after each WRITE or
READ data byte.
The M41T81S has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button supply
when a power failure occurs. Functions available to the user include a non-volatile, time-ofday clock/calendar, alarm interrupts, watchdog timer and programmable square wave
output. The eight clock address locations contain the century, year, month, date, day, hour,
minute, second and tenths/hundredths of a second in 24-hour BCD format. Corrections for
28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically.
The M41T81S is supplied in either an 8-pin SOIC or an 18-pin 300 mil SOIC package which
includes an embedded 32 KHz crystal.
2
C
The 18-pin, embedded crystal SOIC requires only a user-supplied battery to provide nonvolatile operation.
Figure 1. Logic diagram
V
V
BAT
CC
(1)
XI
(1)
XO
SCL
SDA
1. For SO8 package only
M41T81S
V
SS
IRQ/FT/OUT/SQW
AI09160
6/32 Doc ID 10773 Rev 7
M41T81S Description
Table 1. Signal names
(1)
XI
(1)
XO
IRQ/OUT/FT/SQW Interrupt / output driver / frequency test / square wave (open drain)
SDA Serial data input/output
SCL Serial clock input
Oscillator input
Oscillator output
V
V
V
NC
NF
BAT
CC
SS
(2)
(2)
Battery supply voltage
Supply voltage
Ground
No connect
No function
1. For SO8 package only.
2. NC and NF pins should be tied to VSS.
Figure 2. 8-pin SOIC (M) connections
8
7
6
1. Open drain output
1
XI
2
XO
V
BAT
V
SS
M41T81S
3
45
Figure 3. 18-pin, 300 mil SOIC (MY) connections
NF
NF
1
NC
(1)
2
(1)
3
4
NC
5
NC
NC
NC
V
BAT
V
SS
M41T81S
6
7
8
9
18
17
16
15
14
13
12
11
10
V
CC
IRQ/FT/OUT/SQW
SCL
SDA
NC
(1)
NF
(1)
NF
V
CC
NC
IRQ/FT/OUT/SQW
NC
SCL
SDA
(1)
AI09161
(2)
AI09162
1. NC and NF pins should be tied to VSS. Pins 2 and 3 are internally shorted together. Pins 17 and 16 are
internally shorted together.
2. Open drain output
Doc ID 10773 Rev 7 7/32
Description M41T81S
Figure 4. Block diagram
REAL TIME CLOCK
CALENDAR
CRYSTAL
SDA
32KHz
OSCILLATOR
2
I
C
INTERFACE
SCL
WRITE
PROTECT
V
CC
V
BAT
V
SO
V
COMPARE
PFD
1. Open drain output
2. Square wave function has the highest priority on IRQ
OSCILLATOR FAIL
CIRCUIT
RTC W/ALARM
& CALIBRATION
WATCHDOG
SQUARE WAVE
FREQUENCY TEST
OUTPUT DRIVER
/FT/OUT/SQW output.
OFIE
AFE
SQWE
FT
OUT
INTERNAL
POWER
IRQ/FT/OUT/SQW
(2)
(1)
AI09163
8/32 Doc ID 10773 Rev 7
M41T81S Operation
2 Operation
The M41T81S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
1. Tenths/hundredths of a second register
2. Seconds register
3. Minutes register
4. Century/hours register
5. Day register
6. Date register
7. Month register
8. Year register
9. Calibration register
10. Watchdog register
11 - 15. Alarm registers
16. Flags register
17 - 19. Reserved
20. Square wave register
The M41T81S clock continually monitors V
fall below V
, the device terminates an access in progress and resets the device address
PFD
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once V
switchover voltage (V
), the device automatically switches over to the battery and powers
SO
down into an ultra-low current mode of operation to preserve battery life. If V
V
, the device power is switched from VCC to V
PFD
greater than V
V
. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises
PFD
above V
PFD
, the device power is switched from VCC to V
PFD
, it will recognize the inputs.
For more information on battery storage life refer to application note AN1012, "Predicting the
battery life and data retention period of NVRAMs and serial RTCs" .
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
for an out-of-tolerance condition. Should VCC
CC
falls below the
CC
is less than
when VCC drops below V
BAT
when VCC drops below
BAT
BAT
BAT
. If V
BAT
is
Doc ID 10773 Rev 7 9/32
Operation M41T81S
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
10/32 Doc ID 10773 Rev 7
M41T81S Operation
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 5. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
Figure 6. Acknowledgement sequence
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
READ mode
In this mode the master reads the M41T81S slave after setting the slave address (see
Figure 8 on page 12). Following the WRITE mode control bit (R/W
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T81S slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
STA RT
CONDITION
START
CHANGE OF
DATA ALLOWED
12 89
MSB LSB
STOP
CONDITION
AI00587
CLOCK PULSE FOR
ACKNOWLEDGEMENT
AI00601
=0) and the acknowledge
=1). At this
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-13h).
Doc ID 10773 Rev 7 11/32
Operation M41T81S
Note: This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the
M41T81S slave without first writing to the (volatile) address pointer. The first address that is
read is the last one stored in the pointer (see Figure 9 on page 12).
Figure 7. Slave address location
R/W
STA RT A
Figure 8. READ mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
START
S
ADDRESS
SLAVE
R/W
ADDRESS (An)
ACK
DATA n+X
WORD
SLAVE ADDRESS
MSB
0100 011
START
S
ACK
ADDRESS
STOP
P
NO ACK
SLAVE
LSB
R/W
DATA n DATA n+ 1
ACK
AI00602
ACK
ACK
AI00899
Figure 9. Alternative READ mode sequence
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
12/32 Doc ID 10773 Rev 7
STA RT
S
SLAVE
ADDRESS
R/W
DATA n DATA n+1 DATA n+X
ACK
ACK
STOP
PSDA LI NE
ACK
ACK
NO ACK
AI00895
M41T81S Operation
WRITE mode
In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is
shown in Figure 10 on page 13. Following the START condition and slave address, a logic '0'
(R/W
=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T81S slave receiver
will send an acknowledge clock to the master transmitter after it has received the slave
address see Figure 7 on page 12 and again after it has received the word address and each
data byte.
Data retention mode
With valid VCC applied, the M41T81S can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the power input will be switched from the
V
pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At
CC
this time the clock registers will be maintained by the attached battery supply. On power-up,
when V
For a further, more detailed review of lifetime calculations, please see application note
AN1012.
returns to a nominal value, write protection continues for t
CC
REC
.
Figure 10. WRITE mode sequence
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
START
S
ADDRESS
SLAVE
R/W
WORD
ADDRESS (An)
ACK
DATA n DATA n+ 1 DATA n+ X
ACK
ACK
ACK
STOP
PSDA LINE
ACK
AI00591
Doc ID 10773 Rev 7 13/32
Clock operation M41T81S
3 Clock operation
The 20-byte register map (see Table 2: Clock register map on page 15) is used to both set
the clock and to read the date and time from the clock, in a binary coded decimal format.
Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first
four registers.
Note: Tenths/hundredths of seconds cannot be written to any value other than “00.”
Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY
ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle,
either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the
day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and
years. The ninth clock register is the calibration register (this is described in the clock
calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1'
will cause the oscillator to stop. If the device is expected to spend a significant amount of
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'
the oscillator restarts within one second.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
Power-down time-stamp
When a power failure occurs, the HALT (HT) bit will automatically be set to a '1.' This will
prevent the clock from updating the registers, and will allow the user to read the exact time
of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the
registers with the current time. For more information, please refer to AN1572, “Power-down
time-stamp function in serial real-time clocks (RTCs)”.
Clock registers
The M41T81S offers 20 internal registers which contain clock, alarm, watchdog, flags,
square wave and calibration data. These registers are memory locations which contain
external (user accessible) and internal copies of the data (usually referred to as BiPORT
cells). The external copies are independent of internal functions except that they are
updated periodically by the simultaneous transfer of the incremented internal copy. The
internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock
address.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or when
the pointer increments to any non-clock address (08h-13h).
Clock and alarm registers store data in BCD. Calibration, watchdog and square wave
registers store data in binary format.
™
14/32 Doc ID 10773 Rev 7
M41T81S Clock operation
Table 2. Clock register map
Addr
D7 D6 D5 D4 D3 D2 D1 D0
00h 0.1 seconds 0.01 Seconds Seconds 00-99
01h ST 10 seconds Seconds Seconds 00-59
02h 0 10 minutes Minutes Minutes 00-59
03h CEB CB 10 hours Hours (24-hour format) Century/hours 0-1/00-23
04h00000 Day of week Day 01-7
05h 0 0 10 date Date: day of month Date 01-31
06h 0 0 0 10M Month Month 01-12
07h 10 years Year Year 00-99
08h OUT FT S Calibration Calibration
09h OFIE BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
0Ah AFE SQW ABE Al Alarm month Al month 01-12
0Bh RPT4 RPT5 AI 10 date Alarm date Al date 01-31
0Ch RPT3 HT AI 10 hour Alarm hour Al hour 00-23
0Dh RPT2 Alarm 10 minutes Alarm minutes Al min 00-59
0Eh RPT1 Alarm 10 seconds Alarm seconds Al sec 00-59
0Fh WDF AF 0 BL 0 OF 0 0 Flags
10h00000000Reserved
11h00000000Reserved
12h00000000Reserved
13h RS3 RS2 RS1 RS0 0 0 0 0 SQW
Function/range BCD
format
0 = Must be set to '0'
ABE = Alarm in battery backup mode enable bit
AF = Alarm flag (read only)
AFE = Alarm flag enable flag
BL = Battery low bit
BMB0-BMB4 = Watchdog multiplier bits
CB = Century bit
CEB = Century enable bit
FT = Frequency test bit
HT = Halt update bit
OF = Oscillator fail flag
OFIE = Oscillator fail interrupt enable
OUT = Output level
RB0-RB1 = Watchdog resolution bits
RPT1-RPT5 = Alarm repeat mode bits
RS0-RS3 = SQW frequency
S = Sign bit
SQWE = Square wave enable
ST = Stop bit
WDF = Watchdog flag (read only)
Doc ID 10773 Rev 7 15/32
Clock operation M41T81S
Calibrating the clock
The M41T81S is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator
frequency error at 25
Figure 11 on page 17). When the calibration circuit is properly employed, accuracy improves
to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature. The M41T81S design employs
periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 17. The
number of times pulses which are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
calibration register. Adding counts speeds the clock up, subtracting counts slows the clock
down.
The calibration bits occupy the five lower order bits (D4-D0) in the calibration register 08h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
o
C, which equates to about +1.9 to –1.1 minutes per month (see
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register (see Figure 12 on page 17).
Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a
total range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T81S may
require.
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in application
note AN934, “TIMEKEEPER
®
calibration.” This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ
/FT/OUT/SQW pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of
01h) is '0,' the frequency test bit (FT, D6 of 08h) is '1,' the alarm flag enable bit (AFE, D7 of
0Ah) is '0,' and the square wave enable bit (SQWE, D6 of 0Ah) is '0' and the watchdog
register (09h = 0) is reset.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
16/32 Doc ID 10773 Rev 7
M41T81S Clock operation
The IRQ/FT/OUT/SQW pin is an open drain output which requires a pull-up resistor to VCC
for proper operation. A 500-10 k resistor is recommended in order to control the rise time.
The FT bit is cleared on power-down.
Figure 11. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
2
)
O
= 25°C ± 5°C
T
O
2
–80
–100
–120
–140
ΔF
= K x (T – T
F
= –0.036 ppm/°C2 ± 0.006 ppm/°C
K
–160
Figure 12. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second or repeat every
year, month, day, hour, minute, or second. It can also be programmed to go off while the
M41T81S is in the battery backup mode to serve as a system wake-up call.
0 10203040506070
Temperature °C
80–10–20–30–40
AI07888
AI00594B
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 3 on page 19 shows
the possible configurations. Codes not listed in the table default to the once per second
mode to quickly alert the user of an incorrect alarm setting.
Doc ID 10773 Rev 7 17/32
Clock operation M41T81S
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set (and
SQWE is '0.'), the alarm condition activates the IRQ
/FT/OUT/SQW pin.
Note: If the address pointer is allowed to increment to the flags register address, an alarm
condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a
different address. It should also be noted that if the last address written is the “Alarm
Seconds,” the address pointer will increment to the flag address, causing this situation to
occur.
The IRQ
/FT/OUT/SQW output is cleared by a READ to the flags register as shown in
Figure 13. A subsequent READ of the flags register is necessary to see that the value of the
alarm flag has been reset to '0.'
The IRQ
IRQ
/FT/OUT/SQW pin can also be activated in the battery backup mode. The
/FT/OUT/SQW will go low if an alarm occurs and both ABE (alarm in battery backup
mode enable) and AFE are set. Figure 14 illustrates the backup mode alarm timing.
Figure 13. Alarm interrupt reset waveform
0Fh0Eh 10h
ACTIVE FLAG
IRQ/FT/OUT/SQW
HIGH-Z
AI04617
Figure 14. Backup mode alarm waveform
V
CC
V
PFD
V
SO
ABE and AFE Bits
trec
AF Bit in Flags
Register
IRQ/FT/OUT/SQW
HIGH-Z
18/32 Doc ID 10773 Rev 7
AI09164b
M41T81S Clock operation
Table 3. Alarm repeat modes
RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting
1 1 1 1 1 Once per second
1 1 1 1 0 Once per minute
1 1 1 0 0 Once per hour
1 1 0 0 0 Once per day
1 0 0 0 0 Once per month
0 0 0 0 0 Once per year
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,
and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the
specified period, the M41T81S sets the WDF (watchdog flag) and generates a watchdog
interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the
watchdog register. The time-out period then starts over.
Should the watchdog timer time-out, a value of 00h needs to be written to the watchdog
register in order to clear the IRQ
/FT/OUT/SQW pin. This will also disable the watchdog
function until it is again programmed correctly. A READ of the flags register will reset the
watchdog flag (bit D7; register 0Fh).
The watchdog function is automatically disabled upon power-up and the watchdog register
is cleared. If the watchdog function is set, the frequency test function is activated, and the
SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.
Doc ID 10773 Rev 7 19/32
Clock operation M41T81S
Square wave output
The M41T81S offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These
frequencies are listed in Ta bl e 4 . Once the selection of the SQW frequency has been
completed, the IRQ
the square wave enable bit (SQWE) located in register 0Ah.
Table 4. Square wave output frequency
RS3 RS2 RS1 RS0 Frequency Units
0000None-
000132.768kHz
0 0 1 0 8.192 kHz
0 0 1 1 4.096 kHz
0 1 0 0 2.048 kHz
0 1 0 1 1.024 kHz
0110512Hz
0111256Hz
/FT/OUT/SQW pin can be turned on and off under software control with
Square wave bits Square wave
Century bit
Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
11102Hz
11111Hz
20/32 Doc ID 10773 Rev 7
M41T81S Clock operation
Battery low warning
The M41T81S automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than
approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity. Clock data
should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
battery back-up mode, the battery should be replaced.
is supplied. In order to insure data integrity during subsequent periods of
CC
The M41T81S only monitors the battery when a nominal V
applications which require extensive durations in the battery backup mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
Oscillator fail detection
If the oscillator fail bit (OF) is internally set to '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data.
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator.
The following conditions can cause the OF bit to be set:
● The first time power is applied (defaults to a '1' on power-up).
● The voltage present on V
● The ST bit is set to '1.'
● External interference of the crystal.
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.'
is applied to the device. Thus
CC
is insufficient to support oscillation.
CC
Oscillator fail interrupt enable
If the oscillator fail interrupt bit (OFIE) is set to a '1,' the IRQ pin will also be activated. The
IRQ
output is cleared by resetting the OFIE or OF bit to '0' (not be reading the flags register).
Doc ID 10773 Rev 7 21/32
Clock operation M41T81S
Output driver pin
When the FT bit, AFE bit, SQWE bit, and watchdog register are not set, the
IRQ
/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the
calibration register. In other words, when D7 (OUT bit) and D6 (FT bit) of address location
08h are a '0,' then the IRQ
/FT/OUT/SQW pin will be driven low.
Note: The IRQ
/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
Preferred initial power-on default
Upon initial application of power to the device, the following register bits are set to a '0' state:
watchdog register; AFE; ABE; SQWE; OFIE; and FT. The following bits are set to a '1' state:
ST; OUT; OF; and HT (see Ta bl e 5 ).
Table 5. Preferred default values
Condition ST HT Out FT AFE SQWE ABE
Initial power-up
Subsequent power-up
(with battery backup)
1. BMB0-BMB4, RB0, RB1
2. State of other control bits undefined
3. UC = Unchanged
(2)
(3)
11100 0 0 0 1 0
UC 1 UC 0 UC UC UC 0 UC UC
WATCHDOG
register
(1)
OF OFIE
22/32 Doc ID 10773 Rev 7
M41T81S Maximum ratings
4 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 6. Absolute maximum ratings
Sym Parameter Value Unit
T
Storage temperature (VCC off, oscillator off) –55 to 125 °C
STG
V
Supply voltage –0.3 to 7 V
CC
T
Lead solder temperature for 10 seconds
SLD
V
Input or output voltages –0.3 to VCC + 0.3 V
IO
I
Output current 20 mA
O
Power dissipation 1 W
P
D
1. For SO8 package, Lead-free (Pb-free) lead finish, reflow at peak temperature of 260 °C. The time above
255 °C must not exceed 30 seconds.
2. For SOX18 package, reflow at peak temperature of 240 °C. The time above 235 °C must not exceed 20
seconds.
(1)
SO8
SOX18
(2)
260 °C
240 °C
Caution: Negative undershoots below –0.3 volts are not allowed on any pin while in the battery
backup mode.
Doc ID 10773 Rev 7 23/32
DC and AC parameters M41T81S
5 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7. Operating and AC measurement conditions
Parameter M41T81S
Supply voltage (VCC) 2.7 to 5.5 V
Ambient operating temperature (T
Load capacitance (CL) 100 pF
Input rise and fall times ≤ 50 ns
Input pulse voltages 0.2V
Input and output timing ref. voltages 0.3VCC to 0.7V
Note: Output Hi-Z is defined as the point where data is no longer driven.
) –40 to 85 °C
A
to 0.8V
CC
CC
CC
Figure 15. AC measurement I/O waveform
0.8V
0.2V
CC
CC
0.7V
0.3V
CC
CC
Table 8. Capacitance
Symbol Parameter
C
IN
(3)
C
OUT
t
LP
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz
3. Outputs deselected
Input capacitance - 7 pF
Output capacitance - 10 pF
Low-pass filter input time constant (SDA and SCL) - 50 ns
(1)(2)
Min Max Unit
AI02568
24/32 Doc ID 10773 Rev 7
M41T81S DC and AC parameters
Table 9. DC characteristics
Sym Parameter Test condition
(1)
Min Typ Max Unit
I
I
I
CC1
Input leakage current 0 V ≤ V
LI
Output leakage current 0 V ≤ V
LO
Supply current Switch freq = 400 kHz 400 µA
IN
OUT
≤ V
≤ V
CC
CC
±1 µA
±1 µA
SCL = 0 Hz
I
CC2
V
V
Supply current (standby)
Input low voltage –0.3 0.3V
IL
Input high voltage 0.7V
IH
All inputs
≥ VCC – 0.2 V
+ 0.2 V
≤ V
SS
CC
100 µA
CC
VCC +
0.3
Output low voltage IOL = 3.0 mA 0.4 V
V
OL
Output low voltage
(open drain)
(2)
Pull-up supply voltage
(open drain)
(3)
V
BAT
I
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 5.5 V (except where noted).
2. For IRQ/FT/OUT/SQW pin (open drain)
3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
4. For rechargeable back-up, V
Backup supply voltage 2.0 3.5
Battery supply current
BAT
(max) may be considered to be VCC.
BAT
IOL = 10 mA 0.4 V
/OUT/FT/SQW 5.5 V
IRQ
T
= 25 °C, VCC = 0 V
A
Oscillator ON, V
BAT
= 3 V
0.6 1 µA
(4)
V
V
V
Table 10. Crystal electrical characteristics
Sym Parameter
f
R
C
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38:
1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz
crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or
http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T81S. Circuit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. For applications requiring back-up supply operation below 2.5 V, RS (max) should be considered 40 kΩ.
Resonant frequency - 32.768 kHz
O
Series resistance - 60
S
Load capacitance - 12.5 pF
L
(1)and(2)
Min Typ Max Units
(3)
kΩ
Figure 16. Power down/up mode AC waveforms
V
CC
VSO
SDA
SCL
tPD
DON'T CARE
trec
AI00596
Doc ID 10773 Rev 7 25/32
DC and AC parameters M41T81S
Table 11. Power down/up AC characteristics
Symbol Parameter
t
PD
t
rec
1. VCC fall time should not exceed 5 mV/µs.
2. Valid for ambient operating temperature: T
SCL and SDA at VIH before power-down 0 - - nS
SCL and SDA at VIH after power-up 10 - - µS
(1)(2)
= –40 to 85 °C; VCC = 2.7 to 5.5 V (except where noted).
A
Min Typ Max Unit
Table 12. Power down/up trip points DC characteristics
Sym Parameter
Power-fail deselect 2.5 2.6 2.7 V
V
PFD
Hysteresis 25 mV
Battery backup switchover voltage
< V
(V
V
SO
CC
; VCC < V
BAT
PFD
Hysteresis 40 mV
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: T
(1)(2)
V
< V
BAT
PFD
)
= –40 to 85 °C; VCC = 2.7 to 5.5 V (except where noted).
A
> V
V
BAT
PFD
Min Typ Max Unit
V
V
BAT
PFD
V
V
Figure 17. Bus timing requirements sequence
SDA
SCL
tHD:STAtBUF
tHIGH
tLOW
tF
tSU:DAT
tHD:DAT
tR
SP
SR
tHD:STA
tSU:STOtSU:STA
P
AI00589
26/32 Doc ID 10773 Rev 7
M41T81S DC and AC parameters
Table 13. AC characteristics
Sym Parameter
(1)
Min Typ Max Units
f
SCL
t
LOW
t
HIGH
t
t
R
SCL clock frequency 0 - 400 kHz
Clock low period 1.3 - µs
Clock high period 600 - ns
SDA and SCL rise time - 300 ns
SDA and SCL fall time - 300 ns
F
START condition hold time
t
HD:STA
(after this period the first clock pulse is
600 - ns
generated)
t
SU:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 5.5 V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
START condition setup time
(only relevant for a repeated start condition)
Data setup time 100 - ns
(2)
Data hold time 0 - µs
STOP condition setup time 600 - ns
Time the bus must be free before a new
transmission can start
600 - ns
1.3 - µs
Doc ID 10773 Rev 7 27/32
Package mechanical data M41T81S
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 18. SO8 – 8-lead plastic small package outline
A2
b
Note: Drawing is not to scale.
Table 14. SO8 – 8-lead plastic small outline (150 mils body width), package
mechanical data
h x 45°
A
ccc
e
D
8
E1
1
E
A1
L
L1
c
0.25 mm
GAUGE PLANE
k
SO-A
mm inches
Symb
Typ Min Max Typ Min Max
A1.750.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e 1.27 0.050
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 0.127 0.016 0.050
L1 1.04 0.041
28/32 Doc ID 10773 Rev 7
M41T81S Package mechanical data
Figure 19. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline
SOX1 8
Note: Drawing is not to scale.
Table 15. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal,
package mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 2.57 2.44 2.69 0.101 0.096 0.106
A1 0.23 0.15 0.31 0.009 0.006 0.012
A2 2.34 2.29 2.39 0.092 0.090 0.094
B 0.46 0.41 0.51 0.018 0.016 0.020
c 0.25 0.20 0.31 0.010 0.008 0.012
D 11.61 11.56 11.66 0.457 0.455 0.459
E 7.62 7.57 7.67 0.300 0.298 0.302
E1 10.34 10.16 10.52 0.407 0.400 0.414
e1.27 0.050
L 0.66 0.51 0.81 0.026 0.020 0.032
Doc ID 10773 Rev 7 29/32
Part numbering M41T81S
7 Part numbering
Table 16. Ordering information
Example: M41T 81S M 6 F
Device type
M41T
Supply voltage and write protect voltage
81S = VCC = 2.7 to 5.5 V
Package
M = SO8
(1)
MY
= SOX18
Temperature range
6 = –40 °C to 85 °C
Shipping method
E = ECOPACK
F = ECOPACK® package, tape & reel
1. The SOX18 package includes an embedded 32,768 Hz crystal. Contact local ST sales office for
availability.
2. Shipment in tubes is not recommended for new design. Contact local ST sales office for availability.
®
package, tubes
(2)
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
30/32 Doc ID 10773 Rev 7
M41T81S Revision history
8 Revision history
Date Revision Changes
22-Jan-2004 0.1 First draft
06-Feb-2004 0.2
20-Feb-2004 0.3 Update characteristics (Ta bl e 1 1 , Ta bl e 1 2 , Tab l e 7 , Part numbering)
14-Apr-2004 1
05-May-2004 1.1 Update DC characteristics (Ta b le 9 )
16-Jun-2004 1.2 Add shipping package (Ta bl e 1 6 )
13-Sep-2004 2 Update maximum ratings (Ta bl e 6 )
26-Nov-2004 3
23-Sep-2005 4 Update features; added Lead-free information (cover page; Figure 4)
22-Jan-2007 5
13-Sep-2010 6 Updated Section 4, ECOPACK
16-May-2012 7
Update BL information, characteristics, ratings, and Lead (Pb)-free information
(Ta bl e 1 2, Ta b le 6 , Ta b le 1 0 , Ta bl e 1 6 )
Product promoted; reformatted; update characteristics, including Lead-free
package information (Figure 3, Figure 4, Figure 11, Figure 14; Ta b l e 1 3 , Ta bl e 1 6 )
Promote document; update characteristics and marketing status (cover page,
Figure 5)
Remove TIMEKEEPER references and update package mechanical data
(Figure 18 and Figure 19)
®
text in Section 6; reformatted document.
Added reference to AN1572 in Power-down time-stamp on page 14; updated
footnote 1 of Ta b le 6 ; updated Table 16: Ordering information.
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