ST M41T81S User Manual
Serial access real-time clock (RTC) with alarms
Features
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ 32 KHz crystal oscillator with integrated load
capacitance (12.5 pf) which provides
exceptional oscillator stability and high crystal
series resistance operation)
■ Oscillator stop detection (monitors clock
operation)
■ Serial interface supports I
protocol)
■ Ultra-low battery supply current of 0.6 µA (typ)
■ 2.0 to 5.5 V clock operating voltage
■ Automatic switchover and deselect circuitry
(fixed reference) which provides full operation
in 3.0 V applications)
■ V
■ 2.5 V ≤ V
■ Power-down time-stamp (HT bit) which allows
= 2.7 to 5.5 V
CC
PFD
≤ 2.7 V
determination of time elapsed in battery
backup
■ Battery low flag
■ Programmable alarm and interrupt function
(valid even during battery backup mode)
■ Accurate programmable watchdog timer (from
62.5 ms to 128 s)
■ Software clock calibration (to compensate for
crystal deviation due to temperature)
■ Operating temperature of –40 to 85 °C
■ Package options include an 8-lead SOIC or
18-lead embedded crystal SOIC
2
C bus (400 kHz
M41T81S
Datasheet − production data
8
1
SO8
8-pin SOIC
18
1
SOX18
18-pin (300 mil) SOIC
with embedded crystal
May 2012 Doc ID 10773 Rev 7 1/32
This is information on a product in full production.
www.st.com
1
Contents M41T81S
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting alarm clock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Century bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/32 Doc ID 10773 Rev 7
M41T81S Contents
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 10773 Rev 7 3/32
List of tables M41T81S
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 28
Table 15. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/32 Doc ID 10773 Rev 7
M41T81S List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. 18-pin, 300 mil SOIC (MY) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline . . . . . . . . . . . 29
Doc ID 10773 Rev 7 5/32
Description M41T81S
1 Description
The M41T81S is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight bytes of the SRAM are used for the
clock/calendar function and are configured in binary-coded decimal (BCD) format. An
additional 12 bytes of SRAM provide status/control of alarm, watchdog and square wave
functions. Addresses and data are transferred serially via a two line, bidirectional I
interface. The built-in address register is incremented automatically after each WRITE or
READ data byte.
The M41T81S has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button supply
when a power failure occurs. Functions available to the user include a non-volatile, time-ofday clock/calendar, alarm interrupts, watchdog timer and programmable square wave
output. The eight clock address locations contain the century, year, month, date, day, hour,
minute, second and tenths/hundredths of a second in 24-hour BCD format. Corrections for
28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically.
The M41T81S is supplied in either an 8-pin SOIC or an 18-pin 300 mil SOIC package which
includes an embedded 32 KHz crystal.
2
C
The 18-pin, embedded crystal SOIC requires only a user-supplied battery to provide nonvolatile operation.
Figure 1. Logic diagram
V
V
BAT
CC
(1)
XI
(1)
XO
SCL
SDA
1. For SO8 package only
M41T81S
V
SS
IRQ/FT/OUT/SQW
AI09160
6/32 Doc ID 10773 Rev 7
M41T81S Description
Table 1. Signal names
(1)
XI
(1)
XO
IRQ/OUT/FT/SQW Interrupt / output driver / frequency test / square wave (open drain)
SDA Serial data input/output
SCL Serial clock input
Oscillator input
Oscillator output
V
V
V
NC
NF
BAT
CC
SS
(2)
(2)
Battery supply voltage
Supply voltage
Ground
No connect
No function
1. For SO8 package only.
2. NC and NF pins should be tied to VSS.
Figure 2. 8-pin SOIC (M) connections
8
7
6
1. Open drain output
1
XI
2
XO
V
BAT
V
SS
M41T81S
3
45
Figure 3. 18-pin, 300 mil SOIC (MY) connections
NF
NF
1
NC
(1)
2
(1)
3
4
NC
5
NC
NC
NC
V
BAT
V
SS
M41T81S
6
7
8
9
18
17
16
15
14
13
12
11
10
V
CC
IRQ/FT/OUT/SQW
SCL
SDA
NC
(1)
NF
(1)
NF
V
CC
NC
IRQ/FT/OUT/SQW
NC
SCL
SDA
(1)
AI09161
(2)
AI09162
1. NC and NF pins should be tied to VSS. Pins 2 and 3 are internally shorted together. Pins 17 and 16 are
internally shorted together.
2. Open drain output
Doc ID 10773 Rev 7 7/32
Description M41T81S
Figure 4. Block diagram
REAL TIME CLOCK
CALENDAR
CRYSTAL
SDA
32KHz
OSCILLATOR
2
I
C
INTERFACE
SCL
WRITE
PROTECT
V
CC
V
BAT
V
SO
V
COMPARE
PFD
1. Open drain output
2. Square wave function has the highest priority on IRQ
OSCILLATOR FAIL
CIRCUIT
RTC W/ALARM
& CALIBRATION
WATCHDOG
SQUARE WAVE
FREQUENCY TEST
OUTPUT DRIVER
/FT/OUT/SQW output.
OFIE
AFE
SQWE
FT
OUT
INTERNAL
POWER
IRQ/FT/OUT/SQW
(2)
(1)
AI09163
8/32 Doc ID 10773 Rev 7
M41T81S Operation
2 Operation
The M41T81S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
1. Tenths/hundredths of a second register
2. Seconds register
3. Minutes register
4. Century/hours register
5. Day register
6. Date register
7. Month register
8. Year register
9. Calibration register
10. Watchdog register
11 - 15. Alarm registers
16. Flags register
17 - 19. Reserved
20. Square wave register
The M41T81S clock continually monitors V
fall below V
, the device terminates an access in progress and resets the device address
PFD
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once V
switchover voltage (V
), the device automatically switches over to the battery and powers
SO
down into an ultra-low current mode of operation to preserve battery life. If V
V
, the device power is switched from VCC to V
PFD
greater than V
V
. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises
PFD
above V
PFD
, the device power is switched from VCC to V
PFD
, it will recognize the inputs.
For more information on battery storage life refer to application note AN1012, "Predicting the
battery life and data retention period of NVRAMs and serial RTCs" .
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
for an out-of-tolerance condition. Should VCC
CC
falls below the
CC
is less than
when VCC drops below V
BAT
when VCC drops below
BAT
BAT
BAT
. If V
BAT
is
Doc ID 10773 Rev 7 9/32
Operation M41T81S
The following protocol has been defined:
● Data transfer may be initiated only when the bus is not busy.
● During data transfer, the data line must remain stable whenever the clock line is high.
● Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
10/32 Doc ID 10773 Rev 7
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