Siemens SAK-C167CR-LM, SAK-C167CR-L25M User Manual

Microcontroller Components

Errata Sheet

May 29, 1998 / Release 1.1

Device: SAK-C167CR-LM

SAK-C167CR-L25M

Stepping Code / Marking: ES-DB, DB

Package: MQFP-144

This Errata Sheet describes the deviations from the current user documentation. The
classification and numbering system is module oriented in a continual ascending sequence
over several derivatives, as well already solved deviations are included. So gaps inside this
enumeration could occur.

The current documentation is: Data Sheet: C167CR-4RM Data Sheet 07.97,

C167SR/CR-L25M Data Sheet Addendum 1998-03
User’s Manual: C167 Derivatives User’s Manual V2.0 03.96
Instruction Set Manual 12.97 Version 1. 2

Note:

completely tested in all functional and electrical characteristics, therefore they should
be used for evaluation only.

The specific test conditions for EES and ES are documented in a separ at e Status Sheet.

Change summary to Errata Sheet Rel.1.0 for devices with stepping code/marking
ES-DB:

• Modifications of ADM field while bit ADST = 0 (ADC.11)

• P0H spikes after XPER write access and external 8-bit Non-multiplexed bus (X12)

• ADC Overload Current (ADCC.2)

• DC specification deviations added, limit for I

• AC timing relaxations added, t5 (ALE high time) tested according to specification

Devices marked with EES- or ES are engineering samples w hi ch may not be

= –110 µA added

P0L

Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 1 of 11 -

Functional Problems:

PWRDN.1: Execution of PWRDN Instructi on w h i le pin NMI# = high

When instruction PWRDN is executed while pin NMI# is at a high level, power down mode should not
be entered, and the PWRDN instruction should be ignored. However, under the conditions described
below, the PWRDN instruction may not be ignored, and no further instructions are fetched from
external memory, i.e. the CPU is in a quasi-idle state. This problem will only occur in the following
situations:
a) the instructions following the PWRDN instruction are located in external memory, and a multiplexed

bus configuration with memory tristate waitstate (bit MTTCx = 0) is used, or

b) the instruction preceeding the PWRDN instruction writes to external memory or an XPeripheral

(XRAM, CAN), and the instructions following the PWRDN instruction are located in external
memory. In this case, the problem will occur for any bus configuration.

Note: the on-chip peripherals are still working correctly, in particular the Watchdog Timer will reset the
device upon an overflow. Interrupts and PEC transfers, however, can not be processed. In case NMI#
is asserted low while the device is in this quasi-idle state, power down mode is entered.

Workaround:

Ensure that no instruction which writes to external memory or an XPeripheral preceeds the PWRDN
instruction, otherwise insert e.g. a NOP instruction in front of PWRDN. When a muliplexed bus with
memory tristate waitstate is used, the PWRDN instruction should be executed out of internal RAM or
XRAM.

Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 2 of 11 -

CPU.17: Arithmetic Overflow by DIVLU instruction

For specific combinations of the values of the dividend (MDH,MDL) and divisor (Rn) , the Overflow ( V)
flag in the PSW may not be set for unsigned divide operations, although an overflow occured.

E.g.:

MDH MDL Rn MDH MDL
F0F0 0F0Fh : F0F0h = FFFF FFFFh, but no Overflow indicated !

(result with 32-bit precision: 1 0000h)

The same malfunction appears for the following combinations:

n0n0 0n0n : n0n0
n00n 0nn0 : n00n
n000 000n : n000

n0nn 0nnn : n0nn where n means any Hex Digit between 8 ... F
i.e. all operand combinations where at least the most significat bit of the dividend (MDH) and the divisor
(Rn) is set.

In the cases where an overflow occurred after DIVLU, but the V flag is not set, the result in MDL is
equal to FFFFh.

Workaround:

Skip execution of DIVLU in case an overflow would occur, and explicitly set V = 1.
E.g.: CMP Rn, MDH

JMPR cc_ugt, NoOverflow ; no overflow if Rn > MDH
BSET V ; set V = 1 if overflow would occur

JMPR cc_uc, NoDivide ; and skip DIVLU
NoOverflow: DIVLU Rn
NoDivide: ... ; next instruction, may evaluate correct V flag

Note:

- the KEIL C compiler, run time libraries and operating system RTX166 do not generate or use
instruction sequences where the V flag in the PSW is tested after a DIVLU instruction.

- with the TASKING C166 compiler, for the following intrinsic functions code is generated which uses
the overflow flag for minimizing or maximizing the function result after a division with a DIVLU:

_div_u32u16_u16()
_div_s32u16_s16()
_div_s32u16_s32()

Consequently, an incorrect overflow flag (when clear instead of set) might affect the result of one of the
above intrinsic functions but only in a situation where no correct result could be calculated anyway.
These intrinsics first appeared in version 5.1r1 of the toolchain.

Libraries: not affected

Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 3 of 11 -

ADC.11: Modificat i ons of ADM field while bit ADST = 0

The A/D converter may unintentionally start one auto scan single conversion sequence when the
following sequence of conditions is true:
(1) the A/D converter has finished a fixed channel single or continuous conversion of an analog

channel n > 0 (i.e. contents of ADCON.ADCH = n during this conversion)
(2) the A/D converter is idle (i.e. ADBSY = 0)
(3) then the conversion mode in the ADC Mode Selection field ADM is changed to Auto Scan Single

(ADM = 10b) or Continuous (ADM = 11b) mode without setting bit ADST = 1 with the same

instruction
Under these conditions, the A/D converter will unintentionally start one auto scan single conversion
sequence, beginning with channel n-1, down to channel number 0.

In case the channel number ADCH has been changed before or with the same instruction which
selected the auto scan mode, this channel number has no effect on the unintended auto scan
sequence (i.e. it is not used in this auto scan sequence).

Note:

When a conversion is already in progress, and then the configuration in register ADCON is changed,

- the new conversion mode in ADM is evaluated after the current conversion

- the new channel number in ADCH and new status of bit ADST are evaluated after the current

conversion when a conversion in fixed channel conversion mode is in progress, and after the

current conversion sequence (i.e. after conversion of channel 0) when a conversion in an auto scan

mode is in progress.
In this case, it is a specified operational behaviour that channels n-1 .. 0 are converted when ADM is

changed to an auto scan mode while a fixed channel conversion of channel n is in progress (see e.g.
C167 User’s Manual, V2.0, p16-4)

Workaround:

When an auto scan conversion is to be performed, always start the A/D converter with the same
instruction which sets the configuration in register ADCON.

X9: Read Access to XPERs in Visible Mode

The data of a read access to an XBUS-Peripheral (XRAM, CAN) in Visible Mode is not driven to the
external bus. PORT0 is tristated during such read accesses.

Semiconductor Group Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh - 4 of 11 -